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preface guide to the S7-300 documentation 1 operating and display elements 2 communication 3 memory concept 4 cycle and reaction times 5 technical data of cpu 31xc 6 technical data of cpu 31x 7 appendix a simatic S7-300 cpu 31xc and cpu 31x, technical data manual edition 08/2004 a5e00105475-05 this manual is part of t he documentation package with the order number : 6es7398-8fa10-8ba0
safety guidelines this manual contains notices which you should observe to ensure your own personal safe ty as well as to avoid property damage. the notices ref erring to your per sonal safety are highlighted in the manu al by a safety alert symbol, notices referring to pr operty damage only have no safet y alert symbol. danger indicates an imminently hazardous situation which, if not avoid ed, will result in deat h or serious injury. warning indicates a potentially hazardo us situation which, if not avoid ed, could result in death or serious injury. caution used with the safety alert symbol indicates a potentially hazar dous situation which, if not avoided, may result in minor or moderate injury. caution used without safety alert symbol i ndicates a potentially hazard ous situation which, if not avoided, may result in property damage. notice used without the safety alert symbol indicates a potential situ ation which, if not avoided, may result in an undesirable result or state. when several danger lev els apply, the notice s of the highest le vel (lower number) are always displayed. if a notice refers to personal damages with the safety alert symbol, then another notice may be added warning of property damage. qualified personnel the device/system may only be se t up and operated in conjunctio n with this documenta tion. only qualified personnel should be allowed to i nstall and work on the equipmen t. qualified persons are defined as persons who are authorized to commission, to earth, and to tag circuits, eq uipment and systems in accordance with established safety practices and standards. intended use please note the following: warning this device and its components may only be used for the applica tions described in the catalog or technical description, and only in connection with devices or c omponents from other manufacturers approved or recommended by siemens. this product can only function correctly and safely if it is tr ansported, stored, set up and installed correctly, and operated and maintained as recommended. trademarks all designations marked with ? are registered trademarks of sie mens ag. other designations in this documentation might be trademar ks which, if used by third parti es for their purposes, might infringe upon the rights of the proprietors. copyright siemens ag ,2004.all rights reserved reproduction, transmission or use of this document or its conte nts is not permitted without express written authority. off enders will be liable for damages . all rights, including rights created by patent grant or registration of a utility model or d esign, are reserved. disclaimer of liability we have checked the contents of this manual for agreement with the hardware and software described. since deviations cannot be precluded entire ly, we cannot guarantee full agreement. however, the data in the manual are reviewed re gularly, and any necessary corrections will be included in subsequent editions. suggestions for improvement are welcomed. siemens ag automation and drives group p.o. box 4848, d-90327 nuremberg (germany) siemens ag 2004 technical data subject to change siemens aktiengesellschaft order no. a5e00105475-05
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 iii preface purpose of the manual this manual contains all the information you will need concerni ng the configuration, communication, memory concept, cyc le, response times and techni cal data for the cpus. you will then learn the points to consider when upgrading to on e of the cpus discussed in this manual. required basic knowledge ? to understand this manual, you require a general knowledge of a utomation engineering. ? you should also be accustomed to working with step 7 basic soft ware. area of application table 1-1 application area covered by this manual as of version cpu convention: cpu designations: order number firmware hardware cpu 312c 6es7312-5bd01-0ab0 v2.0.0 01 cpu 313c 6es7313-5be01-0ab0 v2.0.0 01 cpu 313c-2 ptp 6es7313-6be01-0ab0 v2.0.0 01 cpu 313c-2 dp 6es7313-6ce01-0ab0 v2.0.0 01 cpu 314c-2 ptp 6es7314-6bf01-0ab0 v2.0.0 01 cpu 314c-2 dp cpu 31xc 6es7314-6cf01-0ab0 v2.0.0 01 cpu 312 6es7312-1ad10-0ab0 v2.0.0 01 cpu 314 6es7314-1af10-0ab0 v2.0.0 01 cpu 315-2 dp 6es7315- 2ag10-0ab0 v2.0.0 01 cpu 315-2 pn/dp 6es73 15-2eg10-0ab0 v2.3.0 01 cpu 317-2 dp 6es7317- 2aj10-0ab0 v2.1.0 01 cpu 317-2 pn/dp cpu 31x 6es7317-2ej10-0ab0 v2.3.0 01 note the special features of the cpu 315f-2 dp (6es7 315-6ff00-0ab0) and cpu 317f-2 dp (6es7 317-6ff00-0ab0) are descri bed in their product informatio n, available on the internet at http://www.siemens.com/automation/service&support, article id 1 7015818.
preface cpu 31xc and cpu 31x, technical data iv manual, edition 08/2004, a5e00105475-05 note there you can obtain the descri ptions of all current modules. f or new modules, or modules of a more recent version, we re serve the right to include a pro duct information containing latest information. approvals the simatic S7-300 product serie s has the following approvals: ? underwriters laboratories, inc .: ul 508 (industrial control equ ipment) ? canadian standards association: c sa c22.2 no. 142, (process con trol equipment) ? factory mutual research: approval standard class number 3611 ce label the simatic S7-300 product series satisfies the requirements an d safety specifications of the following ec directives: ? ec directive 73/23/eec "lo w-voltage directive" ? ec directive 89/336/eec "emc directive" c tick mark the simatic S7-300 product serie s is compliant with as/nzs 2064 (australia). standards the simatic S7-300 product serie s is compliant with iec 61131-2 .
preface cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 v documentation classification this manual is part of the s7-3 00 documentation package. name of the manual description you are reading the manual ? cpu 31xc and cpu 31x, technical data control and display elements, communication, memory concept, cycle and response times, technical data reference manual ? cpu data: cpu 312 ifm C 318-2 dp control and display elements, communication, memory concept, cycle and response times, technical data operating instructions ? S7-300, cpu 31xc and cpu 31x: installation configuration, installation, wiring, addressing, commissioning, maintenance and the test functions, diagnostics and troubleshooting. installation manual ? S7-300 automation syst em: installation: cpu 312 ifm C 318-2 dp configuration, installation, wiring, addressing, commissioning, maintenance and the test functions, diagnostics and troubleshooting. system manual profinet system description basic information on profinet: network components , data exchange and communication, profinet i/o, component based automation, application example of profinet i/o and component based automation programming manual from profibus dp to profinet io guideline for the migrat ion from profibus dp to profinet i/o. manual ? cpu 31xc: technological functions ? examples description of the individual technological functions positioning, counting. ptp communication, rules the cd contains examples of the technological functions reference manual ? S7-300 automation system: module data descriptions of the functi ons and technical data of signal modules, power supply modules and interface modules. instruction list ? cpu 312 ifm C 318-2 dp ? cpu 31xc and cpu 31x list of cpu instruction resources and the relevant executi on times. list of executable blocks. getting started the following getting started editions are available as a collective volume: ? cpu 31x: commissioning ? cpu 31xc: commissioning ? cpu 31xc: positioning with analog output ? cpu 31xc: positioning with digital output ? cpu 31xc: counting ? cpu 31xc: rules ? cpu 31xc: ptp communication ? cpu 31x-2 pn/dp: commissioning a profinet io subnet the example used in this getting started guides you through the various steps in commissioning required to obtain a fully functional application.
preface cpu 31xc and cpu 31x, technical data vi manual, edition 08/2004, a5e00105475-05 additional information required: name of the manual description reference manual system software for s7 -300/400 system and standard functions description of the sfcs, sfbs and obs. this manual is part of the step 7 documentation package. for further information, refer to the step 7 online help. manual simatic net: twisted pair and fiber-optic networks description of industrial ethernet networks, network configuration, components, installation guidelines for networked automation systems in buildings, etc. manual component-based automation : configuring systems with simatic imap description of the engineering software imap manual programming with step 7 v5.3 programming with step 7 manual simatic communication basics, services, networks, communication functions, connecting pgs/ops, engineering a nd configuring in step 7. recycling and disposal the devices described in this manual can be recycled, due to th eir ecologically compatible components. for environment-frie ndly recycling and disposal of your old equipment, contact a certified disposal facilit y for electronic scrap.
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 vii table of contents preface ....................................................................................................................... ............................... iii 1 guide to the s7- 300 document ation ............................................................................................ ........... 1-1 2 operating and di splay el ements ............................................................................................... .............. 2-1 2.1 operating and display elements: cp u 31xc ............................................................................. 2-1 2.1.1 status and error indicators: cpu 31 xc .................................................................................... .2-4 2.2 operating and displa y elements: cpu 31x ................................................................................ 2-5 2.2.1 operating and display element s: cpu 312, 314, 315-2 dp : ..................................................... 2-5 2.2.2 operating and display elements: cpu 317-2 dp ...................................................................... 2-7 2.2.3 operating and display el ements: cpu 31x-2 pn/dp ................................................................ 2-9 2.2.4 status and error disp lays of the cpu 31x................................................................................ 2 -11 3 communi cation................................................................................................................ ....................... 3-1 3.1 inte rfaces ................................................................................................................. .................. 3-1 3.1.1 multi-point interface (mpi) .............................................................................................. ........... 3-1 3.1.2 prof ibus dp.............................................................................................................. ............. 3-2 3.1.3 profin et (pn)............................................................................................................ ............. 3-3 3.1.4 point to point (ptp) ..................................................................................................... ............... 3-5 3.2 communication services..................................................................................................... ....... 3-6 3.2.1 overview of communication services ....................................................................................... .3-6 3.2.2 pg co mmunication......................................................................................................... ............ 3-7 3.2.3 op co mmunication......................................................................................................... ............ 3-7 3.2.4 data exchanged by means of s7 basic comm unication ............................................................ 3-7 3.2.5 s7 co mmunication ......................................................................................................... ............ 3-8 3.2.6 global data comm unication (m pi only)..................................................................................... .3-9 3.2.7 r outing.................................................................................................................. ................... 3-10 3.2.8 ptp co mmunication ........................................................................................................ .......... 3-15 3.2.9 data co nsistency......................................................................................................... ............. 3-16 3.2.10 communica tion via profinet (only cpu 31x-2 pn /dp) ...................................................... 3-16 3.2.10.1 profinet io system .................................................................................................... ......... 3-19 3.2.10.2 blocks in profinet io................................................................................................. .......... 3-20 3.2.10.3 system status lists (ssls) in pr ofinet io ........................................................................... 3- 23 3.2.10.4 open communication via industria l ethernet ........................................................................... 3 -24 3.2.10.5 snmp communication service ............................................................................................ ..... 3-26 3.3 s7 conn ections ............................................................................................................. ........... 3-26 3.3.1 s7 connection as communication path .................................................................................... 3- 26 3.3.2 assignment of s7 conne ctions............................................................................................. .... 3-27 3.3.3 distribution and availability of s7 connection resource s ......................................................... 3-29 3.3.4 connection reso urces for routing......................................................................................... .... 3-31 3.4 dpv1....................................................................................................................... ................. 3-32
table of contents cpu 31xc and cpu 31x, technical data viii manual, edition 08/2004, a5e00105475-05 4 memory concept ............................................................................................................... ...................... 4-1 4.1 memory areas and retentivity............................................................................................... ...... 4-1 4.1.1 cpu memo ry areas......................................................................................................... ........... 4-1 4.1.2 retentivity of the load memo ry, system memory and ra m....................................................... 4-2 4.1.3 retentivity of memory objects ............................................................................................ ........ 4-3 4.1.4 address areas of system memory ........................................................................................... .. 4-5 4.1.5 properties of the micr o memory card (mmc) ............................................................................ 4-9 4.2 memory functions........................................................................................................... .......... 4-11 4.2.1 general: memory functions ................................................................................................ ...... 4-11 4.2.2 loading user program from micro me mory card (mmc) to the cp u ...................................... 4-11 4.2.3 handling with modules .................................................................................................... ......... 4-12 4.2.3.1 download of new blocks or del ta downlo ads ........................................................................... 4-1 2 4.2.3.2 uplo ading blocks....................................................................................................... ............... 4-12 4.2.3.3 deleti ng blocks........................................................................................................ ................. 4-13 4.2.3.4 compre ssing blocks..................................................................................................... ............ 4-13 4.2.3.5 promming (ram to rom) .................................................................................................. ...... 4-13 4.2.4 cpu memory re set and restart ............................................................................................. ... 4-13 4.2.5 recipes .................................................................................................................. .................. 4-15 4.2.6 measured va lue log files ................................................................................................. ......... 4-17 4.2.7 backup of project data to a micro memory ca rd (mmc ) ......................................................... 4-19 5 cycle and reac tion ti mes..................................................................................................... .................... 5-1 5.1 overview ................................................................................................................... ................. 5-1 5.2 cycl e time................................................................................................................. .................. 5-2 5.2.1 ov erview ................................................................................................................. ................... 5-2 5.2.2 calculating the cycle time ............................................................................................... ........... 5-5 5.2.3 different cycle times.................................................................................................... ............... 5-8 5.2.4 communi cation load ....................................................................................................... ........... 5-9 5.2.5 cycle time extension as a result of testing and commissi oning func tions ............................... 5-11 5.2.6 cycle extension through co mponent-based autom ation (c ba)............................................... 5-11 5.3 respon se time .............................................................................................................. ........... 5-14 5.3.1 ov erview ................................................................................................................. ................. 5-14 5.3.2 shortest response time ................................................................................................... ......... 5-16 5.3.3 longest re sponse time.................................................................................................... ......... 5-17 5.3.4 reducing the response time with direct i/o access ................................................................. 5-18 5.4 calculating method for calculat ing the cycle/res ponse ti me .................................................... 5-19 5.5 interrupt response time .................................................................................................... ........ 5-21 5.5.1 ov erview ................................................................................................................. ................. 5-21 5.5.2 reproducibility of delay inte rrupts and watchdog interrupt s .................................................... 5-23 5.6 sample ca lculations ........................................................................................................ ......... 5-24 5.6.1 example of cycl e time calculation ........................................................................................ .... 5-24 5.6.2 sample of respon se time calculation ...................................................................................... . 5-25 5.6.3 example of inte rrupt response time calculat ion ....................................................................... 5-27 6 technical data of cpu 31xc................................................................................................... ................ 6-1 6.1 general te chnical data ..................................................................................................... .......... 6-1 6.1.1 dimensions of cpu 31xc ................................................................................................... ....... 6-1 6.1.2 technical data of the mi cro memory card (mmc) ..................................................................... 6-2 6.2 cpu 312c ................................................................................................................... ............... 6-3 6.3 cpu 313c ................................................................................................................... ............... 6-8 6.4 cpu 313c-2 ptp and cpu 313c-2 dp ................................................................................... 6-14
table of contents cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 ix 6.5 cpu 314c-2 ptp and cpu 314c-2 dp ................................................................................... 6-21 6.6 technical data of the int egrated i/o....................................................................................... .. 6-28 6.6.1 arrangement and usage of integrated i/os.............................................................................. 6-2 8 6.6.2 a nalog i/o ............................................................................................................... ................. 6-34 6.6.3 config uration............................................................................................................ ................ 6-39 6.6.4 inte rrupts ............................................................................................................... ................... 6-45 6.6.5 diag nostics.............................................................................................................. ................. 6-46 6.6.6 digita l input s........................................................................................................... .................. 6-46 6.6.7 digita l outputs .......................................................................................................... ................ 6-48 6.6.8 anal og inputs ............................................................................................................ ............... 6-51 6.6.9 anal og outputs ........................................................................................................... .............. 6-53 7 technical data of cpu 31x .................................................................................................... ................. 7-1 7.1 general te chnical data ..................................................................................................... .......... 7-1 7.1.1 dimensions of cpu 31x.................................................................................................... ......... 7-1 7.1.2 technical data of the mi cro memory card (mmc) ..................................................................... 7-2 7.2 cpu 312.................................................................................................................... ................. 7-3 7.3 cpu 314.................................................................................................................... ................. 7-8 7.4 cpu 31 5-2 dp ............................................................................................................... .......... 7-13 7.5 cpu 315- 2 pn/dp ............................................................................................................ ....... 7-19 7.6 cpu 31 7-2 dp ............................................................................................................... .......... 7-26 7.7 cpu 317- 2 pn/dp ............................................................................................................ ....... 7-33 a appendi x..................................................................................................................... ............................a-1 a.1 information about upgrading to a cpu 31xc or cpu 31x ......................................................... a-1 a.1.1 area of applicability.................................................................................................... ................ a-1 a.1.2 changed behavio r of cert ain sfcs......................................................................................... ... a-2 a.1.3 interrupt events from distributed i/os while the cp u status is in stop ................................... a-4 a.1.4 runtimes that change whil e the program is running ................................................................. a-5 a.1.5 converting the diagnostic addresses of dp slaves ................................................................... a-5 a.1.6 reusing existing har dware configurations ................................................................................. a-6 a.1.7 replacing a cpu 31xc/31x ................................................................................................. ...... a-6 a.1.8 using consistent data areas in the process image of a dp slave system ................................. a-7 a.1.9 load memory concept fo r the cpu 31 xc/31x ........................................................................... a-8 a.1.10 pg/op functi ons ......................................................................................................... ............... a-8 a.1.11 routing for the cpu 31xc/31x as an in telligent sl ave............................................................... a-8 a.1.12 changed retent ive behavior for cpus with firmware >= v2.1.0 ................................................ a-9 a.1.13 fms/cps with separate mpi address in the central rack of a cpu 315-2 pn/dp / cpu 317 ... a-9 a.1.14 using loadable blocks for s7 communication for the integrated prof inet interface ........... a-10 glossary ...................................................................................................................... ............... glossary-1 index......................................................................................................................... ....................... index-1
table of contents cpu 31xc and cpu 31x, technical data x manual, edition 08/2004, a5e00105475-05 tables table 1-1 application ar ea covered by this ma nual ...................................................................................... ii i table 1-1 ambient influence on the au tomation syste m (as) .................................................................... 1-1 table 1-2 galvanic is olation ............................................................................................................. .......... 1-1 table 1-3 communication between sensors/ac tuators and t he plc......................................................... 1-2 table 1-4 the use of local and distri buted i/o ........................................................................................... 1-2 table 1-5 configuration consisting of the central unit (cu) and ex pansion modules (ems).................... 1-2 table 1-6 cpu perfor mance ................................................................................................................ ...... 1-3 table 1-7 communication .................................................................................................................. ........ 1-3 table 1-8 software ....................................................................................................................... .............. 1-3 table 1-9 supplementary features ......................................................................................................... .... 1-4 table 2-1 positions of the mode selector switch ........................................................................................ 2- 3 table 2-2 differences of the cpus 31xc ................................................................................................... 2-3 table 2-3 positions of the mode selector switch ........................................................................................ 2- 6 table 2-4 positions of the mode selector switch ........................................................................................ 2- 8 table 2-5 positions of the mode selector sw itch...................................................................................... 2-10 table 2-6 general status and error disp lays of the cpu 31x .................................................................. 2-11 table 2-7 bus error displays of cpu 31x ................................................................................................. 2 -11 table 3-1 operating modes for cpus wi th two dp in terfaces ................................................................... 3-2 table 3-2 communication services of the cpus ....................................................................................... 3-6 table 3-3 client and server in s7 communication, using connections with unilateral / bilateral conf iguration ........................................................................................................ ......... 3-8 table 3-4 gd resources of the cpus....................................................................................................... 3-10 table 3-5 number of routing connect ions for dp cpus .......................................................................... 3-12 table 3-6 new system standard functions of profinet io and profibus dp and those that must be replaced................................................................................................. 3-2 1 table 3-7 system and standard functions in profibus dp that must be implemented with different functions in profinet io ....................................................................................... 3-22 table 3-8 obs in profinet io and profibus dp.............................................................................. 3-22 table 3-9 comparison of the system status lists of profinet and profib us ................................. 3-23 table 3-10 distribution of connections .................................................................................................... ... 3-29 table 3-11 availability of conn ection reso urces......................................................................................... 3- 30 table 3-12 number of routing connection re sources (for dp /pn cpus )................................................... 3-31 table 3-13 interrupt blocks with d pv1 functiona lity................................................................................... 3-33 table 3-14 system function blocks with dpv1 functi onality ...................................................................... 3-33
table of contents cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 xi table 4-1 retentivity of the ram ......................................................................................................... ...... 4-2 table 4-2 retentive behavior of memory objects (applies to all cpus with dp/mpi-ss (31x-2 pn/dp) .. 4-3 table 4-3 retentive behavior of dbs for cpus with firmware >= v2.1.0 .................................................. 4-4 table 4-4 address areas of sy stem memory ............................................................................................. 4-5 table 5-1 cyclic program processing...................................................................................................... ... 5-3 table 5-2 formula for calculating the proces s image (pi) tran sfer time .................................................... 5-5 table 5-3 cpu 31xc: data for calculating the pr ocess image (pi) tr ansfer time....................................... 5-5 table 5-4 cpu 31x: data for calculating the pr ocess image (pi) tr ansfer ti me ......................................... 5-6 table 5-5 extending the user progra m processing time ............................................................................ 5-6 table 5-6 operating system processing time at the scan cycle checkpoint .............................................. 5-7 table 5-7 extended cycle time due to nested inte rrupts............................................................................ 5-7 table 5-8 cycle time extension as a result of errors.................................................................................. 5-8 table 5-9 cycle time extension as a result of testing and commissioni ng functi ons ............................... 5-11 table 5-10 formula: shortest response time............................................................................................. 5-1 6 table 5-11 formula: longest re sponse time ............................................................................................. 5-18 table 5-12 calculating the response time.................................................................................................. 5-20 table 5-13 process/diagnostic interrup t response times ........................................................................... 5-21 table 5-14 process/diagnostic interrup t response times ........................................................................... 5-22 table 6-1 availabl e mmcs ................................................................................................................. ........ 6-2 table 6-2 maximum number of loadab le blocks on the mmc .................................................................... 6-2 table 6-3 technical data of cpu 312c ..................................................................................................... 6-3 table 6-4 technical data of cpu 313c ..................................................................................................... 6-8 table 6-5 technical data for cpu 313c- 2 ptp/ cpu 313 c-2 dp ............................................................ 6-14 table 6-6 technical data of cpu 314c-2 ptp and cpu 314c -2 dp ....................................................... 6-21 table 6-7 parameters of standard di...................................................................................................... .6-39 table 6-8 parameters of the interrupt inputs............................................................................................ 6 -39 table 6-9 parameters of standard ai ...................................................................................................... .6-41 table 6-10 parameters of standard ao ..................................................................................................... 6 -42 table 6-11 start information for ob40, relating to the interrupt inputs of the integrat ed i/o ..................... 6-45 table 6-12 technical data of digital inputs............................................................................................... .. 6-47 table 6-13 technical data of digital outputs .............................................................................................. 6-49 table 6-14 technical data of analog inputs ............................................................................................... 6 -51 table 6-15 technical data of analog out puts ............................................................................................. 6- 53
table of contents cpu 31xc and cpu 31x, technical data xii manual, edition 08/2004, a5e00105475-05 table 7-1 availabl e mmcs ................................................................................................................. ........ 7-2 table 7-2 maximum number of loadab le blocks on the mmc .................................................................... 7-2 table 7-3 technical data fo r the cp u 312................................................................................................. 7-3 table 7-4 technical data fo r the cp u 314................................................................................................. 7-8 table 7-5 technical data for t he cpu 315-2 dp...................................................................................... 7-13 table 7-6 technical data for the cpu 315-2 pn /dp................................................................................ 7-19 table 7-7 technical data for t he cpu 317-2 dp...................................................................................... 7-26 table 7-8 technical data for the cpu 317-2 pn /dp................................................................................ 7-33 table a-1 consistent data ................................................................................................................ ..........a-7
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 1-1 guide to the S7-300 documentation 1 overview there you find a guide leading y ou through the S7-300 documenta tion. selecting and configuring table 1-1 ambient influence on the automation system (as) information on.. is available in ... what provisions do i have to make for as installation space? S7-300, cpu 31xc and cpu 31x operating instructions: installation: configuring - component dimensions S7-300, cpu 31xc and cpu 31x operating instructions: installation: mounting - in stalling the mounting rail how do environmental conditions influence the as? S7-300, cpu 3 1xc and cpu 31x operating instructions: installation: appendix table 1-2 galvanic isolation information on.. is available in ... which modules can i use if ele ctrical isolat ion is required between sensors/actuators? S7-300, cpu 31xc and cpu 31x operating instructions: installation: configuring C el ectrical assembly, protective measures and grounding module data manual under what conditions do i have to isolate the modules electrically? how do i wire that? S7-300, cpu 31xc and cpu 31x operating instructions: installation: configuring C el ectrical assembly, protective measures and grounding cpu 31xc and cpu 31x operating instructions: installation: wiring under which conditions do i have to isola te stations electrically? how do i wire that? S7-300, cpu 31xc and cpu 31x operating instructions: installation C configurin g C configuring subnets
guide to the S7-300 documentation cpu 31xc and cpu 31x, technical data 1-2 manual, edition 08/2004, a5e00105475-05 table 1-3 communication between sensors/actuators and the plc information on.. is available in ... which module is suitable for my sensor/actuator? for cpu: cpu 3 1xc and cpu 31x manual, technical data for signal modules: referenc e manual of your signal module how many sensors/actuators can i connect to the module? for cpu : cpu 31xc and cpu 31x manual, technical data of signal modules: reference manual of your signal module to connect my sensors/actuator s to the plc, how do i wire the front connector ? S7-300, cpu 31xc and cpu 31x operating instructions: installation: wiring C wi ring the front connector when do i need expansion m odules (em) and how do i connect them? S7-300, cpu 31xc and cpu 31x operating instructions: installation: configuring C distr ibution of modules to several racks how to mount modules on racks / m ounting rails S7-300, cpu 31xc and cpu 31x opera ting instructions: installation: assembly C instal ling modules on the mounting rail table 1-4 the use of l ocal and distributed i/o information on.. is available in ... which range of modules do i wan t to use? for local i/o and expa nsion devices: module data reference manual for distributed i/o and prof ibus dp: manual of the relevant i/o device table 1-5 confi guration consisti ng of the central unit (cu) and expansion modules (ems) information on.. is available in ... which rack / mounting rail i s most suitable for my application? S7-300, cpu 31xc and cpu 31x operating instructions: installation: configuring which interface modules (i m) do i need to connect the ems to the cu? S7-300, cpu 31xc and cpu 31x operating instructions: installation: configuring C distr ibution of modules to several racks what is the right power supply (ps) for my application? S7-300, cpu 31xc and cpu 31x operating instructions: installation: configuring
guide to the S7-300 documentation cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 1-3 table 1-6 cpu performance information on.. is available in ... which memory concept is best sui ted to my application? cpu 31xc and cpu 31x manual, technical data how do i insert and remove micro m emory cards? S7-300, cpu 31xc and cpu 31x opera ting instructions: installation: commissionin g C commissioni ng modules C removing / inserting a mi cro memory card (mmc) which cpu meets my dem ands on performance? s 7-300 instruction l ist: cpu 31xc and cpu 31x length of the cpu response / exe cution times cpu 31xc and cpu 3 1x manual, technical data which technological functions ar e implemented? technological fu nctions manual how can i use these technological functions? technological func tions manual table 1-7 communication information on.. is available in ... which principles do i have to take into account? communication with simatic manual profinet system manual, system description options and resources of the cp u cpu 31xc and cpu 31x manual, t echnical data how to use communication pr ocessors (cps) to optimize communication cp manual which type of communication network is best suited to my application? S7-300, cpu 31xc and cpu 31x operating instructions: installation: configuring C configuring subnets how to network the various compo nents S7-300, cpu 31xc and cpu 31x operating instructions: installation: configuring C configuring subnets what to take into account whe n configuring profinet networks simatic net manual, twiste d-pair and fiber optic networks (6gk1970-1ba10-0aa0 ) C network configuration profinet system manual, system description C installation and commissioning table 1-8 software information on.. is available in ... software requirements of my s7-3 00 system cpu 31xc and cpu 31x manual, technical data C technical data
guide to the S7-300 documentation cpu 31xc and cpu 31x, technical data 1-4 manual, edition 08/2004, a5e00105475-05 table 1-9 supplementary features information on.. is available in ... how to implement monito r and modify functions (human machine interface) for text-based displays: the relevant manual for operator panels: the relevant manual for wincc: the relevant manual how to integrate pro cess control modules for pcs7: the relevant manual what options are offered by redundant and fail-safe systems? s7-400h manual C redundant systems fail-safe systems manual information to be observed when migrating from profibus dp to profinet io programming manual: from pr ofibus dp to profinet io
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 2-1 operating and display elements 2 2.1 operating and display elements: cpu 31xc operating and display elements of cpu 31xc sf bf dc5v run stop run stop mres frce x1 x2 x11 x12 mmc 1 2 3 4 5 6 7 the figures show the following cpu elements (1) status and error displays (2) slot for the micro memory c ard (mmc), incl. the ejector (3) connections of the integrated i/o. (4) power supply connection (5) 2. interface x2 (ptp or dp) (6) 1. interface x1 (mpi) (7) mode selector switch
operating and display elements 2.1 operating and display elements: cpu 31xc cpu 31xc and cpu 31x, technical data 2-2 manual, edition 08/2004, a5e00105475-05 the figure below illustrates t he integrated digital and analog i/os of the cpu with open front covers. sf bf dc5v frce run stop run stop mres x11 x12 2 2 1 3 1 2 3 figure 2-1 integrated i/os of cpu 31xc (cpu 314c-2 ptp, for exa mple) the figure shows the following integrated i/os (1) analog i/os (2) each with 8 digital inputs (3) each with 8 digital outputs slot for the simatic micro memory card (mmc) a simatic micro memory card (mmc ) is used as memory module. you can use mmcs as load memory and as portable storage medium. note these cpus do not have an integrated load memory and thus requi re an mmc for operation.
operating and display elements 2.1 operating and display elements: cpu 31xc cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 2-3 mode selector switch use the mode selector switch to set the cpu operating mode. table 2-1 positions of t he mode selector switch position meaning description run run mode the cpu execut es the user program. stop stop mode the cpu does not execute a user program. mres cpu memory reset mode selector switch position with pushbutt on function for cpu memory reset. a cpu memory re set by means of mode selector switch requires a specif ic sequence of operation. reference ? cpu operating modes: step 7 online help . ? information on c pu memory reset: operating instructions cpu 31xc and cpu31x, commissioning, commissioning modules, cpu memory reset by means of mode selector switch ? evaluation of the leds upon error or diagnostic event: operating instructions cpu 31xc and cpu 31x, test functions, dia gnostics and troubleshooting, d iagnostics with the help of status and error leds power supply connection each cpu is equipped with a doubl e-pole power supply socket. th e connector with screw terminals is inserted into this s ocket when the cpu is delivere d. differences between the cpus table 2-2 differences of the cpus 31xc element cpu 312c cpu 313c cpu 313c-2 dp cpu 313c-2 ptp cpu 314c-2 dp cpu 314c-2 ptp 9-pole dp interface (x2) C C x C x C 15-pole ptp interface (x2) C C C x C x digital inputs 10 24 16 16 24 24 digital outputs 6 16 16 16 16 16 analog inputs C 4 + 1 C C 4 + 1 4 + 1 analog outputs C 2 C C 2 2 technological functions 2 counters 3 counter s 3 counters 3 c ounters 4 counters 1 channel for positioning 4 counters 1 channel for positioning
operating and display elements 2.1 operating and display elements: cpu 31xc cpu 31xc and cpu 31x, technical data 2-4 manual, edition 08/2004, a5e00105475-05 2.1.1 status and error indicators: cpu 31xc led designation color meaning sf red hardware or software error bf (for cpus with dp interface only) red bus error dc5v green 5-v power for cp u and S7-300 bus is ok frce yellow force job is active run green cpu in run the led flashes during startup at a rate of 2 hz, and in hold state at 0.5 hz. stop yellow cpu in stop and hold or startup the led flashes at 0.5 hz when the cpu requests a memory reset, and during the reset at 2 hz. reference ? cpu operating modes: step 7 online help . ? information on c pu memory reset: operating instructions cpu 31xc and cpu31x, commissioning, commissioning modules, cpu memory reset by means of mode selector switch evaluation of the leds upon er ror or diagnostic event: operating instructions cpu 31xc and cpu 31 x, test functions, diagnostics and troubleshooting, diagnostics with the help of status and error leds
operating and display elements 2.2 operating and display elements: cpu 31x cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 2-5 2.2 operating and display elements: cpu 31x 2.2.1 operating and display el ements: cpu 312, 314, 315-2 dp: operating and display elements sf bf dc5v run stop run stop mres frce x2 x1 mmc 1 2 3 4 5 6 the figures show the following cpu elements (1) slot for the micro memory c ard (mmc), incl. the ejector (2) 2. interface x2 (only for cpu 315-2 dp) (3) power supply connection (4) 1. interface x1 (mpi) (5) mode selector switch (6) status and error displays
operating and display elements 2.2 operating and display elements: cpu 31x cpu 31xc and cpu 31x, technical data 2-6 manual, edition 08/2004, a5e00105475-05 slot for the simatic micro memory card (mmc) a simatic micro memory card (mmc ) is used as memory module. you can use mmcs as load memory and as portable storage medium. note these cpus do not have an integrated load memory and thus requi re an mmc for operation. mode selector switch the mode selector switch is us ed to set the cpu operating mode. table 2-3 positions of t he mode selector switch position meaning description run run mode the cpu execut es the user program. stop stop mode the cpu does not execute a user program. mres cpu memory reset mode select or switch posit ion with pushbu tton function for cpu memory reset. a cpu memor y reset by means of mode selector switch requires a sp ecific sequence of operation. reference ? cpu operating modes: step 7 online help . ? information on c pu memory reset: operating instructions cpu 31xc and cpu31x, commissioning, commissioning modul es, cp memory reset by means of mode selector switch ? evaluation of the leds upon error or diagnostic event: operating instructions cpu 31xc and cpu 31x, test functions, dia gnostics and troubleshooting, d iagnostics with the help of status and error leds power supply connection each cpu is equipped with a doubl e-pole power supply socket. th e connector with screw terminals is inserted into this socket when the cpu is delivere d.
operating and display elements 2.2 operating and display elements: cpu 31x cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 2-7 2.2.2 operating and displa y elements: cpu 317-2 dp operating and display elements run stop mres bf1 bf2 sf dc5v frce run stop x2 x1 mmc 1 2 3 4 5 6 7 the figures show the following cpu elements (1) bus error indicator (2) status and error displays (3) slot for the micro memory c ard (mmc), incl. the ejector (4) mode selector switch (5) power supply connection (6) 1. interface x1 (mpi/dp) (7) 2. interface x2 (dp)
operating and display elements 2.2 operating and display elements: cpu 31x cpu 31xc and cpu 31x, technical data 2-8 manual, edition 08/2004, a5e00105475-05 slot for the simatic micro memory card (mmc) a simatic micro memory card (mmc ) is used as memory module. you can use mmcs as load memory and as portable storage medium. note these cpus do not have an integrated load memory and thus requi re an mmc for operation. mode selector switch use the mode selector switch to set the cpu operating mode. table 2-4 positions of t he mode selector switch position meaning description run run mode the cpu execut es the user program. stop stop mode the cpu does not execute a user program. mres cpu memory reset mode select or switch posit ion with pushbu tton function for cpu memory reset. a cpu memor y reset by means of mode selector switch requires a sp ecific sequence of operation. reference ? cpu operating modes: step 7 online help . ? information on c pu memory reset: operating instructions cpu 31xc and cpu31x, commissioning, commissioning modul es, cp memory reset by means of mode selector switch ? evaluation of the leds upon error or diagnostic event: operating instructions cpu 31xc and cpu 31x, test functions, dia gnostics and troubleshooting, d iagnostics with the help of status and error leds power supply connection each cpu is equipped with a doubl e-pole power supply socket. th e connector with screw terminals is inserted into this socket when the cpu is delivere d.
operating and display elements 2.2 operating and display elements: cpu 31x cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 2-9 2.2.3 operating and display elements: cpu 31x-2 pn/dp operating and display elements run stop mres bf1 sf dc5v frce run stop x1 link rx / tx mac-add.: x1-x2-x3 x4-x5-x6 x2 bf2 mmc 1 2 3 4 5 6 7 8 the figures show the following cpu elements (1) bus error indicators (2) status and error displays (3) slot for the micro memory c ard (mmc), incl. the ejector (4) mode selector switch (5) status display of 2nd interface (x2) (6) 2. interface x2 (pn) (7) power supply connection (8) 1. interface x1 (mpi/dp)
operating and display elements 2.2 operating and display elements: cpu 31x cpu 31xc and cpu 31x, technical data 2-10 manual, edition 08/2004, a5e00105475-05 slot for the simatic micro memory card (mmc) a simatic micro memory card (mmc ) is used as memory module. you can use mmcs as load memory and as portable storage medium. note these cpus do not have an integrated load memory and thus requi re an mmc for operation. mode selector switch use the mode selector switch to set the cpu operating mode. table 2-5 positions of t he mode selector switch position meaning description run run mode the cpu execut es the user program. stop stop mode the cpu does not execute a user program. mres cpu memory reset mode select or switch posit ion with pushbut ton function for cpu memory reset. a cpu memory re set by means of mode selector switch requires a specif ic sequence of operation. reference ? cpu operating modes: step 7 online help . ? information on c pu memory reset: operating instructions cpu 31xc and cpu31x, commissioning, commissioning modul es, cp memory reset by means of mode selector switch ? evaluation of the leds upon error or diagnostic event: operating instructions cpu 31xc and cpu 31x, test functions, dia gnostics and troubleshooting, d iagnostics with the help of status and error leds power supply connection each cpu is equipped with a doubl e-pole power supply socket. th e connector with screw terminals is inserted into this socket when the cpu is delivere d.
operating and display elements 2.2 operating and display elements: cpu 31x cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 2-11 2.2.4 status and error displays of the cpu 31x general status and error displays table 2-6 general status and er ror displays of the cpu 31x led designation color meaning sf red hardware or software error. dc5v green 5-v power for the cpu and the S7-300 bus frce yellow led is lit: active force job led flashes at 2 hz : node flash test function (only cpus with firmware v2.2.0 or higher) run green cpu in run the led flashes during startup at a rate of 2 hz, and in hold state at 0.5 hz. stop yellow cpu in stop, or hold, or startup the led flashes at 0.5 hz when the cpu requests a memory reset, and during the reset at 2 hz. displays for the x1 and x2 interfaces table 2-7 bus error displays of cpu 31x cpu led designation color meaning 315-2 dp bf red bus error at dp interface (x2) bf1 red bus error at interface 1 (x1) 317-2 dp bf2 red bus error at interface 2 (x1) bf1 red bus error at interface 1 (x1) bf2 red bus error at interface 2 (x1) link green active communica tion at interface 2 (x2). 31x-2 pn/dp rx/tx yellow receive / transmi t data at interface 2 (x2) reference ? cpu operating modes: step 7 online help . ? information on c pu memory reset: operating instructions cpu 31xc and cpu31x, commissioning, commissioning modul es, cp memory reset by means of mode selector switch ? evaluation of the leds upon error or diagnostic event: operating instructions cpu 31xc and cpu 31x, test functions, dia gnostics and troubleshooting, d iagnostics with the help of status and error leds
operating and display elements 2.2 operating and display elements: cpu 31x cpu 31xc and cpu 31x, technical data 2-12 manual, edition 08/2004, a5e00105475-05
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-1 communication 3 3.1 interfaces 3.1.1 multi-point interface (mpi) availability all cpus described in this manual are equipped with an mpi inte rface x1. a cpu equipped with an mpi/dp inte rface is configured and suppl ied as mpi. to use the dp interface, set dp interface mode in step 7. properties the mpi (multi-point interface) r epresents the cpu interface fo r pg/op connections, or for communication on an mpi subnet. the typical (default) transmissi on rate of all cpus is 187.5 kb ps. you can also set 19.2 kbps for communication with an s7-2 00. the 315-2 pn/dp and 317 cpus support transmission rates up to 12 mbps. the cpu automatically broadcasts its bus configuration via the mpi interface (the transmission rate, for example). a pg, for example, can thus re ceive the correct parameters and automatically connect to a mpi subnet. note you may only connect pgs to an mpi subnet which is in run. other stations (for example, op , tp, ...) should not be connect ed to the mpi subnet while the system is in run. otherwise , transferred data might be corr upted as a result interference, or global data packages may be lost.
communication 3.1 interfaces cpu 31xc and cpu 31x, technical data 3-2 manual, edition 08/2004, a5e00105475-05 devices capable of mpi communication ? pg/pc ? op/tp ? S7-300 / s7-400 with mpi interface ? s7-200 (19.2 kbps only) 3.1.2 profibus dp availability cpus with dp name suffix are equipped at least with a dp x2 i nterface. the 315-2 pn/dp and 317 cpus are equipped with an mpi/dp x1 int erface. a cpu with mpi/dp interface is supplied with a default mpi configuration. you need to set dp mode in step 7 if you want to use the dp interface. operating modes for cpus with two dp interfaces table 3-1 operating modes for cpus with two dp interfaces mpi/dp interface (x1) pro fibus dp interface (x2) ? mpi ? dp master ? dp slave 1 ? not configured ? dp master ? dp slave 1 1 simultaneous operation of the dp slave on both interfaces is e xcluded properties the profibus dp interface is m ainly used to connect distributed i/o. profibus dp allows you to create lar ge subnets, for example. the profibus dp interface can be set for operation in master or slave mode, and supports transmission rates up to 12 mbps. the cpu broadcasts its bus param eters (transmission rate, for e xample) via the profibus dp interfac e when master mode is set. a pg, for exampl e, can thus receive the correct parameters and automatica lly connect to a profibus subn et. in your configuration you can specify to disable bus parameter broadcasting.
communication 3.1 interfaces cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-3 note (for dp interface in slave mode only) when you disable the commissi oning / debug mode / routing check box in the dp interface properties dialog in step 7, all user-specific transmission rat e settings will be ignored, and the transmission rate of the mast er is automatically set instea d. this disables the routing function at this interface. devices capable of profibus dp communication ? pg/pc ? op/tp ? dp slaves ? dp masters ? actuators/sensors ? S7-300/s7-400 with profibus dp interface reference further information on profibus: http://www.profibus.com 3.1.3 profinet (pn) availability cpus with a ptp name suffix ar e equipped with a ptp x2 interf ace. x2. connecting to industrial ethernet you can use the integrated prof inet interface of the cpu to est ablish a connection to industrial ethernet. the integrated profinet interfac e of the cpu can be configured via mpi or profinet. requirements ? cpus with fw 2.3.0 or higher (for example cpu 315-2 pn/dp) ? step 7 v5.3 + servicepack 1 or higher
communication 3.1 interfaces cpu 31xc and cpu 31x, technical data 3-4 manual, edition 08/2004, a5e00105475-05 devices capable of profinet (pn) communication ? profinet io components (for example, interface module im 151-3 pn in an et 200s) ? S7-300 / s7-400 with profinet inte rface (for exa mple, cpu 317-2 pn/dp or cp 343-1 pn) ? active network components (a switch, for example) ? pg/pc with network card properties of profinet interface x2 properties ieee standard 802.3 connector design rj45 transmission speed max. 100 mbps media twisted pair cat5 (100base-tx) note networking profinet components the use of switches, rather than hubs, for networking profinet components brings about a substantial improvement in decoupling bus traffic, and improv es runtime performance under higher bus load. profinet cb a with cyclic profinet interc onnections requires the use of switches in order to maintain compliance with performanc e specifications. full duplex mode at 100 mbps is mandatory fo r cyclic profinet interconnecti ons. profinet io also requires the use of switches and 100 mbps full duplex mode. reference ? for information on how to configur e the integrated profinet int erface of the cpu, refer to the S7-300, cpu 31xc and cpu 31x installation operating manual. ? for details on profinet, refer to the profinet system description ? for detailed information on et hernet networks, network configur ation and network components refer to the simatic net manual: twisted pa ir and fiber optic networks , available under article id 8763736 on the internet url http://www.siemens.com/automation/service&support ? tutorial: commissioning compon ent-based automation systems , article id 14142554 ? further information on profinet: http://www.profibus.com see also profinet io system (page 3-19)
communication 3.1 interfaces cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-5 3.1.4 point to point (ptp) availability cpus with a ptp name suffix ar e equipped with a ptp x2 interf ace. properties using the ptp interface of your cpu, you can connect external d evices with serial interface. you can operate such a system at transmission rates up to 19.2 kbps in full duplex mode (rs 422), and up to 38.4 kbps in half duplex mode (rs 485). transmission rate ? half duplex: 38.4 kbps ? full duplex: 19.2 kbps drivers ptp communication drivers installed in those cpus: ? ascii drivers ? 3964(r) protocol ? rk 512 (cpu 314c-2 ptp only) devices capable of ptp communication devices equipped with a serial po rt, for example, barcode reade rs, printers, etc. reference cpu 31xc: technological functions manual
communication 3.2 communication services cpu 31xc and cpu 31x, technical data 3-6 manual, edition 08/2004, a5e00105475-05 3.2 communication services 3.2.1 overview of communication services selecting the communication service you need to decide on a communication service, based on functio nality requirements. your choice of communication servic e will have no effect on: ? the functionality available, ? whether an s7 connection is required or not, and ? the time of connecting. the user interface can vary c onsiderably (sfc, sfb, ...), and i s also determined by the hardware used (sima tic cpu, pc, ...). overview of communication services the table below provides an over view of communication services offered by the cpus. table 3-2 communication services of the cpus communication service function ality time at w hich the s7 connection is established ... via mpi via dp via ptp via pn pg communication commissioning, test, diagnostics from the pg, starting when the service is being used x x C x op communication monitor and m odify via op at power on x x C x s7 basic communication data exch ange is programmed at the block s (sfc parameters) x C C C s7 communication data exchange in server and client mode: configuration of communication required. via active partner at power on. only in server mode only in server mode C x global data communication cyclic data exchange (for example, flag bits) does not require an s7 connection x C C C routing pg functions (only for cpus with dp or pn interface) for example testing, diagnostics on other networks also from the pg, starting when the service is being used x x C x ptp communication data exchange via serial interface does not require an s7 connection C C x C snmp (simple network management protocol) standard protocol for network diagnostics and configuration does not require an s7 connection C C C x open communication by means of tcp/ip data exchange via industrial ethernet with tcp/ip protoco l (by means of loadable fbs) does not require an s7 connection, is handled in the user program by means of loadable fbs C C C x
communication 3.2 communication services cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-7 see also distribution and availability o f s7 connection resources (page 3-29) connection resources fo r routing (page 3-31) 3.2.2 pg communication properties pg communication is used to exch ange data between engineering s tations (pg, pc, for example) and simatic modules which are capable of communication . this service is available for mpi, profibus and i ndustrial ethernet subnets. tr ansition between subnets is also supported. pg communication provides the fu nctions needed to download / up load programs and configuration data, to run tests and to evaluate diagnostic inf ormation. these functions are integrated in the operating system of simatic s7 modules. a cpu can maintain several simul taneous online connections to o ne or multiple pgs. 3.2.3 op communication properties op communication is used to exch ange data between operator stat ions (op, tp, for example) and simatic modules which are capable of communication . this service is available for mpi, profibus and industrial ethernet subnets. op communication provides functions you require for monitoring and modifying. these functions are integrated in t he operating system of simatic s7 modules. a cpu can maintain several simultaneous connections to one or several ops . 3.2.4 data exchanged by means of s7 basic communication properties s7-based communication is used to exchange data between s7 cpus and the communication-capable simatic modules within an s7 station (ack nowledged data exchange). data are exchanged ac ross non-configured s7 connecti ons. the service is available via mpi subnet, or within the station to function mod ules (fm). s7-based communication provides the functions you require for d ata exchange. these functions are integrated into t he cpu operating system. the use r can utilize this service by means of "system function " (sfc) user interface.
communication 3.2 communication services cpu 31xc and cpu 31x, technical data 3-8 manual, edition 08/2004, a5e00105475-05 reference ? details on sfcs are found in the instruction list , for more details refer to the step 7 online help or to the system and standard functions reference manual. ? for further information on communication, refer to the communication with simatic manual. 3.2.5 s7 communication properties a cpu can always oper ate in server or client mode in s7 communi cation: we distinguish between ? communication with unilateral conf iguration (for put/get only) ? communication with bila teral configuration (for usend, urcv, bs end, brcv, put, get) however, the functiona lity depends on the cp u. a cp is therefor e required in certain situations. table 3-3 client and server in s7 communication, using connecti ons with unilate ral / bilateral configuration cpu use in server mode for connections with unilateral configuration use in server mode for connections with bilateral configuration use as client 31xc >= v1.0.0 always possible at the mpi/dp interface, without programming the user interface only possible with cp and loadable fbs. only possible with cp and loadable fbs. 31x >= v2.0.0 always possible at the mpi/dp interface, without programming the user interface only possible with cp and loadable fbs. only possible with cp and loadable fbs. 31x >= v2.2.0 always possible at the mpi/dp interface, without programming the user interface ? possible at pn interface with loadable fbs, or ? with cp and loadable fbs. ? possible at pn interface with loadable fbs, or ? with cp and loadable fbs. the user interface is implemented using standard function modul es (fbs) from the standard library of step 7, under communication blocks. reference for further information on communication, refer to the communication with simatic manual.
communication 3.2 communication services cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-9 3.2.6 global data commu nication (mpi only) properties global data communication is used for cyclic exchange of global data via mpi subnets (for example, i, q, m) between simatic s7 cpus (data exchange withou t acknowledgement). one cpu broadcasts its data to all other dp cpus on the mpi sub net. this function is integrated in the cp u operating system. reduction ratio the reduction ratio specifies t he cyclic intervals for gd commu nication. you can set the reduction ratio when you confi gure global data communication in step 7. for example, if you set a reduction ratio of 7, g lobal data are transferred onl y with every 7th cycle. this reduces cpu load. send and receive conditions conditions which should be satisfied for gd communication: ? for the transmitte r of a gd packet: reduction ratio transmitter x cycle time transmitter 60 ms ? for the receiver of a gd packet: reduction ratio receiver x cycle time receiver < reduction ratio transmitter x cycle time transmitter a gd packet may be lost if you do not adhere to these condition s. the reasons being: ? the performance of the "smalle st" cpu in the gd circuit ? asynchronous transmitting / recei ving of global data at the sta tions when setting in step 7: transm it after each cpu cycle, and th e cpu has a short scan cycle time (< 60 ms), the operatin g system might overwrite a gd packet of the cpu before it is transmitted. the loss of global data is indicated in the sta tus box of a gd circuit, if you set this function in your step 7 configuration.
communication 3.2 communication services cpu 31xc and cpu 31x, technical data 3-10 manual, edition 08/2004, a5e00105475-05 gd resources of the cpus table 3-4 gd resources of the cpus parameters cpu 31xc, 312, 314 cpu 315-2 dp, 315-2 pn/dp, 317 number of gd circuits per cpu max. 4 max. 8 gd packets transmitted per g d circuit max. 1 max. 1 gd packets transmitted by all gd circuits max. 4 max. 8 gd packets received per gd circuit max. 1 max. 1 gd packets received by all gd circuits max. 4 max. 8 data length per gd packet ma x. 22 bytes max. 22 bytes consistency max. 22 bytes max. 22 bytes min. reduction ratio (default) 1 (8) 1 (8) 3.2.7 routing properties step 7 v5.1 + sp4 or higher allo ws you to access your s7 statio ns on all subnets with your pg/pc, for example, to ? download user programs ? download a hardware configuration, or ? perform debugging and diagnostic functions. note when the cpu is used as intelli gent slave, the routing function is only available when the dp interface is set active. in s tep 7, set the test, commission routing check box on the properties dialog of the dp i nterface. for detailed informa tion, refer to the programming with step 7 manual, or directly to the step 7 online help
communication 3.2 communication services cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-11 routing network nodes: mpi - dp gateways between subnets are rout ed in a simatic station that i s equipped with interfaces to the respective subnets. the fi gure below shows cpu 1 (dp mas ter) acting as router for subnets 1 and 2. subnet 1 (e.g. mpi) subnet 2 (e.g. profibus dp) pg S7-300 cpu (dp master) S7-300 cpu (dp slave) the figure below shows the acce ss to an etherne t subnet. cpu 1 (315-2 dp, for example) is the router for subnet 1 and 2; cpu 2 is the router for subnet 2 and 3.
communication 3.2 communication services cpu 31xc and cpu 31x, technical data 3-12 manual, edition 08/2004, a5e00105475-05 routing network nodes: mpi C dp - ethernet cpu 1 (e.g. 315-2 dp) pn subnet 3 (profinet) pn pg subnet 2 (profibus) dp (master) mpi subnet 1 (mpi) mpi/dp (active slave) cpu 2 (317-2 pn/dp) cpu 3 (317-2 pn/dp) number of routed connections the cpus with dp interface provi de a different number of connec tions for the routing function: table 3-5 number of routing connections for dp cpus cpu as of firmware version numbe r of connections for routing 31xc, cpu 31x 2.0.0 max. 4 317-2 dp 2.1.0 max. 8 31x-2 pn/dp 2.2.0 interface x1 configured as: ? mpi: max. 10 ? dp master max. 24 ? dp slave (active): max. 14 interface x2 configured as: ? profinet max. 24
communication 3.2 communication services cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-13 requirements ? the station modules are "capabl e of routing" (cpus or cps). ? the network configuration doe s not exceed project limits. ? the modules have loaded the conf iguration data containing the l atest "knowledge" of the entire network configuration of the project. reason: all modules participating in the network transition mus t receive the routing information defining the paths to other subnets. ? in your network configuration, t he pg/pc you want to use to est ablish a connection via network node must be assigned to t he network it is physically c onnected to. ? the cpu must set to master mode, or ? when set to operate in slave m ode, the test, commissioning, rou ting functionality must be enabled by setting the check box in step 7, in the dp interface for dp slave properties dialog box.
communication 3.2 communication services cpu 31xc and cpu 31x, technical data 3-14 manual, edition 08/2004, a5e00105475-05 routing: example of a teleservice application the figure below shows the exampl e of an application for remote maintenance of an s7 station using a pg. the connec tion to other subnets is here established via modem connection. the lower section of the figure shows how to configure this in step 7. dp master subnet 1 (e.g. mpi) subnet 2 (e.g. profibus dp) modem modem real installation subnet 1 (e.g. mpi) subnet 2 (e.g. profibus dp) configuration in step 7 dp slave teleservice adapter e.g. 31xc-2dp e.g. 31xc-2dp dp master e.g. cpu 31xc-2 dp dp slave e.g. cpu 31xc-2 dp pg pg
communication 3.2 communication services cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-15 reference ? on configuring in step 7 is found in the configuring hardware and connections in step 7 manual ? of a basic nature is contained in the communication with simatic manual. ? on the teleservice adapter can be found on the internet url: http://www.ad.siemens.de/suppor t. in the manual search section, you can enter the search term a5e00078070 to download the documentation. ? on sfcs are found in the instruction list , for more details refer to the step 7 online help or to the system and standard functions reference manual. ? on communication are found in the communication with simatic manual. 3.2.8 ptp communication properties ptp communication enables you to e xchange data via serial port. ptp communication can be used to interconnect automation devices, computers or communica tion-capable systems of external suppliers. the function also allows adaptation to the protocol of the communication partner. reference further information ? on sfcs are found in the instruction list . for detailed information, refer to the step 7 online help , or to the system and standard functions reference manual. ? on communication are found in the communication with simatic manual.
communication 3.2 communication services cpu 31xc and cpu 31x, technical data 3-16 manual, edition 08/2004, a5e00105475-05 3.2.9 data consistency properties a data area is considered consistent, if the operating system c an read/write access the data area in a continuous block. dat a exchanged collectively between the stations should belong together and originate from a si ngle processing cycle, that is, be consistent. if the user program contains a programmed communication function, for examp le, access to shared data with x-send/ x-rcv, access to that data area can be coordi nated by means of the "busy" parameter itself. with put/get functions for s7 communication functions, s uch as put/get or write / read via op communication, which do not require a block in the user program on the cpu (op erating in server mode), allowances must be made in the program for the extent of the da ta consistency. the put/get functions for s7 communi cation, or for reading/writing variables via op communication, are exe cuted at the cpu's sc an cycle checkpoint. in order to ensure a defined process interrupt react ion time, the communication vari ables are copied in consistent blocks with a maximum length o f 64 bytes (cpu 317: 160 bytes) t o / from work memory at the scan cycle checkpoint of the operating system. data consist ency is not guaranteed for larger data areas. note where defined data consistency is required, the length of commu nication variables in the cpu's user program may not exc eed 64 bytes (cpu 317: 160 bytes. ) 3.2.10 communication via prof inet (only cpu 31x-2 pn/dp) what is profinet?? within the framework of totally in tegrated automation (tia), pr ofinet represents a consequent enhancement of: ? profibus dp, the proven field bus, and ? industrial ethernet, the communi cation bus at cell level. experience gained from both syst ems was and is being integrated into profinet. profinet is an ethernet-based autom ation standard of profibus i nternational (previously profibus users organi zation e.v.), and defines a mu lti-vendor communication, automation, and engineering model.
communication 3.2 communication services cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-17 objectives in profinet the objectives in profinet are: ? an open ethernet standard for aut omation based on industrial et hernet industrial ethernet and standard ethernet components can be use d together, however, industrial ethernet devices are more reliable, and are therefor e more suitable for industrial environments (temperature, immunity to noise etc.) ? use of tcp/ip and it standards ? automation with real-time ethernet ? total integration of field bus systems implementation of profinet by us we have integrated profinet as follows: ? we have chosen profinet io for integrated communication between field devices. ? we integrated communication between plcs of distributed systems with profinet cba (component-based automation.) ? installation engineering and net work components are available i n simatic net. ? for remote maintenance and netwo rk diagnostics, we used the pro ven it standards from the office world (for example, snmp = simple network management protocol for network configuration and diagnostics). documentation of profibus international on the internet on the internet at "www.profibus.com" of profibus international (previously profibus user organization, puo) you can find numerous articles relating to profinet. for further information, refer to the internet url "www.siemens .com\profinet\". what is profinet io? within the framework of profinet, profinet io is a communicatio n concept for the implementation of modular, distributed applications. profinet io allows you to creat e automation solutions, which ar e familiar to you from profibus. that is, you have the same app lication view in step 7, regardle ss of whether you configure profinet or profibus devices. what is profinet cba (component based automation)? within the framework of profinet , profinet cba is an automation concept for the implementation of applications with distributed intelligence. profinet cba lets you create dist ributed automation solutions, based on default components and partial solutions. component-based automation allows you to use complete technolog ical modules as standardized components in complex systems. the components are also created in an engineering tool which ma y differ from vendor to vendor. components of simatic dev ices are created, for example, with step 7.
communication 3.2 communication services cpu 31xc and cpu 31x, technical data 3-18 manual, edition 08/2004, a5e00105475-05 extent of profinet cba and profinet io profinet io and cba r epresent two different v iews of automation devices on industrial ethernet. 352),1(7 &rpsrqhqw9lhz 352),1(7&%$ ,2'dwd9lhz 352),1(7,2 'lvwulexwhg,qwhooljhqfh 3odqwzlgh(qjlqhhulqj 'lvwulexwhg,2 1rupdo,29lhzlq67(3 3&' 352),1(7&rpsrqhqw'hvfulswlrq *6' *hqhulf6wdwlrq'hvfulswlrq 2qh&deoh,76wdqgdugv6wdqgdug$ssolfdwlrqv 3urwrfrov1rq57&rqwuroohu figure 3-1 extent of profinet i o and component-based automation component-based automation organi zes the system structure based on the various functions. these functions ar e configured and programmed. profinet io provides you with a view of the system that is very similar to the view obtained in profibus. you conti nue to configure and program the individual automation devices. further information for further information on prof inet io and profinet cba, refer to the profinet system description . differences between profibus dp and profinet io and their common features are described in the from profibus dp to profinet io programming manual. for detailed information on pro finet cba, refer to the simatic imap and component- based automation documentation.
communication 3.2 communication services cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-19 3.2.10.1 profinet io system extended functions of profinet io the following graphic shows the new functions of profinet io &38 [ 31'3 (7 '36/$9( 5rxwhu 6zlwfk ,2 &rqwuroohu '3 0dvwhu (7 6 ,2 'hylfh (7 6 ,2 'hylfh &38 [ 31'3 ,2 &rqwuroohu '3 0dvwhu 6zlwfk (7 '36/$9( 3* 6zlwfk ,( ,(3%/lqn 3% &rpsdq\1hwzrun ,qgxvwuldo(wkhuqhw 352),%86 2 3 4 5 6 1 the graphic displays you can se e the connection path in the gra phic the connection of company network and field level from pcs in your company netwo rk, you can acce ss devices at the field level example: ? pc switch 1 router switch 2 cpu 31x-2 pn/dp (1). the connection between the automation system and field level you can, of course, also access other areas in industrial ether net from a pg at the field level. example: ? pg switch 3 switch 2 to an io device of the et 200s (2). the io controller of the cpu 31x-2 pn/dp (1) controls devices on industrial ethernet and on profibus directly at this point, you see the ex tended io feature between the io c ontroller and io device(s) on industrial ethernet: ? the cpu 31x-2 pn/dp (1) is t he io controller for one of the et 200s (2) io devices. ? the cpu 31x-2 pn/dp (1) is also the io controller for the et 20 0 (dp slave) (5) via the ie/pb link (6). a cpu can be both io controller and dp master here, you can see that a cpu c an be both io controller for an i o device as well as dp master for a dp slave: ? the cpu 31x-2 pn/dp (3) is the io controller for the other et 2 00s (2) io device. cpu 31x-2 pn/dp (3) switch 3 switch 2 et 200s (2) ? the cpu 31x-2 pn/dp (3) is the dp master for a dp slave (4). th e dp slave (4) is assigned locally to the cpu (3) and is not visible on industria l ethernet.
communication 3.2 communication services cpu 31xc and cpu 31x, technical data 3-20 manual, edition 08/2004, a5e00105475-05 requirements ? cpus as of firmware 2.3.0 (f or example cpu 315-2 pn/dp) ? step 7, as of version 5.3 + service pack 1 reference you will find information on the topic of profinet in the follo wing sources: ? in the system description profinet ? in the from profibus dp to profinet io programming manual. this manual also lists the new profinet blocks and system status lists. see also profinet (pn) (page 3-3) 3.2.10.2 blocks in profinet io chapter content this chapter explains the following: ? which blocks are intended for profinet ? which blocks are intended for profibus dp ? which blocks are intended for both profinet io and profibus dp compatibility of the new blocks for profinet io, it was necessary to create some new blocks, am ong other things, because larger configurations are now possible with profinet. y ou can also use these new blocks with profibus.
communication 3.2 communication services cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-21 comparison of the system and standard functions of profinet io and profibus dp for cpus with an integrated pro finet interface, the table below provides you with an overview of: ? system and standard functions for simatic that you may need to replace when converting from profibus dp to profinet io. ? new system and standard functions table 3-6 new system standard f unctions of profinet io and prof ibus dp and those that must be replaced blocks profinet io profibus dp sfc13 (read diagnostic data of a dp slave) no substitute: ? event-related: sfb 54 ? state-related: sfb 52 yes sfc58/59 (write/read data record in i/o) no (replacement: sfb53/52) yes (but should a lready have been replaced by sfb53/52 in dpv1) sfb52/53 (read/write data record) yes yes sfb54 (evaluate alarm) yes yes sfc102 (read predefined parameters) no (replacement: sfb81) yes new: sfb81 (read predefined parameters) yes yes sfc5 (query start address of a module) no (replacement: sfc70) yes new: sfc70 (query start address of a module) yes yes sfc49 (query the slot belonging to a logical address) no (replacement: sfc71) yes new: sfc71 (query the slot belonging to a logical address) yes yes
communication 3.2 communication services cpu 31xc and cpu 31x, technical data 3-22 manual, edition 08/2004, a5e00105475-05 the following table provides you with an overview of the system and standard functions for simatic, whose functionality mus t be implemented by other funct ions when converting from profibus dp to profinet io. table 3-7 system and standard functions in profibus dp that mus t be implemented with different functions in profinet io blocks profinet io profibus dp sfc55 (write dynamic parameters) no (implement with sfb53) yes sfc56 (write predefined parameters) no (implement with sfb81 and sfb53) yes sfc57 (assign parameters to module) no (implement with sfb81 and sfb53) yes you cannot use the following si matic system and standard functi ons with profinet io: ? sfc7 (trigger hardware interrupt on dp master) ? sfc11 (synchronize groups of dp slaves) ? sfc12 (deactivate and activate dp slaves) ? sfc72 (read data from a communication partner within local s7 s tation) ? sfc73 (write data to a communica tion partner within local s7 st ation) ? sfc74 (abort an existing connection to a communication partner within local s7 station) comparison of the organization blocks of profinet io and profib us dp here, there are changes in obs 83 and 86 as shown in the table below. table 3-8 obs in profinet io and profibus dp blocks profinet io profibus dp ob83 (removing and inserting modules and submodules during operation) also possible with an S7-300, new error information with an S7-300 not possible removing and inserting during operation is reported by slaves added using a gsd file by means of a diagnostic interrupt; in other words ob82. with s7 slaves, ob86 is called due to the station failure. ob86 (rack failure) new error information unchanged detailed information for detailed descriptions of the individual blocks, refer to th e manual system software for S7-300/400 system and standard functions .
communication 3.2 communication services cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-23 3.2.10.3 system status lists (ssls) in profinet io chapter content this chapter explains the following: ? which ssls are intended for profinet ? which ssls are intended for profibus dp ? which ssls are intended for both profinet io and profibus dp compatibility of the new ssls for profinet io, it was necessary to create some new ssls, amon g other things, because larger configurations are now possible with profinet. you can also use these new ssls with profibus. you can continue to use a known profibus ssl that is also suppo rted by profinet. if you use an ssl in profinet that does not support profinet, an e rror code is returned in ret_val (8083: index wrong or not permitted). comparison of the system status lists of profinet and profibus table 3-9 comparison of the syst em status lists of profinet and profibus ssl-id profinet io profibus dp applicability w#16#0591 yes (parameter adr1 changed) yes module status informati on for the interfaces of a module/submodule w#16#0a91 yes (parameter adr1 changed) yes status information of a ll subsystems and master systems (S7-300 with out cpu 318-2 dp) w#16#0c91 yes (parameter adr 1/adr2 and expected/actual type id changed) yes module status information of a module/submodule in a central configuration or atta ched to an integrated dp or pn interface module using the logical address of the module. w#16#4c91 yes (parameter adr1 changed) yes not with S7-300 module status information of a module/submodule attached to an external dp or pn interface module using the start address w#16#0d91 yes (parameter adr1 changed) yes module status informa tion of all modules in the specified rack/station new: w#16#0696 yes yes module status informa tion of all submodules of a module using the logical ad dress of the module, not possible for submodule 0 new: w#16#0c96 yes yes module status informa tion of a submodule using the logical address of this submodule w#16#xy92 no (replacement: ssl-id w#16#0x94) yes rack/stations s tatus information replace this ssl with the ssl with the id w#16#xy94 in profibus dp as well. new: w#16#0x94 yes yes rack/station status information
communication 3.2 communication services cpu 31xc and cpu 31x, technical data 3-24 manual, edition 08/2004, a5e00105475-05 detailed information for detailed descriptions of the individual system status lists , refer to the manual system software for S7-300/400 system and standard functions . 3.2.10.4 open communication via industrial ethernet requirements ? cpu 31x-2 pn/dp with firmware version 2.2.0 or higher: ? step 7 v5.3 + servicepack 1 or higher functionality cpus with firmware v2.3.0 or hig her and integrated profinet int erface support the open communication functionality via industrial ethernet (in short: open ie communication ) open ie communication is always handled directly via tcp/ip. how to use open ie communication to be able to exchange data with other tcp/ip-compatible commun ication partners by means of the user program, step 7 provides four fbs and one udt for the configuration of your connection: ? fb 63 "tsend", for sending data ? fb 64 "trcv", for receiving data ? fb 65 "tcon", for connecting ? fb 66 "tdiscon", for disconnecting ? udt 65 "tcon_par" contains the da ta structure for the configura tion of your connection. data block for the configuration of the connection tcp/ip communication is connecti on-oriented. data can only be t ransferred when a connection to the communication partner is established. the cpu supports multiple parallel connections to a communication partner. to configure your connection, y ou need to create a db that cont ains the data structure of udt 65 "tcon_par." this data stru cture contains all parameters you need to establish the connection. you need to create su ch a data structure for each c onnection, and you can also organize it in a global db (for e xample, array[1..8] "t_addr_in fo".) connection parameter connect of fb 65 "tcon" reports the addres s of the corresponding connection description to the user program (for e xample, p#dba.dbxb.c byte 64).
communication 3.2 communication services cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-25 establishing a connection for communication fb 65 "tcon" establishes communi cation between the cpu and a co mmunication partner. you can establish up to eight c onnections. the cpu automaticall y monitors and holds the active connection. communication partner a must initiate the connection. when the connection of communication par tner a is active, it transmits a request to co nnect to communication partner b. communication partner b waits until it receives the request for a passive connection. in your connection configurati on, you define which communicatio n partner activates the connection, and which communication partners respond to the req uest with a passive connection. both communication partners must have established their connect ion in order to be able to exchange data. data exchange bidirectional data exchange is enabled after you established co mmunication, that is, data can be transmitted and received in parallel. fbs available for data exchange: name of the fb description fb 63 "tsend" transmit data fb 64 "trcv" receive data you can transmit and receive up to 1460 bytes of user data. disconnecting fb 66 "tdiscon" disconnects the cpu from a communication partne r. communication interruptions events causing interruptions of communication: ? you program the cancellation of c onnections at fb 66 "tdiscon." ? the cpu goes from run to stop. ? at power off / power on reference for detailed information on the blocks described earlier, refer to the step 7 online help.
communication 3.3 s7 connections cpu 31xc and cpu 31x, technical data 3-26 manual, edition 08/2004, a5e00105475-05 3.2.10.5 snmp communication service availability the snmp communication service i s available for cpus with integ rated profinet interface and firmware 2.3.0 or higher. properties snmp (simple network management p rotocol) is a standard protoco l for tcp/ip networks. reference for further information on the sn mp communication service and d iagnostics with snmp, refer to the profinet system description. 3.3 s7 connections 3.3.1 s7 connection as communication path an s7 connection is established when s7 modules communicate wit h one another. this s7 connection is the communication path. note global data communication, ptp communication, communication wit h tcp/ip and snmp do not require s7 connections. every communication link require s s7 connection resources on th e cpu for the entire duration of this connection. thus, every s7 cpu provides a s pecific number of s7 connection resources. these are used by various communication se rvices (pg/op communication, s7 communication or s7 basic communication).
communication 3.3 s7 connections cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-27 connection points an s7 connection between modules with communication capability is established between connection points. the s7 connecti on always has two connection points: the active and passive connection points: ? the active connection point is assigned to the module that esta blishes the s7 connection. ? the passive connection point is assigned to the module that acc epts the s7 connection. any module that is capable of communication can thus act as an s7 connection point. at the connection point, the established communication link always use s one s7 connection of the module concerned. transition point if you use the routing functiona lity, the s7 con nection between two modules capable of communication is established across a number of subnets. these subnets are interconnected via a network transition. the module that implem ents this network transition is known as a router. the router is thus the point through whic h an s7 connection passes. any cpu with a dp or pn interf ace can be the router for an s7 c onnection. you can establish a certain maximum numbe r of routing connections. this does not limit the data volume of the s7 connections. see also connection resources fo r routing (page 3-31) 3.3.2 assignment of s7 connections there are several ways to alloca te s7 connections on a communic ation-capable module: ? reservation during configuration ? allocating connections via programming ? allocating connections during commissioning, testing and diagno stics routines ? allocating connection resources to ocms services reservation during configuration one connection resource each is automatically reserved on the c pu for pg and op communication. whenever you need more connection resources (for example, when connecting several ops), configur e this increase in the cpu pro perties dialog box in step 7. connections must also be configured (using netpro) for the use of s7 communication. for this purpose, connection resources have to be available, which are not allocated to pg/op or other connections. the requi red s7 connections are then perm anently allocated for s7 communication when the config uration is uploaded to the cpu.
communication 3.3 s7 connections cpu 31xc and cpu 31x, technical data 3-28 manual, edition 08/2004, a5e00105475-05 assigning connections in the program in s7 basic communication, and in open industrial ethernet comm unication with tcp/ip, the user program establishes the co nnection. the cpu operating syst em initiates the connection. s7 basic communicati on uses the corresponding s7 co nnections. the open ie communication does not use any s7 connections. the maximum n umber of eight connections also applies to this type of communication. using connections for commissioning, testing and diagnostics an active online function on t he engineering station (pg/pc wit h step 7) occupies s7 connections for pg communication: ? an s7 connection resource for pg communication which was reserv ed in your cpu hardware configuration is assigne d to the engineering station, that is, it only needs to be allocated. ? if all reserved s7 connection reso urces for pg communication ar e allocated, the operating system automatically a ssigns a free s7 connection res ource which has not yet been reserved. if no more connecti on resources are available, t he engineering station cannot go online to the cpu. allocating connection resources to ocms services an online function of the ocm station (op/tp/... with protool ) allocates s7 connection resources for op communication: ? an s7 connection resource for op communication you have reserve d in your cpu hardware configuration is theref ore assigned to the ocm station engineering station, that is, it only needs to be allocated. ? if all reserved s7 connection reso urces for op communication ar e allocated, the operating system automatically a ssigns a free s7 connection res ource which has not yet been reserved. if no more connecti on resources are available, t he ocm station cannot go online to the cpu. time sequence for allocation of s7 connection resources when you program your project in step 7, the system generates p arameter assignment blocks which are read by the modul es in the startup phase. this allows the module's operating system to reserve or allo cate the relevant s7 connect ion resources. that is, for instance, ops cannot access a re served s7 connection resource f or pg communication. the cpu's s7 connection resource s which were not reserved can b e used freely. these s7 connection resources are allo cated in the order they are req uested. example if there is only one fr ee s7 connection left on the cpu, you ca n still connect a pg to the bus. the pg can then communicate with the cpu. the s7 connection is only used, however, when the pg is communicating wi th the cpu. if you connect an op to the bus while the pg is not communicating, the op can establish a connection to the cpu. since an op maintains its communication link at all times, in contrast to the pg, you cannot subsequently establish another connection via the pg. see also open communication via industrial ethernet (page 3-24)
communication 3.3 s7 connections cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-29 3.3.3 distribution and availabi lity of s7 connection resources distribution of connection resources table 3-10 distribution of connections communication service distribution pg communication op communication s7 basic communication in order to avoid allocation of connection resources being depe ndent only on the chronological sequence in which various communication servi ces are requested, connection resources can be reserved for these servi ces. for pg and op communication respectively, at least one connecti on resource is reserved by default. in the table below, and in the technical data of the cpus, you can find the configurable s7 connection res ources and the default configurat ion for each cpu. you "redistribute connecti on resources by setting the rel evant cpu parameters in step 7. s7 communication other communication r esources (e.g. via cp 343-1, with a data length of > 240 bytes) here you allocate connection r esources which ar e still availabl e and not reserved for a specific service (pg/op communication, s7-based communication). routing pg functions (only for cpus with dp/pn interface) the cpus provide a certain number of connection re sources for r outing. these connections are available in addition to the connection r esources. the subsection below shows the number of connection resources. global data communication point-to-point c ommunication these communication services do not use connection resources. open communication by means of tcp/ip this communication servic e does not occupy any connection resources. eight connections are available in parallel. snmp this communication service does not occupy any connection resources.
communication 3.3 s7 connections cpu 31xc and cpu 31x, technical data 3-30 manual, edition 08/2004, a5e00105475-05 availability of connection resources table 3-11 availability of connection resources reserved for cpu total number connection resources pg communication op communication s7 basic communication free s7 connections 312c 6 1 to 5, default 1 1 to 5 , default 1 0 to 2, default 2 313c 313c-2 ptp 313c-2 dp 8 1 to 7, default 1 1 to 7, default 1 0 to 4, default 4 314c-2 ptp 314c-2 dp 12 1 to 11, default 1 1 to 11, default 1 0 to 8, default 8 312 6 1 to 5, default 1 1 to 5 , default 1 0 to 2, default 2 314 12 1 to 11, default 1 1 to 11, default 1 0 to 8, default 8 315-2 dp 315-2 pn/dp 16 1 to 15, default 1 1 to 15, default 1 0 to 12, default 12 317-2 dp 317-2 pn/dp 32 1 to 31, default 1 1 to 31, default 1 0 to 30, default 0 displays all non- reserved s7 connection resources as free connection resources. note when using a cpu 315-2 pn/dp, you can configure up to 14 connec tion resources for s7 communication in netpro: thes e connections are then reserved . when using a cpu 317-2 pn/dp, you can config ure up to 16 connection resource s for s7 communication in netpro.
communication 3.3 s7 connections cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-31 3.3.4 connection resources for routing number of connection resources for routing the cpus with dp interface provi de a different number of connec tion resources for the routing function: table 3-12 number of routing conn ection resources (for dp/pn cp us) cpu as of firmware version numbe r of connections for routing 31xc, cpu 31x 2.0.0 max. 4 317-2 dp 2.1.0 max. 8 31x-2 pn/dp 2.2.0 interface x1 configured as: ? mpi: max. 10 ? dp master max. 24 ? dp slave (active): max. 14 interface x2 configured as: ? profinet: max. 24 example of a cpu 314c-2 dp the cpu 314c-2 dp provides 1 2 connection resources: ? reserve two connection resources for pg communication. ? reserve three connection resources for op communication. ? reserve one connection resource for s7-based communication. this leaves six connection resources available for other commun ication service, e.g. s7 communication, op communication, etc. example for a cpu 317-2 pn/dp the cpu 317-2 pn/dp provides 32 connection resources: ? reserve four connection resources for pg communication. ? reserve six connection resour ces for op communication. ? reserve two connection resources for s7-based communication. ? in netpro you configure eight s7 connection resources for s7 co mmunication via the integrated profinet interface this leaves 12 s7 connections available for any communication s ervice, e.g. s7 communication, op communication, etc. however, only a maximu m of 16 connection resources can be configured for s7 communication at the integra ted pn interface in netpro. in addition, 24 routing connections are available that do not a ffect the s7 connection resources mentioned above.
communication 3.4 dpv1 cpu 31xc and cpu 31x, technical data 3-32 manual, edition 08/2004, a5e00105475-05 3.4 dpv1 new automation and process engin eering tasks require the range of functions performed by the existing dp protocol to be extended. in addition to cyclica l communication functions, acyclical access to non-s7 field devices is another important r equirement of our customers, and was implemented in the standard en 501 70. in the past, acyc lical access was only possible with s7 slaves. the d istributed i/o s tandard en 50170 has been further developed. all the changes concerning new d pv1 functions are included in i ec 61158/ en 50170, volume 2, profibus. definition dpv1 the term dpv1 is defined as a func tional extension of the acycl ical services (to include new interrupts, for example) pro vided by the dp protocol. availability all cpus with dp interface(s) an d serving as dp masters feature the enhanced dpv1 functionality. note if you want to use the cpu as an intelligent slave, remember th at it does not have dpv1 functionality. requirement for using the dpv1 functionality with dp slaves for dpv1 slaves from other vendors, you w ill need a gsd file co nforming to en 50170, revision 3 or later. extended functions of dpv1 ? use of any dpv1 slaves from ext ernal vendors (in addition to th e existing dpv0 and s7 slaves, of course). ? selective handling of dpv1-specific interrupt events by new int errupt blocks. ? reading/writing sfbs that confor m to standards to the data reco rd (although this can only be used for centralized modules). ? user-friendly sfb for reading diagnostics.
communication 3.4 dpv1 cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 3-33 interrupt blocks with dpv1 functionality table 3-13 interrupt block s with dpv1 functionality ob functionality ob 40 process interrupt ob 55 status interrupt ob 56 update interrupt ob 57 vendor-specific interrupt ob 82 diagnostic interrupt note you can now also use organizational blocks ob40 and ob82 for dp v1 interrupts. system blocks with dpv1 functionality table 3-14 system function b locks with dpv1 functionality sfb functionality sfb 52 read data record from d p slave or centralized module sfb 53 write data record to dp slave or centralized module sfb 54 read additional alarm in formation from a dp slave or a c entralized module in the relevant ob. sfb 75 set any interrupts for intelligent slaves note you can also use sfb 52 to sfb 54 for centralized i/o modules. sfbs 52 to 54 can also be used for pn io. reference for further information on the blocks mentioned earlier, refer to the reference manual system software for S7-300/ 400: system and standard software , or directly to the step 7 online help . see also profibus dp (page 3-2)
communication 3.4 dpv1 cpu 31xc and cpu 31x, technical data 3-34 manual, edition 08/2004, a5e00105475-05
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 4-1 memory concept 4 4.1 memory areas and retentivity 4.1.1 cpu memory areas the three memory areas of your cpu: cpu loading memory (located on the mmc) memory of the cpu system memory working memory mmc load memory the load memory is located on a mi cro memory card (mmc). the si ze of the load memory corresponds exactly to the si ze of the mmc. it is used to store code blocks, data blocks and system data (configuration, connections, module parameters, etc .). blocks that are identified as non runtime-related are stor ed exclusively in load memory. y ou can also store all the configuration data for your project on the mmc. note user programs can only be dow nloaded and thus the cpu can only be used if the mmc is inserted in the cpu.
memory concept 4.1 memory areas and retentivity cpu 31xc and cpu 31x, technical data 4-2 manual, edition 08/2004, a5e00105475-05 system memory the ram system memory is integr ated in the cpu and cannot be ex panded. it contains ? the address areas for address area memory bits, timers and coun ters ? the process image of the i/os ? local data ram the ram is integrated in the cp u and cannot be extended. it is used to run the code and process user program data. programs only run in ram and system memory. table 4-1 retentivity of the ram all cpus except c pu 317 cpu 317 ram is always retentive. 256 kb of ram can be used for retentiv e data modules. the remainder o f the ram can only be used for code blocks and no n-retentive data blocks. 4.1.2 retentivity of the load memory, system memory and ram your cpu is equipped with a servi ce-free retentive memory.i.e. its operation does not require a buffer battery. data is kept in retentive memory acro ss power off and restart (warm start). retentive data in load memory your program in load memory is always retentive: it is stored o n the mmc, where it is protected against power failure or cpu memory reset. retentive data in system memory in your configuration (propertie s of cpu, retentivity tab), spe cify which part of memory bits, timers and counters sh ould be kept retentive and which of them are to be initialized with "0" on restart (warm restart). the diagnostic buffer, mpi addr ess (and transmission rate) and operating hour counter data are generally written to the ret entive memory area on the cpu. retentivity of the mpi address and baud rate ensures tha t your cpu can continue to com municate, even after a power loss, memory reset or loss of communication parameters (e .g. due to removal of the mmc or deletion of communication parameters).
memory concept 4.1 memory areas and retentivity cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 4-3 retentive data in ram therefore, the contents of retent ive dbs are always retentive a t restart and power on/off. cpus v2.1.0 or higher also supp ort volatile dbs (the volatile d bs are initialized at restart of power off-on with their initial values from load memory.) see also properties of the micro memo ry card (mmc) (page 4-9) 4.1.3 retentivity of memory objects retentive behavior of memory objects the table below shows the retent ive behavior of memory objects during specific operating state transitions. table 4-2 retentive behavior o f memory objects (applies to all cpus with dp/mpi-ss (31x-2 pn/dp) memory object operating state transition power on / power off stop run cpu memory reset user program/data (load memory) x x x ? retentive behavior of dbs for cpus with firmware < v2.1.0 x x C ? retentive behavior of dbs for cpus with firmware >= v2.1.0 can be set in the properties of the dbs in step 7 v5.2 + sp1 or higher. C flag bits, timers and counters configured as retentive data x x C diagnostics buffers, operating hour counters x x x mpi address, transmission rate (or also dp address, tr ansmission rate of the mpi/dp interface of cpu 315-2 pn/dp and cpu 317, if these are configured as dp nodes.) x x x x = retentive; C = not retentive retentive behavior of a db for cpus with firmware < v2.1.0 for these cpus, the contents of t he dbs are always retentive at power on/off or stop- run.
memory concept 4.1 memory areas and retentivity cpu 31xc and cpu 31x, technical data 4-4 manual, edition 08/2004, a5e00105475-05 retentive behavior of a db for cpus with firmware >= v2.1.0 for these cpus you can specify in step 7 (beginning with versio n 5.2 + sp 1), or at sfc 82 crea_dbl (parameter attrib -> n on_retain bit), whether a db at power on/off or run-stop ? keeps the actual values (retentive db), or ? accepts the initial values from load memory (non-retentive db) table 4-3 retentive behavior of d bs for cpus with firmware >= v 2.1.0 at power on/off or restart (warm start) of the cpu, the db shou ld receive the initial values (non-retentive db) retain the actual values (retentive db) background: at power on/off and restart (stop- run) of the cpu, the actual values of the db are non-retentive. the db receives the start values from load memory. background: at power off/on and restart (stop-run) of the cpu, the actual values o f the db are retained. requirement in step 7: ? the "non-retain" che ck box must be set in the block properties of the db, or ? a non-retentive db w as generated with sfc 82 "crea_dbl" and the corresponding block attribute (attrib - > non_retain bit.) requirement in step 7: ? the "non-retain" check bo x must be reset in the block properties of the db or ? a retentive db was ge nerated with sfc 82. note note that only 256 kb of ram can be used for retentive data blo cks on a cpu 317. the remainder of the ram is used by code blocks and non-retentive d ata blocks.
memory concept 4.1 memory areas and retentivity cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 4-5 4.1.4 address areas of system memory system memory of the s7 cpus is o rganized in address areas (ref er to the table below). in a corresponding operation of your user program, you address dat a directly in the relevant address area. address areas of system memory table 4-4 address areas of system memory address areas description process image of inputs at every start of an ob1 cycle, the cpu reads the values at the input of the input modules and sav es them the proc ess image of inputs. process image of outputs during its cycle, the program calculat es the values for the outputs and writes these to the proces s image of output s. at the end of the ob1 cycle, the cpu writes t he calculated out put values to t he output modules. flag bits this area provides mem ory for saving the intermediate results of a program calculation. timers timers are available in this area. counters counters are av ailable in this area. local data temporary data in a co de block (ob, fb, fc) is saved to this memory area while the block is being edited. data blocks see recipes and measurement value logs reference the address areas of your cpu are listed in the instruction list for cpus 31xc and 31x . i/o process image when the user program addresses the input (i) and output (o) ad dress areas, it does not query the signal states of dig ital signal modules. instead, it rather accesses a memory area in cpu system memory. this partic ular memory area is the proces s image. the process image is organized i n two sections: the process ima ge of inputs, and the process image of outputs. advantages of the process image process image access, compared to direct i/o access, offers the advantage that a consistent image of process signals is made available to the cpu during cy clic program execution. when the signal status at an i nput module changes during progra m execution, the signal status in the process image is maintained until the image is up dated in the next cycle. moreover, since the process image is stored in cpu system memor y, access is significantly faster than direct access to the signal modules.
memory concept 4.1 memory areas and retentivity cpu 31xc and cpu 31x, technical data 4-6 manual, edition 08/2004, a5e00105475-05 process image update the operating system updates t he process image periodically. th e figure below shows the sequence of this operation within a cycle. cycle time startup pio pii user program ccp (os) startup program processing the user program (ob 1) and all programs called inside of it. writing the process image of the outputs into the modules. reading the inputs from the modules and refreshing the data in the process image of the inputs.
memory concept 4.1 memory areas and retentivity cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 4-7 configurable process image with cpu317 (fw v2.3.0 or higher) in step 7, you can define a user-specific size of the i/o proce ss images between 0 to 2048 for a cpu317, fw v2 .3.0 or higher. note the information below: note currently, the dynamic setting of the process image only affect s its update a t the scan cycle control point. that is, the proc ess image of inputs is only upd ated up to the set pii size with the corresponding values of the peripheral input modules existi ng within this address area, or the values of the process im age of outputs up to the set pio size are written to the peripheral output modules existing within this address area. this set size of the process image is ignored with respect to s tep 7 commands used to access the process image (for exa mple u i100.0, l ew200, = q20. 0, t ad150, or corresponding indirect addressing commands also). however, up t o the maximum size of the process image (that is, up to i/o byte 2047), these commands do not return any synchronous access errors, but r ather access the permanently av ailable internal memory area of the process image. the same applies to the use of a ctual parameters of block call s from the i/o area (area of the process image). particularly if these process image limits were changed, you sh ould check to which extent your user program accesses the process image in the area betwee n the set and the maximum process image size. if access to this area continues, t he user program may not detect changes at the inputs of t he i/o module, or actually fai ls to write the data of outputs to the output module, without the sy stem generating an error messa ge. you should also note that certa in cps may only be addressed out side of the process image.
memory concept 4.1 memory areas and retentivity cpu 31xc and cpu 31x, technical data 4-8 manual, edition 08/2004, a5e00105475-05 local data local data store: ? the temporary variables of code blocks ? the start information of the obs ? transfer parameters ? intermediate results temporary variables when you create blocks, you can declare temporary variables (te mp) which are only available during block executi on and then overwritten again. th ese local data have fixed length in each ob. local data mu st be initialized prior to the first read access. each ob also requires 20 bytes of local data for its start information. loca l data access is faster compared to access to data in dbs. the cpu is equipped with memory for storing temporary variables (local data) of currently executed blocks. the size of this memory area depends on the cp u. it is distributed in partitions of equal size to the pr iority classes. each priority class has its own local data area. caution all temporary variables (temp) of an ob and its nested blocks a re stored in local data. when using complex nesting leve ls for block processing, you may cause an overflow in the local data area. the cpus will change to stop m ode if you exceed the permissible length of local data for a priority class. make allowances for local data space required for synchronous e rror obs. this is assigned to the respective triggering priority class. see also retentivity of the load memory, sy stem memory and ram (page 4-2 )
memory concept 4.1 memory areas and retentivity cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 4-9 4.1.5 properties of the mi cro memory card (mmc) the mmc as memory module for the cpu the memory module used on your cpu is a simatic micro memory ca rd (mmc.) you can use mmcs as load memory or as a portable storage medium. note the cpu requires the mmc for operation. data stored on the mmc: ? user programs (all blocks) ? archives and recipes ? configuration data (step 7 projects) ? data for operating s ystem update and backup note you can either store user and configuration dat a or the operati ng system on the mmc. properties of an mmc the mmc ensures mainte nance-free and retent ive operation of the se cpus. caution data on a simatic micro memory c ard can be corrupted if you rem ove the card while it is being accessed by a write operat ion. in this case, you may have to delete the mmc on your pg, or format the card in the cp u. never remove an mmc in run m ode. always remove it when power is off, or when the cp u is in stop state, and when t he pg is not a writing to the card. when the cpu is in st op mode and you cannot not deter mine whether or not a pg is writing to the card (e.g . load/delete block), disconnect the communication lines.
memory concept 4.1 memory areas and retentivity cpu 31xc and cpu 31x, technical data 4-10 manual, edition 08/2004, a5e00105475-05 mmc copy protection your mmc has an internal serial number that provides copy prote ction at user level. you can read this serial number from the ssl partial list 011c h index 8 using sfc 51 "rdsysst." you can then program a stop com mand, for example, in a copy-pro tected block if the expected and actual serial num bers of your mcc do not tally. reference ? ssl partial list in the instruction list, or ? in the manual system and standard functions. information on cpu memory reset: operating instructions cpu 31xc and cpu31x, commissioning, comm issioning modules, cpu memory reset by means of mode selector switch useful life of an mmc the useful life of an mmc depend s mainly on following criteria: 1. the number of delete or programming operations, 2. external influences such as ambient temperature. at ambient temperatures up to 60 c, a maximum of 100,000 delet e/write operations can be performed on an mmc. caution to prevent loss of data, always make sure that you do not excee d the maximum number of delete/write operations. see also operating and display elem ents: cpu 31xc (page 2-1) operating and display elements : cpu 312, 314, 315 -2 dp: (page 2 -5) operating and display element s: cpu 317-2 dp (page 2-7) operating and display elements : cpu 31x-2 pn/dp (page 2-9)
memory concept 4.2 memory functions cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 4-11 4.2 memory functions 4.2.1 general: memory functions memory functions memory functions are used to generate, modify or delete entire user programs or specific blocks. you can also ensure tha t your project data are retained by archiving these. if there is... you created a new user program, use a pg/ pc to download the complete program to mmc. 4.2.2 loading user program from micro memory card (mmc) to the cpu user program download all user program data are downl oaded from your pg/pc to the cpu via mmc. the previous content of the mmc is deleted in t he process. blocks use the lo ad memory area as specified under "load memory requirements" i n "general block properties". the figure shows the load and work memory of the cpu loading memory working memory stored on hard disk code modules data modules comments symbols code modules data modules process-relevant parts of the code and data modules * mmc pg cpu * if not ali of the work memory area is retentive, its retentiv e area is indicated in the step 7 module status as retentive memo ry (same as on cpu 317). you can not run the program until all the blocks are downloaded.
memory concept 4.2 memory functions cpu 31xc and cpu 31x, technical data 4-12 manual, edition 08/2004, a5e00105475-05 note this function is only permitted when the cpu is in stop mode. l oad memory is cleared if the load operation could not be completed due to power loss or illegal block data. 4.2.3 handling with modules 4.2.3.1 download of new blocks or delta downloads there are two ways to download additional user blocks or downlo ad deltas: ? download of blocks: you already created a user program and down loaded it to the cpu via mmc. you then want to add ne w blocks to the user program. i n this case, you do not need to reload the entire user p rogram to the mmc. rather, you can download only the new blocks to the mmc (th is reduces download times for highly c omplex programs). ? delta download: in this case, you only download the deltas in t he blocks of your user program. in the next step, perfo rm a delta download of the user program, or only of changed blocks to the mmc, using the pg/pc. warning the delta download of blocks / u ser programs overwrites all dat a stored under the same name on the mmc. the data of dynamic blocks are tr ansferred to ram and activated after the block is downloaded. 4.2.3.2 uploading blocks uploading blocks other than download operations, an upload operation is the tran sfer of specific blocks or a user program from the cpu to the pg/pc. the block content is he re identical with that of the last download to the cpu. dynam ic dbs form the exception, becau se their actual values are transferred. an upload of bloc ks or of the user program from th e cpu in step 7 does not influence cpu memory.
memory concept 4.2 memory functions cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 4-13 4.2.3.3 deleting blocks deleting blocks when you delete a block, it i s deleted from load memory. in ste p 7, you can also delete blocks with the user program (db s also with sfc 23 "del_db"). r am used by this block is released. 4.2.3.4 compressing blocks compressing blocks when data are compressed, gaps w hich have developed between mem ory objects in load memory/ram as a result of load/delete operations will be elimin ated. this releases free memory in a continuous block. dat a compression is possible when the cpu is in run or in stop. 4.2.3.5 promming (ram to rom) promming (ram to rom) when writing the ram content to rom, the actual values of the d bs are transferred from ram to load memory to form the start values for the dbs. note this function is only permitted when the cpu is in stop mode. l oad memory is cleared if the function could not be comp leted due to power loss. 4.2.4 cpu memory reset and restart cpu memory reset after the insertion/removal of a micro memory card, a cpu memor y reset restores defined conditions for cpu restart (warm start). a cpu m emory reset reb uilds the cpu's memory management. blocks in load memory are retained. all dynamic run time blocks are transferred once again from load memory to ram, in particular t o initialize the data blocks in ram (restore initial values).
memory concept 4.2 memory functions cpu 31xc and cpu 31x, technical data 4-14 manual, edition 08/2004, a5e00105475-05 restart (warm start) ? all retentive dbs retain their ac tual value (non-retentive dbs are also supported by cpus with firmware >= v2.1.0 . non-retentive dbs receive their initia l values). ? the values of all retentive m, c, t are retained. ? all non-retentive user data are initialized: ? m, c, t, i, o with "0" ? all run levels are initialized. ? the process image s are deleted. reference also refer to cpu memory reset by means mode selector switch in the section commissioning in the cpu 31xc and cpu 31x operating instructions .
memory concept 4.2 memory functions cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 4-15 4.2.5 recipes introduction a recipe represents a collecti on of user data. you can implemen t a simple recipe concept using static dbs. in this case, the recipes should have the sam e structure (length). one db should exist per recipe. processing sequence recipe is written to load memory: ? the various data records of reci pes are created as static dbs i n step 7 and then downloaded to the cpu. therefore, r ecipes only use load memory, rather than ram. working with recipe data: ? sfc83 "read_dbl" is called in t he user program to copy the data record of a current recipe from the db in load memory to a static db that is locate d in work memory. as a result, the ram only has to acco mmodate the data of one record. the user program can now access data of the current recipe. the figure below shows h ow to handle recipe data: loading memory : current recipe recipe 1 recipe 2 recipe n working memory (mmc) (cpu) sfc 83 read_dbl sfc 84 writ_dbl saving a modified recipe: ? the data of new or modified reci pe data records generated durin g program execution can be written to load memory. to do this, call sfc 84 "writ_dbl" i n the user program. these data written to load memory are portable and also retenti ve on memory reset. you can backup modified records (recipes) by uploading and saving t hese in a single block to the pg/pc. note active system functions sfc82 to 84 (active access to the mmc) have a distinct influence on pg functions (for e xample, block status, variable status, download block, upload, open). this typically reduces performance (compared to passive system functions) by the factor 10.
memory concept 4.2 memory functions cpu 31xc and cpu 31x, technical data 4-16 manual, edition 08/2004, a5e00105475-05 note as a precaution against loss of data, always make sure that you do not exceed the maximum number of delete/write operations. also refer to the si matic micro memory card (mmc) section in the "struc ture and communication connecti ons of a cpu" chapter. caution data on a simatic micro memory c ard can be corrupted if you rem ove the card while it is being accessed by a write operation. in this case, you may h ave to delete the mmc on your pg, or format the card in the cpu. never remove an mmc in run mode. always remove it when power is off, or when the cpu is in stop state, and when the pg is not a writing to the card. when the cpu is in stop mode and you can not not determine whether or not a pg is writing to the card (e.g. load/delete bl ock), disconnect the communication lines.
memory concept 4.2 memory functions cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 4-17 4.2.6 measured va lue log files introduction measured values are generated w hen the cpu executes the user pr ogram. these values are to be logged and analyzed. processing sequence acquisition of measured values: ? the cpu writes all measured valu es to a db (for alternating bac kup mode in several dbs) which is located in ram. measured value logging: ? before the data volume can exceed work memory capacity, you sho uld call sfc 84 "writ_dbl" in the user pro gram to swap measured values f rom the db to load memory. the figure below shows how to handle measured value log files: : measured values 1 measured values 2 measured values n current measured values working memory (cpu) loading memory (mmc) sfc 82 crea_dbl sfc 84 writ_dbl ? you can call sfc 82 "crea_dbl" i n the user program to generate new (additional) static dbs in load memory which do not require ram space. reference for detailed information on sfc 82, refer to the system software for S7-300/400, system and standard functions reference manual, or directly to the step 7 online help. note sfc 82 is terminated and an error message is generated if a db already exists under the same number in load memory and/or ram.
memory concept 4.2 memory functions cpu 31xc and cpu 31x, technical data 4-18 manual, edition 08/2004, a5e00105475-05 the data written to load memory are portable and retentive on c pu memory reset. evaluation of measured values: ? measured value dbs saved to load memory can be uploaded and eva luated by other communication partners (p g, pc, for example). note the active system functions sf c 82 to 84 (current access to the mmc) have a distinct influence on pg functions (block status, variable status, load block, upload, open, for example). this typically reduces performance (compared to passi ve system functions) by the factor 10. note for cpus with firmware v2.1.0 or higher, you can also generate non-retentive dbs using sfc 82 (parameter attri b -> non_retain bit.) note as a precaution against loss of data, always make sure that you do not exceed the maximum number of delete/write operations. for further informat ion, refer to the technical data of the micro memory card (mmc) in the general te chnical data of your cpu. caution data on a simatic micro memory c ard can be corrupted if you rem ove the card while it is being accessed by a write operation. in this case, you may h ave to delete the mmc on your pg, or format the card in the cpu. never remove an mmc in run mode. always remove it when power is off, or when the cpu is in stop state, and when the pg is not a writing to the card. when the cpu is in stop mode and you can not not determine whether or not a pg is writing to the card (e.g. load/delete bl ock), disconnect the communication lines.
memory concept 4.2 memory functions cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 4-19 4.2.7 backup of project data to a micro memory card (mmc) function principle using the save project to memory card and fetch project from memory card functions, you can save all project data to a simatic micro memory card, and r etrieve these at a later time. for this operation, the sima tic micro memo ry card can be located in a cpu or in the mmc adapter of a pg or pc. project data are compressed befor e they are saved to a simatic micro memory card, and uncompressed when fetched. note in addition to project data, you may also have to store your us er data on the mmc. you should therefore first verify mmc memory space. a message warns you if the memory capacity on your mmc is insuf ficient. the volume of project data to be saved corresponds with the siz e of the project's archive file. note for technical reasons, you can only transfer the entire content s (user program and project data) using the save project to memory card action.
memory concept 4.2 memory functions cpu 31xc and cpu 31x, technical data 4-20 manual, edition 08/2004, a5e00105475-05
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-1 cycle and reaction times 5 5.1 overview overview this section contains detail ed information about the following topics: ? cycle time ? reaction time ? interrupt response time ? sample calculations reference: cycle time you can view the cycle time of y our user program on the pg. for further information, refer to the step 7 online help , or to the configuring hardware and connections in step 7 manual reference: execution time can be found in the S7-300 instruction lis t for cpus 31xc and 31x . this tabular list contains the execution times for all ? step 7 instructions the re levant cpu can execute, ? the sfcs / sfbs integrated in the cpus, ? the iec functions which can be called in step 7.
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data 5-2 manual, edition 08/2004, a5e00105475-05 5.2 cycle time 5.2.1 overview introduction this section explains what we mean by the term "cycle time", wh at it consists of, and how you can calculate it. meaning of the term cycle time the cycle time represents the ti me that an operating system nee ds to execute a program, that is, one ob 1 cycle, includi ng all program sections and sys tem activities interrupting this cycle. this time is monitored. time slice model cyclic program processing, and t herefore user program execution , is based on time shares. to clarify these processes, le t us assume that every time share has a length of precisely 1 ms. process image during cyclic program processing, the cpu requires a consistent image of the process signals. to ensure this, the proc ess signals are read/written p rior to program execution. subsequently, the cpu does not a ddress input (i) and output (q) address areas directly at the signal modules, but rather acc esses the system memory area containing the i/o process image.
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-3 sequence of cyclic program processing the table and figure below show the phases in cyclic program pr ocessing. table 5-1 cyclic program processing step sequence 1 the operating system initiat es cycle time monitoring. 2 the cpu copies the values of t he process image of outputs to the output modules. 3 the cpu reads the status at t he inputs of the input modules a nd then updates the process image of inputs. 4 the cpu processes the user pr ogram in time shares and execute s program instructions. 5 at the end of a cycle, the oper ating system executes queued t asks, for example, loading and deleting blocks. 6 the cpu then returns to the start of the cycle, and restarts cycle time monitoring. cycle time time slices (1 ms each) time slice (1 ms) 2 3 4 5 in contrast to s7-400 cpus, the S7-300 cpus data only allow dat a access from an op / tp (monitor and modify functions) a t the scan cycle check point (d ata consistency, see the technical data). processing of t he user program is not interrup ted by the monitor and modify functions.
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data 5-4 manual, edition 08/2004, a5e00105475-05 extending the cycle time always make allowances for the extension of the cycle time of a user program due to: ? time-based interrupt processing ? process interrupt processing ? diagnostics and error processing ? communication with pgs, operator p anels (ops) and connected cps (for example, ethernet, profibus dp) ? testing and commissioning such as, e.g. status/controlling of v ariables or block status functions. ? transfer and deletion of blocks , compressing user program memor y ? write/read access to the mmc, using sfc 82 to 84 in the user pr ogram ? ethernet communication via int egrated profinet interface ? cba communication via profinet i nterface (system load, sfc call , update at scan cycle check point) ? profinet io communication via pr ofinet interface (system load)
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-5 5.2.2 calculati ng the cycle time introduction the cycle time is derived from the sum of the following influen cing factors. process image update the table below shows the time a cpu requires to update the pro cess image (process image transfer time). the times specified might be prolonged as a result of interrupts or cpu communication. the process image tr ansfer time is calculated as follows: table 5-2 formula for calculati ng the process image (pi) transf er time the transfer time of the process image is calculated as follows : base load k + number of bytes i n pi in module rack 0 x (a) + number of bytes in po in m odule rack 1 to 3 x (b) + number of words in po via dp x (d) + number of words in po via profinet x (p) = transfer time for the process image table 5-3 cpu 31xc: data for ca lculating the process image (pi) transfer time const. portions cpu 312c cpu 313c cpu 313c-2 dp cpu 313c-2 ptp cpu 314c-2 dp cpu 314c-2 ptp k base load 150 s 100 s 100 s 100 s a per byte in module rack 0 37 s 35 s 37 s 37 s b per byte in module racks 1 to 3 * - 43 s 47 s 47 s d (dp only) per word in the dp area for the integrated dp interface - - 1 s - 1 s -
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data 5-6 manual, edition 08/2004, a5e00105475-05 table 5-4 cpu 31x: data for calc ulating the proc ess image (pi) transfer time const. portions cpu 312 cpu 314 cpu 315 cpu 317 k base load 150 s 100 s 100 s 50 s a per byte in module rack 0 37 s 35 s 37 s 15 s b per byte in module racks 1 to 3 * - 43 s 47 s 25 s d (dp only) per word in the dp area for the integrated dp interface - - 1 s 1 s p (profinet only) per word in the profinet area for the integrated profinet interface - - 46 s 46 s * + 60 s per rack * + 60 s per rack extending the user program processing time in addition to actually working through the user program, your cpu's operating system also runs a number of processes in parallel such as timer management for t he core operating system. these p rocesses extend the processing time of the user program. the table below lists the multiplication factors required to calculate your user pr ogram processing time. table 5-5 extending the user program processing time cpu factor 312c 1,06 313c 1,10 313c-2dp 1,10 313c-ptp 1,06 314c-2dp 1,10 314c-2ptp 1,09 312 1,06 314 1,10 315 1,10 317 1,07
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-7 operating system processing time at the scan cycle checkpoint the table below shows the operat ing system processing time at t he scan cycle checkpoint of the cpus. these times are calcul ated without taking into consid eration times for: ? testing and commissioning routines, e.g. status/controlling of variables or block status functions ? transfer and deletion of blocks , compressing user program memor y ? communication ? read/write access to the mmc, using sfc82 to 84 table 5-6 operating system pro cessing time at the scan cycle ch eckpoint cpu cycle control at the sc an cycle check point (ccp) 312c 500 s 313c 500 s 313c-2 500 s 314c-2 500 s 312 500 s 314 500 s 315 500 s 317 150 s extension of the cycle time as a result of nested interrupts enabled interrupts also extend cycle time. details are found in the table below. table 5-7 extended cycle time due to nested interrupts interrupt type process interrupt diagnostic interrupt time-of-day interrupt delay interrupt watchdog interrupt 312c 700 s 700 s 600 s 400 s 250 s 313c 500 s 600 s 400 s 300 s 150 s 313c-2 500 s 600 s 400 s 300 s 150 s 314c-2 500 s 600 s 400 s 300 s 150 s 312 700 s 700 s 600 s 400 s 250 s 314 500 s 600 s 400 s 300 s 150 s 315 500 s 600 s 400 s 300 s 150 s 317 190 s 240 s 200 s 150 s 90 s the program runtime at interr upt level must be added to this ti me extension.
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data 5-8 manual, edition 08/2004, a5e00105475-05 extension of the cycle time due to error table 5-8 cycle time extension as a result of errors type of error pr ogramming e rrors i/o access errors 312c 600 s 600 s 313c 400 s 400 s 313c2 400 s 400 s 314c-2 400 s 400 s 312 600 s 600 s 314 400 s 400 s 315 400 s 400 s 317 100 s 100 s the interrupt ob processing time must be added to this extended time. the times required for multiple nested interrupt/e rror obs are added accordingly. 5.2.3 different cycle times overview the cycle time (t cyc ) length is not the same in ever y cycle. the figure below shows different cycle times t cyc1 and t cyc2 . t cyc2 is longer than t cyc1 , because the cyclically executed ob1 is interrupted by a time-of-day interrupt ob (here: ob 10). current cycle next cycle ob10 t cyc 1 cyc 2 t cycle after next updating pio updating pii updating pio updating pii updating pio updating pii ob1 ob1 ob1 ccp ccp block processing times may fluctuate fluctuation of the block processi ng time (e.g. ob 1) may also b e a factor causing cycle time fluctuation, due to: ? conditional instructions, ? conditional block calls, ? different program paths, ? loops etc.
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-9 maximum cycle time in step 7 you can modify the default maximum cycle time. ob80 is called o n when this time expires. in this block you can sp ecify the cpus response to thi s timeout error. the cpu switches to stop mode if ob80 does not exist in its memory. 5.2.4 communication load configured communication load for pg/op communication, s7 commu nication and cba the cpu operating system continuo usly provides a specified perc entage of total cpu processing performance (time-sh aring technology) for communicat ion tasks. processing performance not required for communication is made available to other processes. in hw config, you can specify a comm unication load value between 5% a nd 50%. default value is 20%. you can use the following formula for calculating the cycle tim e extension factor: 100 / (100 C configured co mmunication load in %) interruption of user program share can be configured between 5 % and 50 % time slice (1 ms) example: 20 % communication load in your hardware configuration , you have specified a communicat ion load of 20 %. the calculated cycle time is 10 ms. using the above formula, the cy cle time is extended by the factor 1.25. example: 50 % communication load in your hardware configuration , you have specified a communicat ion load of 50%. the calculated cycle time is 10 ms. using the above formula, the cy cle time is extended by the factor 2.
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data 5-10 manual, edition 08/2004, a5e00105475-05 physical cycle time depending on communication load the figure below describes t he non-linear depen dency of the phy sical cycle time on communication load. in o ur sample we have chosen a cycle time o f 10 ms. 0% 10 % 20 % 30 % 40 % 50 % 60 % cycle time 10 ms 20 ms 25 ms 15 ms 5ms 30 ms 5% communication load the communication load can be defined in this area. influence on the physical cycle time from the statistical viewpoint, a synchronous eventssuch as int erruptsoccur more frequently within the ob1 cycle when the cycle time is extended as a result of communication load. this further e xtends the ob1 cycle. this ex tension depends on the number of events that occur per ob1 cycle and the time required to process these events. note change the value of the "communication load" parameter to check the effects on the cycle time at system runtime. you must consider the communication loa d when you set the maximum cycle time, otherwi se timing errors may occur. tips ? use the default setting wherever possible. ? increase this value only if the cpu is used primarily for commu nications and if the user program is not time critical. ? in all other situations you shoul d only reduce this value.
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-11 5.2.5 cycle time extension as a result of testin g and commissio ning functions runtimes the runtimes of the testing and commissioning functions are ope rating system runtimes, so they are the same for every cp u. initially, there is no differe nce between process mode and testing mode. how the cycle time is extended as a result of act ive testing and commissioning functions is shown in the table below. table 5-9 cycle time extension as a result of testing and commi ssioning functions function cpu 31xc/ cpu 31x status variable 50 s for each variable control variable 50 s for each variable block status 200 s for each monitored line configuration during parameter assignment for process operation , the maximum permissible cycle load by communication is not specified in "cycle load by co mmunication", but rather in "maxi mum permitted increase of cycle time as a result of testi ng functions during process oper ation". thus, the configured time is monitored absolutely in process mode and data acquisiti on is stopped if a timeout occurs. this is how step 7 stop s data requests in loops before a loop ends, for example. when running in testing mode , the complete loop is executed in every cycle. this can significantly increase cycle time. 5.2.6 cycle extensio n through component-based automation (cba) by default, the operating system o f your cpu updates the profin et interface as well as the dp interconnections at the cycle control point. however, if you deactivated these automatic updates dur ing configuration (e .g. to obtain improved capabilities of influencing the time behavior of the cpu), you mu st perform the update manually . this is done by calling sfcs 112 to 114 at the appropriate times. reference information about sfc 112 to 114 is available in the step 7 online help . extending the ob1 cycle time the ob1 cycle is extended by ? increasing the number of profinet interconnections, ? increasing the number of remote partners, ? increasing the data volume and ? incrasing the transfer frequency
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data 5-12 manual, edition 08/2004, a5e00105475-05 note the use of cba with cyclical pro finet interconnections requires the use of switches to maintain the performance data . 100-mbit full-duplex operation i s mandatory with cyclical profinet interconnections. the following graphic shows the c onfiguration that was used for the measurements. industrial ethernet profibus ... ... hmi/opc quantity: 32 quantity: 16 profinet device with proxy functionality (cpu 317-2 pn/dp) number of observed interconnections in simatic imap or opc: 200 profinet remote node 1 profibus device 1 (as dp slave) profinet remote node 32 profibus device 16 (as dp slave) the upper graphic displays incoming/outgoing remote connections number cyclical interconnection via et hernet 200, scan cycle rate: int ervals of 10 ms acyclic interconnection via et hernet 50, scan cycle rate: inte rvals of 500 ms interconnections from the profinet device with proxy functionality (cpu 317-2 pn/d p) to the profibus devices. 16 x 4 interconnections of profibus dev ices among each other 16 x 6
cycle and reaction times 5.2 cycle time cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-13 additional marginal conditions the maximum cycle load through communication in the measurement is 20 %. the lower graphic shows that the ob1 cycle is influenced by inc reasing the cyclical profinet interconnections to r emote partners at profinet: 032 64 96 128 160 200 0 2 4 6 8 10 12 14 cycle time in ms dependency of the ob1 cycle on the number of interconnections number of interconnections ob1 cycle with 32 remote profinet partners ob1 cycle with 5 remote profinet partners base load through profibus devices the 16 profibus devices with t heir interconnections among each other generate an additional base load of up to 1,0 ms. tips and notes the upper graphic already includes the use of uniform values fo r the transfer frequency of all interconnections to a partner. ? the performance can drop by up to 50 % if the values are distri buted to different frequency levels. ? the use of data structures and ar rays in an interconnection ins tead of many single interconnections with simple dat a structures increases the perf ormance.
cycle and reaction times 5.3 response time cpu 31xc and cpu 31x, technical data 5-14 manual, edition 08/2004, a5e00105475-05 5.3 response time 5.3.1 overview definition of response time the response time is the time between the detection of an input signal and the change of a linked output signal. fluctuation width the physical response time lies between the shortest and the lo ngest response time. you must always reckon with the l ongest response time when configur ing your system. the shortest and long est response times ar e shown below, to giv e you an idea of the fluctuation width of the response time. factors the response time depends on the cycle time and following facto rs: ? delay of the inputs and outputs of signal modules or integrated i/o. ? additional update times for profinet io ? additional dp cycle times on profibus dp ? execution in the user program reference ? the delay times are located in t he specifications of the signal modules ( module data reference manual). update times for profinet io if you configured your profinet io system in step 7, step 7 cal culates the update time for profinet io. you can then view the profinet io update times on your pg.
cycle and reaction times 5.3 response time cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-15 dp cycle times in the profibus dp network if you have configured your profibu s dp master system in step 7 , step 7 calculates the typical dp cycle time to be expe cted. you can then view the dp cycle time of your configuration on the pg. the figure below gives you an overview of the dp cycle time. in this example, let us assume that the data of each dp slave h as an average length of 4 bytes . 6ms 4ms 2ms 2 4 8 16 32 1ms 3ms 5ms 7ms 64 17 ms 1 bus runtime number of dp slaves; maximum number is dependent on cpu minimum slave interval transmission rate 1.5 mbit/s transmission rate 12 mbit/s with multi-master operation on a profibus-dp network, you must make allowances for the dp cycle time at each master. t hat is, you will have to calcula te the times for each master separately and then add up the results.
cycle and reaction times 5.3 response time cpu 31xc and cpu 31x, technical data 5-16 manual, edition 08/2004, a5e00105475-05 5.3.2 shortest response time conditions for the shortest response time the figure below shows the conditions under which the shortest response time is reached. delay of inputs immediately before reading in the pii, the status of the monitored input changes. this change of the input signal is still included in the pii. the change of the input signal is processed by the application program. the response of the user program to the change of the input signal is issued to the outputs. delay of outputs response time ccp (os) pio pii user program ccp (os) pio calculation the (shortest) response time is the sum of: table 5-10 formula: shortest response time 1 x process image transfe r time for the inputs + 1 x process image transfer time for the outputs + 1 x program processing time + 1 operating system pro cessing time at the scc + i/o delay = shortest response time the result is equivalent to the su m of the cycle time plus the i/o delay times. see also overview (page 5-14)
cycle and reaction times 5.3 response time cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-17 5.3.3 longest response time conditions for the longest response time the figure below shows the conditions under which the longest r esponse time is reached. response time while reading in the pii, the status of the monitored input changes. this change of the input signal is not included in the pii any longer. the change of the input signal is included in the pii. the change of the input signal is processed by the application program. the response of the user program to the change of the input signal is issued to the outputs. delay of inputs + 2 x dp cycle time at profibus dp delay of outputs + 2 x dp cycle time at profibus dp ccp (os) pio pii ccp (os) pio pii pio
cycle and reaction times 5.3 response time cpu 31xc and cpu 31x, technical data 5-18 manual, edition 08/2004, a5e00105475-05 calculation the (longest) response time is the sum of: table 5-11 formula: longest response time 2 x process image transfe r time for the inputs + 2 x process image transfer time for the outputs + 2 x program processing time + 2 operating system processing time + 2 x program processing time + 4 x profinet io update time (onl y if profinet io is used.) + 4 x dp cycle time on profibus d p (only if profibus dp is used .) + i/o delay = longest response time equivalent to the sum of 2 x the cycle time + i/o delay time + 4 x times the profinet io update time or 4 x times the dp cycle time on profibus dp. see also overview (page 5-14) 5.3.4 reducing the response time with direct i/o access reducing the response time you can reach faster response ti mes with direct access to the i /o in your user program, e.g. with ? l pib or ? t pqw you can partially avoid the response times described above. note you can also achieve fast respons e times by using process inter rupts. see also shortest response time (page 5-16) longest response time (page 5-17)
cycle and reaction times 5.4 calculating method for calculating the cycle/response time cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-19 5.4 calculating method for calculating the cycle/response time introduction this section gives you an overvi ew of how to calculate the cycl e/response time. cycle time 1. determine the user program runtime with the help of the instruction list . 2. multiply the calculated valu e by the cpu-specific factor fro m the table extension of user program processing time . 3. calculate and add the proces s image transfer time. correspon ding guide values are found in table data for calculating process image transfer time . 4. add the processing time at the scan cycle checkpoint. corres ponding guide values are found in the table operating system processing ti me at the scan cycle checkpoint . 5. include the extens ions as a result of testing and commission ing functions as well as cyclical profinet interconnections in your calculation. these v alues are found in the table cycle time extension due to testing and commissioning functions . the final result is the cycle time. extension of the cycle time as a result of interrupts and commu nication load 100 / (100 C configured co mmunication load in %) 1. multiply the cycle time by t he factor as in the formula abov e. 2. calculate the runtime of inter rupt processing program sectio ns with the help of the instruction list. add the corre sponding value from the table be low . 3. multiply both values by the cp u-specific extension factor of the user program processing time. 4. add the value of the interrupt-processing program sequences to the theoretical cycle time, multiplied by the number o f triggering (or expected) inte rrupt events within the cycle time. the result is an approximation of the physical cycle time . note down the result. see also cycle extension through compone nt-based automation (cba) (page 5-11)
cycle and reaction times 5.4 calculating method for calcul ating the cycle/response time cpu 31xc and cpu 31x, technical data 5-20 manual, edition 08/2004, a5e00105475-05 response time table 5-12 calculating the response time shortest response time l ongest response time - multiply the physical cycle time by factor 2. now add i/o delay. now add the i/o delay plus the dp cycle time s on profibus-dp or the profinet io update times. the result is the shortest resp onse time. the result is the lon gest response time. see also longest response time (page 5-17) shortest response time (page 5-16) calculating the cycle time (page 5-5) cycle extension through compone nt-based automation (cba) (page 5-11)
cycle and reaction times 5.5 interrupt response time cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-21 5.5 interrupt response time 5.5.1 overview definition of interrupt response time the interrupt response time is t he time that expires between th e first occurrence of an interrupt signal and the call of t he first interrupt ob instruc tion. generally valid: higher- priority interrupts take prior ity. this means that the interrup t response time is increased by the program processing time of t he higher-priority interrupt ob s and the interrupt obs of equal priority which have not yet been executed (queued). process/diagnostic interrupt response times of the cpus table 5-13 process/diagnostic interrupt response times process interrupt response times diagnostic interrupt response times cpu external min. external max. integrated i/o max. min. max. cpu 312 0.5 ms 0,8 ms - 0.5 ms 1,0 ms cpu 312c 0.5 ms 0,8 ms 0,6 ms 0.5 ms 1,0 ms cpu 313c 0,4 ms 0,6 ms 0.5 ms 0,4 ms 1,0 ms cpu 313c-2 0,4 ms 0,7 ms 0.5 ms 0,4 ms 1,0 ms cpu 314 0,4 ms 0,7 ms - 0,4 ms 1,0 ms cpu 314c-2 0,4 ms 0,7 ms 0.5 ms 0,4 ms 1,0 ms cpu 315-2 dp cpu 315-2 pn/dp 0,4 ms 0,7 ms - 0,4 ms 1,0 ms cpu 317-2 dp cpu 317-2 pn/dp 0,2 ms 0,3 ms - 0,2 ms 0,3 ms
cycle and reaction times 5.5 interrupt response time cpu 31xc and cpu 31x, technical data 5-22 manual, edition 08/2004, a5e00105475-05 calculation the formula below show how you c an calculate the minimum and ma ximum interrupt response times. table 5-14 process/diagnostic interrupt response times calculation of the minimum and maximum interrupt reaction time minimum interrupt reac tion time of the cpu + minimum interrup t reaction time of the signal modules + profinet io update time (only if profinet io is used.) + dp cycle time on profibus dp (only if profibus dp is used.) = quickest interr upt reaction time maximum interrupt reac tion time of the cpu + maximum interrupt reac tion time of the signal modules + 2 x profinet io update time (only if profinet io is used.) + 2 x dp cycle time on profibus dp (only if profibus dp is used.) the maximum interrupt reaction time is longer when the communication functions are active. the extra time is calculated using the following formula: tv: 200 s + 1000 s x n% n = setting of the cycle load as a result of communication extension of interrupt response times with cyclic profinet inte rconnections when using cyclical profinet inte rconnections to a remote partn er, the interrupt response time can increase by up to 1.2 m s in addition to the values men tioned above: ? more than 10 cyclical interconn ections are configured to the re mote partner or ? the interconnection data to the remote partner are greater than 100 bytes. signal modules the process interrupt response time of signal modules is determined by the following factors: ? digital input modules process interrupt response time = internal interrupt preparatio n time + input delay you will find these times in the data sheet for the respective digital input module. ? analog input modules process interrupt response time = internal interrupt preparatio n time + input delay the internal interrupt preparation time for analog input module s can be neglected. the conversion times can be found in t he data sheet for the individ ual analog input modules. the diagnostic interrupt response time of signal modules is equi valent to the period that expires between the time a signal module detects a diagnostic e vent and the time this signal module triggers the di agnostic interrupt. t his short time can b e neglected.
cycle and reaction times 5.5 interrupt response time cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-23 process interrupt processing process interrupt processing begi ns after process interrupt ob4 0 is called. higher-priority interrupts stop process interrup t processing. d irect i/o access is executed during runtime of the instruction. after process in terrupt processing has termina ted, cyclic program execution continues or further interrupt o bs of equal or lower priority a re called and processed. see also overview (page 5-1) 5.5.2 reproducibility of delay interrupts and watchdog interrup ts definition of "reproducibility" delay interrupt : the period that expires between the call of the first instructi on in the interrupt ob and the programmed time of interrupt. watchdog interrupt : the fluctuation width of the inte rval between two successive ca lls, measured between the respective initial instruc tions of the interrupt obs. reproducibility the following times apply for the cpus described in this manual : ? delay interrupt: +/- 200 s ? watchdog interrupt: +/- 200 s these times only apply if the in terrupt can actually be execute d at this time and if not interrupted, for example, by high er-priority interrupts or queu ed interrupts of equal priority.
cycle and reaction times 5.6 sample calculations cpu 31xc and cpu 31x, technical data 5-24 manual, edition 08/2004, a5e00105475-05 5.6 sample calculations 5.6.1 example of cycl e time calculation installation you have configured an S7-300 a nd equipped it with following mo dules in rack "0": ? a cpu 314c-2 ? 2 digital input modules sm 321; d i 32 x 24 vdc (4 bytes each in the pi) ? 2 digital output modules sm 322; do 32 x 24 vdc/0.5 a (4 bytes each in the pi) user program according to the instruction list, the user program runtime is 5 ms. there is no active communication. calculating the cycle time in this example, the cycle time is equivalent to the sum of the following times: ? user program execution time: approx. 5 ms x cpu-specific fa ctor 1.10 = approx. 5.5 ms ? process image transfer time process image of inputs: 100 s + 8 byte x 37 s = approx. 0.4 ms process image of outputs: 100 s + 8 byte x 37 s = approx. 0.4 ms ? operating system runtime a t the scan cycle checkpoint: approx. 0.5 ms cycle time = 5.5 ms + 0.4 ms + 0.4 ms + 0.5 ms = 6.8 ms. calculating the physical cycle time ? there is no active communication. ? interrupts are not processed. hence, the physical cycle time is 6 ms.
cycle and reaction times 5.6 sample calculations cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-25 calculating the longest response time longest response time: 6.8 ms x 2 = 13.6 ms. ? i/o delay can be neglected. ? neither profibus dp, nor profinet io are being used, so you do not have to make allowances for any dp cycle times on profibus dp or for profine t io update times. ? interrupts are not processed. 5.6.2 sample of respons e time calculation installation you have configured an S7-300 a nd equipped it with the followin g modules in two racks: ? a cpu 314c-2 configuring the cycle load as a result of communication: 40 % ? 4 digital input modules sm 321; d i 32 x 24 vdc (4 bytes each in the pi) ? 3 digital output modules sm 322; do 16 x 24 vdc/0.5 a (2 bytes each in the pi) ? 2 analog input modules sm 331; ai 8 x 12-bit (not in the pi) ? 2 analog output modules sm 332; a o 4 x 12 bit (not in the pi) user program according to the instruction list, the user program runtime is 10.0 ms. calculating the cycle time in this example, the cycle time is equivalent to the sum of the following times: ? user program execution time: approx. 10 ms x cpu-specific fa ctor 1.10 = approx. 11 ms ? process image transfer time process image of inputs: 100 s + 16 bytes x 37 s = approx. 0. 7 ms process image of outputs: 100 s + 6 bytes x 37 s = approx. 0. 3 ms ? operating system runtime a t the scan cycle checkpoint: approx. 0.5 ms the sum of the listed times is equivalent to the cycle time: cycle time = 11.0 ms + 0.7 ms + 0.3 ms + 0.5 ms = 12.5 ms.
cycle and reaction times 5.6 sample calculations cpu 31xc and cpu 31x, technical data 5-26 manual, edition 08/2004, a5e00105475-05 calculating the physical cycle time under consideration of communication load: 12.5 ms * 100 / (100-40) = 20.8 ms. thus, under consider ation of time-sharing factors, the actual cycle time is 21 ms . calculation of the longest response time ? longest response time = 21 ms * 2 = 42 ms. ? i/o delay ? the maximum delay of the input d igital module sm 321; di 32 x 2 4 vdc is 4.8 ms per channel. ? the output delay of the digital output module sm 322; do 16 x 2 4 vdc/0.5 a can be neglected . ? the analog input module sm 331; ai 8 x 12 bit was configured fo r an interference suppression at 50 hz. the result is a conversion time of 22 ms per channel. with the eight active channels, the result is a cycle time of 176 ms for the analog input module. ? the analog output module sm 332; a o 4 x 12-bit was programmed f or the measuring range of 0 ...10 hz. this gives a conversion time of 0.8 ms per channel. since 4 channels are active, the resul t is a cycle time of 3.2 ms. a settling time of 0.1 ms for a resistive load must be added to this value. the result is a r esponse time of 3.3 ms for an analog output. ? neither profibus dp, nor profinet io are being used, so you do not have to make allowances for any dp cycle times on profibus dp or for profine t io update times. ? response times plus i/o delay: ? case 1: an output channel of the digita l output module is set when a s ignal is received at the digital input. the result is a response time of: response time = 42 ms + 4.8 ms = 46.8 ms. ? case 2: an analog value is fetched, and an analog value is output. the result is a response time of: longest response time = 42 ms + 176 ms + 3.3 ms = 221.3 ms.
cycle and reaction times 5.6 sample calculations cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 5-27 5.6.3 example of interrup t response time calculation installation you have assembled an S7-300, c onsisting of one cpu 314c-2 and four digital modules in the cpu rack. one of the digita l input modules is an sm 321; di 16 x 24 vdc; with process/diagnostic interrupt function. you have enabled only the process interrupt in your cpu and sm parameter configuration. you decided not to use time-contro lled processing, diagnostics or error handling. you have configured a 20% communi cation load on the cycle. you have configured a delay of 0 .5 ms for the inputs of the di module. no activities are required at the scan cycle checkpoint. calculation in this example, the process in terrupt response time is based o n following time factors: ? process interrupt res ponse time of cpu 314 c-2: approx. 0,7 ms ? extension by communication according to the formula: 200 s + 1000 s x 20 % = 400 s = 0.4 ms ? process interrupt res ponse time of sm 321; di 16 x 24 vdc: ? internal interrupt pre paration time: 0.25 ms ? input delay: 0.5 ms ? neither profibus dp, nor profinet io are being used, so you do not have to make allowances for any dp cycle times on profibus dp or for profine t io update times. the process interrup t response time is equivalent to the sum of the listed time factors: process interrupt response time = 0.7 ms + 0.4 ms + 0.25 ms + 0.5 ms = approx. 1.85 ms . this calculated process interrupt response time expires between the time a signal is received at the digital input and the call of the first instruc tion in ob40.
cycle and reaction times 5.6 sample calculations cpu 31xc and cpu 31x, technical data 5-28 manual, edition 08/2004, a5e00105475-05
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-1 technical data of cpu 31xc 6 6.1 general technical data 6.1.1 dimensions of cpu 31xc each cpu features the same heigh t and depth, only the width dim ensions differ. ? height: 125 mm ? depth: 115 mm, or 180 mm with opened front cover. width of cpu cpu width cpu 312c 80 mm cpu 313c 120 mm cpu 313c-2 ptp 120 mm cpu 313c-2 dp 120 mm cpu 314c-2 ptp 120 mm cpu 314c-2 dp 120 mm
technical data of cpu 31xc 6.1 general technical data cpu 31xc and cpu 31x, technical data 6-2 manual, edition 08/2004, a5e00105475-05 6.1.2 technical data of the micro memory card (mmc) plug-in simatic micro memory cards the following memory modules are available: table 6-1 available mmcs type order number required for a firmware update via mmc mmc 64k 6es7 953-8lfxx-0aa0 C mmc 128k 6es7 953-8lgxx-0aa0 C mmc 512k 6es7 953-8ljxx-0aa0 C mmc 2m 6es7 953-8llxx-0aa0 minim um requirement fo r cpus without dp interface mmc 4m 6es7 953-8lmxx- 0aa0 minimum require ment for cpus with dp interface mmc 8m 1 6es7 953-8lpxx-0aa0 C 1 this mmc cannot be used together with cpu 312c or cpu 312. maximum number of loadable blocks in the mmc the number of blocks that can be stored on the mmc depends on t he capacity of the mmc being used. the maximum number of b locks that can be loaded is therefore limited by the capacity of your mmc (including bl ocks generated with the "crea te db" sfc): table 6-2 maximum number o f loadable blocks on the mmc size of mmc maximum number of blocks that c an be loaded 64 kb 768 128 kb 1024 512 kb 2 mb 4 mb 8 mb here the maximum number of blo cks that can be loaded for the specific cpu is less than the nu mber of blocks that can be stor ed on the mmc. refer to the corresponding specif ications of a specific cpu to determine the maximum number of blocks that can be loaded.
technical data of cpu 31xc 6.2 cpu 312c cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-3 6.2 cpu 312c technical data table 6-3 technical data of cpu 312c technical data cpu and version order number 6es7 312-5bd01-0ab0 ? hardware version 01 ? firmware version v2.0 ? associated programming package step 7 as of v 5.2 + sp 1 (please use previous c pu for step 7 v 5.1 + sp 3 or later) memory ram ? integrated 16 kb ? expandable no load memory plugged in with mmc (max. 4 mb) data storage life on the mmc (following final programming) at least 10 years buffering guaranteed by mmc (maintenance-free) execution times processing times of ? bit operations min. 0.2 s ? word instructions min. 0.4 s ? fixed-point arithmetic min. 5 s ? floating-point arithmetic min. 6 s timers/counters and their retentivity s7 counters 128 ? retentive memory configurable ? default from c0 to c7 ? counting range 0 to 999 iec counters yes ? type sfb ? number unlimited (limited on ly by ram size) s7 timers 128 ? retentive memory configurable ? default not retentive ? timer range 10 ms to 9990 s
technical data of cpu 31xc 6.2 cpu 312c cpu 31xc and cpu 31x, technical data 6-4 manual, edition 08/2004, a5e00105475-05 technical data iec timers yes ? type sfb ? number unlimited (limited on ly by ram size) data areas and their retentivity flag bits 128 bytes ? retentive memory configurable ? default retentivity mb0 to mb15 clock flag bits 8 (1 byte per flag bit) data blocks max. 511 (db 1 to db 511) ? length max. 16 kb local data per priority class max. 256 bytes blocks total 1024 (dbs, fcs, fbs) the maximum number of blocks that can be loaded may be reduced if you are using another mmc. obs see the instruction list ? length max. 16 kb nesting depth ? per priority class 8 ? additional within an error ob 4 fbs max. 512 (fb 0 to fb 511) ? length max. 16 kb fcs max. 512 (fc 0 to fc 511) ? length max. 16 kb address areas (i/o) total i/o address area max . 1024 bytes/1024 bytes (can be freely addressed) i/o process image 128 bytes/128 bytes digital channels max. 256 ? of those local max. 256 ? integrated channels 10 di / 6 do analog channels max. 64 ? of those local max. 64 ? integrated channels none
technical data of cpu 31xc 6.2 cpu 312c cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-5 technical data assembly racks max. 1 modules per rack max. 8 number of dp masters ? integrated none ? via cp max. 1 number of function modules and communication processors you can operate ? fm max. 8 ? cp (ptp) max. 8 ? cp (lan) max. 4 time-of-day real-time clock yes (sw clock) ? buffered no ? accuracy deviation per day < 10 s ? behavior of the realti me clock after power off the clock keeps running, c ontinuing at the time- of-day it had when powe r was switched off. operating hour s counter 1 ? number 0 ? value range 2 31 hours (if sfc 101 is used) ? granularity 1 hour ? retentive yes; must be manually restarted after every restart clock synchronization yes ? in the plc master ? on mpi master/slave s7 signaling functions number of stations tha t can be logged on for signaling functions max. 6 (depends on the number of connections configured for pg / op and s7 basic communication) process diagnostics messages yes ? simultaneously enabled interrupt s blocks max. 20 testing and commissioning functions status/control variables yes ? variables inputs, outputs, memory bits, dbs, timers, counters ? number of variables ? of those as status variable ? of those as cont rol variable max. 30 max. 30 max. 14 forcing yes ? variables inputs, outputs ? number of variables max. 10
technical data of cpu 31xc 6.2 cpu 312c cpu 31xc and cpu 31x, technical data 6-6 manual, edition 08/2004, a5e00105475-05 technical data block status yes single step yes breakpoints 2 diagnostic buffer yes ? number of entries (not configurable) max. 100 communication functions pg/op communication yes global data communication yes ? number of gd circuits 4 ? number of gd packets ? sending stations ? receiving stations max. 4 max. 4 max. 4 ? length of gd packets ? consistent data max. 22 bytes 22 bytes s7 basic communication yes ? user data per request ? consistent data max. 76 bytes 76 bytes (for x_send or x_rcv) 64 bytes (for x_put or x_get as the server) s7 communication ? as server yes ? user data per request ? consistent data max. 180 bytes (with put/get) 64 bytes s5-compatible communication yes (via cp and loadable fcs) number of connections max. 6 can be used for ? pg communication ? reserved (default) ? configurable max. 5 1 from 1 to 5 ? op communication ? reserved (default) ? configurable max. 5 1 from 1 to 5 ? s7-based communication ? reserved (default) ? configurable max. 2 2 from 0 to 2 routing no interfaces 1st interface type of interface integr ated rs485 interface physics rs 485 electrically isolated no interface power supply (15 to 30 vdc) max. 200 ma
technical data of cpu 31xc 6.2 cpu 312c cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-7 technical data functionality ? mpi yes ? profibus dp no ? point-to-point c ommunication no mpi services ? pg/op communication yes ? routing no ? global data communication yes ? s7 basic communication yes ? s7 communication ? as server ? as client yes no ? transmission rates max. 187.5 kbps programming programming language lad/fbd/stl available instructions s ee the instruction list nesting levels 8 system functions (sfcs) see the instruction list system function blocks (sfbs) see the instruction list user program security yes integrated i/o ? default addresses of the integrated ? digital inputs ? digital outputs 124.0 to 125.1 124.0 to 124.5 integrated functions counters 2 channels (see the manual technological functions ) frequency counters 2 channels, m ax. 10 khz (see the manual technological functions ) pulse outputs 2 channels for pulse width modulation, max. 2.5 khz (see the manual technological functions ) controlled positioning no integrated "controlling" sfb no dimensions mounting dimensions w x h x d (mm) 80 x 125 x 130 weight 409 g voltages and currents power supply (rated value) 24 vdc ? permitted range 20.4 v to 28.8 v current consumption (no-load operation) typically 60 ma inrush current typically 11 a power consumption (nominal value) 500 ma
technical data of cpu 31xc 6.3 cpu 313c cpu 31xc and cpu 31x, technical data 6-8 manual, edition 08/2004, a5e00105475-05 technical data i 2 t 0.7 a 2 s external fusing of power supply lines (recommended) ls switch type c min. 2 a, ls switch type b min. 4 a power loss typically 6 w reference in chapter specifications of the integrated i/o you can find ? the specifications o f integrated i/os under digital inputs of cpus 31xc and digital outputs of cpus 31xc . ? the block diagrams of the integrated i/os under arrangement and usage of integrated i/os . 6.3 cpu 313c technical data table 6-4 technical data of cpu 313c technical data cpu and version order number 6es7 313-5be01-0ab0 ? hardware version 01 ? firmware version v2.0.0 ? associated programming package step 7 as of v 5.2 + sp 1 (please use previous c pu for step 7 v 5.1 + sp 3 or later) memory ram ? integrated 32 kb ? expandable no load memory plugged in with mmc (max. 8 mb) data storage life on the mmc (following final programming) at least 10 years buffering guaranteed by mmc (maintenance-free) execution times processing times of ? bit operations min. 0.1 s ? word instructions min. 0.2 s ? fixed-point arithmetic min. 2 s ? floating-point arithmetic min. 6 s
technical data of cpu 31xc 6.3 cpu 313c cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-9 technical data timers/counters and their retentivity s7 counters 256 ? retentive memory configurable ? default from c0 to c7 ? counting range 0 to 999 iec counters yes ? type sfb ? number unlimited (limited on ly by ram size) s7 timers 256 ? retentive memory configurable ? default not retentive ? timer range 10 ms to 9990 s iec timers yes ? type sfb ? number unlimited (limited on ly by ram size) data areas and their retentivity flag bits 256 bytes ? retentive memory configurable ? default retentivity mb0 to mb15 clock flag bits 8 (1 byte per flag bit) data blocks max. 511 (db 1 to db 511) ? length max. 16 kb local data per priority class max. 510 bytes blocks total 1024 (dbs, fcs, fbs) the maximum number of blocks that can be loaded may be reduced if you are using another mmc. obs see the instruction list ? length max. 16 kb nesting depth ? per priority class 8 ? additional within an error ob 4 fbs max. 512 (fb 0 to fb 511) ? length max. 16 kb fcs max. 512 (fc 0 to fc 511) ? length max. 16 kb
technical data of cpu 31xc 6.3 cpu 313c cpu 31xc and cpu 31x, technical data 6-10 manual, edition 08/2004, a5e00105475-05 technical data address areas (i/o) total i/o address area max . 1024 bytes/1024 bytes (can be freely addressed) i/o process image 128 bytes/128 bytes digital channels max. 1016 ? of those local max. 992 ? integrated channels 24 di / 16 do analog channels max. 253 ? of those local max. 248 ? integrated channels 4 + 1 ai / 2 ao assembly racks max. 4 modules per rack max. 8; max. 7 in rack 3 number of dp masters ? integrated none ? via cp max. 2 number of function modules and communication processors you can operate ? fm max. 8 ? cp (ptp) max. 8 ? cp (lan) max. 6 time-of-day real-time clock yes (hw clock) ? buffered yes ? buffered period typically 6 weeks (at an ambient temper ature of 40 c) ? behavior of the clock on expiration of the buffered period the clock keeps running, c ontinuing at the time- of-day it had when powe r was switched off. ? accuracy deviation per day < 10 s operating hour s counter 1 ? number 0 ? value range 2 31 hours (if sfc 101 is used) ? granularity 1 hour ? retentive yes; must be manually restarted after every restart clock synchronization yes ? in the plc master ? on mpi master/slave s7 signaling functions number of stations tha t can be logged on for signaling functions max. 8 (depends on the number of connections configured for pg / op and s7 basic communication)
technical data of cpu 31xc 6.3 cpu 313c cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-11 technical data process diagnostics messages yes ? simultaneously enabled interrupt s blocks max. 20 testing and commissioning functions status/control variables yes ? variables inputs, outputs, memory bits, dbs, timers, counters ? number of variables ? of those as status variable ? of those as control variable max. 30 max. 30 max. 14 forcing yes ? variables inputs, outputs ? number of variables max. 10 block status yes single step yes breakpoints 2 diagnostic buffer yes ? number of entries (not configurable) max. 100 communication functions pg/op communication yes global data communication yes ? number of gd circuits 4 ? number of gd packets ? sending stations ? receiving stations max. 4 max. 4 max. 4 ? length of gd packets ? consistent data max. 22 bytes 22 bytes s7 basic communication yes ? user data per request ? consistent data max. 76 bytes 76 bytes (for x_send or x_rcv) 64 bytes (for x_put or x_get as the server) s7 communication ? as server yes ? as client yes (via cp and loadable fbs) ? user data per request ? consistent data max. 180 bytes (with put/get) 64 bytes s5-compatible communication yes (via cp and loadable fcs) number of connections max. 8
technical data of cpu 31xc 6.3 cpu 313c cpu 31xc and cpu 31x, technical data 6-12 manual, edition 08/2004, a5e00105475-05 technical data can be used for ? pg communication ? reserved (default) ? configurable max. 7 1 from 1 to 7 ? op communication ? reserved (default) ? configurable max. 7 1 from 1 to 7 ? s7 basic communication ? reserved (default) ? configurable max. 4 4 from 0 to 4 routing no interfaces 1st interface type of interface integr ated rs485 interface physics rs 485 electrically isolated no interface power supply (15 to 30 vdc) max. 200 ma functionality ? mpi yes ? profibus dp no ? ptp communication no mpi services ? pg/op communication yes ? routing no ? global data communication yes ? s7 basic communication yes ? s7 communication ? as server ? as client yes no (but via cp and loadable fbs) ? transmission rates max. 187.5 kbps programming programming language lad/fbd/stl available instructions s ee the instruction list nesting levels 8 system functions (sfcs) see the instruction list system function blocks (sfbs) see the instruction list user program security yes
technical data of cpu 31xc 6.3 cpu 313c cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-13 technical data integrated i/o ? default addresses of the integrated ? digital inputs ? digital outputs ? analog inputs ? analog outputs 124.0 to 126.7 124.0 to 125.7 752 to 761 752 to 755 integrated functions counters 3 channels (see the manual technological functions ) frequency counters 3 channels, m ax. 30 khz (see the manual technological functions ) pulse outputs 3 channels for pul se width modulation, max. 2.5 khz (see the manual technological functions ) controlled positioning no integrated "controlling" sfb pi d controller (see the manual technological functions ) dimensions mounting dimensions w x h x d (mm) 120 x 125 x 130 weight 660 g voltages and currents power supply (rated value) 24 vdc ? permitted range 20.4 v to 28.8 v current consumption (no-load operation) typically 150 ma inrush current typically 11 a power consumption (nominal value) 700 ma i 2 t 0.7 a 2 s external fusing of power supply lines (recommended) ls switch type c min. 2 a, ls switch type b min. 4 a, power loss typically 14 w reference in chapter specifications of the integrated i/o you can find ? the specifications o f integrated i/o under digital inputs of cpus 31xc , digital outputs of cpus 31xc, analog inputs of cpus 31xc and analog outputs of cpus 31xc . ? the block diagrams of the integrated i/os under arrangement and usage of integrated i/os .
technical data of cpu 31xc 6.4 cpu 313c-2 ptp and cpu 313c-2 dp cpu 31xc and cpu 31x, technical data 6-14 manual, edition 08/2004, a5e00105475-05 6.4 cpu 313c-2 ptp and cpu 313c-2 dp technical data table 6-5 technical data for cpu 313c-2 ptp/ cpu 313c-2 dp technical data cpu 313c-2 ptp cpu 313c-2 dp cpu and version cpu 313c-2 ptp cpu 313c-2 dp order number 6es7 313-6be01-0ab0 6es7 313-6ce01-0ab0 ? hardware version 01 01 ? firmware version v2.0.0 v2.0.0 associated programming pack age step 7 as of v 5.2 + sp 1 (please use previous cpu for step7 v 5.1 + sp 3 or later) step 7 as of v 5.2 + sp 1 (please use previous cpu for step 7 v 5.1 + sp 3 or later) memory cpu 313c-2 ptp cpu 313c-2 dp ram ? integrated 32 kb ? expandable no load memory plugged in with mmc (max. 8 mb) data storage life on the mmc (following final programming) at least 10 years buffering guaranteed by mmc (maintenance-free) execution times cpu 313c-2 ptp cpu 313c-2 dp processing times of ? bit operations min. 0.1 s ? word instructions min. 0.2 s ? fixed-point arithmetic min. 2 s ? floating-point arithmetic min. 6 s timers/counters and their retentivity cpu 313c-2 ptp cpu 313c-2 dp s7 counters 256 ? retentive memory configurable ? default from c0 to c7 ? counting range 0 to 999 iec counters yes ? type sfb ? number unlimited (limited on ly by ram size) s7 timers 256 ? retentive memory configurable ? default not retentive ? timer range 10 ms to 9990 s iec timers yes ? type sfb ? number unlimited (limited on ly by ram size)
technical data of cpu 31xc 6.4 cpu 313c-2 ptp and cpu 313c-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-15 technical data cpu 313c-2 ptp cpu 313c-2 dp data areas and their retentivity cpu 313c-2 ptp cpu 313c-2 dp flag bits 256 bytes ? retentive memory configurable ? default retentivity mb0 to mb15 clock flag bits 8 (1 byte per flag bit) data blocks max. 511 (db 1 to db 511) ? length max. 16 kb local data per priority class max. 510 bytes blocks cpu 313c-2 ptp cpu 313c-2 dp total 1024 (dbs, fcs, fbs) the maximum number of blocks that can be loaded may be reduced if you are using another mmc. obs see the instruction list ? length max. 16 kb nesting depth ? per priority class 8 ? additional within an error ob 4 fbs max. 512 (fb 0 to fb 511) ? length max. 16 kb fcs max. 512 (fc 0 to fc 511) ? length max. 16 kb address areas (i/o) cpu 313c-2 ptp cpu 313c-2 dp total i/o address area max . 1024 bytes/1024 bytes (can be freely addressed) max. 1024 bytes/1024 bytes (can be freely addressed) ? distributed none max. 1008 bytes i/o process image 128 bytes/128 bytes 128 bytes/128 bytes digital channels max. 1008 max. 8192 ? of those local max. 992 max. 992 ? integrated channels 16 di / 16 do 16 di / 16 do analog channels max. 248 max. 512 ? of those local max. 248 max. 248 ? integrated channels none none assembly cpu 313c-2 ptp cpu 313c-2 dp racks max. 4 modules per rack max. 8; max. 7 in rack 3 number of dp masters ? integrated no 1 ? via cp max. 1 max. 1
technical data of cpu 31xc 6.4 cpu 313c-2 ptp and cpu 313c-2 dp cpu 31xc and cpu 31x, technical data 6-16 manual, edition 08/2004, a5e00105475-05 technical data cpu 313c-2 ptp cpu 313c-2 dp number of function modules and communication processors you can operate ? fm max. 8 ? cp (ptp) max. 8 ? cp (lan) max. 6 time-of-day cpu 313c-2 ptp cpu 313c-2 dp real-time clock yes (hw clock) ? buffered yes ? buffered period typically 6 weeks (at an ambi ent temperatur e of 40 c) ? behavior of the clock on expiration of the buffered period the clock keeps runni ng, continuing at the time-of-day it had w hen power was switched off. ? accuracy deviation per day < 10 s operating hour s counter 1 ? number 0 ? value range 2 31 hours (if sfc 101 is used) ? granularity 1 hour ? retentive yes; must be manually restarted after every restart clock synchronization yes ? in the plc master ? on mpi master/slave s7 signaling functions cpu 313c-2 ptp cpu 313c-2 dp number of stations that can log in for signaling functions (e.g. os) max. 8 (depends on the number of connections confi gured for pg / op an d s7 basic communication) process diagnostics messages yes ? simultaneously enabled interrupt s blocks max. 20 testing and commissioning functions cpu 313c-2 ptp cpu 313c-2 dp status/control variables yes ? variables inputs, outputs, memory bi ts, dbs, timers, counters ? number of variables ? of those as status variable ? of those as cont rol variable max. 30 max. 30 max. 14 forcing yes ? variables inputs, outputs ? number of variables max. 10 block status yes single step yes breakpoints 2 diagnostic buffer yes ? number of entries (not configurable) max. 100
technical data of cpu 31xc 6.4 cpu 313c-2 ptp and cpu 313c-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-17 technical data cpu 313c-2 ptp cpu 313c-2 dp communication functions cpu 313c-2 ptp cpu 313c-2 dp pg/op communication yes global data communication yes ? number of gd circuits 4 ? number of gd packets ? sending stations ? receiving stations max. 4 max. 4 max. 4 ? length of gd packets ? consistent data max. 22 bytes 22 bytes s7 basic communication yes (server) ? user data per request ? consistent data max. 76 bytes 76 bytes (for x_send or x_rcv) 64 bytes (for x_put or x_get as the server) s7 communication ? as server yes ? as client yes (via cp and loadable fbs) ? user data per request ? consistent data max. 180 bytes (with put/get) 64 bytes s5-compatible communication yes (via cp and loadable fcs) number of connections max. 8 can be used for ? pg communication ? reserved (default) ? configurable max. 7 1 from 1 to 7 ? op communication ? reserved (default) ? configurable max. 7 1 from 1 to 7 ? s7-based communication ? reserved (default) ? configurable max. 4 4 from 0 to 4 routing no max. 4 interfaces cpu 313c-2 ptp cpu 313c-2 dp 1st interface type of interface integr ated rs485 interface physics rs 485 electrically isolated no interface power supply (15 to 30 vdc) max. 200 ma functionality ? mpi yes ? profibus dp no ? point-to-point c ommunication no
technical data of cpu 31xc 6.4 cpu 313c-2 ptp and cpu 313c-2 dp cpu 31xc and cpu 31x, technical data 6-18 manual, edition 08/2004, a5e00105475-05 technical data cpu 313c-2 ptp cpu 313c-2 dp mpi services ? pg/op communication yes ? routing no yes ? global data communication yes ? s7 basic communication yes ? s7 communication ? as server ? as client ? ? yes ? no (but via cp and loadable fbs) type of interface integrated rs4 22/rs485 interface integrated r s485 interface physics rs 422/485 rs 485 electrically isolated yes yes interface power supply (15 to 30 vdc) no max. 200 ma number of connections none 8 functionality ? mpi no no ? profibus dp no yes ? point-to-point c ommunication yes no dp master number of connections C 8 services ? pg/op communication C yes ? routing C yes ? global data communication C no ? s7 basic communication C no ? s7 communication C no ? constant bus cycle time C yes ? sync/freeze C yes ? enable/disable dp slaves C yes ? dpv1 C yes ? transmission rates C up to 12 mbps ? number of dp slaves per station C max. 32 ? address area C max. 1 kb i / 1 kb o ? user data per dp slave C max. 244 bytes i / 244 bytes o
technical data of cpu 31xc 6.4 cpu 313c-2 ptp and cpu 313c-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-19 technical data cpu 313c-2 ptp cpu 313c-2 dp dp slave number of connections C 8 services ? pg/op communication C yes ? routing C yes (only if interface is active) ? global data communication C no ? s7 basic communication C no ? s7 communication C no ? direct data exchange C yes ? transmission rates C up to 12 mbps ? automatic baud rate search C yes (only if interface is passive) ? intermediate memory C 244 bytes i / 244 bytes o ? address areas C max. 32, with ma x. 32 bytes each ? dpv1 C no gsd file C the latest gsd f ile is available at: http://www.ad.siemens.de/support in the product support area point-to-poin t communication ? transmission rates 38.4 kbps half duplex 19.2 kbps full duplex C ? cable length max. 1200 m C ? user program can control the interface yes C ? the interface can tr igger a break or an interrupt in the user program yes (message with break id) C ? protocol driver 3964(r); ascii C programming cpu 313c-2 ptp cpu 313c-2 dp programming language lad/fbd/stl available instructions s ee the instruction list nesting levels 8 system functions (sfcs) see the instruction list system function blocks (sfbs) see the instruction list user program security yes integrated i/o cpu 313c-2 ptp cpu 313c-2 dp ? default addresses of the integrated ? digital inputs ? digital outputs 124.0 to 125.7 124.0 to 125.7
technical data of cpu 31xc 6.4 cpu 313c-2 ptp and cpu 313c-2 dp cpu 31xc and cpu 31x, technical data 6-20 manual, edition 08/2004, a5e00105475-05 technical data cpu 313c-2 ptp cpu 313c-2 dp integrated functions counters 3 channels (see the manual technological functions ) frequency counters 3 channels, m ax. 30 khz (see the manual technological functions ) pulse outputs 3 channels for pul se width modulation, max. 2.5 k hz (see the manual technological functions ) controlled positioning no integrated "controlling" sfb pi d controller (see the manual technological functions ) dimensions cpu 313c-2 ptp cpu 313c-2 dp mounting dimensions w x h x d (mm) 120 x 125 x 130 weight approx. 566 g voltages and currents cpu 313c-2 ptp cpu 313c-2 dp power supply (rated value) 24 vdc ? permitted range 20.4 v to 28.8 v current consumption (no-load operation) typically 100 ma inrush current typically 11 a power consumption (nomin al value) 700 ma 900 ma i 2 t 0.7 a 2 s external fusing of power supply lines (recommended) ls switch type b: min. 4 a, type c: min. 2 a power loss typically 10 w reference in chapter specifications of the integrated i/o are found ? under digital inputs of cpus 31xc and digital outputs of cpus 31xc the technical data of integrated i/os. ? the block diagrams of the integrated i/os under arrangement and usage of integrated i/os .
technical data of cpu 31xc 6.5 cpu 314c-2 ptp and cpu 314c-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-21 6.5 cpu 314c-2 ptp and cpu 314c-2 dp technical data table 6-6 technical data of cpu 314c-2 ptp and cpu 314c-2 dp technical data cpu 314c-2 ptp cpu 314c-2 dp cpu and version cpu 314c-2 ptp cpu 314c-2 dp order number 6es7 314-6bf01-0ab0 6es7 314-6cf01-0ab0 ? hardware version 01 01 ? firmware version v2.0.0 v2.0.0 associated programming pack age step 7 as of v 5.2 + sp 1 (please use previous cpu for step 7 v 5.1 + sp 3 or later) step 7 as of v 5.2 + sp 1 (please use previous cpu for step 7 v 5.1 + sp 3 or later) memory cpu 314c-2 ptp cpu 314c-2 dp ram ? integrated 48 kb ? expandable no load memory plugged in with mmc (max. 8 mb) data storage life on the mmc (following final programming) at least 10 years buffering guaranteed by mmc (maintenance-free) execution times cpu 314c-2 ptp cpu 314c-2 dp processing times of ? bit operations min. 0.1 s ? word instructions min. 0.2 s ? fixed-point arithmetic min. 2 s ? floating-point arithmetic min. 6 s timers/counters and their retentivity cpu 314c-2 ptp cpu 314c-2 dp s7 counters 256 ? retentive memory configurable ? default from c0 to c7 ? counting range 0 to 999 iec counters yes ? type sfb ? number unlimited (limited on ly by ram size) s7 timers 256 ? retentive memory configurable ? default not retentive ? timer range 10 ms to 9990 s iec timers yes ? type sfb ? number unlimited (limited on ly by ram size)
technical data of cpu 31xc 6.5 cpu 314c-2 ptp and cpu 314c-2 dp cpu 31xc and cpu 31x, technical data 6-22 manual, edition 08/2004, a5e00105475-05 technical data cpu 314c-2 ptp cpu 314c-2 dp data areas and their retentivity cpu 314c-2 ptp cpu 314c-2 dp flag bits 256 bytes ? retentive memory configurable ? default retentivity mb0 to mb15 clock flag bits 8 (1 byte per flag bit) data blocks max. 511 (db 1 to db 511) ? length max. 16 kb local data per priority class max. 510 bytes blocks cpu 314c-2 ptp cpu 314c-2 dp total 1024 (dbs, fcs, fbs) the maximum number of blocks that can be loaded may be reduced if you are using another mmc. obs see the instruction list ? length max. 16 kb nesting depth ? per priority class 8 ? additional within an error ob 4 fbs max. 512 (fb 0 to fb 511) ? length max. 16 kb fcs max. 512 (fc 0 to fc 511) ? length max. 16 kb address areas (i/o) cpu 314c-2 ptp cpu 314c-2 dp total i/o address area max . 1024 bytes/1024 bytes (can be freely addressed) max. 1024 bytes/1024 bytes (can be freely addressed) ? distributed none max. 1000 bytes i/o process image 128 bytes/128 bytes 128 bytes/128 bytes digital channels max. 1016 max. 8192 ? of those local max. 992 max. 992 ? integrated channels 24 di / 16 do 24 di / 16 do analog channels max. 253 max. 512 ? of those local max. 248 max. 248 ? integrated channels 4 + 1 ai / 2 ao 4 + 1 ai / 2 ao assembly cpu 314c-2 ptp cpu 314c-2 dp racks max. 4 modules per rack max. 8; max. 7 in rack 3 number of dp masters ? integrated no 1 ? via cp max. 1 max. 1
technical data of cpu 31xc 6.5 cpu 314c-2 ptp and cpu 314c-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-23 technical data cpu 314c-2 ptp cpu 314c-2 dp number of function modules and communication processors you can operate ? fm max. 8 ? cp (ptp) max. 8 ? cp (lan) max. 10 time-of-day cpu 314c-2 ptp cpu 314c-2 dp real-time clock yes (hw clock) ? buffered yes ? buffered period typically 6 weeks (at an ambi ent temperatur e of 40 c) ? behavior of the clock on expiration of the buffered period the clock keeps runni ng, continuing at the time-of-day it had w hen power was switched off. ? accuracy deviation per day < 10 s operating hour s counter 1 ? number 0 ? value range 2 31 hours (if sfc 101 is used) ? granularity 1 hour ? retentive yes; must be manually restarted after every restart clock synchronization yes ? in the plc master ? on mpi master/slave s7 signaling functions cpu 314c-2 ptp cpu 314c-2 dp number of stations that can log in for signaling functions (e.g. os) max. 12 (depends on the number of connections confi gured for pg / op an d s7 basic communication) process diagnostics messages yes ? simultaneously enabled interrupt s blocks max. 40 testing and commissioning functions cpu 314c-2 ptp cpu 314c-2 dp status/control variables yes ? variables inputs, outputs, memory bi ts, dbs, timers, counters ? number of variables ? of those as status variable ? of those as control variable max. 30 max. 30 max. 14 forcing yes ? variables inputs, outputs ? number of variables max. 10 block status yes single step yes breakpoints 2 diagnostic buffer yes ? number of entries (not configurable) max. 100
technical data of cpu 31xc 6.5 cpu 314c-2 ptp and cpu 314c-2 dp cpu 31xc and cpu 31x, technical data 6-24 manual, edition 08/2004, a5e00105475-05 technical data cpu 314c-2 ptp cpu 314c-2 dp communication functions cpu 314c-2 ptp cpu 314c-2 dp pg/op communication yes global data communication yes ? number of gd circuits 4 ? number of gd packets ? sending stations ? receiving stations max. 4 max. 4 max. 4 ? length of gd packets ? consistent data max. 22 bytes 22 bytes s7 basic communication yes ? user data per request ? consistent data max. 76 bytes 76 bytes (for x_send or x_rcv) 64 bytes (for x_put or x_get as the server) s7 communication ? as server yes ? as client yes (via cp and loadable fbs) ? user data per request ? consistent data max. 180 bytes (with put/get) 64 bytes s5-compatible communication yes (via cp and loadable fcs) number of connections max. 12 can be used for ? pg communication ? reserved (default) ? configurable max. 11 1 from 1 to 11 ? op communication ? reserved (default) ? configurable max. 11 1 from 1 to 11 ? s7-based communication ? reserved (default) ? configurable max. 8 8 from 0 to 8 routing no max. 4 interfaces cpu 314c-2 ptp cpu 314c-2 dp 1st interface type of interface integr ated rs485 interface physics rs 485 electrically isolated no interface power supply (15 to 30 vdc) max. 200 ma functionality ? mpi yes ? profibus dp no ? point-to-point c ommunication no
technical data of cpu 31xc 6.5 cpu 314c-2 ptp and cpu 314c-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-25 technical data cpu 314c-2 ptp cpu 314c-2 dp mpi number of connections 12 services ? pg/op communication yes ? routing no yes ? global data communication yes ? s7 basic communication yes ? s7 communication ? as server ? as client yes no (but via cp and loadable fbs) ? transmission rates max. 187.5 kbps 2nd interface cpu 314c-2 ptp cpu 314c-2 dp type of interface integrated rs4 22/rs485 interface integrated r s485 interface physics rs 422/485 rs 485 electrically isolated yes yes interface power supply (15 to 30 vdc) no max. 200 ma number of connections none 12 functionality ? mpi no no ? profibus dp no yes ? point-to-point c ommunication yes no dp master number of connections C 12 services ? pg/op communication C yes ? routing C yes ? global data communication C no ? s7 basic communication C no ? s7 communication C no ? constant bus cycle time C yes ? sync/freeze C yes ? enable/disable dp slaves C yes ? dpv1 C yes ? transmission rates C up to 12 mbps ? number of dp slaves per station C max. 32 ? address area C max. 1 kb i / 1 kb o ? user data per dp slave C max. 244 bytes i / 244 bytes o
technical data of cpu 31xc 6.5 cpu 314c-2 ptp and cpu 314c-2 dp cpu 31xc and cpu 31x, technical data 6-26 manual, edition 08/2004, a5e00105475-05 technical data cpu 314c-2 ptp cpu 314c-2 dp dp slave number of connections C 12 services ? pg/op communication C yes ? routing C yes (only if interface is active) ? global data communication C no ? s7 basic communication C no ? s7 communication C no ? direct data exchange C yes ? transmission rates C up to 12 mbps ? intermediate memory C 244 bytes i / 244 bytes o ? automatic baud rate search C yes (only if interface is passive) ? address areas max. 32, with ma x. 32 bytes each ? dpv1 C no gsd file C the latest gsd f ile is available at: http://www.ad.siemens.de/support in the product support area point-to-poin t communication ? transmission rates 38.4 kbps half duplex 19.2 kbps full duplex C ? cable length max. 1200 m C ? user program can control the interface yes C ? the interface can tr igger a break or an interrupt in the user program yes (message with break id) C ? protocol driver 3964 (r); ascii and rk512 C programming cpu 314c-2 ptp cpu 314c-2 dp programming language lad/fbd/stl available instructions s ee the instruction list nesting levels 8 system functions (sfcs) see the instruction list system function blocks (sfbs) see the instruction list user program security yes integrated i/o cpu 314c-2 ptp cpu 314c-2 dp ? default addresses of the integrated ? digital inputs ? digital outputs ? analog inputs ? analog outputs 124.0 to 126.7 124.0 to 125.7 752 to 761 752 to 755
technical data of cpu 31xc 6.5 cpu 314c-2 ptp and cpu 314c-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-27 technical data cpu 314c-2 ptp cpu 314c-2 dp integrated functions counters 4 channels (see the manual technological functions ) frequency counters 4 channels, m ax. 60 khz (see the manual technological functions ) pulse outputs 4 channels for pul se width modulation, max. 2.5 k hz (see the manual technological functions ) controlled positioning 1 channel (see the manual technological functions ) integrated "controlling" sfb pi d controller (see the manual technological functions ) dimensions cpu 314c-2 ptp cpu 314c-2 dp mounting dimensions w x h x d (mm) 120 x 125 x 130 weight approx. 676 g voltages and currents cpu 314c-2 ptp cpu 314c-2 dp power supply (rated value) 24 vdc ? permitted range 20.4 v to 28.8 v current consumption (no-load operation) typically 150 ma inrush current typically 11 a power consumption (nomin al value) 800 ma 1000 ma i 2 t 0.7 a 2 s external fusing of power supply lines (recommended) ls switch type c min. 2 a, ls switch type b min. 4 a power loss typically 14 w
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-28 manual, edition 08/2004, a5e00105475-05 6.6 technical data of the integrated i/o 6.6.1 arrangement and usa ge of integrated i/os introduction integrated i/os of cpu s 31xc can be used for technological func tions or as standard i/o. the figures below illu strate possible usa ge of i/os integrated in the cpus. reference further information on integr ated i/o is found in the manual technical functions . cpu 312c: pin-out of the integrated di/do (connector x11) 1 2 3 4 5 6 8 7 9 10 11 12 13 14 16 15 17 18 20 19 standard x11 di di di di+0.1 di+0.2 di+0.3 di+0.4 di+0.5 di+0.6 di+0.7 interrupt input x x x x x x x x count z0 (a) z0 (b) z0 (hw gate) z1 (a) z1 (b) z1 (hw gate) latch 0 latch 1 v0 v1 di+0.0 di+1.1 do+0.0 do+0.1 do+0.2 do+0.3 do+0.4 do+0.5 di+1.0 di di di di di di di x x do do do do do do 2m 1l+ 1m zn counter n a, b encoder signals vn comparator n x pin usable if not assigned to technology function s hw gate gate control latch store counter distance
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-29 block diagram of the integrated digital i/o cpu interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2m 1m 1l+
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-30 manual, edition 08/2004, a5e00105475-05 cpu 313c, cpu 313c-2 dp/ptp, cpu 314c-2 dp/ptp: di/do (connecto rs x11 and x12) 1 2 3 4 5 6 8 7 9 10 11 12 13 14 16 15 17 18 20 19 standard di posi- tioning x11 of cpu 313c-2 ptp/dp x12 of cpu 314c-2 ptp/dp 21 22 23 24 25 26 28 27 29 30 31 32 33 34 36 35 37 38 40 39 x x x x x x x x di+0.1 di+0.2 di+0.3 di+0.4 di+0.5 di+0.6 di+0.7 x x x x x x x x interrupt input x x x x x x x x x x x x x x x x count z0 (a) z0 (b) z0 (hw gate) z1 (a) z1(b) z1 (hw gate) z2 (a) z2 (b) z2 (hw gate) z3 (a) z3 (b) z3 (hw gate) z0 (latch) z1 (latch) z2 (latch) z3 (latch) a0 b0 n0 prob 0 bero 0 positioning digital analog conv_en r+ rapid r- creep count v0 v1 v2 v3 standard do x x x x x x x x x x x x x x x x di+0.0 di+1.1 di+1.2 di+1.3 di+1.4 di+1.5 di+1.6 di+1.7 di+1.0 do+0.1 do+0.2 do+0.3 do+0.4 do+0.5 do+0.6 do+0.7 do+0.0 do+1.1 do+1.2 do+1.3 do+1.4 do+1.5 do+1.6 do+1.7 do+1.0 1) 1) 1l+ 2l+ 2m 3l+ 1) 1m 3m 1) 1) conv_dir 1) cpu 314c-2 only zn counter n a, b encoder signals hw gate gate control latch store counter distance vn comparator n prob 0 measuring probe 0 bero 0 reference point switch 0 r+, r- directional signal rapid rapid traverse creep creep speed conv_en power section enable conv_dir directional signal (only with control type "voltage 0 to 10 v or current from 0 to 10 ma and directional signal") x pin usable if not assigned to technology functions reference details are found in the manual technical functions under counting, frequency measurement and pulse width modulation
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-31 block diagram of integrated digital i/o of cpus 313c/313c-2/314 c-2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 cpu interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2l+ 3m 1l+ 1m 2m 3l+
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-32 manual, edition 08/2004, a5e00105475-05 cpu 313c/314c-2: pin-out of the integrated ai/ao and di (connec tor x11) 1 2 3 4 5 6 8 7 9 10 11 12 13 14 16 15 17 18 20 19 standard positioning ai (ch0) ai (ch1) ai (ch2) ai (ch3) pt 100 (ch4) ao (ch0) ao (ch1) control output 0 x11 pewx+0 pewx+2 pewx+4 pewx+6 pewx+8 paw x+0 paw x+2 standard di 21 22 23 24 25 26 28 27 29 30 31 32 33 34 36 35 37 38 40 39 x x x x x x x x di+2.1 di+2.2 di+2.3 di+2.4 di+2.5 di+2.6 di+2.7 di+2.0 1) v i c v i c v i c v i c v a v a 4m m ana interrupt input x x x x x x x x 1) cpu 314c-2 only block diagram of integrated digital/analog i/o of cpus 313c/314 c-2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ai0 4m ai ai/a0 8di ai ai ai a0 a0 ai ch0 ch1 ch2 ch3 ch0 ch1 pt100 u u i i cpu interface ai2 ai1 a v a v a v ai3 a v ai4 r ao0 ao1 m ana v a v a controller
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-33 simultaneous usage of technological functions and standard i/o technological functions and stand ard i/o can be used simultaneo usly with appropriate hardware. for example, you can use all digital inputs not used for counting functions as standard di. read access to inputs used by te chnological functions is possib le. write access to outputs used by technological functions is not possible. see also cpu 312c (page 6-3) cpu 313c (page 6-8) cpu 313c-2 ptp and cp u 313c-2 dp (page 6-14) cpu 314c-2 ptp and cp u 314c-2 dp (page 6-21)
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-34 manual, edition 08/2004, a5e00105475-05 6.6.2 analog i/o wiring of the current/voltage inputs the figure below shows the wiring diagram of the current/voltag e inputs operated with 2-/4-wire measuring transducers. 2-wire signal converter ai2 ai2 ai2 u i c 8 9 10 m m ana 20 we recommend connecting aix c with m ana using a bridge. + - + +24v - al 0 : pin 2 to 4 ai 1 : pin 5 to 7 al 2 : pin 8 to 10 al 3 : pin 11 to 13 figure 6-1 connection of a 2-wir e measuring transducer to an an alog current/vol tage input of cpu 313c/314c-2 4-wire signal converter ai : pin 2 to 4 ai : pin 5 to 7 ai : pin 8 to 10 ai : pin 11 to 13 0 1 2 3 l+ ai2 ai2 ai2 ai3 ai3 ai3 u i c u i c 8 9 10 11 12 13 m ana 20 m m + - + - short-circuit non-wired input channels and connect alx c with m ana . we recommend connecting alx c with m ana when using the 4-wire signal converter. figure 6-2 connection of a 4-wir e measuring transducer to an an alog current/vol tage input of cpu 313c/314c-2
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-35 measurement principle 31xc cpus use the measurement principle of actual value encodin g. here, they operate with a sampling rate of 1 khz. t hat is, a new value is availabl e at the peripheral input word register once every millisecond . this value can then be read vi a user program (e.g. l pew). the "previous" value is read again if access times are shorter than 1 ms. integrated hardware low-pass filter an integrated low-pass filter attenuates analog input signals o f channel 0 to 3. they are attenuated according to the trend in the figure below. attenuation <1% attenuation <10% strong attenuation 100 % input frequency internal signal level 400 hz 63 % 200 hz 50 hz inadmissible input frequency figure 6-3 low-pass characterist ics of the integrated filter note the maximum frequency of t he input signal is 400 hz.
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-36 manual, edition 08/2004, a5e00105475-05 input filters (software filter) the current / voltage inputs have a software filter for the inp ut signals which can be programmed with step 7. it filter s the configured interference frequency (50/60 hz) and multiples thereof. the selected interference suppr ession also determines the integ ration time. at an interference su ppression of 50 hz the software filter fo rms the average based on the last 20 measurements and saves t he result as a measurement valu e. you can suppress interference fr equencies (50 hz or 60 hz) acco rding to the parameters set in step 7. a setting of 400 hz will not suppress interference. an integrated low-pass filter attenuates analog input signals o f channel 0 to 3. a i x selection in step 7 (software filter) 50-hz configuration (mean value filter) 60-hz configuration (mean value filter) a/d converter 400-hz configuration hardware low-pass filter (rc circuit) figure 6-4 principle of interfe rence suppression with step 7
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-37 in the two graphics below we illustrate how the 50 hz and 60 hz interference suppression work 1.05 ms value 1 value 2 value 3 ... value 19 value 20 value 1 value 2 value 3 ... value 19 value 20 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms example of a 50-hz parasitic frequency suppression (integration time corresponds to 20 ms ) 1 averaged measured value 1 averaged measured value cycle 1 cycle 2 figure 6-5 50 hz interference suppression
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-38 manual, edition 08/2004, a5e00105475-05 value 1 value 2 value 3 ... value 16 value 17 value 1 value 2 value 3 ... value 16 value 17 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms 1.05 ms example of a 60-hz parasitic frequency suppression (integration time corresponds to 16.7 ms) 1 averaged measured value 1 averaged measured value cycle 1 cycle 2 figure 6-6 60 hz interference suppression note if the interference frequency is no t 50/60 hz or a multiple the reof, the input signal must be filtered externally. in this case, 400 hz frequency s uppression must be configured f or the respective input. this is equivalent to a "deactiva tion" of the software filter. inputs not connected the three inputs of a current/voltage analog output channel tha t is not connected should be bypasses and connected to m ana (pin 20 of the front connector). this ensures maximum interference resistance for these analog inputs. outputs not connected in order to disconnect unused analog outputs from power, you mu st disable and leave them open during parameter assignment with step 7. reference details (visualization and proc essing of analog values, for exa mple) are found in chapter 4 of the module data reference manual.
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-39 6.6.3 configuration introduction you configure the integrated i/o of cpu 31xc with step 7. alway s make these settings when the cpu is in stop. the gene rated parameters are downloade d from the pg to the S7-300 and written to cpu memory . you can also choose to change t he parameters at sfc 55 in the u ser program (see the reference manual system and standard functions ). refer to the structure of record 1 for the respective parameters. parameters of standard di the table below gives you an ov erview of the parameters for sta ndard digital inputs. table 6-7 parameters of standard di parameters value range default range of efficiency input delay (ms) 0,1/0, 5/3/15 3 channel group the table below gives you an ov erview of the parameters when us ing digital inputs as interrupt inputs. table 6-8 parameters of the interrupt inputs parameters value range default range of efficiency interrupt input disabled / positive edge disabled digital input interrupt input disabled/ negative edge disabled digital input
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-40 manual, edition 08/2004, a5e00105475-05 byte 0 7 7 7 7 7 byte 1 byte 2 byte 4 byte 5 byte 8 7 byte 9 7 byte 6 00 01 10 11 : b b b b : : : 3 0,1 ms 0,5 ms 15 ms ms 0: 1: 00 b 7 0 bit-nr. byte 0 0 bit-nr. 0 bit-nr. 0 bit-nr. 0 bit-nr. 0 bit-nr. 0 bit-nr. 0 bit-nr. 0: 1: interrupt input di +0.1 interrupt input di +0.0 interrupt input di +0.7 default setting: deactivated rising edge input delay di +0.0 to di +0.3 input delay di +0.4 to di +0.7 input delay di +1.0 to di +1.3 input delay di +1.4 to di +1.7 input delay di +2.0 to di +2.3 input delay di +2.4 to di +2.7 reserved default setting: byte 3 reserved interrupt input di +1.1 interrupt input di +1.0 interrupt input di +1.7 interrupt input di +2.1 interrupt input di +2.0 interrupt input di +2.7 interrupt input di +0.1 interrupt input di +0.0 interrupt input interrupt input di +1.1 interrupt input di +1.0 interrupt input di +1.7 default setting: deactivated rising edge interrupt input di +2.1 interrupt input di +2.0 interrupt input di +2.7 byte 7 reserved figure 6-7 structure of record 1 for standard di and interrupt inputs (length of 10 bytes)
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-41 parameters of standard do there are no parameters for standard digital outputs. parameters of standard ai the table below gives you an ov erview of the parameters for sta ndard analog inputs. table 6-9 parameters of standard ai parameters value range default range of efficiency integration time (ms) interference suppression (hz) (channel 0 to 3) 2,5/16,6/20 400/60/50 20 50 channel channel measurement range (channel 0 to 3) disabled/ +/- 20 ma/ 0 ... 20 ma/ 4 ... 20 ma/ +/- 10 v/ 0 ... 10 v +/- 10 v channel type of measurement (channel 0 to 3) disabled/ v voltage/ i current u voltage channel unit of measurement (channel 4) celsius/fahrenheit/ kelvin celsius channel measurement range (pt 100 input; channel 4) disabled/ pt 100/600 600 channel type of measurement (pt 100 input; channel 4) disabled/ resistor/ thermocouple resistance channel reference see also chapter 4.3 in the module data reference manual.
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-42 manual, edition 08/2004, a5e00105475-05 parameters of standard ao the table below gives you an ov erview of standard analog output parameters (see also chapter 4.3 in the module data reference manual). table 6-10 paramet ers of standard ao parameters value range default range of efficiency output range (channel 0 to 1) disabled/ +/- 20 ma/ 0 ... 20 ma/ 4 ... 20 ma/ +/- 10 v/ 0 ... 10 v +/- 10 v channel type of output (channel 0 to 1) disabled/ v voltage/ i current u voltage channel
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-43 reserved unit of measure reserved default setting: celsius fahrenheit kelvin parasitic frequency suppression integration time of channel ai 0 default setting: measuring range of channel ai 0 (settings see byte 6) measurement type of channel ai 0 (settings see byte 6) 0 bit no. measuring range of channel ai 3 measurement type of channel ai 3 default setting: deactivated v voltage i current i current default setting: deactivated measuring range of channel ai 3 measurement type of channel ai 4 default setting: deactivated resistance thermal resistance default setting: deactivated reserved parasitic frequency suppression integration time of channel ai 1 parasitic frequency suppression integration time of channel ai 2 parasitic frequency suppression integration time of channel ai 3 measuring range of channel ai 1 (settings see byte 6) measurement type of channel ai 1 (settings see byte 6) measuring range of channel ai 2 (settings see byte 6) measurement type of channel ai 2 (settings see byte 6) % % pv +] pv +] pv +] + + + + 1 p$ 1 p$ p$ 1 9 9 + + + + + + + + 2kp 3w %lw1u %lw1u %lw1u %lw1u %lw1u %lw1u %lw1u + + + + + + + + % % % % % % %\wh %\wh %\wh %\wh %\wh %\wh %\wh %\wh %\whelv
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-44 manual, edition 08/2004, a5e00105475-05 %lw1u %lw1u %\wh %\wh %\wh 0: 2: 3: 4: 8: 9: 9 h h h h h h h 0 ? 20 ma 4 ? 20 ma +/- 20 ma 0 ? 10 v +/- 10 v 0: 1: 3: 9 h h h h output range of channel ao 1 deactivated default setting: output range of channel ao 1 deactivated default setting: v voltage i current output range of channel ao 0 output range of channel ao 0 (setting see byte 12) (setting see byte 12) figure 6-8 structure of record 1 for standard ai/ao (length of 13 bytes) parameter for technological functions the parameters for the respective function are found in the man ual technological functions .
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-45 6.6.4 interrupts interrupt inputs all digital inputs of the on-boar d i/o of cpus 31xc can be used as interrupt inputs. you can specify interrupt behavior for each individual input in your parameter declaration. options are: ? no interrupt ? interrupt at the positive edge ? interrupt at the negative edge ? interrupt at the positive and negative edge note every channel will hol d one event if the rate of incoming inter rupts exceeds the handling capacity of ob40. further event s (interrupts) will be lost, wit hout diagnostics or explicit message. start information for ob40 the table below shows the relev ant temporary variables (temp) o f ob40 for the interrupt inputs of 31xc cpus. a descripti on of process interrupt ob 40 i s found in the reference manual system and standard functions . table 6-11 start information fo r ob40, relating to the interrup t inputs of the integrated i/o byte variables data type description 6/7 ob40_mdl_addr word b#16#7c address of the interrupt- triggering module (here: default addresses of the digital inputs) 8 on ob40_point_addr dword see the figure below displaying the interrupt- triggering integrated inputs
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-46 manual, edition 08/2004, a5e00105475-05 31 30 29 28 27 26 25 24 16 15 ? 8 7654321 ? bit no. pral: process interrupt inputs are designated with default addresses. reserved 23 pral from e124.0 pral from e124.7 pral from e125.0 pral from e125.7 pral from e126.0 pral from e126.7 figure 6-9 displaying the status es of cpu 31xc interrupt inputs pral: process interrupt the inputs are assign ed default addresses. 6.6.5 diagnostics standard i/o diagnostic data is not availabl e for integrated i/o which is op erated as standard i/o (see also the reference manual module data ). technological functions diagnostics options for the respective technological function a re found in the manual technological functions . 6.6.6 digital inputs introduction this section provides the specifications for the digital inputs of cpus 31xc. the table includes the following cpus: ? under cpu 313c-2, the cpu 313c-2 dp and cpu 313c-2 ptp ? under cpu 314c-2, the cpu 314c-2 dp and cpu 314c-2 ptp
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-47 technical data table 6-12 technical data of digital inputs technical data cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 module-specific data cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 number of inputs 10 24 16 24 ? number of these inputs which can be used for technological functions 8 12 12 16 cable length ? unshielded for standard di: max. 600 m for technological functions: no for standard di: max. 1000 m for technological function at max. counting frequency ? shielded 100 m 100 m 100 m 50 m voltage, currents, potentials cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 rated load voltage l+ 24 vdc ? polarity reversal protection yes number of inputs whic h can be controlled simultaneously ? horizontal assembly ? up to 104 f ? up to 60 c 10 5 24 12 16 8 24 12 ? vertical assembly ? up to 104 f 5 12 8 12 electrical isolation ? between channels and the backplane bus yes ? between the channels no permitted potential difference ? between different circuits 75 vdc / 60 vac insulation test voltage 500 vdc current consumption ? on load voltage l+ (no-load) C max. 70 ma max. 70 ma max. 70 ma status, interrupts, diagnostics cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 status display green led per channel interrupts ? yes, if the corresponding channel is configured as interrupt in put ? for using technological functions, please refer to the technological functions manual. diagnostics functions ? no diagnostics when ope rated as standard i/o ? for using technological functions, please refer to the technological functions manual.
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-48 manual, edition 08/2004, a5e00105475-05 technical data cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 data for the selection of an encoder for standard di cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 input voltage ? rated value 24 vdc ? for signal "1" 15 v to 30 v ? for signal "0" -3 v to 5 v input current ? for signal "1" typically 9 ma delay of standard inputs ? configurable yes (0.1 / 0.5 / 3 / 15 ms) you can reconfigure the input delay of the standard inputs duri ng program runtime. please note that your newly set filter time may only t ake effect after the previously set filter time has expired. ? rated value 3 ms for using technological functions: "minimum pulse width/ minimum pause between pulses at maximum counting frequency" 48 s 16 s 16 s 8 s input characteristics curve to iec 1131, type 1 connection of 2-wire beros possible ? permitted quiescent current max. 1,5 ma 6.6.7 digital outputs introduction this chapter contains the specif ications for the digital output s of cpus 31xc. the table includes the following cpus: ? under cpu 313c-2, the cpu 313c-2 dp and cpu 313c-2 ptp ? under cpu 314c-2, the cpu 314c-2 dp and cpu 314c-2 ptp fast digital outputs technological functions us e fast digital outputs.
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-49 technical data table 6-13 technical dat a of digital outputs technical data cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 module-specific data cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 number of outputs 6 16 16 16 2 4 4 4 ? of those are fast outputs caution: you cannot connect the high-spee d outputs of your cpu in parall el. cable length ? unshielded max. 600 m ? shielded max. 1000 m voltage, currents, potentials cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 rated load voltage l+ 24 vdc ? polarity reversal protection no total current of outputs (per group) max. 2.0 a max. 3,0 a m ax. 3,0 a max. 3,0 a ? horizontal assembly ? up to 104 f ? up to 60 c max. 1,5 a max. 2.0 a m ax. 2.0 a max. 2.0 a ? vertical assembly ? up to 104 f max. 1,5 a max. 2.0 a m ax. 2.0 a max. 2.0 a electrical isolation ? between channels and the backplane bus yes no yes yes yes ? between the channels ? in groups of C 8 8 8 permitted potential difference ? between different circuits 75 vdc / 60 vac insulation test voltage 500 vdc current consumption ? with load voltage l+ max. 50 ma max. 100 ma m ax. 100 ma max. 100 ma status, interrupts, diagnostics cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 status display green led per channel interrupts ? no interrupts when o perated as standard i/o ? for using technological functions, please refer to the technological functions manual. diagnostics functions ? no diagnostics when ope rated as standard i/o ? for using technological functions, please refer to the technological functions manual.
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-50 manual, edition 08/2004, a5e00105475-05 technical data cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 data for the selection of an actuator for standard di cpu 312c cpu 313c cpu 313c-2 cpu 314c-2 output voltage ? for signal "1" min. l+ (-0.8 v) output current ? for signal "1" ? rated value ? permitted range 0,5 a 5 ma to 600 ma ? for signal "0" (residual current) max. 0.5 ma load impedance range 48 to 4 k lamp load max. 5 w parallel connecti on of 2 outputs ? for redundant load control possible ? for performance increase not possible controlling of digital inputs possible switching frequency ? under resistive load max. 100 hz ? for inductive load to iec 947-5, dc13 max. 0.5 hz ? under lamp load max. 100 hz ? fast outputs under resistive load max. 2.5 khz inductive breaking voltage limit ed internally to typically (l+) - 48 v short-circuit protection o f the output yes, electronic ? response threshold typically 1 a
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-51 6.6.8 analog inputs introduction this chapter contains the specif ications for analog outputs of cpus 31xc. the table includes the following cpus: ? cpu 313c ? cpu 314c-2 dp ? cpu 314c-2 ptp technical data table 6-14 technical data of analog inputs technical data module-specific data number of inputs 4 channels with current/voltage input 1 channel with resistance input cable length ? shielded max. 100 m voltage, currents, potentials resistance input ? no-load voltage typically 2.5 v ? measurement current typically 1.8 ma to 3.3 ma electrical isolation ? between channels and the backplane bus yes ? between the channels no permitted potential difference ? between inputs (ai c ) and m ana (u cm ) 8.0 vdc ? between m ana and m internal (u iso ) 75 vdc / 60 vac insulation test voltage 600 vdc analog value generation measurement principle actual value encoding (successive approximation) integration time/conversion time /resolution (per channel) ? configurable yes ? integration time in ms 2,5 / 16,6 / 20 ? permitted input frequency max. 400 hz ? resolution (including overdrive) 11 bits + signed bit ? suppression of interference frequency f1 400 / 60 / 50 hz
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-52 manual, edition 08/2004, a5e00105475-05 technical data time constant of the in put filter 0,38 ms basic processing time 1 ms interference suppression, error limits interference voltage su ppression for f = nx (f1 1 %), (f1 = i nterference frequency), n = 1, 2 ? common-mode interference (u cm < 1.0 v) > 40 db ? feedback interference (peak value of the interference < rated v alue of the input range) > 30 db crosstalk between the inputs > 60 db operational error limits (across the temperature range, in rela tion to input range) ? voltage/current < 1 % ? resistance < 5 % basic error limit (operational limit at 25 c, in relation to i nput range) ? voltage/current < 0,7 % ? resistance < 3 % temperature error (in relati on to input range) 0,006 %/k linearity error (referr ed to input range) 0,06 % repeat accuracy (in tr ansient state at 25 c , in relation to in put range) 0,06 % status, interrupts, diagnostics interrupts ? no interrupts when o perated as standard i/o diagnostics functions ? no diagnostics when operated as standard i/o ? for using technological functions, please refer to the technological functions manual. encoder selection data input ranges (rated val ue)/input resistance ? voltage 10 v/100 k 0 v to 10 v/100 k ? current 20 ma/50 0 ma to 20 ma/50 4 ma to 20 ma/50 ? resistance 0 to 600 /10 m ? resistance thermometer pt 100/10 m permitted continuous input v oltage (destruction limit) ? for voltage inputs max. 30 v ? for current inputs max. 2.5 v permitted continuous input current (destruction limit) ? for voltage inputs max. 0,5 ma; ? for current inputs max. 50 ma;
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-53 technical data connection of signal generators ? for voltage measurement possible ? for current measurement ? as 2-wire measuring transducer ? as 4-wire measuring transducer possible, with external power supply possible ? for measuring resistance ? with 2-wire connection ? with 3-wire connection ? with 4-wire connection possible, without compensation of cable resistance not possible not possible linearization of the charac teristics trend by software ? for resistance thermometers pt 100 temperature compensation no technical unit for temperature measurement degr ees celsius/fahr enheit/kelvin 6.6.9 analog outputs introduction this chapter contains the specif ications for digital outputs of cpus 31xc. the table includes the following cpus: ? cpu 313c ? cpu 314c-2 dp ? cpu 314c-2 ptp technical data table 6-15 technical data of analog outputs technical data module-specific data number of outputs 2 cable length ? shielded max. 200 m voltage, currents, potentials rated load voltage l+ 24 vdc ? polarity reversal protection yes electrical isolation ? between channels and the backplane bus yes ? between the channels no
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-54 manual, edition 08/2004, a5e00105475-05 technical data permitted potential difference ? between m ana and m internal (u iso ) 75 vdc / 60 vac insulation test voltage 600 vdc analog value generation resolution (including overdrive) 11 bits + signed bit conversion time (per channel) 1 ms settling time ? with resistive load 0,6 ms ? with capacitive load 1,0 ms ? with inductive load 0.5 ms interference suppression, error limits crosstalk between the outputs > 60 db operational error limits (across the temperature range, in rela tion to output range) ? voltage/current 1 % basic error limit (operational limit at 25 c, in relation to o utput range) ? voltage/current 0,7 % temperature error (in relati on to output range) 0.01 %/k linearity error (in relati on to output range) 0,15 % repeat accuracy (in tr ansient state at 25 c , in relation to ou tput range) 0,06 % output ripple; bandw idth 0 to 50 khz (in relation to output ran ge) 0,1 % status, interrupts, diagnostics interrupts ? no interrupts when o perated as standard i/o ? for using technological functions, please refer to the technological functions manual. diagnostics functions ? no diagnostics when operated as standard i/o ? for using technological functions, please refer to the technological functions manual. actuator selection data output range (rated values) ? voltage 10 v 0 v to 10 v ? current 20 ma 0 ma to 20 ma 4 ma to 20 ma load resistance (wit hin output rating) ? for voltage outputs ? capacitive load min. 1 k max. 0.1 f ? for current outputs ? inductive load max. 300 0.1 mh
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 6-55 technical data voltage output ? short-circuit protection yes ? short-circuit current typically 55 ma current output ? no-load voltage typically 17 v destruction limit for externally applied vo ltages/currents ? voltage measured betwe en the outputs and m ana max. 16 v ? current max. 50 ma; connection of actuators ? for voltage outputs ? wire connection ? wire connection (test lead) possible, without compensation of cable resistance not possible ? for current outputs ? wire connection possible
technical data of cpu 31xc 6.6 technical data of the integrated i/o cpu 31xc and cpu 31x, technical data 6-56 manual, edition 08/2004, a5e00105475-05
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-1 technical data of cpu 31x 7 7.1 general technical data 7.1.1 dimensions of cpu 31x each cpu features the same heigh t and depth, only the width dim ensions differ. ? height: 125 mm ? depth: 115 mm, or 180 mm with opened front cover. 40 115 65 125 figure 7-1 dimensions of cpu 31x width of cpu cpu width cpu 312 40 mm cpu 314 40 mm cpu 315-2 dp 40 mm cpu 315-2 pn/dp 80 mm cpu 317 80 mm
technical data of cpu 31x 7.1 general technical data cpu 31xc and cpu 31x, technical data 7-2 manual, edition 08/2004, a5e00105475-05 7.1.2 technical data of the micro memory card (mmc) plug-in simatic micro memory cards the following memory modules are available: table 7-1 available mmcs type order number required for a firmware update via mmc mmc 64k 6es7 953-8lfxx-0aa0 C mmc 128k 6es7 953-8lgxx-0aa0 C mmc 512k 6es7 953-8ljxx-0aa0 C mmc 2m 6es7 953-8llxx-0aa0 minim um requirement fo r cpus without dp interface mmc 4m 6es7 953-8lmxx- 0aa0 minimum require ment for cpus with dp interface mmc 8m 1 6es7 953-8lpxx-0aa0 C 1 this mmc cannot be used together with cpu 312c or cpu 312. maximum number of loadable blocks in the mmc the number of blocks that can be stored on the mmc depends on t he capacity of the mmc being used. the maximum number of b locks that can be loaded is therefore limited by the capacity of your mmc (including bl ocks generated with the "crea te db" sfc): table 7-2 maximum number o f loadable blocks on the mmc size of mmc maximum number of blocks that c an be loaded 64 kb 768 128 kb 1024 512 kb 2 mb 4 mb 8 mb here the maximum number of blo cks that can be loaded for the specific cpu is less than the nu mber of blocks that can be stor ed on the mmc. refer to the corresponding specif ications of a specific cpu to determine the maximum number of blocks that can be loaded.
technical data of cpu 31x 7.2 cpu 312 cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-3 7.2 cpu 312 technical data table 7-3 technical data for the cpu 312 technical data cpu and version order number 6es7312-1ad10-0ab0 ? hardware version 01 ? firmware version v2.0.0 ? associated programming package step 7 as of v 5.1 + sp 4 memory ram ? integrated 16 kb ? expandable no load memory plugged in with mmc (max. 4 mb) data storage life on the mmc (following final programming) at least 10 years buffering guaranteed by mmc (maintenance-free) execution times processing times of ? bit operations min. 0.2 s ? word instructions min. 0.4 s ? fixed-point arithmetic min. 5 s ? floating-point arithmetic min. 6 s timers/counters and their retentivity s7 counters 128 ? retentive memory configurable ? default from c0 to c7 ? counting range 0 to 999 iec counters yes ? type sfb ? number unlimited (limited on ly by ram size) s7 timers 128 ? retentive memory configurable ? default not retentive ? timer range 10 ms to 9990 s iec timers yes ? type sfb ? number unlimited (limited on ly by ram size)
technical data of cpu 31x 7.2 cpu 312 cpu 31xc and cpu 31x, technical data 7-4 manual, edition 08/2004, a5e00105475-05 technical data data areas and their retentivity flag bits 128 bytes ? retentive memory yes ? default retentivity mb0 to mb15 clock flag bits 8 (1 byte per flag bit) data blocks 511 (db 1 to db 511) ? length 16 kb local data per priority class max. 256 bytes blocks total 1024 (dbs, fcs, fbs) the maximum number of blocks that can be loaded may be reduced if you are using another mmc. obs see the instruction list ? length max. 16 kb nesting depth ? per priority class 8 ? additional within an error ob 4 fbs max. 512 (fb 0 to fb 511) ? length max. 16 kb fcs max. 512 (fc 0 to fc 511 ? length max. 16 kb address areas (i/o) total i/o address area 1024 bytes /1024 bytes (can be freely addressed) i/o process image 128 bytes/128 bytes digital channels max. 256 of those local max. 256 analog channels max. 64 of those local max. 64 assembly racks max. 1 modules per rack max. 8 number of dp masters ? integrated none ? via cp 1
technical data of cpu 31x 7.2 cpu 312 cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-5 technical data number of function modules and communication processors you can operate ? fm max. 8 ? cp (ptp) max. 8 ? cp (lan) max. 4 time-of-day real-time clock yes (sw clock) ? buffered no ? accuracy deviation per day < 15 s ? behavior of the realti me clock after power on the clock keeps running, c ontinuing at the time- of-day it had when powe r was switched off. operating hour s counter 1 ? number 0 ? value range 2 31 (if sfc 101 is used) ? granularity 1 hour ? retentive yes; must be manually restarted after every restart clock synchronization yes ? in the plc master ? on mpi master/slave s7 signaling functions number of stations tha t can be logged on for signaling functions 6 (depends on the number of connections configured for pg / op and s7 basic communication) process diagnostics messages yes ? simultaneously enabled interrupt s blocks max. 20 testing and commissioning functions status/control variables yes ? variables inputs, outputs, memory bits, dbs, timers, counters ? number of variables ? of those as status variable ? of those as cont rol variable 30 30 14 forcing yes ? variables inputs, outputs ? number of variables max. 10 block status yes single step yes breakpoints 2 diagnostic buffer yes ? number of entries (not configurable) max. 100
technical data of cpu 31x 7.2 cpu 312 cpu 31xc and cpu 31x, technical data 7-6 manual, edition 08/2004, a5e00105475-05 technical data communication functions pg/op communication yes global data communication yes ? number of gd circuits 4 ? number of gd packets ? sending stations ? receiving stations max. 4 max. 4 max. 4 ? length of gd packets ? consistent data max. 22 bytes 22 bytes s7 basic communication yes ? user data per request ? consistent data max. 76 bytes 76 bytes (for x_send or x_rcv) 64 bytes (for x_put or x_get as the server) s7 communication ? as server yes ? user data per request ? consistent data max. 180 bytes (with put/get) 64 bytes s5-compatible communication yes (via cp and loadable fcs) number of connections max. 6 can be used for ? pg communication ? reserved (default) ? configurable max. 5 1 from 1 to 5 ? op communication ? reserved (default) ? configurable max. 5 1 from 1 to 5 ? s7-based communication ? reserved (default) ? configurable max. 2 2 from 0 to 2 routing no interfaces 1st interface type of interface integr ated rs485 interface physics rs 485 electrically isolated no interface power supply (15 to 30 vdc) max. 200 ma functionality ? mpi yes ? profibus dp no ? point-to-point c ommunication no
technical data of cpu 31x 7.2 cpu 312 cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-7 technical data mpi services ? pg/op communication yes ? routing no ? global data communication yes ? s7 basic communication yes ? s7 communication ? as server ? as client yes no ? transmission rates 187.5 kbps programming programming language lad/fbd/stl available instructions s ee the instruction list nesting levels 8 system functions (sfcs) see the instruction list system function blocks (sfbs) see the instruction list user program security yes dimensions mounting dimensions w x h x d (mm) 40 x 125 x 130 weight 270 g voltages and currents power supply (rated value) 24 vdc ? permitted range 20.4 v to 28.8 v current consumption (no-load operation) typically 60 ma inrush current typically 2.5 a power consumption (nominal value) 0,6 a i 2 t 0.5 a 2 s external fusing of power supply lines (recommended) min. 2 a power loss typically 2,5 w
technical data of cpu 31x 7.3 cpu 314 cpu 31xc and cpu 31x, technical data 7-8 manual, edition 08/2004, a5e00105475-05 7.3 cpu 314 technical data for the cpu 314 table 7-4 technical data for the cpu 314 technical data cpu and version order number 6es7314-1af10-0ab0 ? hardware version 01 ? firmware version v 2.0.0 ? associated programming package step 7 as of v 5.1 + sp 4 memory ram ? integrated 48 kb ? expandable no load memory plugged in with mmc (max. 8 mb) data storage life on the mmc (following final programming) at least 10 years buffering guaranteed by mmc (maintenance-free) execution times processing times of ? bit operations min. 0.1 s ? word instructions min. 0.2 s ? fixed-point arithmetic min. 2.0 s ? floating-point arithmetic min. 6 s timers/counters and their retentivity s7 counters 256 ? retentive memory configurable ? default from c0 to c7 ? counting range 0 to 999 iec counters yes ? type sfb ? number unlimited (limited on ly by ram size) s7 timers 256 ? retentive memory configurable ? default not retentive ? timer range 10 ms to 9990 s iec timers yes ? type sfb ? number unlimited (limited on ly by ram size)
technical data of cpu 31x 7.3 cpu 314 cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-9 technical data data areas and their retentivity flag bits 256 bytes ? retentive memory yes ? default retentivity mb0 to mb15 clock flag bits 8 (1 byte per flag bit) data blocks ? number 511 (db 1 to db 511) ? length 16 kb local data per priority class max. 510 blocks total 1024 (dbs, fcs, fbs) the maximum number of blocks that can be loaded may be reduced if you are using another mmc. obs see the instruction list ? length 16 kb nesting depth ? per priority class 8 ? additional within an error ob 4 fbs see the instruction list ? number 512 (fb 0 to fb 511) ? length 16 kb fcs see the instruction list ? number 512 (fc 0 to fc 511) ? length 16 kb address areas (i/o) total i/o address area max. 1024 by tes/1024 bytes (can be freel y addressed) i/o process image 128 bytes/128 bytes digital channels max. 1024 of those local max. 1024 analog channels max. 256 of those local max. 256 assembly racks max. 4 modules per rack 8 number of dp masters ? integrated none ? via cp max. 1
technical data of cpu 31x 7.3 cpu 314 cpu 31xc and cpu 31x, technical data 7-10 manual, edition 08/2004, a5e00105475-05 technical data number of function modules and communication processors you can operate ? fm max. 8 ? cp (ptp) max. 8 ? cp (lan) max. 10 time-of-day real-time clock yes (hw clock) ? buffered yes ? buffered period typically 6 weeks (at an ambient temper ature of 104 f) ? behavior of the clock on expiration of the buffered period the clock keeps running, c ontinuing at the time- of-day it had when powe r was switched off. ? accuracy deviation per day: < 10 s operating hour s counter 1 ? number 0 ? value range 2 31 hours (if sfc 101 is used) ? granularity 1 hour ? retentive yes; must be manually restarted after every restart clock synchronization yes ? in the plc master ? on mpi master/slave s7 signaling functions number of stations that can log in for signaling functions (e.g. os) 12 (depends on the number of connections configured for pg / op and s7 basic communication) process diagnostics messages yes ? simultaneously enabled interrupt s blocks max. 40 testing and commissioning functions status/control variables yes ? variables inputs, outputs, memory bits, dbs, timers, counters ? number of variables ? of those as status variable ? of those as cont rol variable 30 30 14 forcing yes ? variables inputs/outputs ? number of variables max. 10 block status yes single step yes breakpoints 2 diagnostic buffer yes
technical data of cpu 31x 7.3 cpu 314 cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-11 technical data ? number of entries (not configurable) max. 100 communication functions pg/op communication yes global data communication yes ? number of gd circuits 4 ? number of gd packets ? sending stations ? receiving stations max. 4 max. 4 max. 4 ? length of gd packets ? consistent data max. 22 bytes 22 bytes s7 basic communication yes ? user data per request ? consistent data max. 76 bytes 76 bytes (for x_send or x_rcv) 64 bytes (for x_put or x_get as the server) s7 communication yes ? as server yes ? as client yes (via cp and loadable fbs) ? user data per request ? consistent data max. 180 (for put/get) 64 bytes s5-compatible communication yes (via cp and loadable fcs) number of connections 12 can be used for ? pg communication ? reserved (default) ? configurable max. 11 1 1 to 11 ? op communication ? reserved (default) ? configurable max. 11 1 1 to 11 ? s7-based communication ? reserved (default) ? configurable max. 8 8 0 to 8 routing no interfaces 1st interface type of interface integr ated rs485 interface physics rs 485 electrically isolated no interface power supply (15 to 30 vdc) max. 200 ma functionality ? mpi yes ? profibus dp no ? point-to-point c ommunication no
technical data of cpu 31x 7.3 cpu 314 cpu 31xc and cpu 31x, technical data 7-12 manual, edition 08/2004, a5e00105475-05 technical data mpi services ? pg/op communication yes ? routing no ? global data communication yes ? s7 basic communication yes ? s7 communication ? as server ? as client yes yes no (but via cp and loadable fbs) ? transmission rates 187.5 kbps programming programming language lad/fbd/stl available instructions s ee the instruction list nesting levels 8 system functions (sfcs) see the instruction list system function blocks (sfbs) see the instruction list user program security yes dimensions mounting dimensions w x h x d (mm) 40 x 125 x 130 weight 280 g voltages and currents power supply (rated value) 24 vdc ? permitted range 20.4 v to 28.8 v current consumption (no-load operation) typically 60 ma inrush current typically 2.5 a power consumption (nominal value) 0,6 a i 2 t 0.5 a 2 s external fusing of power supply lines (recommended) min. 2 a power loss typically 2.5 w
technical data of cpu 31x 7.4 cpu 315-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-13 7.4 cpu 315-2 dp technical data table 7-5 technical data for the cpu 315-2 dp technical data cpu and version order number 6es7315-2ag10-0ab0 ? hardware version 01 ? firmware version v 2.0.0 ? associated programming package step 7 as of v 5.1 + sp 4 memory ram ? integrated 128 kb ? expandable no load memory plugged in with mmc (max. 8 mb) data storage life on the mmc (following final programming) at least 10 years buffering guaranteed by mmc (maintenance-free) execution times processing times of ? bit operations min. 0.1 s ? word instructions min. 0.2 s ? fixed-point arithmetic min. 2.0 s ? floating-point arithmetic min. 6 s timers/counters and their retentivity s7 counters 256 ? retentive memory configurable ? default from c0 to c7 ? counting range 0 to 999 iec counters yes ? type sfb ? number unlimited (limited on ly by ram size) s7 timers 256 ? retentive memory configurable ? default not retentive ? timer range 10 ms to 9990 s iec timers yes ? type sfb ? number unlimited (limited on ly by ram size)
technical data of cpu 31x 7.4 cpu 315-2 dp cpu 31xc and cpu 31x, technical data 7-14 manual, edition 08/2004, a5e00105475-05 technical data data areas and their retentivity flag bits 2048 bytes ? retentive memory yes ? default retentivity mb0 to mb15 clock flag bits 8 (1 byte per flag bit) data blocks ? number 1023 (db 1 to db 1023) ? length 16 kb local data capacity max. 1024 bytes per task/510 per block blocks total 1024 (dbs, fcs, fbs) the maximum number of blocks that can be loaded may be reduced if you are using another mmc. obs see the instruction list ? length 16 kb nesting depth ? per priority class 8 ? additional within an error ob 4 fbs see the instruction list ? number 2048 (fb 0 to fb 2047) ? length 16 kb fcs see the instruction list ? number 2048 (fc 0 to fc 2047) ? length 16 kb address areas (i/o) total i/o address area max . 2048 bytes/2048 bytes (can be freely addressed) distributed max. 2000 i/o process image 128/128 digital channels max. 16384 of those local max. 1024 analog channels max. 1024 of those local max. 256 assembly racks max. 4 modules per rack 8 number of dp masters ? integrated 1 ? via cp 1
technical data of cpu 31x 7.4 cpu 315-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-15 technical data number of function modules and communication processors you can operate ? fm max. 8 ? cp (ptp) max. 8 ? cp (lan) max. 10 time-of-day real-time clock yes (hw clock) ? buffered yes ? buffered period typically 6 weeks (at an ambient temper ature of 104 f) ? behavior of the clock on expiration of the buffered period the clock keeps running, c ontinuing at the time- of-day it had when powe r was switched off. ? accuracy deviation per day: < 10 s operating hour s counter 1 ? number 0 ? value range 2 31 hours (if sfc 101 is used) ? granularity 1 hour ? retentive yes; must be manually restarted after every restart clock synchronization yes ? in the plc master ? on mpi master/slave s7 signaling functions number of stations that can log in for signaling functions (e.g. os) 16 (depends on the number of connections configured for pg / op and s7 basic communication) process diagnostics messages yes ? simultaneously enabled interrupt s blocks 40 testing and commissioning functions status/control variables yes ? variables inputs, outputs, memory bits, dbs, timers, counters ? number of variables ? of those as status variable ? of those as cont rol variable 30 30 14 forcing ? variables inputs/outputs ? number of variables max. 10 block status yes single step yes breakpoints 2
technical data of cpu 31x 7.4 cpu 315-2 dp cpu 31xc and cpu 31x, technical data 7-16 manual, edition 08/2004, a5e00105475-05 technical data diagnostic buffer yes ? number of entries (not configurable) max. 100 communication functions pg/op communication yes global data communication yes ? number of gd circuits 8 ? number of gd packets ? sending stations ? receiving stations max. 8 max. 8 max. 8 ? length of gd packets ? consistent data max. 22 bytes 22 bytes s7 basic communication yes ? user data per request ? consistent data max. 76 bytes 76 bytes (for x_send or x_rcv) 64 bytes (for x_put or x_get as the server) s7 communication yes ? as server yes ? as client yes (via cp and loadable fbs) ? user data per request ? consistent data max. 180 bytes (with put/get) 64 byte (as the server) s5-compatible communication yes (via cp and loadable fcs) number of connections 16 can be used for ? pg communication ? reserved (default) ? configurable max. 15 1 1 to 15 ? op communication ? reserved (default) ? configurable max. 15 1 1 to 15 ? s7-based communication ? reserved (default) ? configurable max. 12 12 0 to 12 routing yes (max. 4) interfaces 1st interface type of interface integr ated rs485 interface physics rs 485 electrically isolated no interface power supply (15 to 30 vdc) max. 200 ma
technical data of cpu 31x 7.4 cpu 315-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-17 technical data functionality ? mpi yes ? profibus dp no ? point-to-point c ommunication no mpi services ? pg/op communication yes ? routing yes ? global data communication yes ? s7 basic communication yes ? s7 communication ? as server ? as client yes yes no (but via cp and loadable fbs) ? transmission rates 187.5 kbps 2nd interface type of interface integr ated rs485 interface physics rs 485 electrically isolated yes type of interface integr ated rs485 interface interface power supply (15 to 30 vdc) max. 200 ma functionality mpi no profibus dp yes point-to-point c ommunication no dp master services ? pg/op communication yes ? routing yes ? global data communication no ? s7 basic communication no ? s7 communication no ? constant bus cycle time yes ? sync/freeze yes ? dpv1 yes transmission speed up to 12 mbps number of dp slaves per station 124 address area max. 244 bytes
technical data of cpu 31x 7.4 cpu 315-2 dp cpu 31xc and cpu 31x, technical data 7-18 manual, edition 08/2004, a5e00105475-05 technical data dp slave services ? pg/op communication yes ? routing yes (only if interface is active) ? global data communication no ? s7 basic communication no ? s7 communication no ? direct data exchange yes ? transmission rates up to 12 mbps ? automatic baud rate search yes (only if interface is passive) ? intermediate memory 244 bytes i / 244 bytes o ? address areas max. 32 with max. 32 bytes each ? dpv1 no gsd file the latest gsd file is available at: http://www.ad.siemens.de/support in the product support area programming programming language lad/fbd/stl available instructions s ee the instruction list nesting levels 8 system functions (sfcs) see the instruction list system function blocks (sfbs) see the instruction list user program security yes dimensions mounting dimensions w x h x d (mm) 40 x 125 x 130 weight 290 g voltages and currents power supply (rated value) 24 vdc ? permitted range 20.4 v to 28.8 v current consumption (no-load operation) typically 60 ma inrush current typically 2.5 a power consumption (nominal value) 0.8 a i 2 t 0.5 a 2 s external fusing of power supply lines (recommended) min. 2 a power loss typically 2,5 w
technical data of cpu 31x 7.5 cpu 315-2 pn/dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-19 7.5 cpu 315-2 pn/dp technical data table 7-6 technical data for the cpu 315-2 pn/dp technical data cpu and version order number 6es7315-2eg10-0ab0 ? hardware version 01 ? firmware version v 2.3.0 ? associated programming package step 7 as of v 5.3 + sp 1 memory ram ? ram 128 kb ? expandable no capacity of the retentiv e memory for retentive data blocks 128 kb load memory plugged in with mmc (max. 8 mb) buffering guaranteed by mmc (maintenance-free) data storage life on the mmc (following final programming) at least 10 years execution times processing times of ? bit operations 0.1 s ? word instructions 0.2 s ? fixed-point arithmetic 2 s ? floating-point arithmetic 6 s timers/counters and their retentivity s7 counters 256 ? retentive memory configurable ? default from c0 to c7 ? counting range 0 to 999 iec counters yes ? type sfb ? number unlimited (limited only by ram size) s7 timers 256 ? retentive memory configurable ? default not retentive ? timer range 10 ms to 9990 s
technical data of cpu 31x 7.5 cpu 315-2 pn/dp cpu 31xc and cpu 31x, technical data 7-20 manual, edition 08/2004, a5e00105475-05 technical data iec timers yes ? type sfb ? number unlimited (limited only by ram size) data areas and their retentivity flag bits 2048 bytes ? retentive memory configurable ? default retentivity from mb0 to mb15 clock flag bits 8 (1 byte per flag bit) data blocks ? number 1023 (db 1 to db 1023) ? length 16 kb ? non-retain support (configured retention) yes local data per priority class max. 1024 bytes per run level / 5 10 bytes per block blocks total 1024 (dbs, fcs, fbs) the maximum number of blocks that can be loaded may be reduced if you are using another mmc. obs see the instruction list ? length 16 kb nesting depth ? per priority class 8 ? additional within an error ob 4 fbs see the instruction list ? number 2048 (fb 0 to fb 2047) ? length 16 kb fcs see the instruction list ? number 2048 (fc 0 to fc 2047) ? length 16 kb address areas (i/o) total i/o address area max . 2048 bytes/2048 bytes (can be freely addressed) distributed max. 2000 bytes i/o process image 128/128 digital channels 16384/16384 of those local max. 1024 analog channels 1024/1024 of those local max. 256
technical data of cpu 31x 7.5 cpu 315-2 pn/dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-21 technical data assembly racks max. 4 modules per rack 8 number of dp masters ? integrated 1 ? via cp 2 number of function modules and co mmunication processors you can operate ? fm max. 8 ? cp (ptp) max. 8 ? cp (lan) max. 10 time-of-day real-time clock yes (hardware clock) ? factory setting dt#1994-01-01-00:00:00 ? buffered yes ? buffered period typically 6 weeks (at an ambient temper ature of 104 f) ? behavior of the clock on expiration of the buffered period the clock keeps running, c ontinuing at the time- of-day it had when powe r was switched off. ? behavior of the realti me clock after power on the clock continues ru nning after power off. ? accuracy deviation per day: < 10 s operating hour s counter 1 ? number 0 ? value range 2 31 hours (if sfc 101 is used) ? granularity 1 hour ? retentive yes; must be manually restarted after every restart clock synchronization yes ? in the plc master/slave ? on mpi master/slave s7 signaling functions number of stations tha t can be logged on for signaling functions 16 (depends on the number of connections configured for pg / op and s7 basic communication) process diagnostics messages yes ? simultaneously enabled interrupt s blocks 40 testing and commissioning functions status/control variables yes ? variables inputs, outputs, memory bits, dbs, timers, counters
technical data of cpu 31x 7.5 cpu 315-2 pn/dp cpu 31xc and cpu 31x, technical data 7-22 manual, edition 08/2004, a5e00105475-05 technical data ? number of variables ? of those as status variable ? of those as cont rol variable 30 max. 30 max. 14 forcing ? variables inputs/outputs ? number of variables max. 10 block status yes single step yes breakpoints 2 diagnostic buffer yes ? number of entries (not configurable) max. 100 communication functions open ie communication via tcp/ip yes (via integrated profinet i nterface and loadable fbs, max. 8 connections) pg/op communication yes global data communication yes ? number of gd circuits 8 ? number of gd packets ? sending stations ? receiving stations max. 8 max. 8 max. 8 ? length of gd packets ? consistent data max. 22 bytes 22 bytes s7 basic communication yes ? user data per request ? consistent data max. 76 bytes 76 bytes s7 communication yes ? as server yes ? as client yes (via integrated pn i nterface and loadable fbs, or even via cp and loadable fbs) ? user data per request ? consistent data see the step 7 online help, common parameters of sfbs/fb s and sfc/fc of the s7 communication) s5-compatible communication yes (via cp and loadable fcs) number of connections 16 can be used for ? pg communication ? reserved (default) ? configurable max. 15 1 1 to 15 ? op communication ? reserved (default) ? configurable max. 15 1 1 to 15 ? s7-based communication ? reserved (default) ? configurable max. 14 0 0 to 14
technical data of cpu 31x 7.5 cpu 315-2 pn/dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-23 technical data routing ? interface x1 configured as ? mpi ? dp master ? dp slave (active) ? interface x2 configured as profinet yes max. 10 max. 24 max. 14 max. 24 cba (at 50 % communication load) ? maximum data length for arrays and structures between two partners ? acyclic profinet interconnections ? cyclic profinet interconnections ? local interconnections 1400 bytes 450 bytes slave-dependent ? number of coupled profibus devices 16 ? total of all master/slave connections 1000 ? number of device-internal and profibus interconnections 500 ? number of remote interconnecting partners 32 remote interconnections with acyclical transmission scan rate: minimum scan interval 500 ms number of incoming interconnections 100 number of outgoing interconnections 100 remote interconnections with cyclical transmission scan rate: minimum scan interval 10 ms number of incoming interconnections 200 number of outgoing interconnections 200 hmi interconnections via profinet (acyclic) hmi interconnections 500 ms number of hmi variables 200 sum of all interconnections 400 0 bytes input/4000 bytes output interfaces 1st interface type of interface integr ated rs485 interface physics rs 485 electrically isolated yes interface power supply (15 to 30 vdc) max. 200 ma functionality ? mpi yes ? profibus dp yes ? point-to-point c ommunication no ? profinet no
technical data of cpu 31x 7.5 cpu 315-2 pn/dp cpu 31xc and cpu 31x, technical data 7-24 manual, edition 08/2004, a5e00105475-05 technical data mpi services ? pg/op communication yes ? routing yes ? global data communication yes ? s7 basic communication yes ? s7 communication ? as server ? as client yes yes no (but via cp and loadable fbs) ? transmission rates max. 12 mbps dp master services ? pg/op communication yes ? routing yes ? global data communication no ? s7 basic communication no ? s7 communication no ? constant bus cycle time yes ? sync/freeze yes ? dpv1 yes transmission speed up to 12 mbps number of dp slaves 124 dp slave services ? routing yes (only if interface is active) ? global data communication no ? s7 basic communication no ? s7 communication no ? direct data exchange yes ? transmission rates up to 12 mbps ? automatic baud rate search yes (only if interface is passive) ? intermediate memory 244 bytes i / 244 bytes o ? address areas max. 32 with max. 32 bytes each ? dpv1 no 2nd interface type of interface profinet physics ethernet electrically isolated yes autosensing (10/100 mbps) yes
technical data of cpu 31x 7.5 cpu 315-2 pn/dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-25 technical data functionality ? profinet yes ? mpi no ? profibus dp no ? point-to-point c ommunication no services ? pg communication yes ? op communication yes ? s7 communication ? max. configurable interconnections yes (with loadable fbs) 14 ? routing yes ? profinet io yes ? profinet cba yes profinet io number of integrated pr ofinet io controllers 1 number of connectable profinet io devices 128 max. user data consistency with profinet io 256 bytes update time 1 ms to 512 ms the minimum value is determined by the set communication portion fo r profinet io, the number of io devices and the amount of configured user data. routing yes s7 protocol functions ? pg functions yes ? op functions yes ? open ie communication via tcp/ip yes gsd file the latest gsd file is available at: http://www.ad.siemens.de/support in the product support area programming programming language lad/fbd/stl available instructions s ee the instruction list nesting levels 8 system functions (sfcs) see the instruction list system function blocks (sfbs) see the instruction list user program security yes dimensions mounting dimensions w x h x d (mm) 80 x 125 x 130 weight 460 g
technical data of cpu 31x 7.6 cpu 317-2 dp cpu 31xc and cpu 31x, technical data 7-26 manual, edition 08/2004, a5e00105475-05 technical data voltages and currents power supply (rated value) 24 vdc ? permitted range 20.4 v to 28.8 v current consumption (no-load operation) 100 ma inrush current typically 2.5 a i 2 t min. 1 a 2 s external fusing of power supply lines (recommended) min. 2 a power loss typically 3.5 w 7.6 cpu 317-2 dp technical data table 7-7 technical data for the cpu 317-2 dp technical data cpu and version order number 6es7317-2aj10-0ab0 ? hardware version 01 ? firmware version v 2.1.0 ? associated programming package step 7 as of v 5.2 + sp 1 memory ram ? integrated 512 kb ? expandable no capacity of the retentiv e memory for retentive data blocks max. 256 kb load memory plugged in with mmc (max. 8 mb) buffering guaranteed by mmc (maintenance-free) data storage life on the mmc (following final programming) at least 10 years execution times processing times of ? bit operations 0.05 s ? word instructions 0.2 s ? fixed-point arithmetic 0.2 s ? floating-point arithmetic 1.0 s
technical data of cpu 31x 7.6 cpu 317-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-27 technical data timers/counters and their retentivity s7 counters 512 ? retentive memory configurable ? default from c0 to c7 ? counting range 0 to 999 iec counters yes ? type sfb ? number unlimited (limited only by ram size) s7 timers 512 ? retentive memory configurable ? default not retentive ? timer range 10 ms to 9990 s iec timers yes ? type sfb ? number unlimited (limited only by ram size) data areas and their retentivity flag bits 4096 bytes ? retentive memory configurable ? default retentivity from mb0 to mb15 clock flag bits 8 (1 byte per flag bit) data blocks ? number 2047 (db 1 to db 2047) ? length 64 kb ? non-retain support (configured retention) yes local data per priority class max. 1024 bytes blocks total 2048 (dbs, fcs, fbs) the maximum number of blocks that can be loaded may be reduced if you are using another mmc. obs see the instruction list ? length 64 kb nesting depth ? per priority class 16 ? additional within an error ob 4 fbs see the instruction list ? number 2048 (fb 0 to fb 2047) ? length 64 kb
technical data of cpu 31x 7.6 cpu 317-2 dp cpu 31xc and cpu 31x, technical data 7-28 manual, edition 08/2004, a5e00105475-05 technical data fcs see the instruction list ? number 2048 (fc 0 to fc 2047) ? length 64 kb address areas (i/o) total i/o address area max . 8192 bytes/8192 bytes (can be freely addressed) distributed max. 8192 bytes i/o process image 256/256 digital channels 65536/65536 of those local max. 1024 analog channels 4096/4096 of those local 256/256 assembly racks max. 4 modules per rack 8 number of dp masters ? integrated 2 ? via cp 2 number of function modules and co mmunication processors you can operate ? fm max. 8 ? cp (ptp) max. 8 ? cp (lan) max. 10 time-of-day real-time clock yes (hw clock) ? buffered yes ? buffered period typically 6 weeks (at an ambient temper ature of 104 f) ? behavior of the clock on expiration of the buffered period the clock keeps running, c ontinuing at the time- of-day it had when powe r was switched off. ? accuracy deviation per day: < 10 s operating hour s counter 4 ? number 0 to 3 ? value range 2 31 hours (if sfc 101 is used) ? granularity 1 hour ? retentive yes; must be manually restarted after every restart clock synchronization yes ? in the plc master/slave ? on mpi master/slave
technical data of cpu 31x 7.6 cpu 317-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-29 technical data s7 signaling functions number of stations tha t can be logged on for signaling functions 32 (depends on the number of connections configured for pg / op and s7 basic communication) process diagnostics messages yes ? simultaneously enabled interrupt s blocks 60 testing and commissioning functions status/control variables yes ? variables inputs, outputs, memory bits, dbs, timers, counters ? number of variables ? of those as status variable ? of those as cont rol variable 30 max. 30 max. 14 forcing ? variables inputs/outputs ? number of variables max. 10 block status yes single step yes breakpoints 2 diagnostic buffer yes ? number of entries (not configurable) max. 100 communication functions pg/op communication yes global data communication yes ? number of gd circuits 8 ? number of gd packets ? sending stations ? receiving stations max. 8 max. 8 max. 8 ? length of gd packets ? consistent data max. 22 bytes 22 bytes s7 basic communication yes ? user data per request ? consistent data max. 76 bytes 76 bytes (for x_send or x_rcv) 76 bytes (for x_put or x_get as the server) s7 communication yes ? as server yes ? as client yes (via cp and loadable fbs) ? user data per request ? consistent data max. 180 bytes (with put/get) 160 byte (as the server) s5-compatible communication yes (via cp and loadable fcs)
technical data of cpu 31x 7.6 cpu 317-2 dp cpu 31xc and cpu 31x, technical data 7-30 manual, edition 08/2004, a5e00105475-05 technical data number of connections 32 can be used for ? pg communication ? reserved (default) ? configurable max. 31 1 1 to 31 ? op communication ? reserved (default) ? configurable max. 31 1 1 to 31 ? s7-based communication ? reserved (default) ? configurable max. 30 0 0 to 30 routing yes (max. 8) interfaces 1st interface type of interface integr ated rs485 interface physics rs 485 electrically isolated yes interface power supply (15 to 30 vdc) max. 200 ma functionality ? mpi yes ? profibus dp yes ? point-to-point c ommunication no mpi services ? pg/op communication yes ? routing yes ? global data communication yes ? s7 basic communication yes ? s7 communication ? as server ? as client yes no (but via cp and loadable fbs) ? transmission rates max. 12 mbps dp master services ? pg/op communication yes ? routing yes ? global data communication no ? s7 basic communication no ? s7 communication no ? constant bus cycle time yes ? sync/freeze yes ? dpv1 yes
technical data of cpu 31x 7.6 cpu 317-2 dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-31 technical data transmission speed up to 12 mbps number of dp slaves 124 address range per dp slave max. 244 bytes dp slave (except for dp s lave at both interfaces) services ? routing yes (only if interface is active) ? global data communication no ? s7 basic communication no ? s7 communication no ? direct data exchange yes ? transmission rates up to 12 mbps ? automatic baud rate search yes (only if interface is passive) ? intermediate memory 244 bytes i / 244 bytes o ? address areas max. 32 with max. 32 bytes each ? dpv1 no 2nd interface type of interface integr ated rs485 interface physics rs 485 electrically isolated yes type of interface integr ated rs485 interface interface power supply (15 to 30 vdc) max. 200 ma functionality mpi no profibus dp yes point-to-point c ommunication no dp master services ? pg/op communication yes ? routing yes ? global data communication no ? s7 basic communication no ? s7 communication no ? constant bus cycle time yes ? sync/freeze yes ? dpv1 yes transmission speed up to 12 mbps number of dp slaves 124 address area max. 244 bytes
technical data of cpu 31x 7.6 cpu 317-2 dp cpu 31xc and cpu 31x, technical data 7-32 manual, edition 08/2004, a5e00105475-05 technical data dp slave (except for dp s lave at both interfaces) services ? pg/op communication yes ? routing yes (only if interface is active) ? global data communication no ? s7 basic communication no ? s7 communication no ? direct data exchange yes ? transmission rates up to 12 mbps ? automatic baud rate search yes (only if interface is passive) ? intermediate memory 244 bytes i / 244 bytes o ? address areas max. 32 with max. 32 bytes each ? dpv1 no gsd file the latest gsd file is available at: http://www.ad.siemens.de/support in the product support area programming programming language lad/fbd/stl available instructions s ee the instruction list nesting levels 8 system functions (sfcs) see the instruction list system function blocks (sfbs) see the instruction list user program security yes dimensions mounting dimensions w x h x d (mm) 80 x 125 x 130 weight 460 g voltages and currents power supply (rated value) 24 vdc ? permitted range 20.4 v to 28.8 v current consumption (no-load operation) typically 100 ma inrush current typically 2.5 a i 2 t 1 a 2 s external fusing of power supply lines (recommended) min. 2 a power loss typically 4 w
technical data of cpu 31x 7.7 cpu 317-2 pn/dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-33 7.7 cpu 317-2 pn/dp technical data table 7-8 technical data for the cpu 317-2 pn/dp technical data cpu and version order number 6es7317-2ej10-0ab0 ? hardware version 01 ? firmware version v 2.3.0 ? associated programming package step 7 as of v 5.3 + sp 1 memory ram ? ram 512 kb ? expandable no capacity of the retentiv e memory for retentive data blocks 256 kb load memory plugged in with mmc (max. 8 mb) buffering guaranteed by mmc (maintenance-free) data storage life on the mmc (following final programming) at least 10 years execution times processing times of ? bit operations 0.05 s ? word instructions 0.2 s ? fixed-point arithmetic 0.2 s ? floating-point arithmetic 1.0 s timers/counters and their retentivity s7 counters 512 ? retentive memory configurable ? default from c0 to c7 ? counting range 0 to 999 iec counters yes ? type sfb ? number unlimited (limited only by ram size) s7 timers 512 ? retentive memory configurable ? default not retentive ? timer range 10 ms to 9990 s
technical data of cpu 31x 7.7 cpu 317-2 pn/dp cpu 31xc and cpu 31x, technical data 7-34 manual, edition 08/2004, a5e00105475-05 technical data iec timers yes ? type sfb ? number unlimited (limited only by ram size) data areas and their retentivity flag bits 4096 bytes ? retentive memory configurable ? default retentivity from mb0 to mb15 clock flag bits 8 (1 byte per flag bit) data blocks ? number 2047 (db 1 to db 2047) ? length 64 kb ? non-retain support (configured retention) yes local data per priority class max. 1024 bytes blocks total 2048 (dbs, fcs, fbs) the maximum number of blocks that can be loaded may be reduced if you are using another mmc. obs see the instruction list ? length 64 kb nesting depth ? per priority class 16 ? additional within an error ob 4 fbs see the instruction list ? number 2048 (fb 0 to fb 2047) ? length 64 kb fcs see the instruction list ? number 2048 (fc 0 to fc 2047) ? length 64 kb address areas (i/o) total i/o address area max . 8192 bytes/8192 bytes (can be freely addressed) distributed max. 8192 bytes i/o process image ? configurable 2048/2048 ? default 256/256 digital channels 65536/65536 of those local max. 1024
technical data of cpu 31x 7.7 cpu 317-2 pn/dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-35 technical data analog channels 4096/4096 of those local 256/256 assembly racks max. 4 modules per rack 8 number of dp masters ? integrated 1 ? via cp 2 number of function modules and co mmunication processors you can operate ? fm max. 8 ? cp (ptp) max. 8 ? cp (lan) max. 10 time-of-day real-time clock yes (hardware clock) ? factory setting dt#1994-01-01-00:00:00 ? buffered yes ? buffered period typically 6 weeks (at an ambient temper ature of 104 f) ? behavior of the clock on expiration of the buffered period the clock keeps running, c ontinuing at the time- of-day it had when powe r was switched off. ? behavior of the realti me clock after power on the clock continues ru nning after power off. ? accuracy deviation per day: < 10 s operating hour s counter 4 ? number 0 to 3 ? value range 2 31 hours (if sfc 101 is used) ? granularity 1 hour ? retentive yes; must be manually restarted after every restart clock synchronization yes ? in the plc master/slave ? on mpi master/slave s7 signaling functions number of stations tha t can be logged on for signaling functions 32 (depends on the number of connections configured for pg / op and s7 basic communication) process diagnostics messages yes ? simultaneously enabled interrupt s blocks 60 testing and commissioning functions status/control variables yes ? variables inputs, outputs, memory bits, dbs, timers, counters
technical data of cpu 31x 7.7 cpu 317-2 pn/dp cpu 31xc and cpu 31x, technical data 7-36 manual, edition 08/2004, a5e00105475-05 technical data ? number of variables ? of those as status variable ? of those as cont rol variable 30 max. 30 max. 14 forcing ? variables inputs/outputs ? number of variables max. 10 block status yes single step yes breakpoints 2 diagnostic buffer yes ? number of entries (not configurable) max. 100 communication functions open ie communication via tcp/ip yes (via integrated profinet i nterface and loadable fbs, max. 8 connections) pg/op communication global data communication yes ? number of gd circuits 8 ? number of gd packets ? sending stations ? receiving stations max. 8 max. 8 max. 8 ? length of gd packets ? consistent data max. 22 bytes 22 bytes s7 basic communication yes ? user data per request ? consistent data max. 76 bytes 76 bytes s7 communication yes ? as server yes ? as client yes (via integrated pn i nterface and loadable fbs, or even via cp and loadable fbs) ? user data per request ? consistent data see the step 7 online help, common parameters of sfbs/fb s and sfc/fc of the s7 communication) s5-compatible communication yes (via cp and loadable fcs) number of connections 32 can be used for ? pg communication ? reserved (default) ? configurable max. 31 1 1 to 31 ? op communication ? reserved (default) ? configurable max. 31 1 1 to 31 ? s7-based communication ? reserved (default) ? configurable max. 30 0 0 to 30
technical data of cpu 31x 7.7 cpu 317-2 pn/dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-37 technical data routing ? interface x1 configured as ? mpi ? dp master ? dp slave (active) ? interface x2 configured as ? profinet yes max. 10 max. 24 max. 14 max. 24 cba (at 50 % communication load) ? maximum data length for arrays and structures between two partners ? acyclic profinet interconnections ? cyclic profinet interconnections ? local interconnections 1400 bytes 450 bytes slave-dependent ? number of coupled profibus devices 16 ? total of all master/slave connections 1000 ? number of device-internal and profibus interconnections 500 ? number of remote interconnecting partners 32 remote interconnections with acyclical transmission scan rate: minimum scan interval 500 ms number of incoming interconnections 100 number of outgoing interconnections 100 remote interconnections with cyclical transmission scan rate: minimum scan interval 10 ms number of incoming interconnections 200 number of outgoing interconnections 200 hmi interconnections via profinet (acyclic) hmi interconnections 500 ms number of hmi variables 200 sum of all interconnections 400 0 bytes input/4000 bytes output interfaces 1st interface type of interface integr ated rs485 interface physics rs 485 electrically isolated yes interface power supply (15 to 30 vdc) max. 200 ma functionality ? mpi yes ? profibus dp yes ? point-to-point c ommunication no ? profinet no
technical data of cpu 31x 7.7 cpu 317-2 pn/dp cpu 31xc and cpu 31x, technical data 7-38 manual, edition 08/2004, a5e00105475-05 technical data mpi services ? pg/op communication yes ? routing yes ? global data communication yes ? s7 basic communication yes ? s7 communication ? as server ? as client yes yes no (but via cp and loadable fbs) ? transmission rates max. 12 mbps dp master services ? pg/op communication yes ? routing yes ? global data communication no ? s7 basic communication no ? s7 communication no ? constant bus cycle time yes ? sync/freeze yes ? dpv1 yes transmission speed up to 12 mbps number of dp slaves 124 dp slave services ? routing yes (only if interface is active) ? global data communication no ? s7 basic communication no ? s7 communication no ? direct data exchange yes ? transmission rates up to 12 mbps ? automatic baud rate search yes (only if interface is passive) ? intermediate memory 244 bytes i / 244 bytes o ? address areas max. 32 with max. 32 bytes each ? dpv1 no 2nd interface type of interface profinet physics ethernet electrically isolated yes autosensing (10/100 mbps) yes
technical data of cpu 31x 7.7 cpu 317-2 pn/dp cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 7-39 technical data functionality ? profinet yes ? mpi no ? profibus dp no ? point-to-point c ommunication no services ? pg communication yes ? op communication yes ? s7 communication ? max. configurable interconnections yes (with loadable fbs) 16 ? routing yes ? profinet io yes ? profinet cba yes profinet io number of integrated pr ofinet io controllers 1 number of connectable profinet io devices 128 max. user data consistency with profinet io 256 bytes update time 1 ms to 512 ms the minimum value is determined by the set communication portion fo r profinet io, the number of io devices and the amount of configured user data. s7 protocol functions ? pg functions yes ? op functions yes ? open ie communication via tcp/ip yes gsd file the latest gsd file is available at: http://www.ad.siemens.de/support in the product support area programming programming language lad/fbd/stl available instructions s ee the instruction list nesting levels 8 system functions (sfcs) see the instruction list system function blocks (sfbs) see the instruction list user program security yes dimensions mounting dimensions w x h x d (mm) 80 x 125 x 130 weight 460 g
technical data of cpu 31x 7.7 cpu 317-2 pn/dp cpu 31xc and cpu 31x, technical data 7-40 manual, edition 08/2004, a5e00105475-05 technical data voltages and currents power supply (rated value) 24 vdc ? permitted range 20.4 v to 28.8 v current consumption (no-load operation) 100 ma inrush current typically 2.5 a i 2 t min. 1 a 2 s external fusing of power supply lines (recommended) min. 2 a power loss typically 3.5 w
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 a-1 appendix a a.1 information about upgrading to a cpu 31xc or cpu 31x a.1.1 area of applicability who should read this information? you are already using a cpu fr om the siemens S7-300 series and now want to upgrade to a new device. please note that problems may occur while downloading your user program to the "new" cpu. if you have used one of the following cpus in the past ... as of version cpu order number firmware hardware cpu 312 ifm 6es7 312-5ac02-0ab0 6es7 312-5ac82-0ab0 1.0.0 01 cpu 313 6es7 313-1ad03-0ab0 1.0.0 01 cpu 314 6es7 314-1ae04-0ab0 6es7 314-1ae84-0ab0 1.0.0 01 cpu 314 ifm 6es7 314-5ae03-0ab0 1.0.0 01 cpu 314 ifm 6es7 314-5ae83-0ab0 1.0.0 01 cpu 315 6es7 315-1af03-0ab0 1.0.0 01 cpu 315-2 dp 6es7 315-2af03-0ab0 6es7 315-2af83-0ab0 1.0.0 01 cpu 316-2 dp 6es7 316-2ag00-0ab0 1.0.0 01 cpu 318-2 dp 6es7 318-2aj00-0ab0 v3.0.0 03
appendix a.1 information about upgrading to a cpu 31xc or cpu 31x cpu 31xc and cpu 31x, technical data a-2 manual, edition 08/2004, a5e00105475-05 ... then please note if you upgrade to one of the following cpu s from version cpu order number firmware hardware hereafter called 312 6es7312-1ad10-0ab0 v2.0.0 01 312c 6es7312-5bd01-0ab0 v2.0.0 01 313c 6es7313-5be01-0ab0 v2.0.0 01 313c-2 ptp 6es7313-6b e01-0ab0 v2.0.0 01 313c-2 dp 6es7313-6ce01-0ab0 v2.0.0 01 314 6es7314-1af10-0ab0 v2.0.0 01 314c-2 ptp 6es7314-6b f01-0ab0 v2.0.0 01 314c-2 dp 6es7314-6cf01-0ab0 v2.0.0 01 315-2 dp 6es7315-2ag 10-0ab0 v2.0.0 01 315-2 pn/dp 6es7315-2eg10-0ab0 v2.3.0 01 317-2 dp 6es7317-2aj10-0ab0 v2.1.0 01 317-2 pn/dp 6es7317-2ej10-0ab0 v2.3.0 01 cpu 31xc/31x reference if you intend to migrate from profi bus dp to profinet, we also recommend the following manual: guide: from profibus dp to profinet io see also dpv1 (page 3-32) a.1.2 changed behavio r of certain sfcs sfc 56, sfc 57 and sfc 13 which work asynchronously some of the sfcs that work asynch ronously, when used on cpus 31 2ifm C 318-2 dp, were always, or under certain conditi ons, processed after the first call ("quasi-synchronous"). on the 31xc/31x cpus these sfcs actually run asynchronously. as ynchronous processing may cover multiple ob1 cycles. a s a result, a wait loop may tur n into an endless loop within an ob. the following sfcs are affected: ? sfc 56 "wr_dparm"; sfc 57 "parm_mod" on cpus 312 ifm to 318-2 dp, thes e sfcs always work "quasi-sync hronously" during communication with centralized i/o modules and always work sync hronously during communication with dis tributed i/o modules.
appendix a.1 information about upgradi ng to a cpu 31x c or cpu 31x cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 a-3 note if you are using sfc 56 "wr_dpar m" or sfc 57 "parm_mod", you sh ould always evaluate the sfc's busy bit. ? sfc 13 "dpnrm_dg" on cpus 312 ifm to 318-2 dp, this sfc always works "quasi synch ronously" when it is called in ob82. on cpus 31xc/31 x it generally works asynchronou sly. note in the user program, the job shou ld merely be started in ob 82. the data should be evaluated in the cyclical progr am, taking account of the busy b its and the value returned in ret_val. hint if you are using a cpu 31xc/31x , we recommend that you use sfb 54, rather than sfc 13 "dpnrm_dg". sfc 20 "blkmov" in the past, this sfc could be us ed with cpus 312 ifm to 318-2 dp to copy data from a non runtime-related db. sfc 20 no longer has this function ality with cpus 31xc/31x. sfc 83 "read_dbl" is now used instead. sfc 54 "rd_dparm" this sfc is no longer availabl e on cpus 31xc/31x. use sfc 102 "rd_dpara" instead, which works asynchronously.
appendix a.1 information about upgrading to a cpu 31xc or cpu 31x cpu 31xc and cpu 31x, technical data a-4 manual, edition 08/2004, a5e00105475-05 sfcs that may return other results you can ignore the following poi nts if you only use logical add ressing in your user program. when using address conversion in your user program (sfc 5 "gadr _lgc", sfc 49 "lgc_gadr"), you must c heck the assignment of the slot a nd logical start address for your dp slaves. ? in the past, the diagnos tic address of a dp slave was assigned to the slave's virtual slot 2. since dpv1 was st andardized, this diagno stic addres s has bee n assigned to virtual slot 0 (station proxy) for cpus 31xc/31x. ? if the slave has modeled a separa te slot for the interface modu le (e.g. cpu31x-2 dp as an intelligent slave or im 153) , then its addres s is assigned t o slot 2. activating / deactivating dp slaves via sfc 12 with cpus 31xc/31x, sla ves that were deactivated via sfc 12 are no longer automatically activated at the run to stop tr ansition. now they are not activ ated until they are restarted (stop to run transition). a.1.3 interrupt events from dis tributed i/os while the cpu stat us is in stop interrupt events from distributed i/os while the cpu status is in stop with the new dpv1 functionality (iec 61158/ en 50170, volume 2, profibus), the handling of incoming interrupt e vents from the distributed i/os while the cpu status is in stop has also changed. previous response by the cpu with stop status with cpus 312ifm C 318-2 dp, ini tially an interrupt event was n oticed while the cpu was in stop mode. when the cpu status subsequently returned to run, th e interrupt was then fetched by an appropriate ob (e.g. ob 82). new response by the cpu with cpus 31xc/31x, an interrupt e vent (process or diagnostic i nterrupt, new dpv1 interrupts) is acknowledged by the distributed i/o while the cp u is still in stop status, and is entered in the diag nostic buffer if necessary (diagnostic in terrupts only). when the cpu status subsequently returns to r un, the interrupt is no longer fetched by the ob. possible slave faults can be read using suitable ssl queries (e.g. read ssl 0x692 via sfc51).
appendix a.1 information about upgradi ng to a cpu 31x c or cpu 31x cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 a-5 a.1.4 runtimes that change wh ile the program is running runtimes that change while the program is running if you have created a user progr am that has been fine-tuned in relation to certain processing times, please note the following points if you are using a cpu 31xc/31x: ? the program will run much fa ster on the cpu 31xc/31x. ? functions that require mmc acces s (e.g. system start-up time, p rogram download in run, return of dp station, etc) , may sometimes run slower on th e cpu 31xc/31x. a.1.5 converting the diagnosti c addresses of dp slaves converting the diagnostic addresses of dp slaves if you are using a cpu 31xc/31x wi th dp interface as the master , please note that you may have to reassign the diagnostic a ddresses for the slaves since the changes to the dpv1 standard sometimes require two diagnostic addresses per slave. ? the virtual slot 0 has its own a ddress (diagnostic address of t he station proxy). the module status data for this slot (read ssl 0xd91 with sfc 51 "r dsysst") contains ids that relate to the entire slave/ station, e.g. the station error id. failure and restoration of the station are also signaled in ob86 on the master via the dia gnostic address of the virtual slot 0. ? at some of the slaves the interf ace module is also modeled as a separate virtual slot (for example, cpu as an intelligent s lave or im153), and a suitable separate address is assigned to virtual slot 2. the change of operating status i s signaled in the master's dia gnostic interrupt ob 82 via this address for cpu 31xc-2dp acting as an intelligent slave. note reading diagnostics data w ith sfc 13 "dpnrm_dg": the originally assigne d diagnostics address still works. intern ally, step 7 assigns this address to slot 0. when using sfc51 "rdsysst", for ex ample, to read module status information or module rack/station status information , you must also consider the cha nge in slot significance as well as the additional slot 0.
appendix a.1 information about upgrading to a cpu 31xc or cpu 31x cpu 31xc and cpu 31x, technical data a-6 manual, edition 08/2004, a5e00105475-05 a.1.6 reusing existing ha rdware configurations reusing existing hardware configurations if you reuse the configuration o f a cpu 312 ifm to 318-2 dp for a cpu 31xc/31x, the cpu 31xc/31x may not run correctly. if this is the case, you will have to replace the cpu in the st ep 7 hardware configuration editor. when you replace the cpu , step 7 will automatically acc ept all the settings (if appropriate and possible). a.1.7 replacing a cpu 31xc/31x replacing a cpu 31xc/31x when supplied, the cpu 31xc/31x adds a connecting plug to the p ower supply connector. you no longer need to disconnec t the cables of the cpu when you replace a 31xc / 31x cpu. insert a screwdr iver with 3.5 mm blade into the right side of the connector to open the interlock mechanism, then unplug i t from the cpu. once you have replaced the cpu, simply plug the connecting plug back int o the power supply connector.
appendix a.1 information about upgradi ng to a cpu 31x c or cpu 31x cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 a-7 a.1.8 using consistent data area s in the process image of a dp slave system consistent data the table below illustrates the points to consider with respect to communication in a dp master system if you want to transfer i/o areas with "total length" consisten cy. you can transfer a maximum of 128 by tes of consistent data. table a-1 consistent data cpu 315-2 dp (as of firmware 2.0.0), cpu 317, cpu 31xc cpu 315-2 dp (as of firmware 1.0.0), cpu 316-2 dp, cpu 318-2 dp (firmware < 3.0) cpu 318-2 dp (firmware >= 3.0) even if they exist in the process image, consistent data is not automatically updated. you can choose whether or not to update the a ddress area of consistent data in the process image. the address area of consistent data in the process image is automatically updated. to read and write consistent data, you can also use sfc 14 and sfc 15. if the address area of consistent data is not in the process image, you must use sfc 14 and sfc 15 to read and write consis tent data. direct access to consistent areas is also possible (e.g. l pew or t paw). to read and write consistent data, you must use sfc14 and 15. to read and write consistent data, you can also use sfc 14 and sfc 15. if the address area of consistent data is not in the process image, you must use sfc 14 and sfc 15 to read and write consis tent data. direct access to consistent areas is also possible (for example, l pew or t paw).
appendix a.1 information about upgrading to a cpu 31xc or cpu 31x cpu 31xc and cpu 31x, technical data a-8 manual, edition 08/2004, a5e00105475-05 a.1.9 load memory concept for the cpu 31xc/31x load memory concept for the cpu 31xc/31x on cpus 312 ifm to 318-2 dp, the load memory is integrated into the cpu and may be extended with a memory card, the load memory of the cpu 31xc/31 x is located on the micro mem ory card (mmc), and is retentive. when blocks are dow nloaded to the cpu , they are stor ed on the mmc and cannot be lost even in the event of a power failure or memory reset. reference see also the memory concept chapter in the cpu data 31xc and 31x manual. note user programs can only be dow nloaded and thus the cpu can only be used if the mmc is inserted. a.1.10 pg/op functions pg/op functions with cpus 315-2 dp (6es7315-2afx3-0ab0), 316-2dp and 318-2 dp, pg/op functions at the dp interface were only pos sible if the interface was set to active. with cpus 31xc/31x, these functions are possible at both active and passive interfa ces. the performance of the passive interface is cons iderably lower, however. a.1.11 routing for the cpu 31x c/31x as an intelligent slave routing for the cpu 31xc/31x as an intelligent slave if you use the cpu 31xc /31x as an intelli gent slave, the routin g function can only be used with an actively-configured dp interface. in the properties of the dp inter face in step 7, select the "te st, commissioning, routing" check box of the "dp-slave" option.
appendix a.1 information about upgradi ng to a cpu 31x c or cpu 31x cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 a-9 a.1.12 changed retentive behavior for cpus with firmware >= v2. 1.0 changed retentive behavior for cpus with firmware >= v2.1.0 for data blocks for these cpus ? you can set the retentive respon se in the block properties of t he db. ? using sfc 82 "crea_dbl" -> para meter attrib, non_retain bit, yo u can specify if the actual values of a db should be maintained at power off/on or stop-run (retentive db) or if the start v alues should be read from the l oad memory (non-retentive db). a.1.13 fms/cps with separate mp i address in the central rack of a cpu 315-2 pn/dp / cpu 317 fms/cps with separate mpi address in the central rack of a cpu 315-2 pn/dp / cpu 317 all cpus, except cpu 3 15-2 pn/dp, cpu 317 and cpu 318-2 dp cpu 315-2 pn/dp, cpu 317 and cpu 318-2 dp if there are fm/cps with t heir own mpi address in the central rack of an s7 -300, then they are in the exact same cpu subnet as the cpu mpi station. if there are fm/cps with their own mpi address in the central rack of an S7-300, then the cpu forms its own communi cation bus via the backplane bus with these fm/cps, which are separated from the other subnets. the mpi address of such an fm/cp is no longer relevant for the stations on other subnets. the communication to the fm/cp is made via the mpi address of the cpu. when exchanging your existing cp u with a cpu 315-2 pn/dp / cpu 317, you therefore need to: ? replace the cpu in your step 7 project with the cpu 315-2 pn/dp / cpu 317. ? reconfigure the ops. the cont rol and the destination address mu st be reassigned (= the mpi address of the cp u 315-2 pn/dp / cpu 317 and the slot of th e respective fm) ? reconfigure the project data fo r fm/cp to be loaded to the cpu. this is required for the fm/cp in this rack to remain "availabl e" to the op/pg.
appendix a.1 information about upgrading to a cpu 31xc or cpu 31x cpu 31xc and cpu 31x, technical data a-10 manual, edition 08/2004, a5e00105475-05 a.1.14 using loadable blocks for s7 communication for the integ rated profinet interface if you have already used s7 comm unication via cp with loadable fbs (fb 8, fb 9, fb 12 C fb 15 and fc 62 with version v1.0 ) from the simatic_net_cp step 7 library (these blocks all feature the family type cp300 pbk) and now want to u se the integrated profinet interface for s7 commu nication, you must use the corre sponding blocks from the standard library\communication bl ocks step 7 library in your pr ogram (the corresponding blocks fb 8, fb 9, fb 12 C fb 15 and fc 62 have at least versio n v1.1 and family type cpu_300). procedure 1. download and overwrite the ol d fbs/fcs in your program conta iner with the corresponding blocks from the standard library. 2. update the corresponding bloc k calls, including updating the instance dbs, in your user program.
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-1 glossary accumulator accumulators represent cpu regist er and are used as buffer memo ry for downl oad, transfer, comparison, calculation and conversion operations. address an address is the identifier of a specific address or address a rea. examples: input i 12.1; flag word mw 25; data block db 3. analog module analog modules convert process v alues (e.g. temperature) into d igital values which can be processing in the cpu, or they c onvert digital values into anal og manipulated variables. application an application is a program tha t runs directly on the ms-dos / windows operating system. applications on the pg include , for example, the step 5 basic p ackage, graph 5 and others. see user program asic asic is the acronym for applicat ion specific integrated circuit s. profinet asics are components wi th a wide range of functions fo r the development of your own devices. they implemen t the requirements of the profin et standard in a circuit and allow extremely high packi ng densities and performance. because profinet is an open standard, simatic net offers profin et asics for the development of your old devices under the name ertec . backplane bus the backplane bus is a serial data bus . it supplies power to th e modules and is also used by the modules to communicate with each other. bus connectors inte rconnect the modules.
glossary cpu 31xc and cpu 31x, technical data glossary-2 manual, edition 08/2004, a5e00105475-05 backup memory backup memory ensures buffering of the memory are as of a cpu wi thout backup battery. it backs up a configurable number of timers, counters, flag bits, data bytes and retentive timers, counters, flag bits and data bytes). bus a bus is a communication medium connecting several nodes. data can be transferred via serial or parallel circuits, tha t is, via electrical conductors or fiber optic. bus segment a bus segment is a self-contained section of a serial bus syste m. bus segments are interconnected via repeaters. clock flag bits flag bit which can be used to gene rate clock pulses in the user program (1 byte per flag bit). note when operating with s7300 cpus , make sure that the byte of the clock memory bit is not overwritten in the user program! coaxial cable a coaxial cable, also known as "coax", is a metallic cabling sy stem used in high-frequency transmission, for example as the antenna cable for radios and t elevisions as well as in modern networks in which high dat a transmission rates are requi red. in a coaxial cable, an inner conductor is surrounded by an outer tube-like conductor. the two conductors are separated by a dielectric laye r. in contrast to other cables, t his design provides a high degree of immunity to and low emission of electromagnetic inter ference. code block a simatic s7 code block contains part of the step 7 user program. (in contrast to a db: this contains only data.) communication processor communications processors are mo dules for point-to-point and bu s links. component-based automation see profinet cba
glossary cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-3 compress the pg online function "compres s" is used to rearrange all vali d blocks in cpu ram in one continuous area of user memory, s tarting at the lowest address. this eliminates fragmentation which occurs when blocks are deleted or edited. configuration assignment of modules to module ra cks/slots and (e.g. for signa l modules) addresses. consistent data data which are related in their contents and no t to be separate d are referred to as consistent data. for example, the values of analog modules must always be handle d consistently, that is, the value of an analog module must not be corrupted as a result of read access at two different points of time. counters counters are part of cpu system memory. the content of "counter cells" can be modified by step 7 instructions (for exa mple, up/down count.) cp see communication processor cpu central processing unit = cpu of t he s7 automation system with a control and arithmetic unit, memory, operating system, and interface for programming d evice. cycle time the cycle time represents the ti me a cpu requires for one execu tion of the user program. cyclic interrupt see interrupt, cyclic interrupt data block data blocks (db) are data areas in the user program which conta in user data. there are global data blocks which can be accessed by all code blocks, an d instance data blocks which are assigned to a specific fb call. data, static static data can only be used wi thin a function block. these dat a are saved in an instance data block that belongs to a func tion block. data stored in an instance data block are retained until the next function block call.
glossary cpu 31xc and cpu 31x, technical data glossary-4 manual, edition 08/2004, a5e00105475-05 data, temporary temporary data represent local data of a block. they are stored in the l-stack when the block is executed. after the bl ock has been proc essed, these da ta are no longer available. default router the default router is the router that is used when data must be forwarded to a partner located within the same subnet. in step 7, the default router is named router . step 7 assigns the local ip address to the default router. determinism see real time device within the context of profinet , "device" is the generic term fo r: ? automation systems, ? field devices (for example, plc, pc), ? active network components (for example, distributed i/o, valve blocks, drives), ? hydraulic devices and ? pneumatic devices. the main characteristic of a dev ice is its integration in profi net communication over ethernet or profibus. the following device types are distinguished based on their att achment to the bus: ? profinet devices ? profibus devices see profibus device see profinet device device name before an io device can be addr essed by an io controller, it mu st have a device name. in profinet, this method was select ed because it is simpler to wor k with names than with complex ip addresses. the assignment of a device name for a concrete io device can be compared with setting the profibus address of a dp slave. when it ships, an io device does not have a device name. an io device can only be addressed by an io controller, for example for the transfer of project engineering data (including the ip address) durin g startup or for user data exch ange in cyclic operation, after it has been assigned a device name with the pg/pc .
glossary cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-5 diagnostic buffer the diagnostics buffer represents a buffered memory area in the cpu. it stores diagnostic events in the order of their occurrence. diagnostic interrupt modules capable of diagnostics op erations report detected syste m errors to the cpu by means of diagnostic interrupts. diagnostics see system diagnostics dp master a master which behaves in accor dance with en 50170, part 3 is k nown as a dp master. dp slave a slave operated on profibus with profibus dp protocol and in a ccordance with en 50170, part 3 is referred to as dp slave. dpv1 the designation dpv1 means extension of the functionality of th e acyclical services (to include new interrupts, for exam ple) provided by the dp protoco l. the dpv1 functionality has been incorporated into iec 61158/en 50170, volume 2, profibus. electrically isolated the reference potential of the c ontrol and on-load power circui ts of isolated i/o modules is electrically isolated; for exam ple, by optocouplers, relay cont act or transformer. i/o circuits can be interconnected with a root circuit. equipotential bonding electrical connection (equipotent ial bonding conductor) which e liminates potential difference between electrical equipment and external conductive bodies by drawing potential to the same or near the same level, in order to prevent disturbing or dangerous voltages between these bodies. error display one of the possible reactions o f the operating system to a runt ime error is to output an error message. further reactions: error reaction in the user program, cpu in stop. error handling via ob after the operating system has det ected a specific error (e.g. access error with step 7 ), it calls a dedicated bloc k (error ob) that determines further cpu actions.
glossary cpu 31xc and cpu 31x, technical data glossary-6 manual, edition 08/2004, a5e00105475-05 error response reaction to a runtime error. reac tions of the operating system: it sets the automation system to stop, indicates the e rror, or calls an ob in which th e user can program a reaction. ertec see asic fast ethernet fast ethernet describes the stand ard with which data is transmi tted at 100 mbps. fast ethernet uses the 100 base-t standard. fb see function block fc see function flag bits flag bits are part of the cpu's sy stem memory. they store inter mediate results of calculations. they can be access ed in bit, word or dword operat ions. flash eprom feproms can retain data in the event of power loss, same as ele ctrically erasable eeproms. however, they can be erase d within a considerably shor ter time (feprom = flash erasable programmable read only memory). they are used on memory cards. force the force function can be used to assign the variables of a use r program or cpu (also: inputs and outputs) constant values. in this context, please note t he limitations listed in the overview of the test functions section in the chapter entitled test func tions, diagnostics and trouble shooting in the S7-300 installation manual . function according to iec 1131-3, a functi on (fc) is a -- > code block wi thout --> static data. a function allows transfer of param eters in user program. functio ns are therefore suitable for programming frequently occurring c omplex functions, e.g. calcul ations.
glossary cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-7 function block according to iec 1131-3, a functi on block (fb) is a --> code bl ock with --> static data. an fb allows the user program to pass parameters. function blocks are therefore suitable for programming frequently occurring complex functions, e.g. contro ls, mode selections. functional ground grounding which has the sole purpose of safeguarding the intend ed function of electrical equipment. with functional groundi ng you short-circuit interfer ence voltage which would otherwise have an unacceptable impact on equipment. gd circuit a gd circuit comprises a number of cpus sharing data by means o f global data communication, and is used as follows: ? a cpu broadcasts a gd pa cket to the other cpus. ? a cpu sends and receives a g d packet from another cpu. a gd circuit is identified by a gd circuit number. gd element a gd element is generated by as signing shared global data. it i s identified by a unique global data id in the global data table. gd packet a gd packet can consist of one or several gd elements transmitt ed in a single message frame. global data global data can be addressed from any code block (fc, fb, ob). in particular, this refers to flag bits m, inputs i, outputs q, ti mers, counters and data blo cks db. global data can be accessed via absolute or symbolic addressing. global data communication global data communication is a method of transferring global da ta between cpus (without cfbs). ground the conductive earth whose electr ical potential can be set equa l to zero at any point. ground potential can be differen t from zero in the area of grou nding electrodes. the term reference ground is frequently u sed to describe this situation. grounding means, to connect an elec trically conductive componen t via an equipotential grounding system to a grounding electrode (one or more conducti ve components with highly conductive contact to earth).
glossary cpu 31xc and cpu 31x, technical data glossary-8 manual, edition 08/2004, a5e00105475-05 chassis ground is the totality of all the interconnected passiv e parts of a piece of equipment on which dangerous fault-voltage cannot occur. gsd file the properties of a profinet de vice are described in a gsd file (general station description) that contains all t he information required for con figuration. just as in profibus, you can inte grate a profinet device in ste p 7 using a gsd file. in profinet io, the gsd file is in xml format. the structure of the gsd file complies with iso 15734, the worldwide standar d for device descriptions. in profibus, the gsd file is in ascii format. hub in contrast to a switc h, a hub sets itsel f to the lowest speed at the ports and forwards the signals to all connected device s. a hub is also not capable of giving priority to signals. this would lead to a high communicati on load on industrial ethernet. see switch industrial ethernet industrial ethernet (formerly sin ec h1) is a technology that al lows data to be transmitted free of interference in an industrial environment. due to the openness of profinet, y ou can use standard ethernet components. we recommend, however, that you insta ll profinet as industrial eth ernet. see fast ethernet instance data block the step 7 user program assigns an automati cally generated db to every ca ll of a function block. the instance data block stores the values of inputs / ou tputs and in/out parameters, as well as local block data. interface, mpi-capable see mpi interrupt the cpu's operating system knows 10 different priority classes for controlling user program execution. these priority classes include interrupts, e.g. proc ess interrupts. when an interrupt is triggered, the operat ing system automatically call s an assigned ob. in this ob the user can program the desir ed response (e.g. in an fb). interrupt, cyclic interrupt a cyclic interrupt is generated periodically by the cpu in a co nfigurable time pattern. a corresponding ob will be processed.
glossary cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-9 interrupt, delay the delay interrupt belongs to one of the priority classes in s imatic s7 program processing. it is generated on expi ration of a time started in the user program. a corresponding ob will be processed. see interrupt, delay interrupt, diagnostic see diagnostic interrupt interrupt, process see process interrupt interrupt, status a status interrupt can be gener ated by a dpv1 slave and causes ob 55 to be called on the dpv1 master. for detailed information on ob 55, see the reference manual system software for S7-300/400: system and standard functions . interrupt, time-of-day the time-of-day interrupt belong s to one of the priority classe s in simatic s7 program processi ng. it is generated at a specific da te (or daily) and time-of-day (e.g. 9:50 or hourly, or every minute). a corresponding ob will be processed. interrupt, update an update interrupt can be generated by a dpv1 slave and causes ob56 to be called on the dpv1 master. for detailed in formation on ob56, see the reference manual system software for S7-300/400: system and standard functions . interrupt, vendor-specific a vendor-specific interrupt can be generated by a dpv1 slave. i t causes ob57 to be called on the dpv1 master. for detailed information on ob 57, see the reference manual system software for S7-300/400: system and standard functions . io controller see profinet io controller see profinet io device see profinet io supervisor see profinet io system
glossary cpu 31xc and cpu 31x, technical data glossary-10 manual, edition 08/2004, a5e00105475-05 io device see profinet io controller see profinet io device see profinet io supervisor see profinet io system io supervisor see profinet io controller see profinet io device see profinet io supervisor see profinet io system io system see profinet io system ip address to allow a profinet device to be addressed as a node on industr ial ethernet, this device also requires an ip address tha t is unique within the network. the ip address is made up of 4 decimal numbers with a range of values from 0 through 255. th e decimal numbers are separated by a period. the ip address is made up of ? the address of the (subnet) network and ? the address of the node (generally called the host or network n ode). lan local area network to which sev eral computers ar e connected wit hin an enterprise. the lan therefore has a limited geographi cal span and is solely availab le to a company or institution. load memory load memory is part of the cpu. it c ontains objects generated b y the programming device. it is implemented either as a plug-in memory card or permanently i ntegrated memory. load power supply power supply to the signal / func tion modules and the process i /o connected to them. local data see data, temporary
glossary cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-11 mac address each profinet device is assig ned a worldwide unique device iden tifier in the factory. this 6-byte long device identif ier is the mac address. the mac address is divided up as follows: ? 3 bytes vendor identifier and ? 3 bytes device identifier (consecutive number). the mac address is normally p rinted on the front of the device. example: 08-00-06-6b-80-c0 master when a master is in possession of the token, it can send data t o other nodes and request data from other nodes (= active node). see slave memory card (mc) memory cards are memory media fo r cpus and cps. they are implem ented in the form of ram or feprom. an mc differs from a micro memory card only in i ts dimensions (mc is approximately the size of a credit card). micro memory card (mmc) micro memory cards are memory me dia for cpus and cps. their onl y difference to the memory card is the smaller size. module parameters module parameters are values which can be used to configure mod ule behavior. a distinction is made between stati c and dynamic module parameter s. mpi the multipoint interface (mpi) i s the programming device interf ace of simatic s7. it enables multiple-node operatio n (pgs, text-based dis plays, ops) on one or several plcs. each node is identified by a unique address (mpi address). mpi address see mpi ncm pc see simatic ncm pc
glossary cpu 31xc and cpu 31x, technical data glossary-12 manual, edition 08/2004, a5e00105475-05 nesting depth a block can be called from another by means of a block call. ne sting depth is referred to as the number of simultaneously called code blocks. network a network is a larger communication system that allows data exc hange between a large number of nodes. all the subnets together form a network. a network consists of one or mor e interconnected subnets with a ny number of nodes. several networks can exis t alongside each other. non-isolated the reference potential of the c ontrol and on-load power circui ts of non-isolated i/o modules is electrically interconnected. ob see organization blocks ob priority the cpu operating system distingui shes between different priori ty classes, for example, cyclic program execution, process interrupt controlled program processing. each priority class is assigned organization bloc ks (obs) in which the s7 use r can program a response. the obs are assigned different def ault priority classes. these determine the order in which obs are executed or interrupt each other when they appear simul taneously. operating state simatic s7 automati on systems know the fo llowing operating stat es: stop, start, run. operating system the cpu os organizes all function s and processes of the cpu whi ch are not associated to a specific control task. see cpu organization blocks organization blocks (obs) form the interface between cpu operat ing system and the user program. obs determine the seque nce for user program execution. parameters 1. variable of a step 7 code block 2. variable for declaring module response (one or several per m odule). all modules have a
glossary cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-13 suitable basic factory setting which can be customized in step 7 . there are static and dynamic parameters parameters, dynamic unlike static parameters, you ca n change dynamic module paramet ers during runtime by calling an sfc in the user progr am, e.g. limit values of an ana log signal input module. parameters, static unlike dynamic parameters, stati c parameters of modules cannot be changed by the user program. you can only modify thes e parameters by editing your c onfiguration in step 7 , for example, modification of the inpu t delay parameters of a digita l signal input module. pc station see simatic pc station pg see programming device plc programmable controllers (plcs) are electronic controllers whos e function is saved as a program in the control unit. ther efore, the conf iguration and w iring of the unit does not dependend on the plc function. a programmable logic controller has the structure of a computer; it consists of a cpu w ith memory, input/output module s and an internal bus system. the i/o and the programmi ng language are oriented to co ntrol engineering needs. a plc in the context of simatic s 7 --> is a programmable logic controller. see cpu pno see profibus international priority class the s7 cpu operating system provi des up to 26 prio rity classes (or "program execution levels"). specific obs are assi gned to these classes. the prior ity classes determine which obs interrupt other obs. multip le obs of the same priority clas s do not interrupt each other. in this case, they are executed sequentially. process image the process image is part of cpu system memory. at the start of cyclic program execution, the signal states at the input modules are written to the proce ss image of the inputs. at the end of cyclic program execution, t he signal status of the proce ss image of the outputs is transferred to the output modules.
glossary cpu 31xc and cpu 31x, technical data glossary-14 manual, edition 08/2004, a5e00105475-05 process interrupt a process interrupt is triggered by interrupt-triggering module s as a result of a specific event in the process. the process inte rrupt is reported to the cpu. t he assigned organization block will be processed accord ing to interrupt priority. process-related function see profinet component product version the product version identifies d ifferences between products whi ch have the same order number. the product version is inc remented when forward-compati ble functions are enhanced, after production-related modifications (use of new pa rts/components) and for bug fixes. profibus process field bus - european fieldbus standard. see profibus dp see profibus international profibus device a profibus node has at least one or more profibus ports. a profibus device cannot take p art directly in profinet communi cation but must be included over a profibus master with a profinet port or an indu strial ethernet/profibus link (ie/pb li nk) with proxy functionality. see device profibus dp a profibus with the dp protocol that complies with en 500170. d p stands for distributed peripheral i/o (fast, real-time, c yclic data exchange). from th e perspective of the user program, the distributed i/o is addressed in exactly the same w ay as the central i/o. see profibus see profibus international profibus international technical committee that defines and further develops the profi bus and profinet standard. also known as the profibus user organization (pno). home page www.profibus.com
glossary cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-15 profinet within the framework of totally in tegrated automation (tia), pr ofinet represents a consequent enhancement of: ? profibus dp, the proven field bus, and ? industrial ethernet, the communi cation bus at cell level. experience gained from both syst ems was and is being integrated into profinet. profinet is an ethernet-based autom ation standard of profibus i nternational (previously profibus users organi zation e.v.), and defines a mu lti-vendor communication, automation, and engineering model. see profibus international profinet asic see asic profinet cba within the framework of profinet , profinet cba is an automation concept for the implementation of applications with distributed intelligence. profinet cba lets you create dist ributed automation solutions, based on default components and partial solutions. component-based automation allows you to use complete technolog ical modules as standardized components in complex systems. the components are also created in an engineering tool which ma y differ from vendor to vendor. components of simatic dev ices are created, for example, with step 7. profinet component a profinet component includes t he entire data of the hardware c onfiguration, the parameters of the modules, and t he corresponding user program. the profinet component is made up as follows: ? technological function the (optional) technological (sof tware) function includes the i nterface to other profinet components in the form of interc onnectable inputs and outputs. ? device the device is the representati on of the physical programmable c ontroller or field device including the i/o, sensors and actuators, mechanical parts, and the device firmware. profinet device a profinet device always has a t least one industrial ethernet p ort. a profinet device can also have a profibus port as a master with proxy functional ity. see device
glossary cpu 31xc and cpu 31x, technical data glossary-16 manual, edition 08/2004, a5e00105475-05 profinet io within the framework of profinet, profinet io is a communicatio n concept for the implementation of modular, distributed applications. profinet io allows you to creat e automation solutions, which ar e familiar to you from profibus. that is, you have the same app lication view in step 7, regardle ss of whether you configure profinet or profibus devices. profinet io controller device via which the connected io devices are addressed. this m eans that the io controller exchanges input and output signals with assigned field devices. the io controller is often the controller on which the automation program runs. see profinet io device see profinet io supervisor see profinet io system profinet io device distributed field device assigned to one of the io controllers (for example, remote i/o, valve terminal, frequency converter, switches) see profinet io controller see profinet io supervisor see profinet io system profinet io supervisor pg/pc or hmi device for commi ssioning and diagnostics. see profinet io controller see profinet io device see profinet io system profinet io system profinet io controller with a ssigned profinet io devices. see profinet io controller see profinet io device programming device basically speaking, pgs are compa ct and portable pcs which are suitable for industrial applications. their distinguishing feature is the special hardw are and software for simatic programmable logic controllers.
glossary cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-17 proxy the profinet device with proxy functionality is the substitute for a profibus device on ethernet. the proxy functionality allows a profibus device to c ommunicate not only with its master but also with all nodes on profinet. you can integrate existing prof ibus systems into profinet commu nication, for example with the help of an ie/pb link o r a cpu 31x-2 pn/dp. ie/pb link the ie/pb link then handles communication over profine t as a substitute for the pro fibus components. see profinet device ram work memory is a ram memory in t he cpu which is a ccessed by the processor during user program execution. ram (random access memory) is a semiconductor read/write memory . real time real time means that a system proc esses external events within a defined time. determinism means that a system reacts in a predictable (determ inistic) manner. in industrial networks, both thes e requirements are important. profinet meets these requirements. profinet is imple mented as a deterministic real-t ime network as follows: ? the transfer of time-critical dat a between different stations o ver a network within a defined interval is guaranteed. to achieve this, profinet provides an optimized communication c hannel for real-time communication : r eal time (rt). ? an exact prediction of the time at which the data transfer take s place is possible. ? it is guaranteed that problem-fr ee communication using other st andard protocols, for example industrial communication for pg/pc can take place withi n the same network. reduction factor the reduction rate determines t he send/receive frequency for gd packets on the basis of the cpu cycle. reference ground see ground reference potential voltages of participating circuits are referenced to this poten tial when they are viewed and/or measured. repeater see hub
glossary cpu 31xc and cpu 31x, technical data glossary-18 manual, edition 08/2004, a5e00105475-05 restart on cpu start-up (e.g. after is swi tched from stop to run mode v ia selector switch or with power on), ob100 (restart) is i nitially executed, prior to cycl ic program execution (ob1). on restart, the input proce ss image is read in and the step 7 user program is executed, starting at the first instruction in ob1. retentive memory a memory area is considered ret entive if its contents are retai ned even after a power loss and transitions from stop to r un. the non-retentive area of mem ory flag bits, timers and counters is reset following a pow er failure and a transition fr om the stop mode to the run mode. retentive can be the: ? flag bits ? s7 timers ? s7 counters ? data areas router a router works in a way similar to a switch. with a router, how ever, it is also possible to specify which communications nodes can communicate via the rout er and which cannot. communication nodes on different sides of a router can only com municate with each other if you have explicitly enabled commu nication via the router betwee n the two nodes. see default router see switch rt see real time runtime error errors occurred in the plc (that i s, not in the process itself) during user program execution. segment see bus segment sfb see system function block sfc see system function
glossary cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-19 signal module signal modules (sm) form the inte rface between the process and the plc. there are digital input and output modules (input/ output module, digital) and ana log input and output modules (input/output module, analog). simatic name of products and systems for industrial automation from sie mens ag. simatic ncm pc simatic ncm pc is a version of s tep 7 tailored to pc configurat ion. for pc stations, it offers the full range o f functions of step 7. simatic ncm pc is the central t ool with which you configure the communication services for your pc station. the confi guration data generated with this tool must be downloaded to the pc station or exported. this makes the pc station ready for communication. simatic net siemens business area for indust rial communication, networks, a nd network components. simatic pc station a "pc station" is a pc with co mmunication modules and software components within a simatic automation solution. slave a slave can only exchange data after being requested to by the master. see master snmp snmp (simple network management p rotocol) is the standardized p rotocol for diagnostics of the ethernet network infrastru cture and for assignment of pa rameters to it. within the office area and in automation engineering, devices o f a wide range of vendors support snmp on ethernet. applications based on snmp can be operated on the same network at the same time as applications with profinet. the range of functions support ed differs depending on the devic e type. a switch, for example, has more functions than a cp 1616. startup a start-up routine is executed at the transition from stop to r un mode. can be triggered by means of the mode se lector switch, or after power on, or by an operator action on the programming device. an S7-300 performs a restart.
glossary cpu 31xc and cpu 31x, technical data glossary-20 manual, edition 08/2004, a5e00105475-05 step 7 engineering system. contains pro gramming software for the creat ion of user programs for simatic s7 controllers. subnet mask the bits set in the subnet mas k decides the part of the ip addr ess that contains the address of the subnet/network. in general: ? the network address is obtained by an and operation on the ip a ddress and subnet mask. ? the node address is obtained by an and not operation on the ip address and subnet mask. subnetwork all the devices connected by swi tches are located in the same n etwork - a subnet. all the devices in a subnet can communicate directly with each other. all devices in the same subne t have the same subnet mask. a subnet is physically res tricted by a router. substitute see proxy substitute value substitute values are configurable values which output modules transfer to the process when the cpu switches to stop mode. in the event of an i/o access erro r, a substitute value can be written to the accumulator instead of the input value whi ch could not be read (sfc 44). switch profibus is based on a bus topology. communication nodes are co nnected by a passive cable - the bus. in contrast, industrial ethernet i s made up of point-to-point l inks: each communication node is connected directly to one other communication node. if a communication node needs to be connected to several other communication nodes, this communication node is connected to the port of an active networ k component- a switch. other communications nodes (inc luding switches) can then be con nected to the other ports of the switch. the connection between a communication node and the switch remains a point-to-point link. the task of a switch is therefor e to regenerate and distribute received signals. the switch "learns" the ethernet address(es) of a connected profinet devic e or other switches and forwards only the signals intended for the connected profinet d evice or connected switch. a switch has a certain number o f ports. at each port, connect a maximum of one profinet device or a further switch.
glossary cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-21 system diagnostics system diagnostics refers to t he detection, evaluation and sign aling of errors which occur within the plc, examples of such error/faults include: program errors or failures on modules. system errors can be i ndicated by leds or in step 7 . system function a system function (sfc) is a --> function integrated in the ope rating system of the cpu that can be called when necessary i n the step 7 user program. system function block a system function block (sfb) is a --> function block integrate d in the operating system of the cpu that can be called when necessary in the step 7 user pr ogram. system memory system memory is an integrated ra m memory in the cpu. system me mory contains the address areas (e.g. timers, counter s, flag bits) and data areas that are required internally by the operating system (for exam ple, communication buffers). system status list the system status list contains data that describes the current status of an S7-300. you can always use this list to obtain an overview of: ? the configuration of the S7-300 ? the current cpu configuration and configurable signal modules ? the current status and processe s in the cpu and in configurable signal modules. terminating resistor the terminating resistor is used to avoid reflections on data l inks. timer see timers timers timers are part of cpu system memory. the content of timer cell s is automatically updated by the operating system, asynchr onously to the user program. step 7 instructions are used to define the precise function of the timer cell (for example, on-delay) and to initiate their execution (for example, start). tod interrupt see interrupt, time-of-day
glossary cpu 31xc and cpu 31x, technical data glossary-22 manual, edition 08/2004, a5e00105475-05 token allows access to the bus for a limited time. topology structure of a network. common structures include: ? bus topology ? ring topology ? star topology ? tree topology transmission rate data transfer rate (in bps) twisted pair fast ethernet via twis ted-pair cables is b ased on the ieee 802. 3u standard (100 base-tx). the transmission medium is a 2x 2 wire, twisted and shielded cab le with a characteristic impedance of 100 ohms (awg 22). t he transmission characteristic s of this cable must meet the requirements of category 5 (see glossary). the maximum length of the connec tion between end device and net work component must not exceed 100 m. the ports are implemented according to the 10 0 base-tx standard with the rj-45 connector system. ungrounded having no direct electrica l connection to ground user memory user memory contains the code b locks / data blocks of the user program. user memory can be integrated in the cpu, or stor ed on plug-in memory cards or memory modules. however, the user program is principally processed from the ram of the c pu. user program in simatic, a distinction is m ade between the oper ating system of the cpu and user programs. the user program contains all instructions and declar ations, as well as signal processing data that can be cont rolled by the plant or the proc ess. it is assigned to a programmable module (for example cpu or fm) and can be structur ed in smaller units (blocks). see operating system see step 7 varistor voltage-dependent resistor
glossary cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 glossary-23 wan network with a span beyond that o f a local area network allowin g, for example, intercontinental operation. legal r ights do not belong to the u ser but to the provider of the transmission networks.
glossary cpu 31xc and cpu 31x, technical data glossary-24 manual, edition 08/2004, a5e00105475-05
cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 index-1 index a aim of this documentation, iii analog inputs configuration, 6-41 not connected, 6-38 technical data, 6-51 analog outputs not connected, 6-38 technical data, 6-53 applicability of this manual, a-1, a-2 application area covered by this manual, iii application view, 3-17, glossary-16 automation concept, 3-17, glossary-15 b blocks, 3-20 compatibility, 3-20 download, 4-11 upload, 4-12, 4-13 c communication cpu services, 3-6 data consistency, 3-16 global data communication, 3-9 s7 basic communication, 3-7 s7 communication, 3-8 communication load configured, 5-9 dependency of physical cycle time, 5-10 influence on the physical cycle time, 5-10 communications concept, 3-17, glossary-16 component-based automation, 3-17, glossary-15 compression, 4-13 configuration interrupt inputs, 6-39 standard ai, 6-41 standard di, 6-39 standard do, 6-41 technological functions, 6-44 consistent data, a-7 cpu 312c technical data, 6-3, 7-3, 7-8, 7-13, 7-26, 7-33 usage of integrated i/os, 6-28 cpu 313c technical data, 6-8 usage of integrated i/os, 6-30 cpu 313c-2 dp technical data, 6-14 usage of integrated i/os, 6-30 cpu 313c-2 ptp technical data, 6-14 usage of integrated i/os, 6-30 cpu 314c-2 dp technical data, 6-21 usage of integrated i/os, 6-30 cpu 314c-2 ptp technical data, 6-21 usage of integrated i/os, 6-30 cpu memory reset, 4-13 cpus 31xc differences, 2-3 cycle time calculation, 5-5 definition, 5-2 extension, 5-4 maximum cycle time, 5-9 process image, 5-2 sample calculation, 5-24 sequence of cyclic program processing, 5-3 time slice model, 5-2
index cpu 31xc and cpu 31x, technical data index-2 manual, edition 08/2004, a5e00105475-05 d data consistency, 3-16 diagnostics standard i/o, 6-46 technological functions, 6-46 differences between the cpus, 2-3 digital inputs configuration, 6-39 technical data, 6-47 digital outputs configuration, 6-41 fast, 6-48 technical data, 6-49 download of blocks, 4-11 e error displays, 2-11 g global data communication, 3-9 i i/o process image, 4-5 ie/pb link, glossary-17 industrial ethernet, 3-16, glossary-15 integrated i/os usage, 6-28, 6-33 interfaces mpi, 3-1 ptp interface, 3-3, 3-5 which devices can i connect to which interface?, 3-2 interrupt inputs, 6-45 configuration, 6-39 interrupt response time calculation, 5-22 definition, 5-21 of signal modules, 5-22 of the cpus, 5-21 process interrupt processing, 5-23 sample calculation, 5-27 interrupt, delay, 5-23 l load memory, 4-1 local data, 4-8 longest response time calculation, 5-18 conditions, 5-17 m maximum cycle time, 5-9 memory compression, 4-13 memory areas load memory, 4-1 ram, 4-2 system memory, 4-2 memory functions compression, 4-13 cpu memory reset, 4-13 download of blocks, 4-11 promming, 4-13 ram to rom, 4-13 restart, 4-14 uploading blocks, 4-12, 4-13 warm start, 4-14 mmc - useful life, 4-10 mode selector switch, 2-3, 2-6, 2-8, 2-10 mpi, 3-1 n network node, 3-11 o ob 83, 3-22 ob86, 3-22
index cpu 31xc and cpu 31x, technical data manual, edition 08/2004, a5e00105475-05 index-3 p power supply connector, 2-3, 2-6, 2-8, 2-10 process interrupt processing, 5-23 profibus, 3-16, glossary-15 profibus international, 3-17 profinet implementation, 3-17 profinet, 3-4, 3-16 interface, 3-3 objectives, 3-17 profinet cba, 3-17 profinet io, 3-17 profinet io, 3-18 ptp interface, 3-3, 3-5 r ram, 4-2 ram to rom, 4-13 required basic knowledge, iii response time calculating the longest, 5-18 calculating the shortest, 5-16 conditions for the longest, 5-17 conditions for the shortest, 5-16 definition, 5-14 dp cycle times, 5-14, 5-15 factors, 5-14 fluctuation width, 5-14 reduction with direct i/o access, 5-18 sample calculation, 5-25 restart, 4-14 retentive memory, 4-2 load memory, 4-2 retentive behavior of memory objects, 4-3 system memory, 4-2 routing access to stations on other subnets, 3-10 example of an application, 3-14 network node, 3-11 requirements, 3-13 s s7 basic communication, 3-7 s7 communication, 3-8 s7 connections distribution, 3-29 end point, 3-27 of cpus 31xc, 3-30 time sequence for allocation, 3-28 transition point, 3-27 sample calculation of the cycle time, 5-24 sample calculation of interrupt response time, 5-27 of the response time, 5-25 scope of this documentation, v sfb 52, 3-21 sfb 53, 3-21 sfb 54, 3-21 sfb 81, 3-21 sfc 49, 3-21 sfc 70, 3-21 sfc 71, 3-21 sfc102, 3-21 sfc13, 3-21 sfc5, 3-21 sfc58, 3-21 sfc59, 3-21 shortest response time calculation, 5-16 conditions, 5-16 simatic micro memory card plug-in mmcs, 6-2, 7-2 properties, 4-9 slot, 2-2, 2-6, 2-8, 2-10 simple network management protocol, 3-26 snmp, 3-26 ssl, 3-23 w#16#0696, 3-23 w#16#0a91, 3-23 w#16#0c91, 3-23 w#16#0c96, 3-23 w#16#0x94, 3-23 w#16#4c91, 3-23 w#16#xy92, 3-23 status displays, 2-11 system and standard functions, 3-21 system memory, 4-2, 4-5 i/o process image, 4-5 local data, 4-8
index cpu 31xc and cpu 31x, technical data index-4 manual, edition 08/2004, a5e00105475-05 t technical data analog inputs, 6-51 analog outputs, 6-53 cpu 312c, 6-3, 7-3, 7-8, 7-13, 7-26, 7-33 cpu 313c, 6-8 cpu 313c-2 dp, 6-14 cpu 313c-2 ptp, 6-14 cpu 314c-2 dp, 6-21 cpu 314c-2 ptp, 6-21 digital inputs, 6-47 digital outputs, 6-49 u upload, 4-12, 4-13 useful life of an mmc, 4-10 user program upload, 4-12, 4-13 w warm start, 4-14 watchdog interrupt, 5-23

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