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publication# 20315 rev. a amendment /0 issue date: august 1995 1 interfacing the am29200 risc microcontroller to the mace tm am79c940 ethernet controller application note by phil simmons introduction this report outlines the interface between a am29200 risc microcontroller and a mace am79c940 ethernet controller to address embedded applications. this solution targets system cost and shows a simple glue- less interface that can significantly reduce hardware de- sign time. the 29k series of microprocessors and microcontrollers are completely software compatible and hence enables a designer to visualize a range of products without having to re-invest major programming resources for every level of processor performance. am29200 risc microcontroller the am29200 microprocessor is the first in a line of risc microcontrollers based on the 29k architecture that targets systems that do not require the extremely high performance of other 29k microprocessors, but needs very low system cost made possible by the integration of processor, certain peripherals and sup- port logic. the on-chip functions include: a rom control- ler, a dram controller, a peripheral interface adapter, a dma controller, a programmable i/o port, a parallel port, a serial port, a video interface, and an interrupt controller. the solution shown in this application note provides a minimal interface between the am29200 risc microcontroller and the am79c940 mace network in- terface controller using the dma facilities integrated into the am29200. mace am79c940 ethernet controller the media access controller for ethernet (mace) is a lan controller designed for a system with centralized or system specific dma facilities. the controller has a high speed 16 bit slave register based interface where all transfers to or from the system are performed using sim- ple read and write cycles. the mace provides an ieee 802.3 interface that may be tailored to a specific application. it provides a com- plete ethernet node solution with integrated 10base-t transceiver and supports up to 25 mhz system clocks. the am79c940 embodies the media access control (mac) and physical layer signaling (pls) sub-layers of the ieee 802.3 standard, and provides an ieee defined attachment unit interface (aui) for coupling to an exter- nal medium attachment unit (mau). additional features also enhance over-all system de- sign. the individual transmit and receive fifos opti- mize system overhead, providing substantial latency during packet transmission and reception, and minimiz- ing intervention during normal network error recovery. the integrated manchester encoder/decoder eliminates the need for an external serial interface adapter (sia) in the node system. hardware design the objective of this design was to produce a processor- ethernet controller interface requiring minimal addi- tional support logic, but also providing the performance expected from ethernet. memory support the memory support required to implement this ether- net engine is both rom and ram based. the rom of choice is the am29f010 flash eprom, although read-only proms are equally applicable if field code up- dates are not necessary. this 5 v only device provides 128 kbytes of memory used primarily for instructions and parameters. the organization of this device is 8 bits wide and if the designer arranges 4 devices together to produce a 32 bit wide image then 512 kbytes provides both sufficient space to run real-world applications as well as the 32 bit bus width that provides an efficient code interface for the processor. if 90 ns devices are used, then the processor will perform 2 cycle access to the rom. dram is required as the destination of the ethernet packets from the network. the am29200 currently pro- vides an interface that will burst 3 cycles for an initial ac- cess to a page, followed by 2 cycles for all subsequent accesses to that page. this uses readily available 100 ns fast page mode drams and requires no support logic for control. dma options the am29200 provides either hardware or software op- tions for producing a dma engine that will transfer an ethernet packet between the mace and dram. software dma the 29k family of risc microprocessors provides two special instructions, load multiple (loadm) and store multiple (storem). these instructions provide the abil- ity to transfer up to 192 data words between on-chip
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 2 registers and memory structures with a single com- mand. this can produce a highly efficient dma engine under complete control of the software kernel, but can also be interrupted by a higher priority task. hardware dma the am29200 provides two on-chip dma channels. the designer can configure one channel to receive packets and the other to transmit packets (note that a printer ap- plication does not necessarily require a dma channel for transmit as almost all traffic is received and a trans- mit packet can be pre-loaded into the large mace fifo before being instructed to transmit). in order to give minimum code development time while meeting the performance requirements of ethernet full- wire speed (see performance), the design uses the hardware dma channels of the am29200. dma channel 0 is set for the receive queue and dma channel 1 for the transmit queue. when a frame is ready to be transmit- ted, the dma channel is configured to transfer the com- plete frame less one 16-bit word. when the transfer has completed, the last word is written to the mace fifo by a simple store command with the eof flag set to indi- cate end of frame. the receive transfer count is set to maximum and runs freely until the frame is completely received into dram at which point the mace will indicate that the last byte of the frame has been trans- ferred with the eof signal which terminates the dma by connecting to the tdma input to the am29200 dma controller. mace interface the mace is set to run at 16 mhz even though the de- vice can operate at 25 mhz. this is so that the interface is synchronous and so that no external logic is required. the sclk for the mace is therefore driven from the am29200 memclk output. the mace can be pro- grammed to operate from either the rising or falling edges. the am29200 requires valid data with respect to rising clock edges and therefore edsel is tied to ground on the mace. the mace is connected to the peripheral port of the am29200. as dma channel 0 and 1 are used and are both connected to the fifo chip select for the mace ( fds ), the piacs (0,1) signals must be anded to pro- vide the fifo select, and the register select for the mace ( cs ) can be directly connected to piacs2 . even though there is an output enable from the am29200 specifically for peripheral interfaces, the normal read/write signal (r/w) is used to meet timing requirements. the rdtreq and tdtreq dma requests issued by the mace are connected to the dreq (1-0) signals of the am29200 (channel 0 for receive and channel 1 for transmit queues). end of frame ( eof ) is connected to tdma though an inverting gate for receive cycles, and from a pio output through an open collector gate for transmit cycles. ethernet interface the mace incorporates both aui and 10base-t stan- dard interfaces. the aui interface can be used to pro- vide 10base-2 connectivity by using an external transceiver. the 10base-t interface simply requires the external filter/transformer and 6 resistors for protec- tion of the mace from the twisted-pair connection to the outside world. system power requirements the system power requirements are especially low for this design as the am29200 is highly integrated and the addition of support logic is minimal. the mace incorpo- rates three modes of sleep, and can be remotely or auto- matically awoken. when the mace is completely asleep the device typically requires 10 m a, when dozing requires typically 3 ma, and when fully operational re- quires typically 40 ma. the am29200 can initiate power savings for the mace by register updates and hardware control of the sleep pin which is connected to a pio output signal. timing diagrams the synchronous cycles required for transfers is programmable for both the am29200 and the mace devices. the peripheral interface on the am29200 that the mace connects to is programmed using software. an am29200 peripheral read cycle can be achieved in 3 clocks and a write cycle in 4 clocks. this design there- fore sets the transfer rate as 4 clocks for the am29200 so that read and write transfers are the same. the transfer timing for the mace is determined by the status of an external pin (tc). this is tied to ground so that the mace is configured to transfer in 3 clock cycles. the number for the am29200 and the mace differ be- cause the initial am29200 clock cycle is used to estab- lish addresses before asserting the appropriate peripheral chip select.
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 3 read cycle am29200 memclk a(23:0) r/ w piacsx id(31:0) s0 s1 s2 w0 w1 sclk add[4:0] r/ w cs or fds dbus[15:0] s3 am79c940 write cycle am29200 memclk a(23:0) r/ w piacsx id(31:0) s0 s1 s2 w0 w1 sclk add[4:0] r/ w cs or fds dbus[15:0] s3 am79c940 software this article describes some details for configuring a mace and the basic philosophy for transmission and re- ception of packets. initialization the mace will power-on with its registers set to the default values. the initialization sequence will configure the bus interface, set the fifo and interrupt configuration, set the ethernet interface configuration, run diagnostics, and then configure for online operation. bus interface (biucc) the byte swap is set to big endian and the transmit start point is set to 112 bytes so that the transmit fifo is as full as possible before transmission commences.
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 4 fifo configuration (fifocc) the transmit and receive fifo watermarks are set to the minimum values (xmtfw = 8 cycles, rcvfw = 16 bytes) so that the processor can commence dma as soon as possible. the update bits are set, in order that the watermarks can be modified. the transmit and re- ceive burst flags are set to enabled these functions. interrupt mask (imr) all interrupts are masked until initialization is complete. pls configuration (plscc) the 10base-t port is selected, but it can be overridden as the phycc register will set automatic port selection. phy configuration the link test, auto polarity correction, and auto port selection are all enabled. internal address (iac) set the address change. if multicast addressing is per- mitted, then the logaddr bit is set and the access is followed by 8 write cycles to the logical address register (ladrf), else the phyaddr bit is set and the access is followed by 6 writes to update the physical address register (padr). logical or physical addressing the logical address register requires a 64 bit mask, and is updated by performing 8 bytes writes, least sig- nificant to most significant. the physical address register is accessed in the same manner except only 48 bits are required through 6 byte write cycles. mac configuration (maccc) the transmit and receive functions are enabled by ac- cessing this register. performance ethernet performance is normally defined by the ability to transfer 64 byte ethernet packets at full wire speed as this requires highest system performance. ethernet will transfer packets at 10 mb/s. for this exam- ple the minimum packet size is defined as 72 bytes (64 bytes of information and 8 bytes of synchronization) and the interpacket gap will be 9.6 m s. using these parameters the cpu must process 14880 packets every second. minimum size packet cpu ethernet packet ieee 802.3 packet bits bytes bits bytes preamble 62 7.75 preamble 56 7 synchronization 2 .25 synchronization 8 1 destination address 48 6 destination address 48 6 source address 48 6 source address 48 6 type 16 2 length 16 2 data 368 46 data 368 46 checksum 32 4 checksum 32 4 total 576 72 total 576 72 time ( m s) @ 10mb/s 57.6 inter-packet-gap ( m s) 9.6 total packet time ( m s) 67.2 packets per second 14880
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 5 bus utilization bytes to be transferred to/from host (includes header and frame status) 64 transfers for 16 bit data bus (4 bytes frame status requires byte access) 34 clocks per dma transfer mace read/write 4 clocks per dma transfer dram read/write 3 total clocks per dma transfer (includes 1 clock dma turn around) 8 total clocks to dma minimum size packet 272 total time to dma minimum size packet @ 16 mhz (60 ns) 16.32 m s percentage bus bandwidth required for packet dma 24.29% time remaining following minimum size packet transfer 50.88 m s number of clocks per instruction (execution from flash memory) 2 time per 29200 instruction 120 ns number of instructions that can be executed in 50.88 m s 424 as all am29200 instructions execute in a single clock cy- cle (except loadm, storem, and iret) we can esti- mate the number of instructions available to perform a real world application while still operating at full ethernet wire speed. the 424 instructions figure is a quick estimate that can be expanded to include such things a interrupt latency, or refresh overhead, and gain an accurate number of instructions available to the programmer while writing driver code. conclusions the design shown here displays the ease of developing real world solutions with the am29200 microcontroller. performance can be quickly estimated due to the single clock per instruction execution unit for all members of the 29k family.
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 6 ;palasm design description ;CCCCCCCCCCCCCCCCCdeclaration segmentCCCCCC title am29200Cmace control pattern a revision 1.0 author phil simmons company amd date 02/21/93 chip _200_mace palce16v8 ;CCCCCCCCCCCCCCCCCCpin declarationsCCCCCCCC pin 2 /piacs0 ; input pin 3 /piacs1 ; input pin 4 /tdtreq ; input pin 5 /rdtreq ; input pin 6 pio1 ; input pin 7 rw ; input pin 8 /reset ; input pin 19 /fcs ; output pin 18 dreq0 ; output pin 17 dreq1 ; output pin 16 /eof ; io pin 15 tdma ; output ;CCCCCCCCCCboolean equation segmentCCCCCCCC equations fcs = piacs0 * /reset + piacs1 * /reset dreq0 = rdtreq * /reset dreq1 = tdtreq * /reset eof = /pio1 * /reset eof.trst = piacs1 * /reset tdma = piacs0 * rw * eof * /reset ;CCCCCCCCCCCCCsimulation segmentCCCCCCCCCCC simulation trace_on eof tdma dreq0 dreq1 fcs ;initialisation setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset ;receive data setf /piacs0 /piacs1 /tdtreq rdtreq pio1 rw /reset setf /piacs0 /piacs1 /tdtreq rdtreq pio1 rw /reset setf piacs0 /piacs1 /tdtreq rdtreq pio1 /eof rw /reset setf piacs0 /piacs1 /tdtreq rdtreq pio1 /eof rw /reset setf piacs0 /piacs1 /tdtreq rdtreq pio1 /eof rw /reset setf piacs0 /piacs1 /tdtreq rdtreq pio1 /eof rw /reset setf /piacs0 /piacs1 /tdtreq rdtreq pio1 rw /reset ;receive last byte of frame setf piacs0 /piacs1 /tdtreq rdtreq pio1 eof rw /reset setf piacs0 /piacs1 /tdtreq rdtreq pio1 eof rw /reset setf piacs0 /piacs1 /tdtreq rdtreq pio1 eof rw /reset setf piacs0 /piacs1 /tdtreq rdtreq pio1 eof rw /reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 7 setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset ;transmit data setf /piacs0 /piacs1 tdtreq /rdtreq pio1 rw /reset setf /piacs0 /piacs1 tdtreq /rdtreq pio1 rw /reset setf /piacs0 piacs1 tdtreq /rdtreq pio1 /rw /reset setf /piacs0 piacs1 tdtreq /rdtreq pio1 /rw /reset setf /piacs0 piacs1 tdtreq /rdtreq pio1 /rw /reset setf /piacs0 piacs1 tdtreq /rdtreq pio1 /rw /reset setf /piacs0 /piacs1 tdtreq /rdtreq pio1 rw /reset setf /piacs0 /piacs1 tdtreq /rdtreq pio1 rw /reset ;transmit last byte of frame setf /piacs0 piacs1 tdtreq /rdtreq /pio1 /rw /reset setf /piacs0 piacs1 tdtreq /rdtreq /pio1 /rw /reset setf /piacs0 piacs1 tdtreq /rdtreq /pio1 /rw /reset setf /piacs0 piacs1 tdtreq /rdtreq /pio1 /rw /reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset setf /piacs0 /piacs1 /tdtreq /rdtreq pio1 rw /reset trace_off ;CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 8 this page contains schematics which can be found in the npd data book pid#14287d
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 9 this page contains schematics which can be found in the npd data book pid#14287d
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 10 this page intentionally left blank.
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 11 this page contains schematics which can be found in the npd data book pid#14287d
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 12 this page contains schematics which can be found in the npd data book pid#14287d
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 13 this page contains schematics which can be found in the npd data book pid#14287d
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 14 this page contains schematics which can be found in the npd data book pid#14287d
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 15 this page contains schematics which can be found in the npd data book pid#14287d
amd interfacing the am29200 risc microcontroller to the mace am79c940 controller 16 this page contains schematics which can be found in the npd data book pid#14287d

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