motherboard clock generator fax id: 3505 icd2025 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 august 1994 C revised april 1995 1i cd20 25 features ? three independent clock outputs: separate cpuclk, sysclk and buffered reference clock ? ideally suited for 386/486 motherboard applications ? phase-locked loop output range of 1.843 mhz - 100 mhz ? phase-locked loop oscillator input derived from single 14.31818 mhz crystal ? sophisticated internal loop-filter requires no external components or manufacturing tweaks as commonly re- quired with external filters ? three-state oscillator control disables outputs for test purposes ? 5v operation ? low-power, high-speed cmos technology ? available in 16-pin soic pac kage functional description a modern personal computer motherboard often requires many different crystal can oscillators. the system logic fam- ily of frequency synthesis parts from cypress/ic designs re- places the large number of oscillators required to build such multi-function motherboards. these parts synthesize all the required frequencies in a single monolithic device, thus lower- ing manufacturing costs and significantly reducing the printed circuit borad space required. the icd2025 is a low-cost approach to the generation of the 3 necessary clocks required by any pc motherboard. pin configuration icd2025C1 1 2 3 4 5 6 7 8 9 10 sysbus sysclk oe gnd f ref /xtalin xtalout c0 s0 av dd cpuclk c3 v dd s2 c2 c1 s1 soic top view 11 12 13 14 15 16 rom xtalout oe vco cpuclk charge pump phase detector ? m pll #2 internal loop filter phaseClockedloop oscillator #1 gnd v dd av dd 7 7 ? n f ref / xtalin c0 c1 c2 c3 sysbus 14.318 mhz sysclk s0 s1 s2 icd2025C2 logic block diagram
icd2025 2025: 8/94 revision: april 10, 1995 2 pin summary name number description sysbus 1 buffered 14.31818 mhz crystal output (z) sysclk 2 system clock output (see ta bl e 2 ) oe 3 output enable three-states output when signal is lo. (pin has internal pull-up) gnd 4 ground f ref / xtalin [1] 5 reference oscillator input for all internal phase-locked loops (nominally from a parallel-resonant 14.31818 mhz crystal). optionally pc system bus clock. xtalout [1] 6 oscillator output to a refe rence crystal. c0 7 cpuclk select signal bit 0 (internal pull-up) s0 8 sysclk clock select signal bit 0 (internal pull-up) s1 9 sysclk select signalbit 1 (internal pull-up) c1 10 cpuclk select signal bit 1 (internal pull-up) c2 11 cpuclk select signal bit 2 (internal pull-up) s2 12 sysclk select signalbit 2 (internal pull-up) vdd 13 +5v to i/o ring c3 14 cpuclk select signal bit 3 (internal pull- down) cpuclk 15 cpu clock output (see cpuclk selection table) avdd 16 +5v to analog core note: 1. for best accuracy, use a parallel-resonant crystal, assume c load = 17 pf. available frequencies (mhz) sysclk cpuclk 1.843 16.000 3.686 20.000 8.000 25.000 12.000 32.000 18.432 33.333 20.000 40.000 24.000 50.000 32.000 66.667 80.000 100.000
icd2025 2025: 8/94 revision: april 10, 1995 3 general considerations cpu and system clock oscillator selection the frequency value of the cpu clock output (cpuclk) is selected by the four cpu clock select inputs: c0, c1, c2, and c3. this feature allows the i cd2025 to support different cpu speeds. the frequency v alue of the system clock output (sy- sclk) is selected by the three system clock selection inputs: s0, s1, and s2. the selection tables are shown in table 1 and 2 . at any time during operation, the select lines can be c hanged to select a different frequ ency. when this oc curs, the internal phase-lo cked loop will immediately seek the newly selected frequency. during the transition period, the clock output will multi plex glitch-free to the 14.31 818 mhz reference signal until the pll settles to the new freq uency. the timing for this tran- sition is shown in ac characteristics. output frequency accuracy the accuracy of the icd2025 output frequencies depends on the target output fre quencies. the tab les within this document contain target frequencies that differ from the actual frequen- cies produced by the clock synthesizer. the output frequencies of the icd2025 are an integral fraction of the input (reference) frequency: f (out) = (2 f (ref) p / q ) only certain output frequencies are possible for a particular reference frequency. however, the icd2025 always produces an output frequency within 0.1% of the target frequencies list- ed, which is more than sufficient to meet standard system logic requirements. (actual values are given in the tables.) three-state output operation the oe signal, when pulled low, will three-state the sy- sclk, cpuclk, and sysbuf output lines. this supports procedures such as automated testing, where the clock must be disabled. the oe signal contains an internal pull-up but should be tied to v dd if not used. short-term stability (also called bit-jitter) is a manifestation of the frequency synthesis pro cess. the cypress/ic designs fre- quency synthesis parts have been designed with an emphasis on reduction of bit-jitter. the primary ca use of this phenome- non is the dance of the vco as it strives to maintain lock. low-gain vcos and sufficient loop filtering are design ele- ments specifically included to minimize bit-jitter. the ic de- signs families of fre quency synthesis components are all guar- anteed to operate at a jitter rate low e nough for system logic applications. table 1. cpuclk selection c3 c2 c1 c0 word desired freq. (mhz) actual freq. (mhz) error (ppm) 0 0 0 0 0 40.000 39.812 4734 0 0 0 1 1 80.000 79.623 4734 0 0 1 0 2 33.333 33.322 320 0 0 1 1 3 66.667 66.645 335 0 1 0 0 4 25.000 25.000 0 0 1 0 1 5 50.000 50.000 0 0 1 1 0 6 16.000 15.923 4848 0 1 1 1 7 32.000 31.846 4848 1 0 0 0 8 20.000 19.906 4734 1 0 0 1 9 100.000 99.840 1600 1 0 1 0 10 40.000 39.812 4734 1 0 1 1 11 80.000 79.623 4734 1 1 0 0 12 33.333 33.322 320 1 1 0 1 13 66.667 66.645 335 1 1 1 0 14 25.000 25.000 0 1 1 1 1 15 50.000 50.000 0 table 2. sysclk selection s2 s1 s0 word desired freq. (mhz) actual freq. (mhz) error (ppm) 0 0 0 0 18.432 18.431 62 0 0 1 1 20.000 20.003 167 0 1 0 2 24.000 23.998 80 0 1 1 3 1.843 1.843 144 1 0 0 4 12.000 11 . 99 9 80 1 0 1 5 8.000 8.001 167 1 1 0 6 3.686 3.687 144 1 1 1 7 32.000 32.005 167
icd2025 2025: 8/94 revision: april 10, 1995 4 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage to ground potential .................- 0.5v to +7.0v dc input voltage ..........................................- 0.5v to v dd +0.5v storage temperature ....................................... - 65 c to +150 c max soldering temperature (10 sec) ............................ 260 c junct ion temperature.................................................... 125 c operating range ambient temperature v dd & av dd 0 c t ambient 70 c 5v 5% electrical characteristics over the operating range icd2025 parameter description test conditions min. max. unit v oh output high voltage i oh = - 4.0ma 2.4 v v ol output low voltage i ol = 4.0 ma 0.4 v v ih input high voltage except crystal inputs 2.0 v v il input low voltage wxcept crystal inputs 0.8 v i ih input high current v ih = v dd - 0.5v 150 m a i il input low current v il = 0.5v - 250 m a i oz output leakage current (three-state) 10 m a i dd power supply current inputs @ v dd or gnd 60 ma i add analog power supply current 6 ma
icd2025 2025: 8/94 revision: april 10, 1995 5 switching characteristics over the operating range [2] parameter name drscription min. typ. max. unit f (ref) reference frequency reference oscillator nominal value 4 14.318 26 mhz t (ref) ref clock period 1 ? f (ref) 38.5 69.8 2500 ns t 1 input duty cycle duty cycle for the inputs defined as t 1 ? t (ref) 25% 50% 75% t 2 output period cpuclk output value 10 100 mhz 544 1.84 mhz ns t 3 output duty cycle duty cycle for the outputs defined as t 3 ? t 2 (measured at 2.5v) 40% 60% t 4 rise time rise time for the outputs into a 25 pf load 4 ns t 5 fall time fall time for the outputs into a 25 pf load 4 ns t 6 three-state time for the outputs to go into three-state mode after oe signal assertion 12 ns t 7 clk valid time for the outputs to recover from three-state mode after oe signal goes high 12 ns t muxref clk stable time required for the outputs to become valid after c0 - c3 or s0 - s2 select signals change value 3.4 5 6.9 msec t freq1 freq1 output old frequency output t freq2 freq2 output new frequency output t 8 f (ref) mux time time clock output remains high while out- put muxes to reference frequency ns t 9 t freq2 mux time time clock output remains high while out- put muxes to new frequency value ns note: 2. input capacitance is typically 10 pf, except for the crystal pads. t ref () 2 --------------- 3 t ref () 2 --------------- t freq2 2 ------------- 3 t freq2 2 -------------
icd2025 2025: 8/94 revision: april 10, 1995 6 switching waveforms rise and fall times icd2025C3 f (ref) cpuclk sysclk sysbus t 2 t 3 t 4 t 5 10% 90% 10% 90% t (ref) t 1 three-state timing icd2025C4 oe cpuclk sysclk t 6 t 7 threeCst ateoutput vclkout icd2025C5 s0 s1 (internal timeout) t freq1 t 8 t (ref) t 9 t freq2 t muxref original frequency vco settle time new frequency selection timing
icd2025 2025: 8/94 revision: april 10, 1995 ? cypress s emiconduc tor corporation, 1996. the information contained herein is subject to change without noti ce. cypress semiconductor corporation assumes no re sponsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it c onvey or imply any license under patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress semiconduc tor products in life-support sy stems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress semiconductor against all charges. test circuit note: all capacitors should be placed as close to each pin as possible. 4 16 22 m f v dd v dd c load outputs 13 .01 m f .01 m f 22 w icd2025C6
icd2025 2025: 8/94 revision: april 10, 1995 8 example: order i cd2025sc for the icd2025, 16-pin plastic soic, commercial temperature range device. document #: 38 - 00398 ordering information [3] ordering code package name package type operating range icd2025 - s1 16-pin soic commercial [4] notes: 3. contact your local cypress representative. 4. 0c to +70c package diagram 16-lead molded soic s1 icd2025C7
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