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ds04-28309-3e fujitsu semiconductor data sheet assp tv/vcr d/a converter (3 ch, 8 bit) MB86029 n description the MB86029 is a 3-channel high-speed cmos 8-bit d/a converter for tv and vcr application. the MB86029 features on-chip voltage reference, pedestal insertion, and power-down circuits, and a maximum conversion speed of 60 msps for digital tv and graphic display application. n features ? functions maximum conversion speed: 60 msps max. current output mode output current adjusted by external resistor pedestal insertion power-down function on-chip reference power supply (external reference power supply can be used.) ?conversion ? supply voltage single +5 v supply ? current consumption typical stage: 500 mw power-down mode: 20 mw max. n packages characteristics load resistance 37.5 w 75 w 150 w output voltage amplitude 0.80v 1.60v 1.60v conversion speed 60 mpsp 30 mpsp 20 mpsp (dip-42p-m03) 42 pin, plastic dip (fpt-48p-m16) 48 pin, plastic qfp this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circu it.
2 MB86029 n pin assignments b6 1 42 b7 b5 2 41 clk b4 3 40 blank b3 4 39 v ddd b2 5 38 pd b1 6 37 v rout b0 7 36 v rin v ssd 8 35 ped bout 9 34 fs v dda 10 33 v dda v dda 11 32 v dda gout 12 31 rout v ssa 13 30 v ssa g0 14 29 r0 g1 15 28 r1 g2 16 27 r2 g3 17 26 r3 g4 18 25 r4 g5 19 24 r5 g6 20 23 r6 g7 21 22 r7 v rout v rin ped fs v dda nc. v dda rout v ssa r0 r1 r2 (top view) (dip-42p-m03) v ssa 1 pd 2 v ddd 3 blank 4 clk 5 b7 6 b6 7 b5 8 b4 9 b3 10 b2 11 b1 12 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 36 nc. 35 r3 34 r4 33 r5 32 r6 31 r7 30 g7 29 g6 28 g5 27 g4 26 g3 25 nc. (top view) (fpt-48p-m16) b0 v ssd v ssa bout v dda v dda nc. gout v ssa g0 g1 g2
3 MB86029 n pin descriptions circuit pin no. symbol i/o pin name function dip fpt power supply circuit 10, 11, 32, 33 17, 18, 42, 44 v dda analog power supply analog power supply +5v 13, 30 1, 15, 21, 40 v ssa analog ground analog power supply ground 39 3 v ddd digital power supply digital power supply +5 v 8 14 v ssd digital ground digital power supply ground input circuit 22 to 29 39 to 37, 35 to 31 r0 to r7 i digital signal input digital signal input. msb : r7, g7, b7 lsb : r0, g0, b0 14 to 21 22 to 24, 26 to 30 g0 to g7 i 1 to 7, 42 13 to 6 b0 to b7 i 38 2 pd i power-down control high : power-down mode low : operating 41 5 clk i clock input data is read in, and analog signal is output on the falling edge of the clk. 40 4 blank i pedestal control high : pedestal output low : no pedestal 36 47 v rin i external voltage reference for connection of an external reference voltage (2.5 v typ.) output circuit 31 41 rout o analog output analog rgb output 12 20 gout o 9 16 bout o 34 45 fs o full-scale current adjustment the full-scale current is adjusted by an external resistor connected between this pin and the gnd pin. 35 46 ped o pedestal current adjustment the pedestal current is adjusted by an external resistor connected between this pin and the gnd pin. 37 48 v rout o reference voltage output on-chip 2.5 v reference output
4 MB86029 n block diagram decoder latch circuit circuit 8 bit dac 1 bit dac 8 decoder latch circuit circuit 8 bit dac 1 bit dac 8 decoder latch circuit circuit 8 bit dac 1 bit dac 8 reference voltage circuit pedestal current adjustment circuit full-scale current adjustment circuit r0 to r7 g0 to g7 b0 to b7 blank clk pd rout gout bout v dda (+5 v) v ssa (0 v) v ddd (+5 v) v ssd (0 v) v rout v rin ped 5.1 k w fs 5.1 k w :data signal :control signal 2.5 v
5 MB86029 n absolute maximum ratings * : v dd = v ddd = v dda note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating conditions * : v dd = v ddd = v dda (v ssd = v ssa = 0 v, ta= +25 c) parameter symbol rating unit power supply voltage v dd * C0.3 to +7.0 v analog power supply current i dda C10 to +200 ma analog ground current i ssa C10 to +50 ma digital supply current i ddd C200 to +10 ma digital ground current i ssd C10 to +50 ma analog output current i o C10 to +30 ma digital input/output current i i/o C10 to +10 ma input/output voltage v i/o C0.3 to v dd +0.3 v storage temperature t stg C40 to +125 c (v ssd = v ssa = 0 v) parameter symbol value unit min. typ. max. power supply voltage v dd * 4.75 5.00 5.25 v reference power supply input voltage v rin 2.2 2.5 2.8 v low-level digital input voltage v il 0 0.8 v high-level digital input voltage v ih 2.2 v dd v ambient operating temperature t op 0 25 70 c
6 MB86029 n electrical characteristics 1. dc characteristics * : v dd = v ddd = v dda ? output voltage setting conditions * : the output voltage amplitude can be adjusted with slight changes in external resistances. (v dd * = 4.75 to 5.25 v, v rin = 2.5 v, v ssd = v ssa = 0 v, ta= 0 c to +70 c) parameter symbol conditions value unit min. typ. max. nonlinearity le see the table below for conditions 1 1 lsb differential linearity de see the table below for conditions 1 1 lsb full-scale current i fs see the table below for conditions 1 18.0 20.0 22.0 ma see the table below for conditions 2 18.0 20.0 22.0 see the table below for conditions 3 9.2 10.2 11.2 pedestal current i ped see the table below for conditions 1 1.12 1.25 1.38 ma see the table below for conditions 2 1.12 1.25 1.38 see the table below for conditions 3 0.57 0.64 0.71 channel to channel matching error dm i fs average variation between channels under condition 1 5.0 %fsr output voltage range v oc 0 1.6 v supply current i d see the table below for conditions 1 100 120 ma see the table below for conditions 2 100 120 see the table below for conditions 3 60 70 reference output voltage v rout 2.4 2.5 2.6 v conditions output voltage amplitude r fs * r ped * load resistance maximum conversion speed condition 1 (typical condition) 0.8 v 5.1 k w 5.1 k w 37.5 w 60 msps condition 2 1.6 v 5.1 k w 5.1 k w 75 k w 30 msps condition 3 1.6 v 10 k w 10 k w 150 k w 20 msps
7 MB86029 2. ac characteristics * : v dd = v ddd = v dda ? output voltage setting conditions * : the output voltage amplitude can be adjusted with slight changes in external resistances. (v dd * = 4.75 to 5.25 v, v rin = 2.5 v, v ssd = v ssa = 0 v, t a = 0 c to +70 c) parameter symbol conditions value unit min. typ. max. output rise time t r 2 ns output fall time t f 2 ns high-level pulse width t wh 6 ns low-level pulse width t wl 6 ns clock signal period t ck 16.6 ns setup time t su 8 ns hold time t h 2 ns output propagation deley time t d 20 ns settling time t s see the table below for conditions 1 15 ns see the table below for conditions 2 30 see the table below for conditions 3 50 output transition time t tlh see the table below for conditions 1 6 ns see the table below for conditions 2 12 see the table below for conditions 3 20 output trasition time t thl see the table below for conditions 1 6 ns see the table below for conditions 2 12 see the table below for conditions 3 20 conditions output voltage amplitude r fs * r ped * load resistance maximum conversion speed condition 1 (typical condition) 0.8 v 5.1 k w 5.1 k w 37.5 w 60 msps condition 2 1.6 v 5.1 k w 5.1 k w 75 k w 30 msps condition 3 1.6 v 10 k w 10 k w 150 k w 20 msps
8 MB86029 n timing chart clock signal (clk) t wh t wl t r t f t su t h t s t d t thl , t tlh v ih data (n) data (n + 1) data (n) data (n + 1) 90% 50% 10% 1lsb 1lsb note: r0 to r7, g0 to g7, b0 to b7 are read on the rising edge of the clock. v ih v fs v zs v il v il output signal (rout) (gout) (bout) input signal (r0 to r7) (g0 to g7) (b0 to b7) (blank)
9 MB86029 n output voltage calculation the dac output voltage can be calculated from the load resistance, external resistors, and reference voltage values. v o [mv] = r l [ w ] x ( x x + x b) x v rin [v] x =$00 to $ff digital signal input code b =0 (without pedestal voltage) =1 (with pedestal voltage) k fs =0.16 (constant) k ped =2.56 (constant) r l =load resistance r fs , r ped = external resistors v rin =reference voltage n output voltage characteristics 1. with pedestal table of equation for output voltage code output waveform chart 2. without pedestal table of equation for output voltage code output waveform chart k fs r fs [k w ] k ped r ped [k w ] output voltage code blank 800.0 mv 425.1 mv 47.2 mv 0.0 mv $ff $80 $00 $00 "h" "h" "h" "l" [condition] r fs = r ped = 5.1 k w , v rin = 2.5 v, r l = 75 w (according to the above conditions, 1 lsb = approx. 3.0 mv) white level pedestal voltage black level blank level output voltage code blank 752.8 mv 377.9 mv 0.0 mv $ff $80 $00 "l" "l" "l" [condition] r fs = r ped = 5.1 k w , v rin = 2.5 v, r l = 75 w (according to the above conditions, 1 lsb = approx. 3.0 mv) white level black level
10 MB86029 n specificaiton of analog output current 1. pedestal current not output 2. pedestal current not output analog output current digital input code d7 d6 d5 d4 d3 d2 d1 d0 blank 0 0 0 0 0 0 0 0 0 0 i fs 0 0 0 0 0 0 0 1 0 i fs 0 0 0 0 0 0 1 0 0 i fs 0 0 0 0 0 0 1 1 0 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : i fs 1 1 1 1 1 1 0 1 0 i fs 1 1 1 1 1 1 1 0 0 i fs 1 1 1 1 1 1 1 1 0 i fs :full-scale current analog output current digital input code d7 d6 d5 d4 d3 d2 d1 d0 blank i ped 0 0 0 0 0 0 0 0 0 i ped + i fs 0 0 0 0 0 0 0 1 0 i ped + i fs 0 0 0 0 0 0 1 0 0 i ped + i fs 0 0 0 0 0 0 1 1 0 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : i ped + i fs 1 1 1 1 1 1 0 1 0 i ped + i fs 1 1 1 1 1 1 1 0 0 i ped + i fs 1 1 1 1 1 1 1 1 0 i fs : full-scale current i ped : pedestal current 255 1 255 2 255 3 255 253 255 254 255 255 255 1 255 2 255 3 255 253 255 254 255 255
11 MB86029 n application circuit digital input digital power supply analog output analog power supply r g b r0 to r7 g0 to g7 b0 to b7 blank clk pd v ddd v ssd 5 v rout gout bout v rout v rin v dda v ssa 5 v 5.1 k w 5.1 k w 75 w 75 w 75 w 75 w 75 w 75 w 75 w coaxial cable 75 w coaxial cable 75 w coaxial cable MB86029 ped fs r g b
12 MB86029 n package dimensions (dip-42p-m03) 42 pin, plastic dip +0.50 C0 +.020 C0 +0.20 C0.30 +.008 C.012 C0 +.020 C0 +0.50 0.865 .034 index-2 52.40 2.063 13.800.25 (.543.010) 15max typ 15.24(.600) (.010.002) 0.250.05 0.51(.020)min (.018.003) 0.460.08 typ 2.54(.100) max 1.27(.050) 3.00(.118)min 4.96(.195)max .050 1.27 index-1 1994 fujitsu limited d42009s-2c-2 c dimensions in mm (inch). (continued)
13 MB86029 (fpt-48p-m16) 48 pin, plastic fpt dimensions in mm (inch). +0.05 C0.01 +.002 C.0004 +0.30 C0.10 +.012 C.004 0.15 .006 12.00 .472 0.05(.002)min (stand off) "b" (.071.012) 1.800.30 0~10 0.15(.006)max 0.50(.020)max 0.20(.008) 0.15(.006) "a" sq sq (.677.016) lead no. 0.80(.0315)typ 48 13 24 37 36 25 112 details of "b" part index 0.15(.006) ref (.346) (.535.016) 8.80 13.600.40 2.70(.106)max m 0.16(.006) (.012.002) 0.300.06 17.200.40 details of "a" part 1994 fujitsu limited f48026s-1c-1 c
16 MB86029 all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 f9703 ? fujitsu limited printed in japan

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