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soc k et 754 design and qualification requirements p u b l i c a t i o n # 2485 0 re v: 3.07 i s s u e d a t e : augu st 20 03
? 2001?2003 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (?amd?) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel, or otherwise, to any intellectual property rights are granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd?s product co uld create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. trademarks amd, the amd arrow logo, amd athlon, and combinations thereof are trademarks of advanced micro devices, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements contents revision history ............................................................................................................... .............. 7 1 i n t r o d u c t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........... 9 1 . 1 o b j e c t i v e ................................................................................................................. .... 9 1 . 2 r e l a t e d inform ation ....................................................................................................... 1 0 1 . 3 a b b r e v i a t i o n s .............................................................................................................. ... 11 2 processor p a ckage descriptions .............................................................................................. 13 3 socket 754 design requirements ............................................................................................ 15 3 . 1 s o c k e t 7 5 4 ................................................................................................................ ... 15 3 . 2 base and cover ............................................................................................................. . 17 3 . 2 . 1 socket 754 vendor marking .................................................................................. 17 3 . 2 . 2 other socket 754 markings ................................................................................... 17 3 . 3 socket 754 contact material and plating ...................................................................... 18 4 s o c k e t 7 5 4 q u a l i f i c a t i o n r e q u i r e m e n t s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 . 1 qualification test report .............................................................................................. 19 4 . 2 t e s t i n g ................................................................................................................... 19 5 documentation requirements ................................................................................................. 21 6 mechanical test procedure conditions and requirements ................................................. 23 6 . 1 t e s t m a t r i x ............................................................................................................... .... 23 7 electrical qualification requirements ................................................................................... 29 7 . 1 f i x t u r e ................................................................................................................... 29 7 . 1 . 1 capacitance and inductance matrices ................................................................... 29 7 . 1 . 2 mated partial self inductance ................................................................................ 29 7 . 1 . 3 mated loop inductance ......................................................................................... 30 contents 3
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 7 . 1 . 4 mated partial loop inductance matrix .................................................................. 30 7 . 2 d i f f e r e n t i a l im pedance definition ................................................................................. 3 1 7 . 2 . 1 d i f f e r e n t i a l im pedance .......................................................................................... 3 2 7 . 3 differential and single e nded crosstalk ....................................................................... 33 7 . 3 . 1 t e s t procedure ....................................................................................................... 3 3 7 . 3 . 2 t e s t condition ....................................................................................................... 3 3 7 . 3 . 3 r e q u i r e m e nts ......................................................................................................... 3 3 7 . 4 p r o p a g a t i o n delay skew ................................................................................................ 3 3 7 . 4 . 1 single ended propagation delay skew ................................................................. 34 7 . 4 . 2 differential propagation delay skew .................................................................... 35 7 . 5 c a p a c i t a n c e ............................................................................................................... .... 35 7 . 5 . 1 t e s t procedures ...................................................................................................... 3 5 7 . 5 . 2 t e s t condition ....................................................................................................... 3 6 7 . 5 . 3 r e q u i r e m e nts ......................................................................................................... 3 6 7 . 6 e l e c t r i c a l s p ecifications ................................................................................................ 36 4 contents
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements list of figures figure 1. a 3-d view of socket 754 ............................................................................................. ........... 9 figure 2. 754-pin opga package drawing ........................................................................................ . 13 figure 3. so cket 754 outlin e ................................................................................................... ............... 16 figure 4. recommended pcb keepout .............................................................................................. .... 17 figure 5. socket 754 qualification t e st matrix ................................................................................. .... 23 figure 6. pin configuration for the maxwell capacitance an d partial inductance matrix measurem ent .................................................................................. 29 figure 7. loop measurem ent for ext r acting [l p ] for a mated three-pin c o m b ination ........................ 30 figure 8. current/voltag e def i nition s and equiv a lent circuit of the partial ?loop? inductance matrix ........................................................................................... 31 figure 9. pin configurations for the propa gation delay skew measurem ents of single-ended signals .......................................................................................................... ..... 3 4 list of figu res 5
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 list of tables table 1 list of abbreviations .................................................................................................. ...... 11 table 2. mechanical qualification t e st procedures ...................................................................... 24 table 3. summary of required measurem ents for the socket 754 ............................................... 37 6 list of tables
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements revision history d a t e r e v d e s c r i p t i o n july 20 03 3.07 corrected the base opening mea s ure m ents given in note 14 and note 15 of figure 3, s o cket 754 outl i n e. novem b er 2002 3.01 initial public release. revision history 7
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 8 revision history
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements 1 intr oduction 1.1 objective this document defines the socket 754, shown in figure 1 as it is intended f o r use in value and perform a nce desktop and worksta tion applications using an amd athlon? 64 processor. socket 754 is a zero in sertion forc e (zif) m i c r o pin grid array ( pga) socket using ball grid array (bga) surface m o unt techno log y on 1.27 mm pitch. figure 1. a 3-d view of socket 754 socket 754 dim e nsional, perform a n ce, and qualification testing requir em ents are defined and designed to ensure that socket 754 perform s to the am d electrical and m echanical design requ irem ents. this document includes socket 754 outline and qualif ic atio n tes t s r e quired f o r a su pplie r to b e com e qualified by amd as a socket 754 vendor. s o cket 754 is designed for the amd product line of m i croprocessors. chapter 1 introduction 9
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 1.2 related information the following docum ents contain ad dition a l info rm a tion related to the so cket 754 m i croprocessor: note : e i a standards are referenced throughout this document to help perf orm measurements. the eia standards from global engineering can be found on the global e ngineering website at http://global.ihs.com or by calling 1-800-624-3974. eia 364?09 durability test procedure for electrical connectors and contacts eia 364?1 1 resistance to solvents test pro cedure for electrical connectors and sockets eia 364?1 7 tem p erature life with or without electrical load test procedure for electrical connectors and sockets eia 364?2 0 withstanding voltage test procedure fo r electrical connectors, so ckets, and coaxial contacts eia 364?2 1 insulation resistance test procedure for electrical co nnectors sockets and coaxial contacts eia 364?2 3 low level contact resistance test procedure for electrical connectors and sockets eia 364?2 7 mechanical shock (specified pulse) test procedure for electrical connectors eia 364?2 8 vibration test procedure for electrical connectors and sockets eia 364?3 0 capacitance test procedure for electrical connectors eia 364?3 1 hu m i dity tes t procedure for electrical connectors and sockets eia 364?3 2 therm a l shock (tem perature cy clin g) test procedure for electrical connectors and sockets eia 364?48 test procedure for metallic coating thic kness measur e m e nts of co ntacts eia 364?5 6 resistance to soldering he at t est procedure for electrical connectors eia 364?6 0 test procedure no.60 general methods for porosit y t esting of con t act finishes for electrical co nnectors eia 364?6 5 mixed flowi ng gas eia 364?7 0 tem p erature rise versus current test procedure for electrical co nnectors and sockets eia 364?9 0 crosstalk ratio test procedure for electrical connectors, sockets, cable assem b lies or interconnection sy stem s eia 364?1 03 propagation delay test procedure for el ectrical con n ectors, sock ets, cable assem b lies, or interconne ction s y stems eia 364?1 08 im pedance, reflection coefficient, retu rn loss, and vswr measured in the ti me and frequency d o main test procedure for electrical co nnectors, cable ass e m b lies or interconnection sy stem s 10 introduction chapter 1
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements 1.3 abbreviations table 1 shows a list of abbrevia tions used in this docum ent. table 1 list of abbreviations a b b r e v i a t i o n d e f i n i t i o n amd advanced micro devices e i a e l e c t r o n i c i n d u s t r i e s a s s o c i a t i o n lcp liquid crystal polym e r llcr low level contact res i stan ce s m i c r o s econ d bga micro ball grid array pga micro pin g r id array m ? ?
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 12 introduction chapter 1
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements 2 pr ocessor package descriptions the 754-pin opga processor package is illustrated in figure 2. the pin a1 designator is shown in the pin a1 location. figure 2. 754-pin opga package draw ing note: socket 754 must be designed so that a 1.95 mm o pga package pin length makes full electrical contact. chapter 2 processor p a ckage descriptions 13
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 14 processor p a ckage descriptions chapter 2
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements 3 socket 754 design requir ements this chapter shows the design requirem ents for the socket 754, including: ? socket 754 ? base and cover ? vendor m a r k ings ? other m a rkings ? contact m a terial and plating 3.1 socket 754 a socket 754 outline is illus t rated in figure 3 on page 16. the critical dim e nsions and required n o tes are shown. the pin a1 designator is shown on the socket 754 outline . the pga pin pattern is not symmetrical. the opga processor package m a y only be inse rted o n e way into socket 754 . the socket 754 does not incorporate tabs for heat si nk attachm e nt. the recomm ended pcb keepout for socket 754 is shown in figure 4 on page 17. chapter 3 socket 754 design requirements 15
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 figure 3. socket 754 outline 16 socket 754 design requirements chapter 3
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements figure 4. recommended pcb keepout 3.2 base and cover socket 754 base and co ver is m a de of liquid cry s ta l po lym e r (lcp) with a ul fla m m a bility rating of 94v-0. the base color is black a nd the cover is natural in color. 3.2.1 sock et 754 vendor mark ing socket 754 must be m o lded into the cam box as shown in figure 3 on page 16. the vendors ul approved tradem ark identifier and lo t traceab ility num b er m u s t be shown on the socket 754 such that, af ter solde r ing to the printed cir c uit board (pcb), it is vis i ble and re a d able. the lot tra c eab ility num b er can be ink stam ped or laser m a rked. 3.2.2 other socket 754 mark ings an open and close designator m u st be m o lded in to the cam box in close proxim ity to the lever handle. chapter 3 socket 754 design requirements 17
socket 754 design and qualification requirements 2485 0 rev. 3.07 aug ust 2003 18 socket 754 design requirements chapter 3 3.3 socket 754 contact material and plating the contact material must be high strength copper alloy. plating must be 30 micro inches (minimum) gold over 50 micro inches minimum nickel in the c ontact area. the solder ball on the bottom side must be 0.76 0.15 millimeter diameter , tin/lead (63/37 5%). the contact must be plated to create a solder barrier that prevents th e solder from wicking up into the contact area during soldering.
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements 4 socket 754 qualification requir ements all qualification testing must be co nducted in a m d?s designated test f acilities. qu alif ica tion te stin g expenses are the responsibility of the socket 754 s upplier. qualification tes ting m u st be perform e d on production lots of socket 754. 4.1 qualification test report a test repo rt m u st be written for each test listed in figure 5 on page 23. all tes t reports for groups 1 to 8 and group 10 m u st be presented in one folder. gr oup 9 can be presented in a separate folder. the test report must contain the following for each test conducted: ? ? ? ? ? ? ? ? ? ? ? ? 4.2 testing please con t act the local amd field application s engi neer (f ae) for testing locations. the local am d fae can be reached at 1 - 800-538-84 50. chapter 4 socket 754 qualif ication requirements 19
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 20 socket 754 qualification requirements chapter 4
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements 5 documentation requir e ments the supplier of the socket 754 m u st subm it a m i nim u m a m ount of docum entation to amd. ? ? ? ? ? ? ?
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 22 documentation requirements chapter 5
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements 6 mechanical t e st pr ocedur e conditions and requir e ments 6.1 test matrix the socket 754 qualification m a trix is shown in figure 5. figure 5. socket 754 qualification test matrix chapter 6 mechanical test proced ure conditions and requirements 23
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 for a socket 754 to be added to the amd deve lopm en t partners list, they m u st m eet all m e chanical requirem e nts listed in t a ble 2 and electrical requirem ents shown in section 7 on page 29, when t e sted in the s e que nce listed in figure 5 on page 23. table 2. mechanical qualification test proced ures test proced ure test condition requireme n ts lo w level contact resistance (llcr) eia 364-23 100 m a maxim u m, 20 mv 336 con t acts (168 con t act pairs) (m inim u m ) m onitored per test sa m p le record initially after testing, llcr-per-co n tact m u st not exceed 20.0 m ? mechanical shock eia 364-27 condition a 50 g, 11 m s , half-sine conducted wi th 45 0 g heatsink test mas s attached to the retention mechanis m a nd pcb asse m b ly no ph y s ical d a m a ge no contact interruptions gr eater than 1.0 s. random vibration eia 364?28, condition vii, level d 3.1 g rm s, 20 to 50 0 hz, 1 5 minutes per axis duration conducted wi th 45 0 g heatsink test mas s attached to the retention mechanis m a nd pcb asse m b ly no ph y s ical d a m a ge no contact interruptions gr eater than 1.0 s. llcr 20.0 m ? durability eia 364?0 9 fifty c y cles per test sample no ph y s ical d a m a ge llcr 20.0 m ? thermal shock eia 364?3 2 ?55c to +11 0 c, 30 m i nutes at each extre m e, five cy cles group 2 samples exposed to the environm ent mated group 3 samples exposed to the environm ent unm ated no ph y s ical d a m a ge group 2?ll cr 20 m ? ? 24 mechanical test proced ure conditi ons and requirements chapter 6
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements table 2. mechanical qualification test proced ures (continued) test proced ure test condition requireme n ts cyclic hu m i dity eia 364-31 method iii condition c 25 to 65c, at 90 to 95% relative hum idity group 2 samples exposed to the environm ent mated group 3 samples exposed to the environm ent unm ated no ph y s ical d a m a ge group 2?ll cr ? 20.0 m ? ? insulation resistance (ir) eia 364-21 20 adjacent contacts, 500 vdc 1000 m ? dielectric withstanding voltage (dwv) eia 364-20 20 adjacent contacts, 650 vac no breakdown, flashover, arcing, etc. mixed flow ing gas eia 364-65 condition ii a chlorine 10 ppb hy dr ogen su lfide 10 p pb nitrogen dio x ide 200 ppb sulfur dioxi d e 100 ppb tem p erature 30c relative hu midit y 70 % duration 10 day s total: first five days one half sam ples mated and one half unm ated second five d a y s all sam p les are mated no ph y s ical d a m a ge llcr 20.0 m ? temperatu re life eia 364-17 method a +115c, 432 hours no ph y s ical d a m a ge llcr 20.0 m ?
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 table 2. mechanical qualification test proced ures (continued) test proced ure test condition requireme n ts solvent res i stance eia 364-11 four sol u tion test in table 1 of eia 364-11 no ph y s ical d a m a ge and markings are legible socket retention clam p socket 754 so that a p ga package is ac cessible. place a pg a package in the clam ped socket 754, then close and lock the socket. with socket 754 l o cked, p u ll the pga pa cka g e out of the socket and record the force required. extraction for ce to be 8 kg m i n i mu m record the forces required. porosity (gold contacts only) eia 364-60 test loose contacts (quantity - 20) procedure 1.1 . 1 (au/ni): nitric acid technique count and re cord pores. plating thickness eia 364-48 method c 20 contacts? measure the gold and nickel thickness. thickness m a y be m e asure d by x- ray , florescen ce, or cross sectioning. 30 m i croinch minim u m ? gold 50 m i croinch minim u m ? nickel resistance to solder heat eia 364-56 using convection reflow, s o lder the socket 754 t o the pcb. asse mbly is to be reflowed three times. no ph y s ical d a m a ge reflow soldering, solder stencil para m e t e rs an d solder paste percentage ti n and lead specified measured aft e r three pass e s throug h reflo w flatness per figure 3 on page 16, section a-a, before and after soldering. llcr 20.0 m ? 26 mechanical test proced ure conditi ons and requirements chapter 6
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements table 2. mechanical qualification test proced ures (continued) test proced ure test condition requireme n ts pin current rating eia 364-70 method 2 330 con t acts m u st be in series. ther m o couple to be placed under socket 754 be tween pins (p22, p2 3, r22, and r2 3 ) during testin g 12 v p o wer m u st be supplied to the fan. generat e graph tem p er ature rise vs. current 1.2 am p per pin at t ? rise of 20c m a x i mu m continue testing until delta t ? rise is 30c. thermal cycling life no ph y s ical d a m a ge llcr 20.0 m ? a socket has failed if one contact exceeds the 20.0 m ? chapter 6 mechanical test proced ure conditions and requirements 27
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 28 mechanical test proced ure conditi ons and requirements chapter 6
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements 7 electrical qualification requir e ments 7.1 fixture all test fixtures that are required to conduct the electrical qualification requirem e nts will be furnished by amd to the amd designated testing facility. 7.1.1 capacitance and inductance matrices the partial ?loop? inductance and maxwell capacitance matrices (s ee section 7.6 on page 36 for def i nition s ) are m easured f o r the thr ee m a ted pin conf igurations shown in figure 6 on page 29. for the pin configurations, the size of the maxwell capacitance matrix is 2 x 2, as is the size of the partial ?loop? inductance m a trix. figure 6. pin configuration for the maxw ell capacitance and partial inductance matrix measurement 7.1.2 mated partial self inductance the following procedures are required to prope rly test for m a ted pa rtial self-inductance. 7.1.2.1 test procedure use a validated ?indus try-standard? 3-d em field solv er. th is is th e only quantity in the specification that need no t be m easured. values o b tained fro m an accurate detailed 3-d em field solver m o del are acceptable. this com puted quantity must not be used in any calcu lations involving m easured d a ta. chapter 7 electrical q u alification requiremen ts 29
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 7.1.2.2 test condition ? ? ? 7.1.2.3 requirements mated partial self-inductance is 4 nh m a xim u m, assum i ng the current return is at infinity. 7.1.3 mated loop inductance the following procedures are required to properly test for m a ted loop inductance. 7.1.3.1 test procedure the inductance of a loop is form ed by a pair of pins. all current is injected in one pin and returned through the other. on a vector ne tw ork analyzer using one port m easurem ent, read the values from the sm ith chart at the specified frequencies. 7.1.3.2 test condition ? ? 7.1.3.3 requirements mated loop inductance shall be 3 nh 10%?two n earest pins, current in one pin, return the other pin. record all pin pattern readings, but use only the near est neighbors for qualification. 7.1.4 mated partial l oop inductance matrix the following procedures are required to proper ly test for m a ted partial loop inductance fro m m easured mated loop inductance data. figure 7 shows the loop m easure m ent for extracting [l p ] for a m a ted three-pin com b ination figure 7. loop measurement fo r extracting [l p ] for a mated three-pin combination 30 electr i cal q u alification requiremen ts chapter 7
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements figure 8. current/voltage definitions and equivalen t circuit of the partial ?lo o p? inductance matrix 7.1.4.1 test procedure as shown in figure 7 on page 30, th e partial inductance m a trix of a m a t e d three-pin com b ination that is extracted from a m a ted two-pin loop inductance m easurem ents with one of the pins used as the reference (c urrent re turn ). use the f o rm ula in e quation (1) below to calculat e th e m a ted pa rtial loop inductance from m easur ed m a ted loop inductance data. 2 3 2 1 12 loop loop loop l l l m ? + = . (1) 7.1.4.2 test condition test frequencies are 500 mhz and 2 ghz. 7.1.4.3 requirements ? m < 2 nh 10%?three pin loop with one pin used as reference. ? measurem ent of the off diagonal entries in the loop partial inductance m a trix. ? diagonal entries of this m a trix correspond to mated loop inductance and m u st m eet specified values in section 7.1.3.3. on page 30. 7.2 differential impedance definition if the dim e nsions of the socket pins and the spacing between them are sm all com p ared to the wavelength of the highest frequency com pone nt of interest, then the im pedance of the three-pin configuration shown in figure 6 on page 29 and figur e 8 on page 31 can be calculated approxim ate l y from the lumped ?loop? inductance and maxwell capaci tance m a trices. when pins 1 and 2 in (figure 8 on page 31) are driven differentially, with pin 3 acting as ground, then the differential im pedance of the transm ission lin e f o r m ed by this pin configuration is given by 12 12 2 c c m l z loop diff + ? = . (2) chapter 7 electrical q u alification requiremen ts 31
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 the equation (2) definition of the differential im pedance assum e s that the d r iven (or s i gnal) conductors have the sam e geom etrical shape note : equation (2) is only valid for non-symmetric differential lines in homogenous media. the differential im pedance should be m easured for all com b inations of the th ree-p i n arrangem e nts as shown in figure 6 on page 29. th e pins are intentionally num b ered in a spec if ic m a nner as to yield identical > @ loop l and > m a trices for pin configurations (a) through (d). this is not the case for the pin arrangem ent in figure 6e on page 29. @ c 7.2.1 differential impedance the following procedures are required to pr operly test for differential im pedance. 7.2.1.1 test procedure x use the procedures show n in eia-364-108 or se e the equations in te rm s of partial loop inductance and maxwell capacitanc e m a trices. if the tim e dom a in m e thod is used in m easurem ent, then the signal should have ris e tim e of 35 to 150 ps for signal am plitu de to go from 10 ? 90%. x the dif f e rentia l tr ansm ission lin e im pedance f o r three m a ted pins, using one pin as the voltage/current reference. x any frequency dom ain test equipm e n t recomm e nde d in eia-364-108 may be used to perform the m easurem ents. x if tim e domain equipm ent is used, it should have sufficient sampling rates to resolve the specified frequencies. 7.2.1.2 test condition x frequency or tim e domain method x tim e domain m e thod uses a rise tim e : 35 to 150 ps, 10 to 90% x frequency dom a in m e thod use 500mhz and 2 ghz x the differential im pedance m easured for a three-pin configuration (s1, s2, g). 7.2.1.3 requirements the accep table range for differential im pedance is 10 0 10% ? with an additional 2- ? m easurem ent erro r. 32 electr i cal q u alification requiremen ts chapter 7
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements 7.3 differential and single ended crosstalk the following procedures are required to properly test for crosstalk. 7.3.1 test procedure use the p r o cedures sho w n in eia 3 6 4 ? 9 0 , m e t h o d a o r b , for the d e finitions of crosstalk in term s of the elem ents of the m easured [ ] partial loop l and maxwell cap acitan ce m a trices. 7.3.2 test condition ? frequency or tim e domain method ? for tim e dom a in m e thod use rise tim e 35 to 150 ps, 10 to 90% ? for frequency dom a in m e thod use 500 mhz and 2 ghz ? measurem ents perform e d for specified pin patter n differential in figure 6 on page 29 and single ended in figure 9 on page 34 that include, m i ni mu m , the nearest, and next to nearest neighboring pins. 7.3.3 requirements crosstalk sh ould be reco rded and serve as an accuracy check for the partial ?loop ? in ductance [ ] partial loop l and the max w ell capacitance m a trices. 7.4 propagation delay skew the propagation delay skew for single-ended signal pins is to be m easured fo r the pin configurations shown in figure 9 on page 34. chapter 7 electrical q u alification requiremen ts 33
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 figure 9. pin configurations for the propagatio n delay skew measurements of single-ended signals each m easurem ent consists of driving one (gray-sh aded) pin as signal and using the center pin (blue) as return. t h e propagation delay sk e w f o r all sig n al pin s in figur e 9 ( a) are m easured. the m a ximu m allowable deviation for all the pins in the array must be less than the specified valu e. an identical set of m easurem ents m u st also be repeated for the pin array shown infigure 9(b). the differential propagation delay skew is m easured for every pin configuration shown in figure 6 on page 29.. in each m easurem ent the two gray-s haded pi n s (denoted 1 and 2) and d r iven as sig n als in differential f o rm , using the blue pin as ground. the m a xi mum allowable deviation in the propagation delay skew f o r all spec if ied pi n configurations must be less than the specified value. 7.4.1 single ended pr opagati o n delay sk ew the following procedures are required to properl y test for single ended propagation delay. 7.4.1.1 test procedure use the procedures show n in eia-364-103 for tes ting the single ended propagation delay skew. propagation delay skew can also be m easured us i ng a tim e delay reflectom e ter (tdr) by launching the signals through the designated pins, such as those infigure 9. th e signals are launched from the inte rposer a nd the delay skew is ob served at th e te s t bo ard. the d i fference in the propagation tim es (delay skew) through different pins in the socket can be clearly seen a nd m easured at the open circuited end of th e test board. 34 electr i cal q u alification requiremen ts chapter 7
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements 7.4.1.2 test condition for the tim e dom a in m e t hod: tim e delay of single-ended signals between the top pads of the interposer and the pads on the bottom side fixture. the ground return for the specified signal pin pattern of single ended signals is to be located as specified 7.4.1.3 requirements ? ? 7.4.2 differential propagation delay sk ew the following procedures are required to properly test f o r d i f f e rentia l pro p agation d e lay skew. 7.4.2.1 test procedure use the procedures show n in eia-364?103 and section 7.4.1.1 on page 34. 7.4.2.2 test condition for the tim e dom a in m e t hod: tim e delay of a differential signal between the top pads of the inte rposer and the pads on the bottom side of the fixture. 7.4.2.3 requirements ? ? 7.5 capacitance at low frequencies, th e m easurem ent of the capaci tance sh ould be carried out acco rding to the eia standard eia-364-30. two types of m easure m ents are required?single cap acitance between the two neares t pins that a r e sep a rated by 1.2 7 m m and maxwell cap a c itan ce m a trix f o r m u ltiple pins. 7.5.1 test procedures use the procedures show n in eia-364-30 and section7.1.2.2 on page 30. chapter 7 electrical q u alification requiremen ts 35
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 7.5.2 test condition test frequencies: 500 mhz and 2 ghz note : do not short pins for this test. the m a trix is def i ned as the maxwell (not c i rcu it) capacitanc e m a trix. 7.5.3 requirements ? the m a ted capacitance m a trix of any tw o adjacent pins is 1 pf m a xi m u m . ? measure fro m the top or bottom of the socket. ? mated capacitance of three nei ghboring pins is 1 pf m a xi m u m. ? the maxwell capacitan c e m a trix is m easured fo r a specified m a ted three-pin configuration. ? the capacitance m a trix of three ne ighboring pins that are in the sam e pattern as thos e u s ed to extract the m a ted par tial inductance m a trix. 7.6 electrical specifications table 3 on page 37 contains a summ ary of the electr ical param e ter specification for socket 754. the specification s do not include the effects of the fix t ures. note : proper calibration should be used to de-embed the parasitic cont ributions for the fixture of the specified electrical parameter. 36 electr i cal q u alification requiremen ts chapter 7
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements table 3. summary of required mea surements for the socket 754 measured quantity d e f i n i t i o n s p e c i f i e d value(s) m e a s u r e m e n t a p p l i c a b l e standard mated partial self- inductance of a single pin. this is the only quantit y i n the specification that need not be measured. values obtained from an accur a te detailed 3-d em field solver model are ac ceptabl e. partial self- inductance of a single mated (interposer-socket co m b ination) pin that is calculated using a 3-d e m field solver. four nh m a x i mu m assu m i ng the current return at infinit y . this quantit y cannot be measured directly n o r can it be calculated uniquel y fro m the m e as urem e n ts . see, section 7.1.2 , mated partial self inductance on page 29, for t h e dis c ussion on the m a ted self- partial induct a nce. use a validat ed ?industr y - standard? 3d em field solver. this com puted quantit y must not be used in any calculations involvi ng measured data. mated loop inductance of two nearest pins (i.e., pins separate d by shortest distance). the inductan ce of a loop f o rm ed b y two nearest mated pins. all current is injected into one pin and retur n ed throug h the o t her. three nh 10% the inductan ce of a loop f o rm ed b y two nearest pins, which are shorted at the bottom of the socket, with current injected into one pin and returned t h roug h the other. see section 7.1.3, mated loop inductance, o n page 30, for specified pin configuration s . mated partial ?loop? ind u ctance matrix [ ] partial loop l of three neighbo ring pins. partial inductance matrix of a mated three-pin co m b ination extracted from mated two-pin loop- i nducta nce m e as urem e n ts . one of the pi ns is used as the reference (cur rent return). loop l 3nh 10% these are the diagonal entri es in the ?loop? partial induct a nce matrix. m 12 < 2 nh 10%. these are the off- diagonal entri es in the ?loop? partial induct a nce matrix. the partial inductance matrix is extracted fro m a series of two-pin l oop inductance mea s ure m ents (as described above) for specified thre e-pin configuration s . see section7.1.4, mated partial loop inductance on page 30 for the definit i on of this matrix and the m e as urem e n ts tha t should be used to back-calculat e the self and m u tual partial ?loop? inductances. use the for m ulas in paragraph 7.1 . 4, mated partial loop inductance matrix, equation (1)p rovided in this document. chapter 7 electrical q u alification requiremen ts 37
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 table 3. summary of required measuremen ts for the socket 754 (continued) measured quantity d e f i n i t i o n s p e c i f i e d value(s) m e a s u r e m e n t a p p l i c a b l e standard mated capaci tance between two nearest pins (i.e., pins separate d by shortest distance). the capacitan ce between two nearest mated pins. one pf max. capacitance between two nearest pins measured from the top or bott o m sid e of the socket. the pins are not to be shor ted together for t h is m e as urem e n t. use the eia-364-3 0 standard for low frequency ( 1 0 mhz) measurements. or, use the network analy zer for s- param e t e r measurements with minim u m frequenc y of 500 mhz or lower. see section 7.5.1, test procedures, on page 35 mated capaci tance matrix of three neighbori ng p i ns. the matrix is defined as the maxwell (not circuit) capacitanc e matrix the capacitan ce matrix of three neighbori ng p i ns that are in the sa me pattern as those used to extract the mated partial inductance matrix. all entries in the matrix should not exceed 1pf. the maxwell capacitanc e matrix measured for the specified m a t e d three- pin confi gurations. note : the pi ns are not to be shorted together for this measurement. use the eia-364-3 0 standard for low frequency ( 1 0 m hz) measurements. or, use the network analy zer for s- param e t e r measurements with minim u m frequenc y of 500 mhz or lower. see section 7.5.1, test procedures, on page 35 differential im pedance between two nearest pins (i.e., pins separate d by shortest distance). the trans m iss i on line im pedan ce of the odd m ode for three m a ted p i ns, using o n e pin as the voltage/current reference. 100 : r 10% with an additional 2 - ? m e as urem e n t error the differential (or an odd m ode) im p e dance mea s ured for a three- pin confi guration (s1, s2, g). if equipm ent perm its, this quantit y may be measured directly . if not, it can be calculated from the mea s ured mated partial ?loop? inductance and maxwell cap acitance matric es a cco rding to equations pro v ided in this docum en t. use the eia-364-1 08 standard or see the equations in t e rm s of partial induct a nce and maxwell cap acitance matrices, section 7.5, capacitance, on page 35. if the time domain method is used in measurement, then the signal should have rise tim e of 35 to 1 50 ps for signal am plitude to go from 10 ? 90% . 38 electr i cal q u alification requiremen ts chapter 7
2485 0 rev. 3.07 aug u st 2003 socket 754 design and qu alification requirements table 3. summary of required measuremen ts for the socket 754 (continued) measured quantity d e f i n i t i o n s p e c i f i e d value(s) m e a s u r e m e n t a p p l i c a b l e standard propagation d e lay skew am ong single ended signals. deviation in t h e propagation d e lay skew of a single ended signal throug h differ e nt mated (single) pins in the socket. ten ps max plus 3 ps m a x m e as urem e n t error. tim e delay o f single ended signal between the top pads o f the interposer and the pads on the bottom side fixture. the groun d r e turn for the specified signal pin pattern of sin g le ended signals is to be located as specifi ed. use eia-364-103 standard or pr ovided in section 7. 4 . 1.1, test procedure, on page 34. see figure 6 on page 29 for specified signal pin patterns, which also include the location of th e current return pin. propagation d e lay skew am ong differential signal pairs. deviation in t h e propagation d e lay skew of differential signals throu gh mated pin pairs in the socket. ten ps max plus 3 ps m a x m e as urem e n t error. ti m e delay of a differential signal between the top pads of the interposer and the pads on the b o ttom side of the fixture. the specified thre e-pin (s1, s2, g) arrangem e nt should be used. use eia-364-103 standard or pr ovided in section 7. 4 . 1.1, test procedure, on page 34. see figure 6 on page 2 9 fo r specified differential pin-pair patte rns, which also include the location of th e current return pin frequencies for the inductanc e m e as urem e n ts . the frequencies at which induct a nce is to be m e asured. 500 mhz and 2 ghz any frequency dom ain test equipment reco mmended in eia standards m a y be used to perform the measurements. if time dom ain equipment is used, it shoul d have sufficient sa m p ling rates to resol v e the specified freq u encies. frequencies for the capacitan ce m e as urem e n ts . the frequencies at which capacit a nce is to be m e asured. 500 mhz and 2 ghz any frequency dom ain test equipment reco mmended in eia standards m a y be used to perform the measurements. if time dom ain equipment is used, it shoul d have sufficient sa m p ling rates to resol v e the specified freq u encies. chapter 7 electrical q u alification requiremen ts 39
socket 754 design and qua lification requirements 2485 0 rev. 3.07 aug u st 2003 table 3. summary of required measuremen ts for the socket 754 (continued) measured quantity d e f i n i t i o n s p e c i f i e d value(s) m e a s u r e m e n t a p p l i c a b l e standard cross talk between nearest single - ended and differential signals. this quantit y should be reported and shoul d serve as an ac curac y check for the partial ?loop? i n d u c t a n c e [ ] partial loop l and the maxwell capacitanc e matrices. cross talk is defined as the voltage (and current) indu ced on quiet (no n -dri ven) transm ission lines (single-ended or differential) due to the nearest driven (single-ended or differentially driven) neigh bors. cross talk should be measured and co m p ared to the results predicted from the m e a s ured [ ] partial loop l and maxwell capacitanc e matrices. measure ment s are to be performed for specified pin patterns t h at will include, at least, the nearest and next to nearest neighbors. use eia-364-90 standard: method a or method b for pin patterns speci fied in figure 6 o n p a ge 29. see section7.3, and section 7.3. 1, on page 33 for t h e definitions of cross talk in terms of the ele m en ts of the mea s ured [ ] partial loop l and capacitan ce matrices. resist ance of a single mated pin. m i n i mu m n u mb e r of pin pairs to be tested is 168. dc resi stance of a single mated pin. 20 m ? ma x i mu m for alloy - 194 at the end-of-lif e the resistanc e mea s ured between the top of t h e pin and the solder pad. use eia-364-23 standard. minim u m pin current rating. dc current flowing throug h the mated pin. 1.2 am ps/pin at voltages 2 v for alloy - 194? the te m p erat ure rise for a specified pattern of currents du e to heating shoul d not exceed 20 o c. u s e e i a - 3 6 4 - 7 0 standard m i n i mu m breakdown v o ltage of the insulat o r. dielectri c m a terials abilit y to wit h stand the stress due to the applied electric fields. 650 vac use eia-364-20 standard 40 electr i cal q u alification requiremen ts chapter 7

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