View B150PN01_1572559.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 1 / 20 no reproduction and redistribution allowed. product functional specification 15 inch sxga+ color tft lcd module model name : B150PN01 ( u ) preliminary speci fication ( ) final specification note: this specification is subject to change without notice.
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 2 / 20 no reproduction and redistribution allowed. i. contents 1.0 handling precautions 2.0 general description 2.1 characte ristics 2.2 functional block diagram 3.0 absolute maximum ratings 4.0 optical characteristics 5.0 signal interface 5.1 connectors 5.2 signal pin 5.3 signal description 5.4 signal electrical characteristics 5.5 signal for lamp connector 6.0 pixel format image 7.0 parameter guide line for cfl inverter 8.0 interface timings 8.1 timing characteristics 8.2 timing definition 9.0 power consumption 10.0 power on/off sequence 11.0 mechanical characteristics ii record of revision version and date page old de scription new description remark 0.1. 2001/1/29 all first edition for customer all 0.2. 2001/4/16 5 weight 650g max. weight 570g max. 0.3 2001/6/14 5 thickness 6.3mm max. thickness 6.2mm max. 0.4 2001/7/6 5 weight 570g max. weight 550g typ. 0.5 20 01/7/13 5 power consumption 5.5w 0.6 2001/8/13 8 signal connector: jae fi - signal connector: jae fi - xb30sr - connector type
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 3 / 20 no reproduction and redistribution allowed. seb20p - hf13 hf11 change from 20 pin to 30 pin. 0.6 2001/8/13 18 update mechanical drawing 1.0 handing precautions 1) since front polar izer is easily damaged, pay attention not to scratch it. 2) be sure to turn off power supply when inserting or disconnecting from input connector. 3) wipe off water drop immediately. long contact with water may cause discoloration or spots. 4) when the panel surfac e is soiled, wipe it with absorbent cotton or other soft cloth. 5) since the panel is made of glass, it may break or crack if dropped or bumped on hard surface. 6) since cmos lsi is used in this module, take care of static electricity and insure human earth when handling. 7) do not open nor modify the module assembly. 8) do not press the reflector sheet at the back of the module to any directions. 9) in case if a module has to be put back into the packing container slot after once it was taken out from the container, do not press the center of the ccfl reflector edge. instead, press at the far ends of the cfl reflector edge softly. otherwise the tft module may be damaged. 10) at the insertion or removal of the signal interface connector, be sure not to rotate nor tilt the in terface connector of the tft module. 11) after installation of the tft module into an enclosure (notebook pc bezel, for example), do not twist nor bend the tft module even momentary. at designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the tft module from outside. otherwise the tft module may be damaged. 12) cold cathode fluorescent lamp in lcd contains a small amount of mercury. please follow local ordinances or regulations for disposal. 13) small amou nt of materials having no flammability grade is used in the lcd module. the lcd module should be supplied by power complied with requirements of limited power source(2.11, iec60950 or ul1950), or be applied exemption.
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 4 / 20 no reproduction and redistribution allowed. 14) the lcd module is designed so that the cfl in it is supplied by limited current circuit(2.4, iec60950 or ul1950). do not connect the cfl in hazardous voltage circuit.
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 5 / 20 no reproduction and redistribution allowed. 2.0 general description this specification applies to the 15.0 inch color tft/lcd module B150PN01. this module is designed for a display unit of notebook style personal computer. the screen format is intended to support the sxga+ (1400(h) x 1050(v)) screen and 262k colors (rgb 6 - bits data driver). all input signals are lvds interface compatible. this module does not contain an inver ter card for backlight.
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 6 / 20 no reproduction and redistribution allowed. 2.1 display characteristics the following items are characteristics summary on the table under 25 j condition: items unit specifications screen diagonal [mm] 381 active area [mm] 304.5 x 228.375 pixels h x v 1400(x3) x 1050 pixel pitch [mm] 0.2175x0.2175 pixel arrangement r.g.b. vertical stripe display mode normally white typical white lumina nce (icfl=5.5ma) [cd/m 2 ] 150 (5 point average) contrast ratio 2 5 0 optical rise time/fall time [msec] 15/35 nominal input voltage vdd [volt] +3.3 typ. typical power consumption (vdd line + vcfl line) [watt] 5.5w weight [grams] 550g typ. physical siz e [mm] 315.8 x 240.6 x 5.9 typ. electrical interface 2 channel lvds support color native 262k colors ( rgb 6 - bit data driver ) temperature range operating storage (shipping) [ o c] [ o c] 0 to +50 - 20 to +60
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 7 / 20 no reproduction and redistribution allowed. 2.2 functional block diagram the followin g diagram shows the functional block of the 15.0 inches color tft/lcd module: tft array/cell vdd lcd controller lcd drive card backlight unit 1400(r/g/b) x 3 1050 gnd dc - dc converter ref circuit y - driver x - driver ro/ein0+/ - ro/ein1+/ - ro/ein2+/ - ro/eclkin+/ - ( 8 pairs lvds) jae fi - xb30sr - hf11 fi - c3 - a1 mating jae fi - x30m or fi - x30h jst bhsr - 02vs - 1 mating type sm02b - bhss - 1 - tb lamp connector(2pin)
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 8 / 20 no reproduction and redistribution allowed. 3.0 absolute maximum ratings absolute maximum ratings of the module is as following: item symbol min max unit conditions logic/lcd drive voltage vdd - 0 .3 +4.0 [volt] input voltage of signal vin - 0.3 vdd+0.3 [volt] ccfl current icfl - 7 [ma] rms ccfl ignition voltage vs - 1150 vrms operating temperature top 0 +50 [ o c] note 1 operating humidity hop 8 95 [%rh] note 1 storage temperature tst - 20 +6 0 [ o c] note 1 storage humidity hst 5 95 [%rh] note 1 vibration 1.5 10 - 500 (random) g hz 2hr/axis, x,y,z shock 220 , 2 g ms half sine wave note 1 : maximum wet - bulb should be 39 j and no condensation.
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 9 / 20 no reproduction and redistribution allowed. 4.0 optical characteristics the optical charact eristics are measured under stable conditions as follows under 25 j condition : item conditions typ. note viewing angle [degree] [degree] horizontal (right) k = 10 (left) 40 40 ? ? k: contrast ratio [degree] [degree] vertical (upper) k = 10 (lower) 10 30 ? ? contrast ratio 250 ? response time [msec] rising 15 45(max.) (room temp.) [msec] falling 35 45(max.) color red x tbd tbd chromaticity red y tbd tbd coordinates (cie) green x tbd tbd green y tbd tbd blue x tbd tbd bl ue y tbd tbd white x 0.313 tbd white y 0.329 tbd white luminance (ccfl 5.5 ma) [cd/m 2 ] 150 ( 5 points average)
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 10 / 20 no reproduction and redistribution allowed. 5.0 signal interface 5.1 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. connector name / designation for signal connector manufacturer jae type / part number fi - xb30sr - hf11 mating housing/part number fi - x30m or fi - x30h mating contact/part number fi - c3 - a1 connector name / designation for lamp connector manufacturer jst type / part number bhsr - 02vs - 1 mating type / part number sm02b - bhss - 1 - tb 5.2 signal pin pin# signal name pin# signal name 1 gnd 2 vdd 3 vdd 4 reserved 5 reserved 6 reserved 7 r eserved 8 roin0 - 9 roin0+ 10 gnd 11 roln 1 - 12 roln1+ 13 gnd 14 roin2 - 15 roin2+ 16 gnd 17 roclkin - 18 roclkin+ 19 gnd 20 reln0 - 21 reln0+ 22 gnd 23 reln1 - 24 reln1+ 25 gnd 26 reln2 - 27 reln2+ 28 gnd 29 reclkin - 30 reclkin+
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 11 / 20 no reproduction and redistribution allowed. 5.3 signal descripti on the module using a lvds receiver. lvds is a differential signal technology for lcd interface and high speed data transfer device. transmitter shall be sn75lvds84 (negative edge sampling) or compatible. signal name description roin0 - , roin0+ lvds diffe rential odd data input(red0 - red5, green0) roin1 - , roin1+ lvds differential odd data input(green1 - green5, blue0 - blue1) roin2 - , roin2+ lvds differential odd data input(blue2 - blue5, hsync, vsync, dsptmg) roclkin - , roclkin0+ lvds odd differential clock inpu t rein0 - , rein0+ lvds differential even data input(red0 - red5, green0) rein1 - , rein1+ lvds differential even data input(green1 - green5, blue0 - blue1) rein2 - , rein2+ lvds differential even data input(only blue2 - blue5) reclkin - , reclkin0+ lvds even differen tial clock input vdd +3.3v power supply gnd ground note: input signals shall be low or hi - z state when vdd is off. internal circuit of lvds inputs are as following.
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 12 / 20 no reproduction and redistribution allowed. sn75lvds86 or compatible 5. roin0- 6. roin0+ 7. roin1- 8. roin1+ 9. roin2- 10. roin2+ 11. roclkin- 12. roclkin+ 13. rein0- 14. rein0+ 15. rein1- 16. rein1+ 17. rein2- 18. rein2+ 19. reclkin- 20. reclkin+ signal input the module uses a 100ohm resistor between positive and neg ative data lines of each receiver input
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 13 / 20 no reproduction and redistribution allowed. signal name description +red5 +red4 +red3 +red2 +red1 +red0 red data 5 (msb) red data 4 red data 3 red data 2 red data 1 red data 0 (lsb) red - pixel data red - pixel data each red pixel's brightness data consist s of these 6 bits pixel data. +green 5 +green 4 +green 3 +green 2 +green 1 +green 0 green data 5 (msb) green data 4 green data 3 green data 2 green data 1 green data 0 (lsb) green - pixel data green - pixel data each green pixel's brightness data consists of these 6 bits pixel data. +blue 5 +blue 4 +blue 3 +blue 2 +blue 1 +blue 0 blue data 5 (msb) blue data 4 blue data 3 blue data 2 blue data 1 blue data 0 (lsb) blue - pixel data blue - pixel data each blue pixel's brightness data consists of these 6 bits pixe l data. - dtclk data clock the typical frequency is 54.0 mhz.. the signal is used to strobe the pixel data and dsptmg signals. all pixel data shall be valid at the falling edge when the dsptmg signal is high. dsptmg display timing this signal is strobed at the falling edge of - dtclk. when the signal is high, the pixel data shall be valid to be displayed. vsync vertical sync the signal is synchronized to - dtclk . hsync horizontal sync the signal is synchronized to - dtclk . note: ou tput signals from any system shall be low or hi - z state when vdd is off. 5.4 signal electrical characteristics input signals shall be low or hi - z state when vdd is off. it is recommended to refer the specifications of sn75lvds86dgg(texas instruments) in de tail. signal electrical characteristics are as follows;
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 14 / 20 no reproduction and redistribution allowed. parameter condition min max unit vth differential input high voltage(vcm=+1.2v) 100 [mv] vtl differential input low voltage(vcm=+1.2v) - 100 [mv] lvds macro ac characteristics are as follo ws: min. max. clock frequency (t) tbd tbd data setup time (tsu) tbd data hold time (thd) tbd 5.5 signal for lamp connector pin # signal name 1 lamp high voltage 2 lamp low voltage 6.0 pixel format image following figure shows the relation ship of the input signals and lcd pixel format. thd tsu input clock input data t
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 15 / 20 no reproduction and redistribution allowed. r g b r g b r g b r g b r g b r g b r g b r g b 1(odd) 2(even) 1399 1400 1st line 1050th 7.0 parameter guide line for cfl inverter parameter min dp - 1 max units condition white luminance 5 points average - 150 ? [cd/m 2 ] (ta=25 j ) ccfl current(icfl) 3.0 5.5 7.0 [ma] rms (ta=25 j ) note 2 ccfl frequency(fcfl) 50 60 70 [khz] (ta=25 j ) note 3 ccfl ignition voltage(vs) ? 1,150 [volt] rms (ta= 0 j ) note 4 ccfl voltage (reference) (vcfl) ? 700 ? [volt] rms (ta=25 j ) note 5 ccfl power consumption (pcfl) ? 3.9 ? [watt] (ta=25 j ) note 5 note 1: dp - 1 are adt recommended design points. *1 all of characteristics listed are measured under the condition using the adt test inverter.
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 16 / 20 no reproduction and redistribution allowed. *2 in case of using an inverter other than listed, it is reco mmended to check the inverter carefully. sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. *3 in designing an inverter, it is suggested to check safety circuit ver carefully. impedance of cfl, for instance, becomes more than 1 [m ohm] when cfl is damaged. *4 generally, cfl has some amount of delay time after applying kick - off voltage. it is recommended to keep on applying kick - off voltage for 1 [sec] until discharge. *5 cfl discharge fre quency must be carefully chosen so as not to produce interfering noise stripes on the screen. *6 reducing cfl current increases cfl discharge voltage and generally increases cfl discharge frequency. so all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high - voltage output of the inverter. note 2: it should be emplyed the inverter which has ?duty dimming?, if icfl is less than 4ma. note 3: cfl discharge frequency shouldbe carefully determined to avoid interference between inverter and tft lcd. note 4: cfl inverter should be able to give out a power that has a generating capacity of over 1,400 voltage. lamp units need 1,400 voltage minimum for ignition. note 5: calculator value for reference (icfl vcfl=pcfl) 8.0 interface timings basically, interface timings should match the vesa 1024x768 /60hz (vg901101) manufacturing guide line timing. 8.1 timing characteristics symbol description min typ max unit fdck dtclk frequency 54.00 [mhz] tck dtclk cy cle time 18. 5 [nsec] tx x total time tbd 844 tbd [tck] tacx x active time tbd 700 [tck] tbkx x blank time 144 [tck] hsync h frequency 63.98 [khz] hsw h - sync width tbd 56 [tck] hbp h back porch tbd 64 [tck] hfp h front porch tbd 24 [tck] t y y total time tbd 1066 tbd [tx] tacy y active time 1050 [tx] vsync frame rate (55) 60 61 [hz]
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 17 / 20 no reproduction and redistribution allowed. vw v - sync width 1 3 [tx] vfp v - sync front porch 1 1 [tx] vbp v - sync back porch 7 12 63 [tx] note: hsw(h - sync width) + hbp(h - sync back porch) should be less than 515 tck. 8.2 timing definition 1688 dot 112 dot 128 dot 48 dot 1400 dot h-sync dsptm 16 h 1 h 12 h 3 h 1050 h v-sync dsptmg 9.0 power consumption input power specifications are as follows; symble parameter min typ max units condition vdd logic/lcd drive voltage 3.0 3.3 3.6 [volt] load capacitance 20uf pdd vdd power tbd [watt] all black pattern pdd max vdd power max tbd [watt] max pattern note idd idd current tbd ma all black pattern idd max idd current max tbd ma max pattern note vddrp allowable 100 [mv]
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 18 / 20 no reproduction and redistribution allowed. logic/lcd drive ripple voltage p - p vddns allowable logic/lcd drive ripple noise 100 [mv] p - p note : vdd=3.3v 10. power on/off sequence vdd power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi - z state or low level when vdd is off. 5. package instruction 90% 10% 10% 10% 90% 10ms max. 0 min. 0 min. 0 v 0 v vdd signals 10% 10% 180ms min. 0 min. 0 v lamp on 10% 10% 150ms min.
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 19 / 20 no reproduction and redistribution allowed. 11. mechanical characteristics u
(c) copyright a u optronics , inc. july , 2001 all rights reserved. B150PN01 ve r.0 6 20 / 20 no reproduction and redistribution allowed.

▲Up To Search▲

Price & Availability of B150PN01

	To Download B150PN01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .