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ultralogic? 64-macrocell flash cpld cy7c373i cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 july 10, 2000 features ? 64 macrocells in four logic blocks 64 i/o pins 5 dedicated inputs including 4 clock pins in-system reprogrammable? (isr?) flash technology ? jtag interface bus hold capabilities on all i/os and dedicated inputs no hidden delays high speed ?f max = 125 mhz ?t pd = 10 ns ?t s = 5.5 ns ?t co = 6.5 ns fully pci compliant 3.3v or 5.0v i/o operation available in 84-pin plcc and 100-pin tqfp packages pin compatible with the cy7c374i functional description the cy7c373i is an in-system reprogrammable complex programmable logic device (cpld) and is part of the f lash 370i? family of high-density, high-speed cplds. like all members of the f lash 370i family, the cy7c373i is de- signed to bring the ease of use and high performance of the 22v10, as well as pci local bus specification support, to high-density cplds. like all of the ultralogic? f lash 370i devices, the cy7c373i is electrically erasable and in-system reprogrammable (isr), which simplifies both design and manufacturing flows, thereby reducing costs. the cypress isr function is implemented through a jtag serial interface. data is shifted in and out through the sdi and sdo pins.the isr interface is enabled using the programming voltage pin (isr en ). additionally, be- cause of the superior routability of the f lash 370i devices, isr often allows users to change existing logic designs while si- multaneously fixing pinout assignments. 7c373i?1 logic block diagram pim input macrocell clock inputs input logic logic 2 2 36 16 16 36 16 i/os 16 i/os 32 32 logic 36 16 16 36 16 i/os 16 i/os 4 1 input/clock macrocells i/o 0 -i/o 15 logic i/o 16 -i/o 31 i/o 48 ? i/o 63 i/o 32 ? i/o 47 block a block b block c block d selection guide 7c373i?125 7c373i?100 7c373i?83 7c373il-83 7c373i?66 7c373il?66 maximum propagation delay [1] , t pd (ns) 10 12 15 15 20 20 minimum set-up, t s (ns) 5.5 6.0 8 8 10 10 maximum clock to output [1] , t co (ns) 6.5 6.5 8 8 10 10 typical supply current, i cc (ma) 75 75 75 45 75 45 note: 1. the 3.3v i/o mode timing adder, t 3.3io , must be added to this specification when v ccio = 3.3v.
cy7c373i 2 pin configurations top view tqfp 100 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 37 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 sdi nc v ccio i/o 55 i/o 54 i/o 53 i/o 52 clk 3 /i 4 i/o 50 i/o 48 gnd nc i/o 47 i/o 46 i/o 49 gnd smode sclk gnd i/o 8 i/o 9 i/o 10 i/o 11 i/o 15 v ccio gnd clk 1 /i 1 i/o 15 i/o 17 clk 0 /i 0 90 91 i/o 51 v ccio clk 2 /i 3 i/o 14 n/c i/o 12 i/o 13 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 gnd nc gnd nc i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 v ccio nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 48 49 50 7c373i ? 2 gnd i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 v ccint v ccio i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i 2 nc v ccio sdo i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 7 6 5 4 3 2 1 v ccint i/o 0 v ccio nc 63 i/o 62 61 60 59 58 57 56 v ccio i/o i/o 14 i/o 15 i/o 48 7c373i ? 3 top view plcc 98 6 7 5 13 14 12 11 49 48 58 59 60 23 24 26 25 27 15 16 47 46 4 3 28 33 20 21 19 18 17 22 34 35 37 36 38 42 41 43 40 66 65 63 64 62 61 7c373 67 68 69 74 72 73 71 70 84 81 82 80 279 gnd i/o gnd i/o i/o i/o i/o i/o i/o i/o gnd i/o 55 i/o 54 /sdi i/o 53 i/o 52 i/o 51 gnd i/o 49 clk 3 /i 4 v ccio clk 2 /i 3 i/o 45 i/o 44 gnd i/o i/o 8 i/o 9 i/o 10 /sclk i/o 11 i/o 12 i/o 13 clk 0 /i 0 v ccio clk 1 /i 1 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 53 52 50 30 29 31 32 i/o i/o i/o i/o 54 55 56 57 i/o 43 i/o 42 i/o 41 i/o 40 77 78 76 75 i/o 21 i/o 22 i/o 23 gnd i/o i/o 50 i/o 47 i/o 46 gnd 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 v ccint v ccio i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 gnd i 2 7 6 5 4 3 2 1 v ccint i/o 0 v ccio 63 i/o 62 61 60 59 58 57 56 isr en /smode /sdo isr en 10 39 44 83 45 51 1 99 47
cy7c373i 3 functional description (continued) the 64 macrocells in the cy7c373i are divided between four logic blocks. each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. the logic blocks in the f lash 370i architecture are connected with an extremely fast and predictable routing resource ? the programmable interconnect matrix (pim). the pim brings flex- ibility, routability, speed, and a uniform delay to the intercon- nect. like all members of the f lash 370i family, the cy7c373i is rich in i/o resources. every macrocell in the device features an associated i/o pin, resulting in 64 i/o pins on the cy7c373i. in addition, there is one dedicated input and four input/clock pins. finally, the cy7c373i features a very simple timing model. unlike other high-density cpld architectures, there are no hidden speed delays such as fanout effects, interconnect de- lays, or expander delays. regardless of the number of resourc- es used or the type of application, the timing parameters on the cy7c373i remain the same. logic block the number of logic blocks distinguishes the members of the f lash 370i family. the cy7c373i includes four logic blocks. each logic block is constructed of a product term array, a prod- uct term allocator, and 16 macrocells. product term array the product term array in the f lash 370i logic block includes 36 inputs from the pim and outputs 86 product terms to the product term allocator. the 36 inputs from the pim are avail- able in both positive and negative polarity, making the overall array size 72 x 86. this large array in each logic block allows for very complex functions to be implemented in single passes through the device. product term allocator the product term allocator is a dynamic, configurable resource that shifts product term resources to macrocells that require them. any number of product terms between 0 and 16 inclu- sive can be assigned to any of the logic block macrocells (this is called product term steering). furthermore, product terms can be shared among multiple macrocells. this means that product terms that are common to more than one output can be implemented in a single product term. product term steer- ing and product term sharing help to increase the effective density of the f lash 370i cplds. note that the product term allocator is handled by software and is invisible to the user. i/o macrocell each of the macrocells on the cy7c373i has a separate i/o pin associated with it. in other words, each i/o pin is shared by two macrocells. the input to the macrocell is the sum of be- tween 0 and 16 product terms from the product term allocator. the macrocell includes a register that can be optionally by- passed, polarity control over the input sum-term, and two glo- bal clocks to trigger the register. the macrocell also features a separate feedback path to the pim so that the register can be buried if the i/o pin is used as an input. programmable interconnect matrix the programmable interconnect matrix (pim) connects the four logic blocks on the cy7c373i to the inputs and to each other. all inputs (including feedbacks) travel through the pim. there is no speed penalty incurred by signals traversing the pim. programming for an overview of isr programming, refer to the f lash 370i family data sheet and for isr cable and software specifica- tions, refer to isr data sheets. for a detailed description of isr capabilities, refer to the cypress application note, ? an intro- duction to in system reprogramming with f lash 370i. ? pci compliance the f lash 370i family of cmos cplds are fully compliant with the pci local bus specification published by the pci special interest group. the simple and predictable timing model of f lash 370i ensures compliance with the pci ac specifications independent of the design. on the other hand, in cpld and fpga architectures without simple and predictable timing, pci compliance is dependent upon routing and product term distribution. 3.3v or 5.0v i/o operation the f lash 370i family can be configured to operate in both 3.3v and 5.0v systems. all devices have two sets of v cc pins: one set, v ccint , for internal operation and input buffers, and another set, v ccio , for i/o output drivers. v ccint pins must always be connected to a 5.0v power supply. however, the v ccio pins may be connected to either a 3.3v or 5.0v power supply, depending on the output requirements. when v ccio pins are connected to a 5.0v source, the i/o voltage levels are compatible with 5.0v systems. when v ccio pins are connect- ed to a 3.3v source, the input voltage levels are compatible with both 5.0v and 3.3v systems, while the output voltage lev- els are compatible with 3.3v systems. there will be an addi- tional timing delay on all output buffers when operating in 3.3v i/o mode. the added flexibility of 3.3v i/o capability is avail- able in commercial and industrial temperature ranges. bus hold capabilities on all i/os and dedicated inputs in addition to isr capability, a new feature called bus-hold has been added to all f lash 370i i/os and dedicated input pins. bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device ? s performance. as a latch, bus-hold recalls the last state of a pin when it is three-stated, thus re- ducing system noise in bus-interface applications. bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to v cc or gnd. design tools development software for the cy7c371i is available from cypress ? s warp ? , warp professional ? , and warp enter- prise ? software packages. please refer to the data sheets on these products for more details. cypress also actively sup- ports almost all third-party design tools. please refer to third-party tool support for further information.
cy7c373i 4 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................... ? 65 c to +150 c ambient temperature with power applied ............................................... ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... ? 0.5v to +7.0v dc input voltage ............................................ ? 0.5v to +7.0v dc program voltage .....................................................12.5v output current into outputs......................................... 16 ma static discharge voltage ........................................... >2001v (per mil ? std ? 883, method 3015) latch-up current..................................................... >200 ma operating range range ambient temperature v cc v ccint v ccio commercial 0 c to +70 c 5v 0.25v 5v 0.25v or 3.3v 0.3v industrial ? 40 c to +85 c 5v 0.5v 5v 0.5v or 3.3v 0.3v electrical characteristics over the operating range [2] parameter description test conditions min. typ. max. unit v oh output high voltage v cc = min. i oh = ? 3.2 ma (com ? l/ind) [3] 2.4 v v ohz output high voltage with output disabled [7] v cc = max. i oh = 0 a (com ? l/ind) [3, 4] 4.0 v i oh = ? 50 a (com ? l/ind) [3, 4] 3.6 v v ol output low voltage v cc = min. i ol = 16 ma (com ? l/ind) [3] 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs [5] 2.0 7.0 v v il input low voltage guaranteed input logical low voltage for all inputs [5] ? 0.5 0.8 v i ix input load current v i = internal gnd, v i = v cc ? 10 +10 a i oz output leakage current v cc = max., v o = gnd or v o = v cc , output disabled ? 50 +50 a v cc = max., v o = 3.3v, output disabled [4] 0 ? 70 ? 125 a i os output short circuit current [6, 7] v cc = max., v out = 0.5v ? 30 ? 160 ma i cc power supply current [8] v cc = max., i out = 0 ma, f = 1 mhz, v in = gnd, v cc com ? l/ind. 75 125 ma com ? l ? l ? , ? 66 45 75 ma i bhl input bus hold low sustaining current v cc = min., v il = 0.8v +75 a i bhh input bus hold high sustaining current v cc = min., v ih = 2.0v ? 75 a i bhlo input bus hold low overdrive current v cc = max. +500 a i bhho input bus hold high overdrive current v cc = max. ? 500 a capacitance [ ] parameter description test conditions min. max. unit c in [9] input capacitance v in = 5.0v at f = 1 mhz 8 pf c clk clock signal capacitance v in = 5.0v at f = 1 mhz 5 12 pf notes: 2. if v ccio is not specified, the device can be operating in either 3.3v or 5v i/o mode; v cc =v ccint . 3. i oh = ? 2 ma, i ol = 2 ma for sdo. 4. when the i/o is three-stated, the bus-hold circuit can weakly pull the i/o to a maximum of 4.0v if no leakage current is allo wed. this voltage is lowered significantly by a small leakage current. note that all i/os are three-stated during isr programming. refer to the application note ? understanding bus hold ? for additional information. 5. these are absolute values with respect to device ground. all overshoots due to system or tester noise are included. 6. not more than one output should be tested at a time. duration of the short circuit should not exceed 1 second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. 7. tested initially and after any design or process changes that may affect these parameters. 8. measured with 16-bit counter programmed into each logic block. 9. c i/o for dedicated inputs, and i/os with jtag functionality is 12 pf max., and for isr en is 15 pf max.
cy7c373i 5 note: 10. t er measured with 5-pf ac test load and t ea measured with 35-pf ac test load. inductance [ ] parameter description test conditions 100-pin tqfp 84-lead plcc unit l maximum pin inductance v in = 5.0v at f = 1 mhz 8 8 nh endurance characteristics [ ] parameter description test conditions max. unit n maximum reprogramming cycles normal programming conditions 100 cycles ac test loads and waveforms 7c373i ? 4 7c373i ? 5 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 35 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) <2ns <2 ns output 238 ? (com'l) 170 ? (com'l) 236 ? (mil) 99 ? (com'l) equivalent to: th venin equivalent 2.08v(com'l) 238 ? (com'l) 319 ? (mil) 170 ? (com'l) (c) parameter [10] v x output waveform ? measurement level t er( ? ) 1.5v t er(+) 2.6v t ea(+) 1.5v t ea( ? ) v the (d) test waveforms v oh 0.5v v x 0.5v v ol v x 0.5v v x v oh 0.5v v x v ol
cy7c373i 6 switching characteristics over the operating range [ ] 7c373i ? 125 7c373i ? 100 7c373i ? 83 7c373il-83 7c373i ? 66 7c373il ? 66 parameter description min. max. min. max. min. max. min. max. unit combinatorial mode parameters t pd input to combinatorial output [1] 10 12 15 20 ns t pdl input to output through transparent input or output latch [1] 13 15 18 22 ns t pdll input to output through transparent input and output latches [1] 15 16 19 24 ns t ea input to output enable [1] 14 16 19 24 ns t er input to output disable 14 16 19 24 ns input registered/latched mode parameters t wl clock or latch enable input low time [7] 3345ns t wh clock or latch enable input high time [7] 3345ns t is input register or latch set-up time 2 2 3 4 ns t ih input register or latch hold time 2 2 3 4 ns t ico input register clock or latch enable to combinatorial output [1] 14 16 19 24 ns t icol input register clock or latch enable to output through transparent output latch [1] 16 18 21 26 ns output registered/latched mode parameters t co clock or latch enable to output [1] 6.5 6.5 8 10 ns t s set-up time from input to clock or latch enable 5.5 6 8 10 ns t h register or latch data hold time 0 0 0 0 ns t co2 output clock or latch enable to output delay (through memory array) [1] 14 16 19 24 ns t scs output clock or latch enable to output clock or latch enable (through memory array) 8101215ns t sl set-up time from input through transparent latch to output register clock or latch enable 10 12 15 20 ns t hl hold time for input through transparent latch from output register clock or latch enable 0000ns f max1 maximum frequency with internal feedback (least of 1/t scs , 1/(t s + t h ), or 1/t co ) [7] 125 100 83 66 mhz f max2 maximum frequency data path in output registered/latched mode (lesser of 1/(t wl + t wh ), 1/(t s + t h ), or 1/t co ) [7] 153.8 153.8 125 100 mhz f max3 maximum frequency of (2) cy7c373is with external feedback (lesser of 1/(t co + t s ) and 1/(t wl + t wh ) [7] 83.3 80 62.5 50 mhz t oh ? t ih 37x output data stable from output clock minus input register hold time for 7c37x [7, 12] 0000ns notes: 11. all ac parameters are measured with 16 outputs switching and 35-pf ac test load. 12. this specification is intended to guarantee interface compatibility of the other members of the cy7c370i family with the cy7 c373i. this specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.
cy7c373i 7 pipelined mode parameters t ics input register clock to output register clock 8 10 12 15 ns f max4 maximum frequency in pipelined mode (least of 1/(t co + t is ), 1/t ics , 1/(t wl + t wh ), 1/(t is + t ih ), or 1/t scs ) [7] 125 83.3 66.6 50.0 mhz reset/preset parameters t rw asynchronous reset width [7] 10 12 15 20 ns t rr asynchronous reset recovery time [7] 12 14 17 22 ns t ro asynchronous reset to output [1] 16 18 21 26 ns t pw asynchronous preset width [7] 10 12 15 20 ns t pr asynchronous preset recovery time [7] 12 14 17 22 ns t po asynchronous preset to output [1] 16 18 21 26 ns tap controller parameter f ta p tap controller frequency 500 500 500 500 khz 3.3v i/o mode parameters t 3.3io 3.3v i/o mode timing adder 1 1 1 1 ns switching characteristics over the operating range [ ] frqwlqxhg 7c373i ? 125 7c373i ? 100 7c373i ? 83 7c373il-83 7c373i ? 66 7c373il ? 66 parameter description min. max. min. max. min. max. min. max. unit switching waveforms combinatorial output t pd 7c373i ? 6 input combinatorial output t s 7c373i ? 7 input clock t co registered output t h clock t wl t wh registered output
cy7c373i 8 switching waveforms (continued) latched output t s 7c373i ? 8 input latch enable t co latched output t h t pdl clock to clock 7c373i ? 10 registered input input register clock t ics output register clock t scs latched input t is 7c373i ? 11 latched input latch enable t ico combinatorial output t ih t pdl latch enable t wl t wh
cy7c373i 9 switching waveforms (continued) latched input and output t ics 7c373i ? 12 latched input output latch enable latched output t pdll latch enable t wl t wh t icol input latch enable t sl t hl asynchronous reset 7c373i ? 13 input t ro registered output clock t rr t rw asynchronous preset 7c373i ? 14 input t po registered output clock t pr t pw
cy7c373i 10 document #: 38-00495-f f lash 370, f lash 370i, isr, ultralogic, warp, warp professional, and warp enterprise are trademarks of cypress semiconductor corporation. switching waveforms (continued) output enable/disable 7c373i ? 16 input t er outputs t ea ordering information speed (mhz) ordering code package type package type operating range 125 cy7c373i ? 125ac a100 100-pin thin quad flatpack commercial cy7c373i ? 125jc j83 84-lead plastic leaded chip carrier 100 cy7c373i ? 100ac a100 100-pin thin quad flatpack commercial cy7c373i ? 100jc j83 84-lead plastic leaded chip carrier cy7c373i ? 100ai a100 100-pin thin quad flatpack industrial cy7c373i ? 100ji j83 84-lead plastic leaded chip carrier 83 cy7c373i ? 83ac a100 100-pin thin quad flatpack commercial cy7c373i ? 83jc j83 84-lead plastic leaded chip carrier cy7c373i ? 83ai a100 100-pin thin quad flatpack industrial cy7c373i ? 83ji j83 84-lead plastic leaded chip carrier cy7c373il ? 83jc j83 84-lead plastic leaded chip carrier commercial 66 cy7c373i ? 66ac a100 100-pin thin quad flatpack commercial cy7c373i ? 66jc j83 84-lead plastic leaded chip carrier cy7c373i ? 66ai a100 100-pin thin quad flatpack industrial cy7c373i ? 66ji j83 84-lead plastic leaded chip carrier cy7c373il ? 66jc j83 84-lead plastic leaded chip carrier commercial
cy7c373i 11 package diagrams 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-b
cy7c373i ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams 84-lead plastic leaded chip carrier j83 51-85006-a

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