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hb56a472e series 4,194,304-word 72-bit high density dynamic ram module description the hb56a472e belongs to 8 byte dimm (dual in-line memory module) family, and has been developed as an optimized main memory solution for 4- and 8-byte processor applications. the hb56a472e is a 4 m 72 dynamic ram module, mounted 18 pieces of 16-mbit dram (hm5116400bts) sealed in tsop package and 2 pieces of 16-bit bicmos line driver (74abt16244) sealed in tssop package. an outline of the hb56a472e is 168-pin socket type package (dual lead out). therefore, the hb56a472e makes high density mounting possible without surface mount technology. the hb56a472e provides common data inputs and outputs. decoupling capacitors are mounted beside each tsop on the module board. features 168-pin socket type package (dual lead out) ? lead pitch: 1.27 mm single 5 v ( 5%) supply high speed ? access time: t rac = 60/70/80 ns (max) ? access time: t cac = 20/23/25 ns (max) low power dissipation ? active mode: 7.90/6.95/6.48 w (max) ? standby mode (ttl): 525 mw (max) ? standby mode (cmos): 431 mw (max) buffered inputs except ras and dq 4 byte interleave enabled, dual address inputs (a0/b0) fast page mode capability 4,096 refresh cycle: 64 ms 2 variations of refresh ? ras -only refresh ? cas -before- ras refresh ttl compatible
datasheet title 2 ordering information type no. access time package contact pad hb56a472e-6b 60 ns 168-pin dual lead out socket type gold HB56A472E-7B 70 ns 168-pin dual lead out socket type gold hb56a472e-8b 80 ns 168-pin dual lead out socket type gold pin arrangement front side back side 1pin 85pin 10pin 94pin 11pin 95pin 40pin 124pin 41pin 125pin 84pin 168pin pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 16 dq12 31 oe0 46 ce4 2 dq0 17 dq13 32 v ss 47 nc 3 dq1 18 v cc 33 a0 48 we2 4 dq2 19 dq14 34 a2 49 v cc 5 dq3 20 dq15 35 a4 50 nc 6v cc 21 dq16 36 a6 51 nc 7 dq4 22 dq17 37 a8 52 dq18 8 dq5 23 v ss 38 a10 53 dq19 9 dq6 24 nc 39 nc 54 v ss 10 dq7 25 nc 40 v cc 55 dq20 11 dq8 26 v cc 41 nc 56 dq21 12 v ss 27 we0 42 nc 57 dq22 13 dq9 28 ce0 43 v ss 58 dq23 14 dq10 29 nc 44 oe2 59 v cc 15 dq11 30 re0 45 re2 60 dq24
datasheet title 3 pin arrangement (cont) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 61 nc 88 dq38 115 nc 142 dq59 62 nc 89 dq39 116 v ss 143 v cc 63 nc 90 v cc 117 a1 144 dq60 64 nc 91 dq40 118 a3 145 nc 65 dq25 92 dq41 119 a5 146 nc 66 dq26 93 dq42 120 a7 147 nc 67 dq27 94 dq43 121 a9 148 nc 68 v ss 95 dq44 122 a11 149 dq61 69 dq28 96 v ss 123 nc 150 dq62 70 dq29 97 dq45 124 v cc 151 dq63 71 dq30 98 dq46 125 nc 152 v ss 72 dq31 99 dq47 126 b0 153 dq64 73 v cc 100 dq48 127 v ss 154 dq65 74 dq32 101 dq49 128 nc 155 dq66 75 dq33 102 v cc 129 nc 156 dq67 76 dq34 103 dq50 130 nc 157 v cc 77 dq35 104 dq51 131 nc 158 dq68 78 v ss 105 dq52 132 pde 159 dq69 79 pd1 106 dq53 133 v cc 160d dq70 80 pd3 107 v ss 134 nc 161 dq71 81 pd5 108 nc 135 nc 162 v ss 82 pd7 109 nc 136 dq54 163 pd2 83 id0 (v ss ) 110 v cc 137 dq55 164 pd4 84 v cc 111 nc 138 v ss 165 pd6 85 v ss 112 nc 139 dq56 166 pd8 86 dq36 113 nc 140 dq57 167 id1 (v ss ) 87 dq37 114 nc 141 dq58 168 v cc
datasheet title 4 pin description pin name function a0?11, b0 address input: a0?11, b0 row address: a0?11, b0 column address: a0?9, b0 refresh address: a0?11, b0 dq0?q71 data-in/data-out re0 , re2 row address strobe ( ras ) ce0 , ce4 column address strobe ( cas ) we0 , we2 read/write enable oe0 , oe2 output enable v cc power supply v ss ground pd1?d8 presence detect id0, id1 id bit pde presence detect enable nc no connection presence detect pin assignment pde = low pde = high pin name pin no. 60 ns 70 ns 80 ns all pd1 79 1 1 1 high-z pd2 163 1 1 1 high-z pd3 80 0 0 0 high-z pd4 164 1 1 1 high-z pd5 81 0 0 0 high-z pd6 165 1 0 1 high-z pd7 82 1 1 0 high-z pd8 166 0 0 0 high-z note: 1: high level (driver output) 0: low level (driver output)
datasheet title 5 block diagram v cc dq0 dq1 dq2 dq3 i/o i/o i/o i/o cas ras d0 we oe dq4 dq5 dq6 dq7 i/o i/o i/o i/o cas ras d1 we oe dq8 dq9 dq10 dq11 i/o i/o i/o i/o cas ras d2 we oe dq12 dq13 dq14 dq15 i/o i/o i/o i/o cas ras d3 we oe dq16 dq17 dq18 dq19 i/o i/o i/o i/o cas ras d4 we oe dq20 dq21 dq22 dq23 i/o i/o i/o i/o cas ras d5 we oe dq24 dq25 dq26 dq27 i/o i/o i/o i/o cas ras d6 we oe dq28 dq29 dq30 dq31 i/o i/o i/o i/o cas ras d7 we oe dq32 dq33 dq34 dq35 i/o i/o i/o i/o cas ras d8 we oe re0 oe0 we0 ce0 dq36 dq37 dq38 dq39 i/o i/o i/o i/o cas ras d9 we oe dq40 dq41 dq42 dq43 i/o i/o i/o i/o cas ras d10 we oe dq44 dq45 dq46 dq47 i/o i/o i/o i/o cas ras d11 we oe dq48 dq49 dq50 dq51 i/o i/o i/o i/o cas ras d12 we oe dq52 dq53 dq54 dq55 i/o i/o i/o i/o cas ras d13 we oe dq56 dq57 dq58 dq59 i/o i/o i/o i/o cas ras d14 we oe dq60 dq61 dq62 dq63 i/o i/o i/o i/o cas ras d15 we oe dq64 dq65 dq66 dq67 i/o i/o i/o i/o cas ras d16 we oe dq68 dq69 dq70 dq71 i/o i/o i/o i/o cas ras d17 we oe re2 oe2 we2 ce4 d0 to d17, 74abt16244 v ss a1 to a11 b0 a0 d0 to d17 d0 to d17, 74abt16244 d9 to d17 d0 to d8 v pd1 cc note : d0 to d17 : hm5116400 : 74abt16244 pd1 to pd8 0.1 f 20pcs 0.68 f 4pcs m m v pd2 cc v pd3 ss v pd4 cc v pd5 ss v pd6 cc v pd7 cc v pd8 ss v ss v ss
datasheet title 6 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t ?.5 to +7.0 v supply voltage relative to v ss v cc ?.5 to +7.0 v short circuit output current iout 50 ma power dissipation p t 19 w operating temperature topr 0 to +70 c storage temperature tstg ?5 to +125 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit note supply voltage v ss 000v v cc 4.75 5.0 5.25 v 1 input high voltage v ih 2.4 5.5 v 1 input low voltage v il ?.5 0.8 v 1 note: 1. all voltage referred to v ss
datasheet title 7 dc characteristics (ta = 0 to +70 c, v cc = 5 v 5%, v ss = 0 v) hb56a472e 60 ns 70 ns 80 ns parameter symbol min max min max min max unit test conditions notes operating current i cc1 1504 1324 1234 ma t rc = min 1,2 standby current i cc2 100 100 100 ma ttl interface ras , cas = v ih dout = high-z 82 82 82 ma cmos interface ras , cas 3 v cc -0.2 v dout = high-z ras -only refresh current i cc3 1504 1324 1234 ma t rc = min 2 standby current i cc5 154 154 154 ma ras = v ih , cas = v il dout = enable 1 cas -before- ras refresh current i cc6 1504 1324 1234 ma t rc = min fast page mode current i cc7 1324 1144 964 ma t pc = min 1, 3 input leakage current i li ?0 10 ?0 10 ?0 10 m a 0 v vin 5.5 v output leakage current i lo ?0 10 ?0 10 ?0 10 m a 0 v vout 5.5 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v cc 2.4 v high iout = ?.0 ma output low voltage v ol 0 0.4 0 0.4 0 0.4 v low iout = 4.2 ma notes: 1. i cc depends on output load condition when the device is selected, i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih . capacitance (ta = 25 c, v cc = 5 v 5%) parameter symbol typ max unit notes input capacitance (address) c i1 ?0pf1 input capacitance ( cas , we , oe )c i2 ?0pf1 input capacitance ( ras )c i3 ?8pf1 i/o capacitance (dq) c i/o 20 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable dout.
datasheet title 8 ac characteristics (ta = 0 to 70 c, v cc = 5 v 5%, v ss = 0 v) *1, *2, *18 test conditions input rise and fall time: 5 ns input timing reference levels: 0.8 v, 2.4 v output load: 2 ttl gate + c l (100 pf) (including scope and jig) read, write, read-modify-write, and refresh cycles (common parameters) hb56a472e 60 ns 70 ns 80 ns parameter symbol min max min max min max unit notes random read or write cycle time t rc 110 130 150 ns ras precharge time t rp 40 50 60 ns cas precharge t cp 10 10 10 ns ras pulse width t ras 60 10000 70 10000 80 10000 ns cas pulse width t cas 15 10000 18 10000 20 10000 ns row address setup time t asr 5 5 5 ns row address hold time t rah 10 10 10 ns column address setup time t asc 0 0 0 ns column address hold time t cah 10 15 15 ns ras to cas delay time t rcd 20 40 20 47 20 55 ns 3 ras to column address delay time t rad 15 25 15 30 15 35 ns 4 ras hold time t rsh 20 23 25 ns cas hold time t csh 60 70 80 ns cas to ras precharge time t crp 10 10 10 ns oe to din delay time t oed 20 23 25 ns 5 oe delay time from din t dzo 0 0 0 ns6 cas delay time from din t dzc 0 0 0 ns6 transition time (rise and fall) t t 350350350ns7 refresh period t ref ?4 64 ?4 ms19
datasheet title 9 read cycle hb56a472e 60 ns 70 ns 80 ns parameter symbol min max min max min max unit notes access time from ras t rac 60 70 80 ns 8, 19 access time from cas t cac 20 23 25 ns 9, 10, 17 access time from address t aa 35 40 45 ns 9, 11, 17 access time from oe t oea ?0 23 ?5 ns9 read command setup time t rcs 0 0 0 ns read command hold time to cas t rch 0 0 0 ns12 read command hold time to ras t rrh 0 0 0 ns12 column address to ras lead time t ral 35 40 45 ns column address to cas lead time t cal 30 35 40 ns cas to output in low-z t clz 2 2 2 ns output data hold time t oh 3 3 3 ns output data hold time from oe t oho 3 3 3 ns output buffer turn-off time t off ?0 20 ?0 ns13 output buffer turn-off to oe t oez ?0 20 ?0 ns13 cas to din delay time t cdd 20 23 25 ns 5 write cycle hb56a472e 60 ns 70 ns 80 ns parameter symbol min max min max min max unit notes write command setup time t wcs 0 0 0 ns14 write command hold time t wch 10 15 15 ns write command pulse width t wp 10 10 10 ns write command to ras lead time t rwl 20 23 25 ns write command to cas lead time t cwl 15 18 20 ns data-in setup time t ds 0 0 0 ns15 data-in hold time t dh 15 20 20 ns 15
datasheet title 10 read-modify-write cycle hb56a472e 60 ns 70 ns 80 ns parameter symbol min max min max min max unit notes read-modify-write cycle time t rwc 155 181 205 ns ras to we delay time t rwd 90 103 115 ns 14 cas to we delay time t cwd 40 46 50 ns 14 column address to we delay time t awd 55 63 70 ns 14 oe hold time from we t oeh 15 18 20 ns refresh cycle hb56a472e 60 ns 70 ns 80 ns parameter symbol min max min max min max unit notes cas setup time (cbr refresh cycle) t csr 10 10 10 ns cas hold time (cbr refresh cycle) t chr 10 10 10 ns we setup time (cbr refresh cycle) t wrp 5 5 5 ns we hold time (cbr refresh cycle) t wrh 10 10 10 ns ras precharge to cas hold time t rpc 0 0 0 ns fast page mode cycle hb56a472e 60 ns 70 ns 80 ns parameter symbol min max min max min max unit notes fast page mode cycle time t pc 40 45 50 ns fast page mode ras pulse width t rasp 100000 100000 100000 ns 16 access time from cas precharge t cpa 40 45 50 ns 9, 17 ras hold time from cas precharge t cprh 40 45 50 ns
datasheet title 11 fast page mode read-modify-write cycle hb56a472e 60 ns 70 ns 80 ns parameter symbol min max min max min max unit notes fast page mode read-modify-write cycle time t prwc 85 96 105 ns we delay time from cas precharge t cpw 60 68 75 ns 14 notes: 1. ac measurements assume t t = 5 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh or cas -before- ras refresh). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles are required. 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd < t rcd (max) and t rad < t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 2ttl loads and 100 pf. 10. assumes that t rcd 3 t rcd (max) and t rad t rad (max) 11. assumes that t rcd t rcd (max) and t rad 3 t rad (max). 12. either t rch or t rrh must be satisfied for a read cycle. 13. t off (max) and t oez (max) are defined the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd, t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t awd 3 t awd (min), or t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. these parameters are referred to cas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycle. 16. t rasp defines ras pulse width in fast page mode cycles. 17. access time is determined by the longest among t aa , t cac and t cpa . 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. after ras is reset, if t oeh 3 t cwl , the dq pins will remain open circuit (high impedance); if t oeh t cwl , invalid data will be out at each dq. 19. t ref is determined by 4,096 refresh cycle.
datasheet title 12 timing waveforms refer to the hm5116400b series data sheet. physical outline unit: mm/inch 2 ? 3.00 f 8.89 11.43 a c 36.83 1.270 b 54.61 4.00 17.78 25.40 127.35 133.35 3.00 3.00 4.00 max 1.27 ?0.10 4.00 min 1.00 ?0.05 2.54 min 0.25 max 1.00 6.35 2.00 ?0.10 3.125 ?0.125 6.35 2.00 ?0.10 3.125 ?0.125 detail a detail b detail c 5.250 5.014 0.118 0.118 0.350 0.450 1.450 2.150 0.157 0.700 1.000 0.157 max 0.050 ?0.004 0.157 min 2 ? 0.118 f 0.100 min 0.039 ?0.002 0.010 max 0.039 0.250 0.079 ?0.004 0.123 ?0.005 0.250 0.079 ?0.004 0.123 ?0.005 0.050 84 85 168 1.27 0.050 1

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