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lxt363 integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications datasheet the lxt363 is a fully integrated, combination transceiver for t1 isdn primary rate interface and general t1 long and short haul applications. the device operates over 22 awg twisted-pair cables from 0 to 6 kft and offers line build outs and pulse equalization settings for all t1 line interface unit (liu) applications. the lxt363 features an intel or motorola compatible parallel port for microprocessor control. the lxt363 incorporates advanced crystal-less digital jitter attenuation in either the transmit or receive data path starting at 3 hz. b8zs encoding/decoding and unipolar or bipolar data i/o are available. the liu provides loss of signal monitoring and a variety of diagnostic loopback modes. the parallel port is ideal for applications with multiple t1 interfaces. applications product features isdn primary rate interface (isdn pri) csu/ntu interface to t1 service t1 lan/wan bridge/routers t1 mux; channel banks digital loop carrier - subscriber carrier systems fully integrated transceiver for long or short-haul t1 interfaces crystal-less digital jitter attenuation ? select either transmit or receive path ? no crystal or high speed external clock required meets or exceeds specifications in ansi t1.102, t1.403 and t1.408; and at&t pub 62411 supports 100 ? (t1 twisted-pair) applications selectable receiver sensitivity ? fully restores the received signal after transmission through a cable with attenuation of either 0 to 26 db, or 0 to 36 db @ 772 khz five pulse equalization settings for t1 short-haul applications four line build-outs for t1 long-haul applications from 0 db to -22.5 db transmit/receive performance monitors with driver fail monitor open and loss of signal outputs selectable unipolar or bipolar data i/o and b8zs encoding/decoding line attenuation indication output in 2.9 db steps qrss generator/detector for testing or monitoring local, remote, and analog loopback, plus in-band network loopback code generation and detection intel/motorola compatible 8-bit parallel interface for microprocessor control available in 28-pin plcc, 44-pin pqfp and 44-pin lqfp packages as of january 15, 2001, this document replaces the level one document order number: 249034-001 known as lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications . january 2001
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt363 may contain design defects or errors known as errata which may cause the product to deviate from published specifica tions. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
datasheet 3 integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 contents 1.0 pin assignments and signal descriptions ...................................................... 8 1.1 mode dependent signals ...................................................................................... 9 2.0 functional description ...........................................................................................13 2.1 initialization..........................................................................................................13 2.1.1 reset operation .....................................................................................13 2.2 transmitter ..........................................................................................................13 2.2.1 transmit digital data interface...............................................................13 2.2.2 transmit monitoring................................................................................13 2.2.3 transmit drivers .....................................................................................14 2.2.4 transmit idle mode.................................................................................14 2.2.5 transmit pulse shape ............................................................................14 2.3 receiver ..............................................................................................................14 2.3.1 receive equalizer ..................................................................................14 2.3.2 receive data recovery..........................................................................15 2.3.3 receiver monitor mode ..........................................................................15 2.4 jitter attenuation .................................................................................................15 2.5 diagnostic mode operation.................................................................................16 2.5.1 loopback modes ....................................................................................16 2.5.1.1 local loopback .........................................................................16 2.5.1.2 analog loopback.......................................................................18 2.5.1.3 remote loopback .....................................................................18 2.5.1.4 network loopback.....................................................................19 2.5.1.5 dual loopback ..........................................................................19 2.5.2 internal pattern generation and detection.............................................20 2.5.2.1 transmit all ones ......................................................................20 2.5.2.2 quasi-random signal source (qrss) .....................................20 2.5.2.3 in-band network loop up or down code generator ................21 2.5.3 error insertion and detection .................................................................21 2.5.3.1 bipolar violation insertion (insbpv) .........................................21 2.5.3.2 logic error insertion (insler)..................................................22 2.5.3.3 bipolar violation detection (bpv)..............................................22 2.5.4 alarm condition monitoring ....................................................................22 2.5.4.1 loss of signal ............................................................................22 2.5.4.2 alarm indication signal detection .............................................22 2.5.4.3 driver failure open mode .........................................................22 2.5.4.4 elastic store overflow/underflow ..............................................23 2.5.5 other diagnostic reports .......................................................................23 2.5.5.1 receive line attenuation indication ..........................................23 2.5.5.2 built-in self test ........................................................................23 2.6 parallel microprocessor interface........................................................................23 2.6.1 interrupt handling...................................................................................24 3.0 register definitions .................................................................................................25 4.0 application information .........................................................................................30 4.1 transmit return loss ..........................................................................................30 4.2 transformer data ................................................................................................30
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 4 datasheet 4.3 application circuits.............................................................................................. 30 5.0 test specifications .................................................................................................. 33 6.0 mechanical specifications ................................................................................... 41 figures 1 lxt363 block diagram ......................................................................................... 7 2 lxt363 pin assignments...................................................................................... 8 3 50% duty cycle coding ...................................................................................... 14 4 taos with lloop .............................................................................................. 17 5 local loopback ................................................................................................... 17 6 analog loopback ................................................................................................ 18 7 remote loopback ............................................................................................... 19 8 dual loopback .................................................................................................... 19 9 taos data path ................................................................................................. 20 10 qrss mode ........................................................................................................ 20 11 typical lxt363 application................................................................................. 32 12 1.544 mhz t1 pulse (ds1 and dsx-1) (see table 23 ) ...................................... 35 13 transmit clock timing ........................................................................................ 36 14 receive clock timing ......................................................................................... 37 15 lxt363 i/o timing diagram for intel address/data bus .................................... 38 16 lxt363 i/o timing diagram for motorola address/data bus ............................. 39 17 typical t1 jitter tolerance at 36 db ................................................................... 39 18 t1 jitter attenuation ............................................................................................ 40 19 plastic leaded chip carrier package specifications .......................................... 41 20 plastic quad flat package specifications........................................................... 42 21 low-profile quad flat package specifications ................................................... 43
datasheet 5 integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 tables 1 lxt363 clock and data pin assignments by mode1............................................ 9 2 lxt363 processor interface pins.......................................................................... 9 3 lxt363 signal descriptions ................................................................................10 4 diagnostic mode summary .................................................................................16 5 register addresses .............................................................................................25 6 register and bit summary ..................................................................................25 7 control register #1 read/write, address (a7-a0) = x010000x ..........................26 8 equalizer control bit settings..............................................................................26 9 control register #2 read/write, address (a7-a0) = x010001x ..........................27 10 control register #3 read/write, address (a7-a0) = x010010x ..........................27 11 interrupt clear register read/write, address (a7-a0) = x010011x....................28 12 transition status register read only, address (a7-a0) = x010100x.................28 13 performance status register read only, address (a7-a0) = x010101x ............29 14 equalizer status register read only, address (a7-a0) = x010110x .................29 15 control register #4 read/write, address (a7-a0) = x010111x ..........................29 16 transmit return loss ..........................................................................................30 17 transformer specifications for lxt363...............................................................30 18 recommended transformers for lxt363...........................................................31 19 absolute maximum ratings.................................................................................33 20 recommended operating conditions .................................................................33 21 digital characteristics..........................................................................................34 22 analog characteristics ........................................................................................34 23 1.544 mhz t1 pulse mask corner point specifications......................................35 24 master and transmit clock timing characteristics (see figure 13 )...................35 25 receive timing characteristics (see figure 14 ).................................................36 26 lxt363 20 mhz intel bus parallel i/o timing characteristics (see figure 15 ) ...................................................................................................37 27 lxt363 16.78 mhz motorola bus parallel i/o timing characteristics (see figure 16 ) ...................................................................................................38
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 6 datasheet revision history revision date description
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 7 figure 1. lxt363 block diagram
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 8 datasheet 1.0 pin assignments and signal descriptions figure 2. lxt363 pin assignments and markings lxt363pe mclk 1282726 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 432 tclk tpos / tdata / insler tneg / insbpv gnd vcc rring rtip tring tvcc tgnd ttip rclk rpos / rdata rneg / bpv ale / as rd / ds wr / r/w cs int ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 LXT363QE lxt363le n/c rneg / bpv n/c n/c gnd n/c vcc n/c rring rtip n/c n/c 44 43 42 41 40 39 38 37 36 35 34 23 12 13 14 15 16 17 18 19 20 21 22 11 10 9 8 7 6 5 4 3 2 1 33 32 31 30 29 28 27 26 25 24 tneg / insbpv tpos / tdata / insler tclk mclk n/c n/c ttip tgnd n/c tvcc tring n/c n/c rpos / rdata rclk n/c ad7 n/c n/c n/c ale / as rd / ds ad6 wr / r/w cs int ad0 ad1 ad2 ad3 ad4 ad5 lxt363pe xx xxxxxx xxxxxxxx l xt363 q e xx l xt363le xx x xxxxx x xxxxxxx
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 9 1.1 mode dependent signals as shown in figure 2 , the lxt363 has several pins that change function (and signal name) according to the selected mode(s) of operation. these pins, associated signal names, and operating modes are summarized in table 1 and table 2 . lxt363 signals are described in table 3 . table 1. lxt363 clock and data pin assignments by mode 1 pin # external data modes qrss modes plcc qfp bipolar mode unipolar mode bipolar mode unipolar mode 139 mclk 241 tclk 3 42 tpos tdata insler 4 43 tneg insbpv insbpv 6 3 rneg bpv rneg bpv 7 4 rpos rdata rpos rdata 85 rclk 13 15 ttip 16 19 tring 19 24 rtip 20 25 rring 1. data pins change based on whether external data or internal qrss mode is active. table 2. lxt363 processor interface pins pin # address/data bus type pin # address/data bus type plcc qfp intel motorola plcc qfp intel motorola 52 ale as 25 35 ad2 97 rd ds 26 36 ad3 12 13 wr r/w 27 37 ad4 17 20 cs 28 38 ad5 18 21 int 10 9 ad6 23 31 ad0 11 10 ad7 24 32 ad1 - - -
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 10 datasheet table 3. lxt363 signal descriptions pin # symbol i/o 1 description plcc qfp 139 mclk di master clock . external, independent 1.544 mhz clock signal required to generate internal clocks. mclk must be jitter-free and have an accuracy better than 50 ppm with a typical duty cycle of 50%. upon loss of signal (los), rclk is derived from mclk. 241 tclk di transmit clock . a 1.544 mhz clock is required. the transceiver samples tpos and tneg on the falling edge of tclk (or mclk, if tclk is not present). 3 4 42 43 tpos / tdata / insler tneg / insbpv di di bipolar modes: transmit ? positive and negative . tpos and tneg are the positive and negative sides of a bipolar input pair. data to be transmitted onto the twisted-pair line is input at these pins. tpos/tneg are sampled on the falling edge of tclk (or mclk, if tclk is not present). unipolar modes: transmit data . tdata carries unipolar data to be transmitted onto the twisted-pair line and is sampled on the falling edge of tclk. transmit insert logic error. in qrss mode , a low-to-high transition on insler inserts a logic error into the transmitted qrss data pattern. the error follows the data flow of the active loopback mode. the lxt363 samples this pin on the falling edge of tclk (or mclk, if tclk is not present). transmit insert bipolar violation . insbpv is sampled on the falling edge of tclk (or mclk, if tclk is not present) to control bipolar violation (bpv) insertions in the transmit data stream. a low-to-high transition is required to insert each bpv. in qrss mode , the bpv is inserted into the transmitted qrss pattern. 5 2 ale / as di address latch enable. connect to ale signal of intel microprocessor address strobe connect to as signal of motorola microprocessor. note that leaving this pin floating forces all output pins to a high impedance state. 6 7 3 4 rneg / bpv rpos / rdata do do bipolar modes: receive ? negative and positive . rpos and rneg are the positive and negative sides of a bipolar output pair. data recovered from the line interface is output on these pins. a signal on rneg corresponds to receipt of a negative pulse on rtip/rring. a signal on rpos corresponds to receipt of a positive pulse on rtip/rring. rneg/rpos are non-return- to-zero (nrz). the plcke bit in register cr3 selects the rclk clock edge when rpos /rneg are stable and valid. unipolar modes: receive bipolar violation. bpv goes high to indicate detection of a bipolar violation from the line. this is an nrz output, valid on the rising edge of rclk. receive data . rdata is the unipolar nrz output of data recovered from the line interface. the plcke bit in register cr3 selects the rclk clock edge when rdata is stable and valid. 8 5 rclk do receive recovered clock . the clock recovered from the line input signal is output on this pin. under los conditions, there is a smooth transition from the rclk signal (derived from the recovered data) to the mclk signal at the rclk pin. 1. di = digital input; do = digital output; di/o = digital input/output; ai = analog input; ao = analog output.
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 11 97 rd / ds di read. on an intel bus, driving rd low commands a lxt363 register read operation. data strobe. on a motorola bus, ds goes low when data is being driven on the address/data bus. data is valid on the rising edge of ds . 10 11 9 10 ad6 ad7 di/o address/data bus 6 and 7. used with ad0 - ad5 to form the address/ data bus. conforms to intel and motorola multiplexed address/data bus specifications. 12 13 wr / r/w di write. on an intel bus, driving wr low commands a lxt363 register write operation. read/write. on a motorola bus, driving r/w high commands a lxt363 register read operation; driving it low commands a write operation. 13 16 15 19 ttip tring ao transmit tip and ring . differential driver output pair designed to drive a 50 - 200 ? load. the transformer and line matching resistors should be selected to give the desired pulse height and return loss performance. see ? application information ? on page 30 . 14 16 tgnd - ground return for the transmit driver power supply tvcc. 15 18 tvcc - +5 vdc power supply for the transmit drivers. tvcc must not vary from vcc by more than 0.3 v. 17 20 cs di chip select. during a read or write operation, cs must remain low. see figure 15 and figure 16 for timing requirements. in the case of a single processor controlling several chips, this line is used to select a specific transceiver. 18 21 int do interrupt. int goes low to flag the host when los, ais, nloop, qrss, dfms or dfmo bits changes state, or when an elastic store overflow or underflow occurs. to identify the specific interrupt, read the performance status register (psr). to clear or mask an interrupt, write a one to the appropriate bit in the interrupt clear register (icr). to re-enable the interrupt, write a zero. int is an open drain output that must be connected to vcc through a pull-up resistor. 19 20 24 25 rtip rring ai receive tip and ring . the alternate mark inversion (ami) signal received from the line is applied at these pins. a 1:1 transformer is required. data and clock recovered from rtip/rring are output on the rpos/rneg (or rdata in unipolar mode ), and rclk pins. 21 27 vcc - +5 vdc power supply for all circuits except the transmit drivers. transmit drivers are supplied by tvcc. table 3. lxt363 signal descriptions (continued) pin # symbol i/o 1 description plcc qfp 1. di = digital input; do = digital output; di/o = digital input/output; ai = analog input; ao = analog output.
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 12 datasheet 22 29 gnd - ground return for vcc. 23 24 25 26 27 28 31 32 35 36 37 38 ad0 ad1 ad2 ad3 ad4 ad5 di/o address/data bus 0 - 5 . used with ad6 and ad7 to form the address/ data bus. conforms to intel and motorola multiplexed address/data bus specifications. - 8, 11, 12, 14, 17, 22, 23, 26, 28, 30, 33, 34, 40, 44 n/c - not connected table 3. lxt363 signal descriptions (continued) pin # symbol i/o 1 description plcc qfp 1. di = digital input; do = digital output; di/o = digital input/output; ai = analog input; ao = analog output.
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 13 2.0 functional description the lxt363 is a fully integrated, pcm transceiver for 1.544 mbps (t1) long- or short-haul applications allowing full-duplex transmission of digital data over existing twisted-pair installations. the device interfaces with two twisted-pair lines (one pair each for transmit and receive) through standard pulse transformers and appropriate resistors. the figure on the front page of this data sheet shows a block diagram of the lxt363. control of the chip is via the 8-bit parallel microprocessor port. stand-alone operation is not supported. the lxt363 provides a high-precision, crystal-less jitter attenuator (ja). the user may place the ja in the transmit or receive path, or bypass it completely. the transceiver meets or exceeds fcc, ansi, and at&t specifications for csu and dsx-1 applications. 2.1 initialization during power up, the transceiver remains static until the power supply reaches approximately 3 v. upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the phase lock loops (pll). the transceiver uses a reference clock to calibrate the plls: the transmitter reference is tclk, and the receiver reference clock is mclk. mclk is mandatory for chip operation and must be independent, free running, and jitter free. 2.1.1 reset operation a reset operation initializes the status and state machines for the los, ais, nloop, and qrss blocks. writing a 1 to the bit cr2.reset commands a reset which clears all registers to 0. allow 32 ms for the device to settle. 2.2 transmitter 2.2.1 transmit digital data interface input data for transmission onto the line is clocked serially into the device at the tclk rate. tpos and tneg are the bipolar data inputs. in unipolar mode, the tdata pin accepts unipolar data. input data may pass through either the jitter attenuator or b8zs encoder or both. setting cr1.encenb = 1 enables b8zs encoding. tclk supplies input synchronization. see the figure 13 on page 36 for the transmit timing requirements for tclk and the master clock (mclk). 2.2.2 transmit monitoring the performance status register (psr) flags open circuits in bit psr.dfmo. a transition of dfmo can provide an interrupt, and its transition sets bit tsr.dfmo = 1. writing a 1 in bit icr.cdfmo clears the interrupt; leaving a 1 in the bit masks that interrupt.
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 14 datasheet 2.2.3 transmit drivers the transceiver transmits data as a 50% line code as shown in figure 3 . to reduce power consumption, the line driver is active only during transmission of marks, and is disabled during transmission of spaces. biasing of the transmit dc level is on-chip. 2.2.4 transmit idle mode transmit idle mode allows multiple transceivers to be connected to a single line for redundant applications. when tclk is not present, transmit idle mode becomes active, and ttip and tring change to the high impedance state. remote loopback, dual loopback, taos, or detection of network loop up code in the receive direction, temporarily disable the high impedance state. 2.2.5 transmit pulse shape as shown in table 8 on page 26 , the transmitted pulse shape is established by bits ec1 through ec4 of control register #1 (cr1). shaped pulses meeting the various t1, ds1, and dsx-1 specifications are applied to the ami line driver for transmission onto the line at ttip and tring. the transceiver produces dsx-1 pulses for short-haul t1 applications (settings from 0 db to +6.0 db of cable), and ds1 pulses for long-haul t1 applications (settings from 0 db to -22.5 db). refer to the test specifications section for pulse mask specifications. 2.3 receiver a 1:1 transformer provides the interface to the twisted-pair line. recovered data is output at rpos/ rneg (rdata in unipolar mode), and the recovered clock is output at rclk. refer to table 25 on page 36 for receiver timing specifications. 2.3.1 receive equalizer the receive equalizer processes the signal received at rtip and rring. the equalizer gain is up to 36 db. in long-haul applications, bits ec1 through ec4 in control register #1 determine the maximum gain applied at the equalizer. when ec1 = 0, up to 36 db of gain may be applied. when ec1 = 1, 26 db is the gain limit to provide an increased noise margin in shorter loop operations. figure 3. 50% duty cycle coding 10 1 bit cell
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 15 2.3.2 receive data recovery the transceiver filters the equalized signal and applies it to the peak detector and data slicers. the peak detector samples the inputs and determines the maximum value of the received signal. the data slicers are set at 50% of the peak value to ensure optimum signal-to-noise performance. after processing through the data slicers, the received signal goes to the data and timing recovery section, then to the b8zs decoder (if selected) and to the receive monitor. the data and timing recovery circuits provide input jitter tolerance significantly better than required by at&t pub 62411. see ? test specifications ? on page 33 for details. recovered data is routed to the loss of signal (los) monitor and through the alarm indication signal (ais, blue alarm) monitor. the jitter attenuator (ja) may be enabled or disabled in the receive data path or the transmit path. received data may be routed to either the b8zs or hdb3 decoder or neither. finally, the device may send the digital data to the framer as either unipolar or bipolar data. when transmitting unipolar data to the framer, the device reports reception of bipolar violations by driving the bpv pin high. 2.3.3 receiver monitor mode the lxt363 receive equalizer can be used in monitor mode applications. monitor mode applications require 20 db to 30 db resistive attenuation of the signal, plus a small amount of cable attenuation (less than 6 db). setting bit cr3.eqzmon = 1 configures the device to operate in monitor mode. the device must be in t1 long-haul receiver mode (set bits cr1.ec4:1 = 0xx0 or 1001 or 1010) for monitor mode. 2.4 jitter attenuation a jitter attenuation loop (jal) with an elastic store (es) provides jitter attenuation as shown in the test specifications section. the jal requires no special circuitry, such as an external quartz crystal or high-frequency clock (higher than the line rate). its timing reference is mclk. bit cr1.jasel0 enables or disables the ja circuit. with bit cr1.jasel0 = 1, bit cr1.jasel1 controls the ja circuit placement (see table 7 on page 26 ). the es can be either a 32 x 2-bit or 64 x 2-bit register depending on the value of bit cr3.es64 (see table 10 on page 27 .) the device clocks data into the es using either tclk or rclk depending on whether the ja circuitry is in the transmit or receive data path, respectively. data is shifted out of the elastic store using the dejittered clock from the jal. when the fifo is within two bits of overflowing or underflowing, the es adjusts the output clock by 1 / 8 of a bit period. the es produces an average delay of 16 bits (or 32 bits, with the 64-bit es option selected) in the associated data path. when the jitter attenuator is in the receive path, the output rclk transitions smoothly to mclk in the event of a los condition. the transition status register bits tsr.esovr and tsr.esunf indicate an elastic store overflow or underflow, respectively. note that these are sticky bits that once set to 1, remain set until the host reads the register. the es can also provide a maskable interrupt on either overflow or underflow.
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 16 datasheet 2.5 diagnostic mode operation the lxt363 offers multiple diagnostic modes as listed in table 4 . the diagnostic modes are selected by setting the appropriate register bits as described in the following paragraphs. 2.5.1 loopback modes 2.5.1.1 local loopback see figure 4 and figure 5 . local loopback is selected by setting cr2.elloop to 1. lloop inhibits the receiver circuits. the transmit clock and data inputs (tclk and tpos/tneg or tdata) loop back through the jitter attenuator (if enabled) and show up at rclk and rpos/ rneg or rdata. note that during lloop, the jasel input is strictly an enable/disable control; it does not affect the placement of the jal. if ja is enabled, it is active in the loopback circuit. if ja is bypassed, it is not active in the loopback circuit. the transmitter circuits are unaffected by lloop. lxt363 transmits the tpos/tneg or tdata inputs (or a stream of 1s if taos is asserted) normally. when used in this mode, the transceiver can function as a stand-alone jitter attenuator. table 4. diagnostic mode summary diagnostic mode interrupt maskable loopback modes local loopback (lloop) no analog loopback (aloop) no remote loopback (rloop) no in-band network loopback (nloop) yes dual loopback (dloop) no internal data pattern generation and detection transmit all ones (taos) no quasi-random signal source (qrss) yes in-band loop up/down code generator no error insertion and detection bipolar violation insertion (insbpv) no logic error insertion (insler) no bipolar violation detection (bpv) no alarm condition monitoring receive loss of signal (los) monitoring yes receive alarm indication signal (ais) monitoring yes transmit driver failure monitoring open (dfmo) yes elastic store overflow and underflow monitoring yes
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 17 other diagnostic reports receive line attenuation indicator (latn) no built-in self test (bist) yes figure 4. taos with lloop figure 5. local loopback table 4. diagnostic mode summary diagnostic mode interrupt maskable timing recovery ttip rtip tring ja* rring * if enabled encoder* decoder* tclk rclk tpos rpos tneg rneg timing & control timing recovery ttip tring * if enabled decoder* tclk rclk tpos rpos tneg rneg timing & control rtip rring ja* encoder* local loopback with ja in transmit path local loopback with ja in receive path
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 18 datasheet 2.5.1.2 analog loopback see figure 6 . analog loopback (aloop) exercises the maximum number of functional blocks. aloop operation disconnects the rtip/rring inputs from the line and routes the transmit outputs back into the receive inputs. this tests the encoders/decoders, jitter attenuator, transmitter, receiver and timing recovery sections. writing a 1 to bit cr2.ealoop enables the aloop mode. note that aloop will override all other loopback modes. 2.5.1.3 remote loopback see figure 7 . in remote loopback (rloop) mode, the device ignores the transmit data and clock inputs (tclk and tpos/tneg or tdata), and bypasses the in-line encoders/decoders. the rpos/rneg or rdata outputs loop back through the transmit circuits to ttip and tring at the rclk frequency. the rloop command does not affect the receiver circuits which continue to output the rclk and rpos/rneg or rdata signals received from the twisted-pair line. rloop is selected by writing a 1 to bit cr2.erloop. figure 6. analog loopback ttip rtip tring ja* rring * if enabled encoder* decoder* tclk rclk tpos rpos tneg rneg ttip rtip tring rring * if enabled decoder* tclk rclk tpos rpos tneg rneg ja* encoder* analog loopback with ja in transmit path analog loopback with j a in receive path timing recovery timing recovery
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 19 2.5.1.4 network loopback network loopback (nloop) can be initiated only when the network loopback detect function is enabled. writing a 1 to cr2.enloop enables nloop detection. with nloop detection enabled, the receiver looks for the nloop data patterns (00001 = enable, 001 = disable) in the input data stream. when the receiver detects an nloop enable data pattern repeated for a minimum of five seconds, the device enables rloop. the device responds to both framed and unframed nloop patterns. once nloop detection is enabled at the chip and activated by the appropriate data pattern, it is identical to remote loopback (rloop). nloop is disabled by receiving the 001 pattern for five seconds, or by activating rloop or aloop, or by disabling nloop detection. the device goes into dual loopback mode (dloop) in the case where it detects both the nloop and lloop functions. 2.5.1.5 dual loopback see figure 8 . to select dual loopback (dloop) set bits cr2.erloop and cr2.elloop to 1. in dloop mode, the transmit clock and data inputs (tclk and tpos/tneg or tdata) loop back through the jitter attenuator (unless disabled) to rclk and rpos/rneg or rdata. the data and clock recovered from the twisted-pair line loop back through the transmit circuits to ttip and tring without jitter attenuation. figure 7. remote loopback tclk ttip rtip tring rring rclk timing recovery ja* * if enabled tpos rpos tneg rneg tclk ttip rtip tring rring rclk ja* * if enabled timing & control tpos rpos tneg rneg remote loopback with ja in receive path remote loopback with ja in transmit path timing & control timing recovery figure 8. dual loopback encoder* decoder* ttip rtip tring rring rclk timing recovery ja* * if enabled timing & control rpos rneg tclk tpos tneg
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 20 datasheet 2.5.2 internal pattern generation and detection 2.5.2.1 transmit all ones see figure 9 . in transmit all ones (taos) mode the transceiver ignores the tpos and tneg inputs and transmits a continuous stream of 1s at the tclk frequency. (with no tclk, the taos output clock is mclk.) this can be used as the alarm indication signal (ais ? also called the blue alarm). taos is commanded by writing a 1 to bit cr2.etaos. both taos and local loopback can occur simultaneously as shown in figure 4 , however, remote loopback inhibits taos. when both taos and lloop are active, tclk and tpos/tneg loop back to rclk and rpos/rneg through the jitter attenuator (if enabled), and an all ones pattern goes to ttip/tring. 2.5.2.2 quasi-random signal source (qrss) see figure 10 . the quasi-random signal source (qrss) is a 2 20 -1 pseudo-random bit sequence (prbs) with no more than 14 consecutive zeros. setting bits cr2.epat0 = 0 and cr2.epat1 = 1 enables this function. the qrss pattern is normally locked to tclk; but if there is no tclk, mclk is the clock source. bellcore pub 62411 defines the t1 qrss transmit format. figure 9. taos data path ttip rtip tring rring taos *ifenabled encoder* decoder* tclk rclk tpos rpos tneg rneg timing & control timing recovery figure 10. qrss mode int*
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 21 with qrss transmission enabled, it is possible to insert a logic error into the transmit data stream by causing a low-to-high transition on insler. however, if no logic or bit errors are to be inserted into the qrss pattern, insler must remain low. logic error insertion waits until the next bit if the current bit is ? jammed ? . when there are more than 14 consecutive 0s, the output is jammed to a 1. furthermore, a bipolar violation in the qrss pattern is possible by causing a low-to-high transition on the insbpv pin, regardless of whether the device is in bipolar or unipolar mode. choosing qrss mode also enables the qrss pattern detection in the receive path. the qrss pattern is synchronized when there are fewer than four errors in 128 bits. the psr.qrss bit provides an indication of qrss pattern synchronization. this bit goes low when no qrss pattern detected ( i . e ., when there are more than four errors in 128 bits). the tqrss bit in the transition status register indicates that qrss status has changed since the last qrss interrupt clear command. the lxt363 can generate an interrupt to indicate that qrss detection has occurred, or that synchronization is lost. the interrupt is enabled when icr.cqrss = 0. 2.5.2.3 in-band network loop up or down code generator the lxt363 can transmit in-band network loop up or loop down code. the loop up code is 00001; loop down code is 001. a loop up code transmission occurs when control register #2 bits epat0 = 1 and epat1 = 0. a loop down code transmission requires that both epat0 and epat1 = 1. with this mode enabled, logic errors and bipolar violations can be inserted into the transmit data stream. inserting a logic error requires a low-to-high transition in insler (pin 3). if no logic or bit errors are to be inserted, insler must remain low. inserting a bipolar violation requires a low-to-high transition on the insbpv pin, regardless of unipolar or bipolar operation. 2.5.3 error insertion and detection 2.5.3.1 bipolar violation insertion (insbpv) bipolar violation insertion is available in unipolar mode. choosing unipolar mode configures the insbpv pin. to insert bipolar violation (bpv), a low-to-high transition on the insbpv is required. sampling occurs on the falling edge of tclk. when insbpv goes high a bpv is inserted on the next available mark except in the four following situations: zero suppression (b8zs) is not violated if lloop and taos are both active, the bpv is looped back to rneg/bpv indicator and the line driver transmits all ones with no violation bpv insertion is disabled with rloop active bpv insertion is disabled when nloop is active with the lxt363 configured to transmit internally generated data patterns (qrss or nloop), a bpv can be inserted into the transmit pattern regardless of whether the device is in the unipolar or bipolar mode of operation.
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 22 datasheet 2.5.3.2 logic error insertion (insler) when configured to transmit internally generated data patterns (qrss or nloop up/down codes), a logic error is inserted into the transmit data pattern when the insler pin transitions low-to-high. note that in qrss mode, there is no logic error insertion on a jammed bit (i.e., a bit forced to one to suppress transmission of more than 14 consecutive zeros). the transceiver routes data patterns the same way it routes data applied to tpos/tneg. therefore, the inserted logic error will follow the data flow path of the active loopback mode. 2.5.3.3 bipolar violation detection (bpv) when the internal encoders/decoders are disabled or when configured in unipolar mode, bipolar violations are reported at the bpv pin. bpv goes high for a full clock cycle to indicate receipt of a bpv. when the encoders/decoders are enabled, the lxt363 does not report bipolar violations due to the line coding scheme. 2.5.4 alarm condition monitoring 2.5.4.1 loss of signal the receiver los monitor loads a digital counter at the rclk frequency. the count increments with each received 0 and the counter resets to 0 on receipt of a 1. when the count reaches ? n ? 0s, bit psr.los is set to ? 1 ? , and the mclk replaces the recovered clock at the rclk output in a smooth transition. ? n ? can be set to either 175 or 2048 with bit cr4.los2048. when the received signal has 12.5% 1s (16 marks in a sliding 128-bit period, with fewer than 100 consecutive 0s), bit psr.los = 0 and the recovered clock replaces mclk at the rclk output in another smooth transition. during los, the device sends received data to the rpos/rneg pins (or rdata in unipolar mode). bit psr.los = 1 indicates a los condition, and can generate an interrupt if enabled. 2.5.4.2 alarm indication signal detection the receiver detects an ais pattern when it receives fewer than three 0s in any string of 2048 bits. the device clears the ais condition when it receives three or more 0s in a string of 2048 bits. the ais bit in the performance status register indicates ais detection. whenever the ais status changes, bit tsr.tais =1. unless masked, a change of ais status generates an interrupt. 2.5.4.3 driver failure open mode the dfm open (dfmo) bit is available in the performance status register to indicate an open condition on the lines. dfmo can generate an int to the host controller. the transition status register bit tdfmo indicates a transition in the status of the bit. writing a 1 to icr.cdfmo will clear or mask the interrupt.
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 23 2.5.4.4 elastic store overflow/underflow when the bit count in the elastic store (es) is within two bits of overflowing or underflowing the es adjusts the output clock by 1 / 8 of a bit period. the es provides an indication of overflow and underflow via bits trs.esovr and tsr.esunf. these are sticky bits and will stay set to 1 until the host controller reads the register. these interrupts can be cleared or masked by writing a 1 to the bits icr.ceso and icr.cesu, respectively. 2.5.5 other diagnostic reports 2.5.5.1 receive line attenuation indication the equalizer status register (esr) provides an approximation of the line attenuation encountered by the device. the four most significant bits of the register (esr.latn7:4) indicate line attenuation in approximately 2.9 db steps of the receive equalizer. for instance, if esr.latn7:4 is 10 (decimal), then the receiver is seeing a signal attenuated by approximately 29 db (2.9 db x 10) of cable loss. 2.5.5.2 built-in self test lxt363 provides a built-in self test (bist) capability. the bist exercises the internal circuits by providing an internal qrss pattern, running it through the encoders and the transmit drivers then looping it back through the receive equalizer, jitter attenuator and decoders to the qrss pattern detection circuitry. if all the blocks in this data path function correctly, the receive pattern detector locks onto the pattern. it then pulls int low and sets the following bits: tsr.tqrss = 1 psr.qrss = 1 psr.bist = 1 the most reliable test will result when a separate tclk and mclk are applied and the line build-out (lbo) is set to -22.5 db (cr1.ec4:1 = 011x). 2.6 parallel microprocessor interface the lxt363 multiplexed address/data bus and timing/control signals are compatible with both the intel and motorola microprocessors. see figure 15 and figure 16 for the i/o timing diagram for each bus. the lxt363 detects and distinguishes between intel and motorola timing and then automatically selects the appropriate bus timing. the maximum recommended processor speed for an intel device is 20 mhz; for a motorola device, 16.78 mhz. see ? test specifications ? on page 33 for microprocessor interface timing details. the lxt363 contains five read/write and three read-only registers for control and status purposes. table 6 on page 25 is a summary of the registers. table 7 through table 15 identify and explain the function of the register bits.
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 24 datasheet 2.6.1 interrupt handling the lxt363 provides a latched interrupt output pin (int ). when enabled, a change in any of the performance status register bits will generate an interrupt. an interrupt can also be generated when the elastic store overflows (tsr.esovr) or underflows (tsr.esunf). when an interrupt occurs, the int output pin is pulled low. note that the output stage of the int pin has internal pull-down only. therefore, each device that shares the int line requires an external pull-up resistor . the interrupt is cleared when the interrupt condition no longer exists, and the host processor writes a 1 to the respective interrupt causing bit(s) in the interrupt clear register (icr). leaving a 1 in any of the icr bits masks that interrupt. to re-enable an interrupt bit, write a 0.
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 25 3.0 register definitions the lxt363 contains five read/write and three read-only registers. table 5 lists the lxt363 register addresses. note that only bits a6 through a1 of the address byte are valid; the address decoder ignores bits a7 and a0. table 6 identifies the name of each register bit. table 7 through table 15 describe the function of the bits in each register. note that upon power-up or reset, all registers are cleared to 0. table 5. register addresses register address 1 a7 - a0 name abbr control #1 cr1 x010000x control #2 cr2 x010001x control #3 cr3 x010010x interrupt clear icr x010011x transition status tsr x010100x performance status psr x010101x equalizer status esr x010110x control #4 cr4 x010111x 1. x = don ? t care table 6. register and bit summary register bit nametype76543210 control #1 cr1 r/w jasel1 jasel0 encenb unienb ec4 ec3 ec2 ec1 control #2 cr2 r/w reset epat1 epat0 etaos enloop ealoop elloop erloop control #3 cr3 r/w ja6hz pclke sbist eqzmon reserved 1 es64 escen esjam interrupt clear icr r/w cesu ceso cdfmo reserved 2 cqrss cais cnloop clos transition status tsr r esunf esovr tdfmo reserved 1 tqrss tais tnloop tlos performance status psr r reserved 1 bist dfmo reserved 1 qrss ais nloop los equalizer status esr r latn7 latn6 latn5 latn4 reserved 1 reserved 1 reserved 1 reserved 1 control #4 cr4 r/w reserved 1 reserved 1 reserved 1 reserved 1 reserved 1 los2048 reserved 1 reserved 1 1. in writable registers, bits labeled reserved should be set to 0 (except as in note 2 below) for normal operation and ignored in read only registers. 2. write a 1 to this bit for normal operation.
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 26 datasheet table 7. control register #1 read/write, address (a7-a0) = x010000x bit name function jitter attenuator jasel0 jasel1 position 0ec1 sets t1 mode and equalizer (see table 8 below for control codes). 1 0 transmit 1ec2 1 1 receive 2ec3 0 x disabled 3ec4 4 unienb 1 = enable unipolar i/o mode and allow insertion/detection of bpvs. 0 = enable bipolar i/o mode 5 encenb 1 = enable b8zs encoders/decoders and force unipolar i/o mode. 0 = disable b8zs encoders/decoders 6 jasel0 select jitter attenuation circuitry position in data path or disables the ja. see right hand section of table for codes. ? 7 jasel1 table 8. equalizer control bit settings control register #1 function pulse cable gain coding 2 ec4 ec3 ec2 ec1 1 0 0 0 0 t1 long haul 0.0 db pulse 100 ? tp 36 db b8zs 0 0 1 0 t1 long haul -7.5 db pulse 100 ? tp 36 db b8zs 0 1 0 0 t1 long haul -15.0 db pulse 100 ? tp 36 db b8zs 0 1 1 0 t1 long haul -22.5 db pulse 100 ? tp 36 db b8zs 0 0 0 1 t1 long haul 0.0 db pulse 100 ? tp 26 db b8zs 0 0 1 1 t1 long haul -7.5 db pulse 100 ? tp 26 db b8zs 0 1 0 1 t1 long haul -15.0 db pulse 100 ? tp 26 db b8zs 0 1 1 1 t1 long haul -22.5 db pulse 100 ? tp 26 db b8zs 1 0 0 1 d4 short haul 6 v pulse 100 ? tp 12 db b8zs 1 0 1 1 t1 short haul 0-133 ft / 0.6 db 100 ? tp 12 db b8zs 1 1 0 0 t1 short haul 133-266 ft / 1.2 db 100 ? tp 12 db b8zs 1 1 0 1 t1 short haul 266-399 ft / 1.8 db 100 ? tp 12 db b8zs 1 1 1 0 t1 short haul 399-533 ft / 2.4 db 100 ? tp 12 db b8zs 1 1 1 1 t1 short haul 533-655 ft / 3.0 db 100 ? tp 12 db b8zs 1. ec1 sets the receive equalizer gain (egl) during t1 long-haul operation. 2. when enabled.
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 27 table 9. control register #2 read/write, address (a7-a0) = x010001x bit name function pattern epat0 epat1 selected 0erloop 1 1 = enable remote loopback mode 0 = disable remote loopback mode 0 0 transmit tpos/tneg 1 elloop 1 1 = enable local loopback mode 0 = disable local loopback mode 0 1 detect and transmit qrss 2 ealoop 1 = enable analog loopback mode 0 = disable analog loopback mode 10 in-band loop up code 00001 3enloop 1 = enable network loopback detection 0 = disable network loopback detection 11 in-band loop down code 001 4etaos 1 = enable transmit all ones 0 = disable transmit all ones 5epat0 selects internal data pattern transmission. see right hand section of table for codes. ? 6epat1 7 reset 1 = reset device states and clear all registers. 0 = reset complete. 1. to enable dual loopback (dloop), set both erloop = 1 and elloop = 1. table 10. control register #3 read/write, address (a7-a0) = x010010x bit name description 0 esjam 1 = disable jamming of elastic store read out clock ( 1 / 8 bit-time adjustment for over/underflow). 0 = enable jamming of elastic store read out clock 1escen 1 = center es pointer for a difference of 16 or 32, depending on depth (clears automatically). 0 = centering completed 2es64 1 = set elastic store depth to 64 bits. 0 = set elastic store depth to 32 bits. 3 - reserved ? set to 0 for normal operation. 4eqzmon 1 = configure receiver equalizer for monitor mode application (dsx-1 monitor). 0 = configure receiver equalizer for normal mode application 5 sbist 1 = start built-in self test. 0 = built-in self test complete. 6plcke 0 = rpos/rneg valid on the rising edge of rclk. 1 = rpos/rneg valid on the falling edge of rclk. 7ja6hz 1 = set bandwidth of jitter attenuation loop to 6 hz. 0 = set bandwidth of jitter attenuation loop to 3 hz.
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 28 datasheet table 11. interrupt clear register read/write, address (a7-a0) = x010011x bit name function 1 0clos 1 = clear/mask loss of signal interrupt. 0 = enable loss of signal interrupt. 1 cnloop 1 = clear/mask network loopback interrupt. 0 = enable network loopback interrupt. 2cais 1 = clear/mask alarm indication signal interrupt. 0 = enable alarm indication signal interrupt. 3cqrss 1 = clear/mask quasi-random signal source interrupt. 0 = enable quasi-random signal source interrupt. 4 - reserved ? set to 1 for normal operation. 5 cdfmo 1 = clear/mask driver failure monitor open interrupt. 0 = enable driver failure monitor open interrupt. 6 ceso 1 = clear/mask elastic store overflow interrupt. 0 = enable elastic store overflow interrupt. 7cesu 1 = clear/mask elastic store underflow interrupt. 0 = enable elastic store underflow interrupt. 1. leaving a 1 of in any of these bits masks the associated interrupt. table 12. transition status register read only, address (a7-a0) = x010100x bit name function 0tlos 1 = loss of signal (los) has changed since last clear los interrupt occurred. 0 = no change in status. 1 tnloop 1 = nloop has changed since last clear nloop interrupt occurred. 0 = no change in status. 2tais 1 = ais has changed since last clear ais interrupt occurred. 0 = no change in status. 3tqrss 1 = qrss has changed since last clear qrss interrupt occurred 1 . 0 = no change in status. 4 - reserved-ignore. 5tdfmo 1 = dfmo has changed since last clear dfms interrupt occurred. 0 = no change in status. 6esovr 1 = es overflow status sticky bit 2 . 0 = no change in status. 7 esunf 1 = es underflow status sticky bit 2 . 0 = no change in status. 1. a qrss transition indicates receive qrss pattern sync or loss. a simple error in qrss pattern is not reported as a transition. 2. tripping the overflow or underflow indicator in the es sets the esovr/esunf status bit(s). reading the transition status register clears these bits. setting ceso and cesu in the interrupt clear register masks these interrupts.
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 29 table 13. performance status register read only, address (a7-a0) = x010101x bit name function 0los 1 = loss of signal occurred. 0 = loss of signal did not occur. 1 nloop 1 = network loopback active. 0 = network loopback not active. 2ais 1 = alarm indicator signal detected. 0 = alarm indicator signal not detected. 3qrss 1 = quasi-random signal source pattern detected. 0 = quasi-random signal source pattern not detected. 4 - reserved ? ignore. 5dfmo 1 = driver failure monitor open detected. 0 = driver failure monitor open not detected. 6bist 1 = built-in self test passed. 0 = built-in self test did not pass (or was not run). 7 - reserved ? ignore. table 14. equalizer status register read only, address (a7-a0) = x010110x bit name function 0 - reserved ? ignore (least significant bit) 1 - reserved ? ignore 2 - reserved ? ignore 3 - reserved ? ignore 4latn4 receive line attenuation indicators. convert this binary output to a decimal number and multiply by 2.9 db to determine the approximate cable attenuation as seen by the receiver. for example, if latn7-4 = 1010 bin (= 10 dec ), then the receiver is seeing a signal attenuated by approximately 29 db (2.9 db x 10) of cable. this approximation assumes that a 3 v pulse was transmitted. 5latn5 6latn6 7latn7 table 15. control register #4 read/write, address (a7-a0) = x010111x bit name function 0 - reserved ? set to 0 for normal operation; ignore when reading. 1 - reserved ? set to 0 for normal operation; ignore when reading. 2 los2048 1 = set los detection threshold to 2048 consecutive zeros. 0 = set los detection threshold to 175 consecutive zeros. 3 - reserved ? set to 0 for normal operation; ignore when reading. 4 - reserved ? set to 0 for normal operation; ignore when reading. 5 - reserved ? set to 0 for normal operation; ignore when reading. 6 - reserved ? set to 0 for normal operation; ignore when reading. 7 - reserved ? set to 0 for normal operation; ignore when reading.
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 30 datasheet 4.0 application information 4.1 transmit return loss table 16 shows the transmit return loss values for t1 applications. table 22 on page 34 specifies the receive return loss values. 4.2 transformer data specifications for transformers are listed in table 17 . a list of transformers recommended for use with the lxt363 are specified in table 18 . 4.3 application circuits figure 11 shows a typical lxt363 applications for hardware and host modes of operation. table 16. transmit return loss ec4:1 xfrmr/rt r l ( ? ) c l (pf) return loss (db) refer to table 8 1:2 / 9.1 ? 100 016 470 17 1:1.15 1 / 0 ? 100 02 470 2 1001 (d4 mode) 1:2 2 / 0 ? 100 01 470 1 1. a 1:1.15 transmit transformer keeps the total transceiver power dissipation at a low level, a 0.47 f dc blocking capacitor must be placed on ttip or tring. 2. a 0.47 f dc blocking capacitor must be placed on ttip or tring. table 17. transformer specifications for lxt363 tx/rx frequency mhz turns ratio primary inductance h (minimum) leakage inductance h (max) interwinding capacitance pf (max) dcr ? (maximum) dielectric breakdown v (minimum) tx 1.544 1:1.15 600 0.80 60 0.90 pri, 1.70 sec 1500 v rms 1 1.544 1:2 600 0.80 60 0.70 pri, 1.20 sec 1500 v rms 1 rx 1.544 1:1 600 1.10 60 1.10 pri, 1.10 sec 1500 v rms 1 1. some applications require transformers with a center tap (long-haul applications with dc current in the t1 loop).
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 31 figure 11 shows a typical lxt363 application. see table 16 through table 18 to select the transformers (t1 and t2), resistors (rt) and capacitor (c l ). note that if the application includes surge protection, such as a varistor or sidactor on the ttip/ tring lines, it may be necessary to reduce the value of the capacitor c l or eliminate it completely. excessive capacitance at c l will distort the transmitted signals. table 18. recommended transformers for lxt363 tx/rx turns ratio part number manufacturer tx 1:1.15 pe-65388 pulse engineering pe-65770 16z5952 vitec 1:2 pe-65351 pulse engineering pe-65771 0553-5006-ic bell-fuse 66z-1308 fil-mag 671-5832 midcom 67127370 schott corp 67130850 td61-1205d halo (combination tx/rx set) tg26-1205ni halo (surface mount dual transformer 1ct:2ct & 1ct:2ct) tg48-1205ni halo (surface mount dual transformer 1ct:2ct & 1:1) 16z5946 vitec rx 1:1 fe 8006-155 fil-mag 671-5792 midcom pe-64936 pulse engineering pe-65778 67130840 schott corp 67109510 td61-1205d halo (combination tx/rx set) 16z5936 vitec 16z5934
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 32 datasheet figure 11. typical lxt363 application mclk ttip tring rtip rring tclk tpos tneg tclk tpos tneg rclk rpos rneg rclk rpos rneg t1 framer p (intel or motorola) 1.544 mhz lxt363 68 f 0.1 f ad0-7 int cs wr/r/w rd/ds ale/as vcc 22 k ? tvcc vcc tgnd gnd rt 1 c l 1 (0 to 470 p f rt 1 100 ? 1:1 t1 1 0.47 f 2 notes: 1. see table 16 through table 18 for cl, rt, and transformer selection. 2. optional for power savings.
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 33 5.0 test specifications note: table 19 through table 27 and figure 12 through figure 18 represent the performance specifications of the lxt363 and are guaranteed by test except, where noted, by design. the minimum and maximum values listed in table 21 through table 27 are guaranteed over the recommended operating conditions specified in table 20 . table 19. absolute maximum ratings parameter sym min max unit dc supply (reference to gnd) v cc , tv cc ? 6.0 v input voltage, any pin 1 v in gnd - 0.3 v v cc + 0.3 v v input current, any pin 2 i in - 10 10 ma storage temperature t stg -65 150 c caution: exceeding these values may cause permanent damage. caution: functional operation under these conditions is not implied. caution: exposure to maximum rating conditions for extended periods may affect device reliability. 1. tvcc and vcc must not differ by more than 0.3 v during operation. tgnd and gnd must not differ by more than 0.3 v during operation. 2. transient currents of up to 100 ma will not cause scr latch-up. ttip, tring, tvcc, and tgnd can withstand continuous currents of up to 100 ma. table 20. recommended operating conditions parameter sym min typ 1 max unit test conditions dc supply 2 v cc , tv cc 4.75 5.0 5.25 v ambient operating temperature t a -40 ? 85 c to t a l power dissipation 3 short haul p d ? 450 540 mw 100% mark density p d ? 300 360 mw 50% mark density long haul p d ? 350 425 mw 100% mark density p d ? 250 300 mw 50% mark density d4 p d ? 400 485 mw 100% mark density p d ? 275 330 mw 50% mark density 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. tvcc and vcc must not differ by more than 0.3 v. 3. power dissipation while driving 100 ? load over operating range. includes power dissipation on device and load. digital levels are within 10% of the supply rails and digital outputs driving a 50 pf capacity load, r l =9.1, t1=1:2.
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 34 datasheet table 21. digital characteristics parameter sym min typ max unit test conditions high level input voltage (pins 1-5, 9-12, 17, 23-28) 2 v ih 2.0 ?? v low level input voltage (pins 1-5, 9-12, 17, 23-28) 2 v il ?? 0.8 v high level output voltage 1 (pins 6-8, 10, 11,23, 28) 2 v oh 2.4 ?? vi out = 400 a low level output voltage 1 (pins 6-8, 10, 11,23, 28) 2 v ol ?? 0.4 v i out = 1.6 ma input leakage current i ll ?? 50 a 1. output drivers will output cmos logic levels into cmos loads. 2. referenced pin numbers are for the plcc package. refer to figure 2 on page 8 for the corresponding qfp pins. table 22. analog characteristics parameter min typ 1 max unit test conditions recommended output load on ttip/tring 50 ? 200 ? ami output pulse amplitudes dsx-1, ds1 2.4 3.0 3.6 v r l = 100 ? jitter added by the transmitter 2 10 hz - 8 khz 3 ?? 0.02 ui 8 khz - 40 khz 3 ?? 0.025 ui 10 hz - 40 khz 3 ?? 0.025 ui broad band ?? 0.05 ui receiver sensitivity @ 772 khz mode 1 (ec1 = 1) (long-haul) 0 ? 26 db see table 8 on page 26 for gain setting mode 2 (ec1 = 0) (long-haul) 0 ? 36 db mode 3 (ec4 = 1) (short-haul) 0 ? 13.6 db allowable consecutive zeros before los 160 175 190 ? input jitter tolerance 10 khz - 100 khz 0.4 ?? ui 0 db line at&t pub 62411 1 hz 3 138 ?? ui jitter attenuation curve corner frequency 4 ? 3 ? hz selectable in data port 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. input signal to tclk is jitter-free. the jitter attenuator is in the receive path or disabled. 3. guaranteed by characterization; not subject to production testing. 4. circuit attenuates jitter at 20 db/decade above the corner frequency.
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 35 figure 12. 1.544 mhz t1 pulse (ds1 and dsx-1) (see table 23 ) table 23. 1.544 mhz t1 pulse mask corner point specifications ds1 template (per ansi t1. 403-1995) dsx-1 template (per ansi t1. 102-1993) minimum curve maximum curve minimum curve maximum curve time (ui) amplitude time (ui) amplitude time (ui) amplitude time (ui) amplitude -0.77 -0.05 -0.77 0.05 -0.77 -0.05 -0.77 0.05 -0.23 -0.05 -0.39 0.05 -0.23 -0.05 -0.39 0.05 -0.23 0.50 -0.27 0.80 -0.23 0.50 -0.27 0.80 -0.15 0.90 -0.27 1.20 -0.15 0.95 -0.27 1.15 0.0 0.95 -0.12 1.20 0.0 0.95 -0.12 1.15 0.15 0.90 0.0 1.05 0.15 0.90 0.0 1.05 0.23 0.50 0.27 1.05 0.23 0.50 0.27 1.05 0.23 -0.45 0.34 -0.05 0.23 -0.45 0.35 -0.07 0.46 -0.45 0.77 0.05 0.46 -0.45 0.93 0.05 0.61 -0.26 1.16 0.05 0.66 -0.20 1.16 0.05 0.93 -0.05 0.93 -0.05 1.16 -0.05 1.16 -0.05 table 24. master and transmit clock timing characteristics (see figure 13 ) parameter sym min typ 1 max unit notes master clock frequency mclk ? 1.544 ? mhz must be supplied master clock tolerance mclkt ? 50 ? ppm master clock duty cycle mclkd 40 ? 60 % transmit clock frequency tclk ? 1.544 ? mhz transmit clock tolerance tclkt ?? 100 ppm 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. time (in unit intervals) 0.5 1.0 1.5 -0.5 normalized amplitude 0.0 0.5 1.0 1.5 -0.5 1.5 time (in unit intervals) 0.5 1.0 -0.5 normalized amplitude 0.0 0.5 1.0 1.5 -0.5
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 36 datasheet transmit clock duty cycle tclkd 10 ? 90 % tpos/tneg to tclk setup time t sut 50 ?? ns tclk to tpos/tneg hold time t ht 50 ?? ns figure 13. transmit clock timing table 25. receive timing characteristics (see figure 14 ) parameter sym min typ 1 max unit receive clock duty cycle 2, 3 rlckd 40 50 60 % receive clock pulse width 2, 3 t pw ? 648 ? ns receive clock pulse width high t pwh ? 324 ? ns receive clock pulse width low 1,3 t pwl 260 324 388 ns rpos/rneg to rclk rising time t sur ? 274 ? ns rclk rising to rpos/rneg hold time t hr ? 274 ? ns 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. rclk duty cycle widths will vary according to extent of received pulse jitter displacement. max and min rclk duty cycles are for worst case jitter conditions. 3. worst case conditions guaranteed by design only. table 24. master and transmit clock timing characteristics (see figure 13 ) parameter sym min typ 1 max unit notes 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 37 figure 14. receive clock timing table 26. lxt363 20 mhz intel bus parallel i/o timing characteristics (see figure 15 ) parameter sym min max unit test conditions ale pulse width t lhll 35 ? ns address valid to ale falling edge t avll 10 ? ns ale falling edge to address hold time t llax 10 ? ns ale falling edge to rd falling edge t llrl 10 ? ns ale falling edge to wr falling edge t llwl 10 ? ns cs falling edge to rd falling edge t clrl 10 ? ns cs falling edge to wr falling edge t clwl 10 ? ns rd low pulse width t rlrh 95 ? ns rd falling edge to data valid t rldv 10 55 ns data hold time after rd rising edge t rhdx 535ns rd rising edge to ale rising edge t rhlh 15 ? ns rd rising edge to address valid t rhav 35 ? ns cs low hold time after rd rising edge t rhch 0 ? ns wr low pulse width t wlwh 95 ? ns data setup time before wr rising edge t dvwh 40 ? ns data hold time after wr rising edge t whdx 30 ? ns wr rising edge to ale rising edge t whlh 15 ? ns cs low hold time after wr rising edge t whch 15 ? ns
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 38 datasheet figure 15. lxt363 i/o timing diagram for intel address/data bus table 27. lxt363 16.78 mhz motorola bus parallel i/o timing characteristics (see figure 16 ) parameter symbol min max units test conditions ds rising edge to as rising edge t dshash 15 ? ns as high pulse width t ashasl 35 ? ns address valid setup time at as falling edge t avasl 10 ? ns as falling edge to address valid hold time taslax 10 ? ns as falling edge to ds falling edge t asldsl 20 ? ns cs falling edge to ds falling edge t csldsl 10 ? ns ds low pulse width t dsldsh 95 ? ns ds falling edge to data valid t dsldv 10 55 ns data hold time after ds rising edge t dshdx 535ns r/w falling edge to ds falling edge t rwldsl 10 ? ns data setup time before ds rising edge t dvdsh 40 ? ns data hold time after ds rising edge tdxdsh 30 ? ns r/w low hold time after ds rising edge t dshrwh 15 ? ns cs low hold time after ds rising edge t dshcsh 15 ? ns t clrl t clwl t rhch t whch t lhll t avll t llax t llrl t llwl t rhlh t whlh t rlrh t rhav t wlwh t dvwh t whdx t rldv t rhdx cs ale rd ad0-7_r wr ad0-7_w
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 39 figure 16. lxt363 i/o timing diagram for motorola address/data bus figure 17. typical t1 jitter tolerance at 36 db t dxdsh t csldsl t dshcsh t avasl t aslax t asldsl t dshash t dsldsh t rwldsl t dvdsh t dshrwh t dsldv t dshdx cs as ds r/w _read ad0-7_read r/w _write ad0-7_write t ashasl 1hz 10hz 100hz 1khz 10khz 100khz .1 ui 1ui 10 ui 100 ui 1000 ui 138 ui 0.4 ui 28 ui pub 62411 0.6 ui @10khz 500 ui @10hz jitter typical jitter tolerance loop mode dec 1990 lxt363 device frequency
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 40 datasheet figure 18. t1 jitter attenuation
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 41 6.0 mechanical specifications figure 19. plastic leaded chip carrier package specifications a 2 a d f a 1 c b d 1 d c l dim inches millimeters min max min max a 0.165 0.180 4.191 4.572 a1 0.090 0.120 2.286 3.048 a2 0.062 0.083 1.575 2.108 b .050 bsc 1 (nominal) 1.27 bsc 1 (nominal) c 0.026 0.032 0.660 0.813 d 0.485 0.495 12.319 12.573 d1 0.450 0.456 11.430 11.582 f 0.013 0.021 0.330 0.533 1. bsc ? basic spacing between centers. 28-pin plcc part number lxt363pe extended temperature range (-40 c to 85 c)
lxt363 ? integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications 42 datasheet figure 20. plastic quad flat package specifications a 1 a 2 l a b l 1 d d 1 e d 3 e 1 e 3 3 3 e 44-pin pqfp part number LXT363QE extended temperature range (-40 c to 85 c) dim inches millimeters min max min max a ? 0.096 ? 2.45 a1 0.010 ? 0.25 ? a2 0.077 0.083 1.95 2.10 b 0.012 0.018 0.30 0.45 d 0.510 0.530 12.95 13.45 d1 0.390 0.398 9.90 10.10 d3 0.315 bsc 1 (nominal) 8.00 bsc 1 (nominal) e 0.510 0.530 12.95 13.45 e1 0.390 0.398 9.90 10.10 e3 0.315 bsc 1 (nominal) 8.00 bsc 1 (nominal) e 0.031 bsc 1 (nominal) 0.80 bsc 1 (nominal) l 0.029 0.041 0.73 1.03 l1 0.063 bsc 1 (nominal) 1.60 bsc 1 (nominal) q3 5 16 5 16 q0 7 0 7 1. bsc ? basic spacing between centers.
integrated t1 lh/sh transceiver for ds1/dsx-1 or pri applications ? lxt363 datasheet 43 figure 21. low-profile quad flat package specifications d d/2 e1 e1/2 e e/2 d1 d1/2 note: all dimensions in millimeters. a a1 a2 l 1.00 ref. 0.20 min. 0 - 7 deg. 0.08 / 0.20 r. 0.08 r. min. 0 deg. min. e/2 m b e 44-pin lqfp part number lxt363le extended temperature range (-40 c to 85 c) dimension 1 millimeters minimum nominal maximum a--1.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 b 0.300.370.45 d 12.00 (basic spacing between centers) d1 10.00 (basic spacing between centers) e 12.00 (basic spacing between centers) e1 10.00 (basic spacing between centers) e 0.80 (basic spacing between centers) l 0.450.600.75 m0.15- - 1. see jedec publication for additional specifications.

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