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utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1 ? revision history revision description date preliminary rev. 0.1 original may 4,2001 rev. 1.0 sample ready and release jul 16,2001 rev. 1.1 1.add 28-pin 8x20 mm tsop-i 2.add 28l 8x20mm tsop-i outline dimension jul 16,2002 rev. 1.2 add order information for lead free product may 13,2003
utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2 ? features fast access time : 35/70ns (max.) low power consumption: operating current : 40/20 ma (max) standby current : 1 a (typical) l-version 0.5 a(typical) ll-version single 2.7v ~ 3.6v power supply all inputs and outputs ttl compatible fully static operation three state outputs data retention voltage : 1.5v (min.) package : 28-pin 600 mil pdip 28-pin 330 mil sop 28-pin 8x13.4mm stsop 28-pin 8x20 mm tsop-i general description the UT62L256C is a 262,144-bit low power cmos static random access memory organized as 32,768 words by 8 bits. it is fabricated using high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the UT62L256C is designed for high-speed and low power application. it is particularly well suited for battery back-up nonvolatile memory application. the UT62L256C operates from a single 2.7v ~ 3.6v power supply and all inputs and outputs are fully ttl compatible functional block diagram decoder i/o data circuit control circuit 32k ?? 8 memory array column i/o oe we a0-a14 vcc vss i/o1-i/o8 ce utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3 ? pin configuration a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 vcc a8 a9 a11 a10 i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 vss UT62L256C pdip/sop 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 ce we oe a13 a14 stsop/tsop-i i/o4 a11 a9 a8 a13 i/o3 a10 a14 a12 a7 a6 a5 vcc i/o8 i/o7 i/o6 i/o5 vss i/o2 i/o1 a0 a1 a2 a4 a3 UT62L256C 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 we oe ce pin description symbol description a0 - a14 address inputs i/o1 - i/o8 data inputs/outputs ce chip enable input we write enable input oe output enable input v cc power supply v ss ground utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4 ? absolute maximum ratings * parameter symbol rating unit terminal voltage with respect to v ss v term -0.5 to 4.5 v operating temperature t a 0 to 70 j storage temperature t stg -65 to 150 j power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 sec) tsolder 260 j *stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating only and functional operation of the dev ice or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliabil ity. truth table mode ce oe we i/o operation supply current standby h x x high - z i sb , i sb1 output disable l h h high - z i cc, i cc1, i cc2 read l l h d out i cc, i cc1, i cc2 write l x l d in i cc, i cc1, i cc2 note: h = v ih , l=v il , x = don't care. dc electrical characteristics (v cc = 2.7v ~ 3.6v, t a = 0 j to 70 j ) parameter symbol test condition min. typ. max. unit input high voltage v ih *1 2.0 - v cc +0.5 v input low voltage v il *2 - 0.5 - 0.6 v input leakage curren t i li v ss ?? v in ?? v cc - 1 - 1 a output leakage current i lo v ss ?? v i/o ?? v cc ce =v ih or oe = v ih or we = v il - 1 - 1 a output high voltage v oh i oh = - 1ma 2.4 - - v output low voltage v ol i ol = 4ma - - 0.4 v - 35 - - 40 ma i cc cycle time=min., ce = v il ,i i/o = 0ma , - 70 - - 20 ma icc1 cycle time=1us ce =0.2v; i i/o = 0ma other pins at 0.2v or vcc-0.2v; - - 6 ma average operating power supply current icc2 cycle time=500ns ce =0.2v; i i/o = 0ma other pins at 0.2v or vcc-0.2v - - 12 ma i sb ce =v ih - - 3 ma standby power supply current i sb1 ce ? v cc -0.2v -l - 1 40 a -ll - 0.5 20 a notes: 1. overshoot : vcc+3.0v fo r pulse width less than 10ns. 2. undershoot : vss-3.0v fo r pulse width less than 10ns. 3. overshoot and undershoot ar e sampled, not 100% tested. utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5 ? capacitance (t a =25 j , f=1.0mhz) parameter symbol min. max unit input capacitance c in - 8 pf input/output capacitance c i/o - 10 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0v to 3.0v input rise and fall times 5ns input and output timing reference levels 1.5v output load c l = 100pf, i oh /i ol = -1ma/4ma ac electrical characteristics (v cc = 2.7v~3.6v , t a = 0 j to 70 j ) (1) read cycle parameter symbol UT62L256C-35 UT62L256C-70 unit min. max. min. max. read cycle time t rc 35 - 70 - ns address access time t aa - 35 - 70 ns chip enable access time t ace - 35 - 70 ns output enable access time t oe - 25 - 35 ns chip enable to output in low z t clz* 10 - 10 - ns output enable to output in low z t olz* 5 - 5 - ns chip disable to output in high z t chz* - 25 - 35 ns output disable to output in high z t ohz* - 25 - 35 ns output hold from address change t oh 5 - 5 - ns (2) write cycle parameter symbol UT62L256C-35 UT62L256C-70 unit min. max. min. max. write cycle time t wc 35 - 70 - ns address valid to end of write t aw 30 - 60 - ns chip enable to end of write t cw 30 - 60 - ns address set-up time t as 0 - 0 - ns write pulse width t wp 25 - 50 - ns write recovery time t wr 0 - 0 - ns data to write time overlap t dw 20 - 30 - ns data hold from end of write time t dh 0 - 0 - ns output active from end of write t ow* 5 - 5 - ns write to output in high z t whz* - 15 - 25 ns *these parameters are guaranteed by device char acterization, but not production tested. utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6 ? timing waveforms read cycle 1 (address controlled) (1,2) t rc t aa data valid address dout t oh t oh previous data valid read cycle 2 ( ce and oe controlled) (1,3,4,5) t rc t aa t ace t oe t ohz t clz t oh t olz high-z data valid high-z t chz address dout ce oe notes : 1. we is high for read cycle. 2.device is continuously selected oe =low, ce =low . 3.address must be valid prior to or coincident with ce =low , ; otherwise t aa is the limiting parameter. 4.t clz , t olz , t chz and t ohz are specified with c l =5pf. transition is measured ? 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz . utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7 ? write cycle 1 ( we controlled) (1,2,3,5,6) t wc t aw t cw t as t wp t whz t ow t wr high-z (4) (4) address ce we dout din data valid t dw t dh write cycle 2 ( ce controlled) (1,2,5,6) t wc t aw t cw t as t wr t wp t whz t dw t dh data valid high-z (4) address ce we dout din utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8 ? notes : 1. we , ce must be high during all address transitions. 2.a write occurs during the overlap of a low ce , low we . 3.during a we controlled write cycle with oe low, t wp must be greater than t whz +t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce low transition occurs simultaneously with or after we low transition, the outputs remain in a high impedance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured ? 500mv from steady state. data retention characteristics (t a = 0 j to 70 j ) parameter symbol test condition min. typ. max. unit vcc for data retention v dr ce ? v cc -0.2v 1.5 - 3.6 v data retention current i dr vcc=2.5v - l - 1 20 a ce ? v cc -0.2v - ll - 0.5 10 a chip disable to data t cdr see data retention 0 - - ns retention time waveforms (below) recovery time t r t rc* - - ns t rc* = read cycle time data retention waveform v dr ? 1.5v ce ? v cc -0.2v v cc(min.) v cc(min.) v ih v ih v cc t r t cdr ce utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9 ? package outline dimension 28 pin 600 mil pdip package outline dimension unit symbol inch(base) mm(ref) a1 0.010 (min) 0.254 (min) a2 0.150 ? 0.005 3.810 ? 0.127 b 0.020 (max) 0.508(max) b1 0.055 (max) 1.397(max) c 0.012 (max) 0.304 (max) d 1.430 (max) 36.322 (max) e 0.6 (typ) 15.24 (typ) e1 0.52 (max) 13.208 (max) e 0.100 (typ) 2.540(typ) eb 0.625 (max) 15.87 (max) l 0.180(max) 4.572(max) s 0.06 (max) 1.524 (max) q1 0.08(max) 2.032(max) k 15 o (max) 15 o (max) utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10 ? 28 pin 330 mil sop package outline dimension unit symbol inch(base) mm(ref) a 0.120 (max) 3.048 (max) a1 0.002(min) 0.05(min) a2 0.098 ? 0.005 2.489 ? 0.127 b 0.0016 (typ) 0.406(typ) c 0.010 (typ) 0.254(typ) d 0.728 (max) 18.491 (max) e 0.340 (max) 8.636 (max) e1 0.465 ? 0.012 11.811 ? 0.305 e 0.050 (typ) 1.270(typ) l 0.05 (max) 1.270 (max) l1 0.067 ? 0.008 1.702 ? 0.203 s 0.047 (max) 1.194 (max) y 0.003(max) 0.076(max) k 0 o ?? 10 o 0 o ?? 10 o utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 11 ? 28 pin 8x13.4mm stsop package outline dimension note ?g e dimension is not including end flash the total of both sides? end flash is not above 0.3mm. unit symbol inch(base) mm(ref) a 0.047 (max) 1.20 (max) a1 0.004 ? 0.002 0.10 ? 0.05 a2 0.039 ? 0.002 1.00 ? 0.05 b 0.006 (typ) 0.15(typ) c 0.010 (typ) 0.254(typ) db 0.465 ? 0.004 11.80 ? 0.10 e 0.315 ? 0.004 8.00 ? 0.10 e 0.022 (typ) 0.55(typ) d 0.528 ? 0.008 13.40 ? 0.20 l 0.020 ? 0.004 0.50 ? 0.10 l1 0.0315 ? 0.004 0.80 ? 0.10 y 0.08(max) 0.003(max) k 0 o ?? 5 o 0 o ?? 5 o utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 12 ? 28 pin 8x20mm tsop-i package outline dimension note ?g e dimension is not including end flash the total of both sides? end flash is not above 0.3mm. unit symbol inch(base) mm(ref) a 0.047 (max) 1.20 (max) a1 0.004 ? 0.002 0.10 ? 0.05 a2 0.039 ? 0.002 1.00 ? 0.05 b 0.008 (typ) 0.20(typ) c 0.008 (typ) 0.15(typ) db 0.465 ? 0.004 11.80 ? 0.10 e 0.315 ? 0.004 8.00 ? 0.10 e 0.022 (typ) 0.55(typ) d 0.528 ? 0.008 13.40 ? 0.20 l 0.020 ? 0.004 0.50 ? 0.10 l1 0.0315 ? 0.004 0.80 ? 0.10 y 0.003(max) 0.08(max) k 0 o ?? 5 o 0 o ?? 5 o utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 13 ? ordering information part no. access time (ns) standby current ( a) typ. package UT62L256Cpc-35l 35 1 a 28pin pdip UT62L256Cpc-35ll 35 0.5 a 28pin pdip UT62L256Cpc-70l 70 1 a 28pin pdip UT62L256Cpc-70ll 70 0.5 a 28pin pdip UT62L256Csc-35l 35 1 a 28pin sop UT62L256Csc-35ll 35 0.5 a 28pin sop UT62L256Csc-70l 70 1 a 28pin sop UT62L256Csc-70ll 70 0.5 a 28pin sop UT62L256Cls-35l 35 1 a 28pin stsop UT62L256Cls-35ll 35 0.5 a 28pin stsop UT62L256Cls-70l 70 1 a 28pin stsop UT62L256Cls-70ll 70 0.5 a 28pin stsop UT62L256Clc-35l 35 1 a 28pin tsop-i UT62L256Clc-35ll 35 0.5 a 28pin tsop-i UT62L256Clc-70l 70 1 a 28pin tsop-i UT62L256Clc-70ll 70 0.5 a 28pin tsop-i ordering information (for lead free product) part no. access time (ns) standby current ( a) typ. package UT62L256Cpcl-35l 35 1 a 28pin pdip UT62L256Cpcl-35ll 35 0.5 a 28pin pdip UT62L256Cpcl-70l 70 1 a 28pin pdip UT62L256Cpcl-70ll 70 0.5 a 28pin pdip UT62L256Cscl-35l 35 1 a 28pin sop UT62L256Cscl-35ll 35 0.5 a 28pin sop UT62L256Cscl-70l 70 1 a 28pin sop UT62L256Cscl-70ll 70 0.5 a 28pin sop UT62L256Clsl-35l 35 1 a 28pin stsop UT62L256Clsl-35ll 35 0.5 a 28pin stsop UT62L256Clsl-70l 70 1 a 28pin stsop UT62L256Clsl-70ll 70 0.5 a 28pin stsop UT62L256Clcl-35l 35 1 a 28pin tsop-i UT62L256Clcl-35ll 35 0.5 a 28pin tsop-i UT62L256Clcl-70l 70 1 a 28pin tsop-i UT62L256Clcl-70ll 70 0.5 a 28pin tsop-i utron UT62L256C rev. 1.2 32k x 8 bit low power cmos sram ___________________________________________________________________________________________________________ utron technology inc. p80057 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 14 ? 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