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? implementation of write allocate in the k86 processors publication # 21326 rev: f amendment/ 0 issue date: february 1999 application note ?
trademarks amd, the amd logo, k6, and combinations thereof, k86, and amd-k5 are trademarks, and amd-k6 is a registered trademark of advanced micro devices, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 1999 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice.
contents iii 21326f/0 february 1999 implementation of write allocate in the k86? processors contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii what is write allocate? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 models 6, 7, and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 model 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 all amd-k6 ? models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 programming details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 step 1: determine processor model and stepping . . . . . . . . . . 3 write allocate support . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 msr format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 step 2: amd-k6 processor models 6, 7 and amd-k6-2 processor model 8/[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 write handling control register (whcr) . . . . . . . . . . . 4 step 2: amd-k6-2 processor model 8/[f:8] and amd-k6-iii processor model 9 . . . . . . . . . . . . . . . . . . . . . . . . . . 6 write handling control register (whcr) . . . . . . . . . . . 6 step 3: amd-k6 processor (all models) . . . . . . . . . . . . . . . . . . 8 amd-k6 processor programming example for write allocate registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 code sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 code sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 case 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 code sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 step 2: amd-k5? processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 step 3: amd-k5 processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 amd-k5 processor programming example for write allocate registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 code sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 code sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
iv contents implementation of write allocate in the k86? processors 21326f/0february 1999
list of figures v 21326f/0 february 1999 implementation of write allocate in the k86? processors list of figures figure 1. write handling control register (whcr) msr c000_0082h (models 6, 7, and 8/[7:0]) . . . . . . . . . . . 4 figure 2. write handling control register (whcr) msr c000_0082h (model 8/[f:8] and model 9). . . . . . . . . 6 figure 3. write allocate top-of-memory and control register (watmcr)msr 85h. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. write allocate programmable memory range register (wapmrr)msr 86h . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. hardware configuration register (hwcr) msr 83h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
vi list of figures implementation of write allocate in the k86? processors 21326f/0february 1999
revision history vii 21326f/0 february 1999 implementation of write allocate in the k86? processors revision history date rev description sept 1997 c modified description of wcde bit in write handling control register (whcr) model-specific register. see pages 4 and 8. may 1998 d switched order of the amd-k6 and amd-k5 information. may 1998 d revised step 1: determine processor model and stepping on page 3. may 1998 d revised step 2: amd-k6 ? processor models 6, 7 and amd-k6-2 processor model 8/[7:0] on page 3. nov 1998 e added step 2: amd-k6 ? -2 processor model 8/[f:8] and amd-k6- iii processor model 9 on page 6. nov 1998 e added case 3 and code sample to amd-k6 ? processor programming example for write allocate registers on page 8. feb 1999 f added models 6, 7, and 8 and model 9 on page 1 and all amd-k6 ? models on page 2. feb 1999 f revised write allocate enable limit and write allocate enable 15-to-16-mbyte paragraphs in both step 2: amd-k6 ? processor models 6, 7 and amd-k6-2 processor model 8/[7:0] and step 2: amd-k6 ? -2 processor model 8/[f:8] and amd-k6- iii processor model 9 . feb 1999 f added amd-k6- iii information to step 2: amd-k6 ? -2 processor model 8/[f:8] and amd-k6- iii processor model 9 on page 6.
viii revision history implementation of write allocate in the k86? processors 21326f/0february 1999
21326f/0 february 1999 implementation of write allocate in the k86? processors what is write allocate? 1 application note implementation of write allocate in the k86 processors what is write allocate? write allocate, if enabled, occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the level-1 (l1) data cache. the behavior of the processor thereafter differs depending on whether the processor model contains a level-2 (l2) cache. the amd-k6 ? processor model 6 and model 7, and the amd-k6-2 processor model 8 do not contain a l2 cache, whereas the amd-k6-iii processor model 9 does contain a l2 cache. models 6, 7, and 8 after the l1 data cache miss, the processor performs a 32-byte burst read cycle on the system bus to fetch the data-cache line addressed by the pending write cycle. the data associated with the pending write cycle is merged with the recently-allocated cache line and stored in the processors l1 data cache. the final mesi (modified, exclusive, shared, invalid) state of the cache line depends on the state of the wb/wt# and pwt signals during the burst read cycle and the subsequent cache write hit. model 9 after the l1 data cache miss, the processor checks for the cache line in the l2 cache. if the line does not exist in the l2 cache, the processor performs a 32-byte burst read cycle on the system bus to fetch the data-cache line addressed by the pending write cycle. if the line does exist in the l2 cache, the data is supplied directly from the l2 cache, in which case a system bus cycle is tm
2 programming details implementation of write allocate in the k86? processors 21326f/0february 1999 not executed. the data associated with the pending write cycle is merged with the recently-allocated data-cache line and stored in the processors l1 data cache. if the data-cache line was fetched from memory (because of an l2 cache miss), the data is stored without modification in the l2 cache. the final mesi state of the cache lines depends on the state of the wb/wt# and pwt signals during the burst read cycle and the subsequent l1 data cache write hit. if the l1 data cache line is stored in the modified state, then the same cache line is stored in the l2 cache in the exclusive state. if the l1 data cache line is stored in the shared state, then the same cache line is stored in the l2 cache in the shared state. all amd-k6 ? models during the write allocation, a 32-byte burst read cycle is executed in place of a non-burst write cycle (in the case of the model 9, this assumes the data-cache line was not present in the l2 cache). while the burst read cycle generally takes longer to execute than the non-burst write cycle, performance gains are realized on subsequent write cycle hits to the write-allocated cache line. due to the nature of software, memory accesses tend to occur within proximity of each other (principle of locality). the likelihood of additional write hits to the write-allocated cache line is high. for the model 9, write allocates that hit the l2 cache increase performance by avoiding accesses to the system bus. programming details the steps required for programming write allocate on k 86? processors are as follows: 1. verify write allocate support by using the cpuid instruction to check for the correct model and stepping of the processor. 2. configure the model-specific registers (msrs). 3. enable write allocate. note: the bios should enable the write allocate mechanisms only after performing any memory sizing or typing algorithms.
programming details 3 21326f/0 february 1999 implementation of write allocate in the k86? processors step 1: determine processor model and stepping the first step in supporting the write allocate feature of the amd k86 processors is determining the model and stepping of the processor. write allocate support write allocate is supported on every stepping for every model of the amd-k6 processor. write allocate in the amd-k5? processor is supported only on the following models with a stepping of 4 or greater: models 1, 2, and 3. use the cpuid instruction to determine if the proper model and stepping of the processor is present. see the amd processor recognition application note , order# 20734 for more information. msr format after determining that the processor supports write allocate, the next step is to configure the corresponding msr that enables write allocate. this msr on the amd-k6 processor is the write handling control register (whcr), which has two formats. amd-k6 processor models 6 and 7 and amd-k6-2 processor model 8 steppings 0 through 7 use the same whcr format. amd-k6-2 processor model 8 steppings 8 through f and amd-k6-iii processor model 9 use a different whcr format. for amd-k6 processors, go to either step 2: amd-k6 ? processor models 6, 7 and amd-k6-2 processor model 8/[7:0] on page 3 or step 2: amd-k6 ? -2 processor model 8/[f:8] and amd-k6-iii processor model 9 on page 6. for an amd-k5 processor models 1, 2, or 3 with a stepping of 4 or greater, go to step 2: amd-k5? processor on page 10. step 2: amd-k6 ? processor models 6, 7 and amd-k6-2 processor model 8/[7:0] the amd-k6 processor uses two mechanisms (programmable within the whcr) to determine when to perform write allocates. a write allocate is performed when either of these mechanisms detects that a pending write is to a cacheable area of memory. before programming the whcr or changing memory cacheability/writeability, the bios must writeback and invalidate the internal cache by using the wbinvd instruction. in addition, the whcr should enable the write allocate
4 programming details implementation of write allocate in the k86? processors 21326f/0february 1999 mechanisms only after performing any memory sizing or typing algorithms. write handling control register (whcr) the whcr c ontains three fieldsthe wcde bit, the write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit (see figure 1). figure 1. write handling control register (whcr)msr c000_0082h (models 6, 7, and 8/[7:0]) wcde. for proper functionality, always program bit 8 of whcr to 0. write allocate enable limit. the waelim field is 7 bits wide. this field, multiplied by 4 mbytes, defines an upper memory limit. any pending write cycle that misses the l1 cache and that addresses memory below this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are disallowed). write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector (for more information, see the cache organization chapter in the amd-k6 ? processor data sheet , order# 20695 or the amd-k6 ? -2 processor data sheet , order# 21850). the maximum value of this limit is ((2 7 C1) 4 mbytes) = 508 mbytes. when all the bits in this field are set to 0, all memory is above this limit and the write allocate mechanism is disabled (even if all bits in the waelim field are set to 0, write allocates can still occur due to the write to a cacheable page and write to a sector mechanisms). 710 63 reserved waelim 8 0 note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits wcde always program to 0 8 waelim write allocate enable limit 7C1 wae15m write allocate enable 15-to-16-mbyte 0 9
programming details 5 21326f/0 february 1999 implementation of write allocate in the k86? processors once the bios determines the amount of ram installed in the system, this number should also be used to program the waelim field. for example, a system with 32 mbytes of ram would program the waelim field with the value 000_1000b. this value (8), when multiplied by 4 mbytes, yields 32 mbytes as the write allocate limit. write allocate enable 15-to-16-mbyte. the wae15m bit is used to enable write allocations for memory write cycles that address the 1 mbyte of memory between 15 mbytes and 16 mbytes. this bit must be set to 1 to allow write allocates in this memory area. this sub-mechanism of the waelim provides a memory hole to prevent write allocates. this memory hole is provided to account for a small number of uncommon memory-mapped i/o adapters that use this particular memory address space. if the system contains one of these peripherals, the bit should be set to 0 (even if the wae15m bit is set to 0, write allocates can still occur between 15 mbytes and 16 mbytes due to the write to a cacheable page and write to a sector mechanisms). the wae15m bit is ignored if the value in the waelim field is set to less than 16 mbytes. by definition, write allocations in the amd-k6 are not performed in the memory area between 640 kbytes and 1 mbyte unless the processor determines a pending write cycle is cacheable by means of write to a cacheable page or write to a sector. it is not safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because it is considered a noncacheable region of memory. to complete programming write allocate on the amd-k6 processor, go to step 3: amd-k6 ? processor (all models) on page 8.
6 programming details implementation of write allocate in the k86? processors 21326f/0february 1999 step 2: amd-k6 ? -2 processor model 8/[f:8] and amd-k6- iii processor model 9 the amd-k6-2 processor and the amd-k6-iii processor use two mechanisms (programmable within the whcr) to determine when to perform write allocates. a write allocate is performed when either of these mechanisms detects that a pending write is to a cacheable area of memory. before programming the whcr or changing memory cacheability/writeability, the bios must writeback and invalidate the internal cache by using the wbinvd instruction. in addition, the whcr should enable the write allocate mechanisms only after performing any memory sizing or typing algorithms. write handling control register (whcr) the whcr contains two fieldsthe write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit (see figure 2). note: the whcr register as defined in the model 6, model 7, and model 8/[7:0] has changed in the model 8/[f:8] and model 9. figure 2. write handling control register (whcr)msr c000_0082h (model 8/[f:8] and model 9) write allocate enable limit. the waelim field is 10 bits wide. this field, multiplied by 4 mbytes, defines an upper memory limit. any pending write cycle that misses the l1 cache and that addresses memory below this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are disallowed). write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by 15 22 0 63 reserved waelim 16 note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits waelim write allocate enable limit 31-22 wae15m write allocate enable 15-to-16-mbyte 16 17 21 31 32
programming details 7 21326f/0 february 1999 implementation of write allocate in the k86? processors means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector (for more information, see the cache organization chapter in the amd-k6 ? -2 processor data sheet , order# 21850 or amd-k6 ? -iii processor data sheet , order# 21918). the maximum value of this limit is ((2 10 C1) 4 mbytes) = 4092 mbytes. when all the bits in this field are set to 0, all memory is above this limit and the write allocate mechanism is disabled (even if all bits in the waelim field are set to 0, write allocates can still occur due to the write to a cacheable page and write to a sector mechanisms). once the bios determines the amount of ram installed in the system, this number should also be used to program the waelim field. for example, a system with 32 mbytes of ram would program the waelim field with the value 00_0000_1000b. this value (8), when multiplied by 4 mbytes, yields 32 mbytes as the write allocate limit. write allocate enable 15-to-16-mbyte. the wae15m bit is used to enable write allocations for memory write cycles that address the 1 mbyte of memory between 15 mbytes and 16 mbytes. this bit must be set to 1 to allow write allocates in this memory area. this sub-mechanism of the waelim provides a memory hole to prevent write allocates. this memory hole is provided to account for a small number of uncommon memory-mapped i/o adapters that use this particular memory address space. if the system contains one of these peripherals, the bit should be set to 0 (even if the wae15m bit is set to 0, write allocates can still occur between 15 mbytes and 16 mbytes due to the write to a cacheable page and write to a sector mechanisms). the wae15m bit is ignored if the value in the waelim field is set to less than 16 mbytes. by definition, write allocations are not performed in the memory area between 640 kbytes and 1 mbyte unless the processor determines a pending write cycle is cacheable by means of write to a cacheable page or write to a sector. it is not safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because it is considered a noncacheable region of memory. additionally, if a memory region is defined as write-combinable or uncacheable by a memory type range register (mtrr), write allocates are not performed in that region.
8 programming details implementation of write allocate in the k86? processors 21326f/0february 1999 step 3: amd-k6 ? processor (all models) the bios programmer has several options regarding what the end-user can control. the bios can provide the end-user with a setup screen option to enable/disable write allocate or options to define the write allocate enable limit field and set the write allocate enable 15-to-16-mbyte bit. the bios can also automatically enable and setup the write allocate feature and its registers without end-user intervention. this automatic setup is recommended. to disable all write allocate features for the amd-k6 processor, the whcr must be set to 0000_0000_0000_0000hthe default value after power-on reset. amd-k6 ? processor programming example for write allocate registers the following cases show examples of programming the write allocate feature for three types of systems: case 1 for amd-k6 processor models 6 and 7 and amd-k6-2 processor model 8/[7:0] systems that have a 1-mbyte memory hole starting at the 15-mbyte boundary, and 32 mbytes of total memory: n program the whcr msr (ecx=c000_0082h) with wcde=0, waelim=8, and wae15m=0 ? use the wrmsr instruction and the 64-bit hex value 0000_0000_0000_0010h code sample ;flush cache pushf ;save state cli ;disable interrupts wbinvd ;write back and invalidate cache ;set write allocate limit and clear wae15m bit mov ecx,0c0000082h mov eax,10h ;wcde=0,waelim=8,wae15m=0 xor edx,edx wrmsr popf ;restore original state
programming details 9 21326f/0 february 1999 implementation of write allocate in the k86? processors case 2 for amd-k6 processor models 6 and 7 and amd-k6-2 processor model 8/[7:0] systems that do not have a memory hole starting at the 15-mbyte boundary, and have 16 mbytes of total memory: n program the whcr msr (ecx=c000_0082h) with wcde=0, waelim=4, and wae15m=1 ? use the wrmsr instruction and the 64-bit hex value 0000_0000_0000_0009h code sample ;flush cache pushf ;save state cli ;disable interrupts wbinvd ;write back and invalidate cache ;set write allocate limit and set wae15m bit mov ecx,0c0000082h mov eax,09h ;wcde=0,waelim=4,wae15m=1 xor edx,edx wrmsr popf ;restore original state case 3 for amd-k6-2 processor model 8/[f:8] and amd-k6-iii processor model 9 systems that do not have a memory hole starting at the 15-mbyte boundary, and have 64 mbytes of total memory: n program the whcr msr (ecx=c000_0082h) with waelim=16d and wae15m=1 ? use the wrmsr instruction and the 64-bit hex value 0000_0000_0401_0000h code sample ;flush cache pushf ;save state cli ;disable interrupts wbinvd ;write back and invalidate cache ;set write allocate limit and set wae15m bit mov ecx,0c0000082h mov eax,04010000h ;waelim=16d,wae15m=1 xor edx,edx wrmsr popf ;restore original state
10 programming details implementation of write allocate in the k86? processors 21326f/0february 1999 step 2: amd-k5? processor the amd-k5 processor implements write allocate by providing a global write allocate enable bit, three range-protection enable bits, and two memory range registers. the global write allocate enable bit is accessed using the hardware configuration register (hwcr). the memory range registers and range enable bits are programmed by read/write msr instructions. the write allocate enable bit (bit 4 of hwcr) should be set to 0, which prevents potential erroneous behavior in the case of a warm boot during write allocate initialization. two msrs are defined to support write allocate. the msrs are accessed using the rdmsr and wrmsr instructions (see rdmsr and wrmsr in the amd-k5? processor software development guide , order# 20007). the following index values in the ecx register access the msrs: n write allocate top-of-memory and control register (watmcr)ecx = 85h n write allocate programmable memory range register (wapmrr)ecx = 86h three non-write-allocatable memory ranges are defined for use with the write allocate featureone fixed range and two programmable ranges. fixed range. the fixed memory range is 000a_0000hC 000f_ffffh and can be enabled or disabled. when enabled, write allocate can not be performed in this range. this region of memory, which includes standard vga and other peripheral and bios access, is considered noncacheable. performing a write allocate in this area can cause compatibility problems. it is recommended that this bit be enabled (set to 1) to prevent write allocate to this range. set bit 16 of watmcr to enable protection of this range. programmable range. one programmable memory range is xxxx_0000hCyyyy_ffffh, where xxxx and yyyy are defined using bits 15C0 and bits 31C16 of wapmrr, respectively. set bit 17 of watmcr to enable protection of this range. when enabled, write allocate can not be performed in this range.
programming details 11 21326f/0 february 1999 implementation of write allocate in the k86? processors this programmable memory range exists because a small number of uncommon memory-mapped i/o adapters are mapped to physical ram locations. if a card like this exists in the system configuration, it is recommended that the bios program the memory hole for the adapter into this non-write-allocatable range. top of memory. the other programmable memory range is defined by the top-of-memory field. the top of memory is equal to zzzz_0000h, where zzzz is defined using bits 15C0 of watmcr. addresses above zzzz_0000h are protected from write allocate when bit 18 of watmcr is enabled. once the bios determines the size of ram installed in the system, this size should also be used to program the top of memory. for example, a system with 32 mbytes of ram requires that the top-of-memory field be programmed with a value of 0200h, which enables protection from write allocate for memory above that value. set bit 18 of watmcr to enable protection of this range. caching and write allocate are generally not performed for the memory above the amount of physical ram in the system. video frame buffers are usually mapped above physical ram. if write allocate were attempted in that memory area, there could be performance degradation or compatibility problems. bits 18C16 of watmcr control the enabling or disabling of the three memory ranges as follows: n bit 18: top-of-memory enable bit 0 = disabled (default) 1 = enabled (write allocate can not be performed above top of memory) n bit 17: programmable range enable bit 0 = disabled (default) 1 = enabled (write allocate can not be performed in this range) n bit 16: fixed range enable bit 0 = disabled (default) 1 = enabled (write allocate can not be performed in this range)
12 programming details implementation of write allocate in the k86? processors 21326f/0february 1999 figures 3 and 4 show the bit positions for these two new registers. figure 3. write allocate top-of-memory and control register (watmcr)msr 85h figure 4. write allocate programmable memory range register (wapmrr)msr 86h step 3: amd-k5? processor all of the write allocate features in the amd-k5 processor are enabled by setting bit 4 (wa) of the hwcr (msr 83h) to 1. for more information on the hwcr, see hardware configuration register in the amd-k5? processor software development guide , order# 20007. figure 5 shows the definition of hwcr. the bios programmer has several options regarding what the end-user can control. the bios can provide the end-user with a setup screen option to enable write allocate. the bios can provide the end-user with a setup screen option to also setup the other features (programmable ranges and fixed range). the bios can automatically enable and setup the write allocate symbol description bits tme top-of-memory enable 18 pre programmable range enable 17 fre fixed range enable 16 18 17 16 15 0 63 reserved f r e p r e t m e top of memory zzzz 19 16 31 32 15 0 63 reserved programmable rangexxxx (low - xxxx_0000h) programmable rangeyyyy (high - yyyy_ffffh)
programming details 13 21326f/0 february 1999 implementation of write allocate in the k86? processors feature and its registers without end-user intervention. this automatic setup is recommended. figure 5. hardware configuration register (hwcr)msr 83h amd-k5? processor programming example for write allocate registers the following cases show examples of programming the write allocate feature for two types of systems: case 1 for systems without a memory hole and 16 mbytes of total memory: n program the watmcr msr (ecx=85h) with top of memory (0100h) and enable bits (0005h) to protect the fixed range and above the top of memory ? use the wrmsr instruction and the 64-bit hex value 0000_0000_0005_0100h note: for 8-mbyte systems, program 0080h in the lowest 16 bits. for 32-mbyte systems, program 0200h in the lowest 16 bits. code sample ;disable wa bit (bit 4 of hwcr) mov ecx,83h ;read hwcr (83h) rdmsr and eax,not 10h wrmsr ;program top-of-memory and control bits mov ecx,85h ;select watmcr mov eax,50100h ;tme=1,pre=0,fre=1,tom=0100h xor edx,edx wrmsr 876543210 31 d i c d d c d b p d c d s p c reserved w a symbol description bits ddc disable data cache 7 dic disable instruction cache 6 dbp disable branch prediction 5 wa write allocate enable 4 dc debug control 3C1 000 off 001 enable branch trace usages dspc disable stopping processor clocks 0
14 programming details implementation of write allocate in the k86? processors 21326f/0february 1999 ;enable wa bit mov ecx,83h ;read hwcr (83h) rdmsr or eax,10h ;set bit 4 wrmsr case 2 for systems with a 1-mbyte memory hole starting at the 15 mbyte boundary and 32 mbytes of total memory: n program the wapmrr msr (ecx=86h) with 15 mbytes (00f0h) to 16 m bytes C1 (00ffh) ? use the wrmsr instruction and the 64-bit hex value 0000_0000_00ff_00f0h n program the watmcr msr (ecx=85h) with top of memory (0200h) and all enable bits (0007h) to protect above the top of memory, the fixed range, and the programmable range ? use the wrmsr instruction and the 64-bit hex value 0000_0000_0007_0200h note: for 8-mbyte systems, program 0080h in the lowest 16 bits. for 16-mbyte systems, program 0100h in the lowest 16 bits. code sample ;disable wa bit (bit 4 of hwcr) mov ecx,83h ;read hwcr (83h) rdmsr and eax,not 10h wrmsr ;program programmable range to 15-16mbytes mov ecx,86h ;select wapmrr mov eax,0ff00f0h ;address from f00000 to ffffff xor edx,edx ;clear wrmsr ;program top of memory and control bits mov ecx,85h ;select watmcr mov eax,70200h ;tme=1,pre=1,fre=1,tom=0200h xor edx,edx ;clear wrmsr ;enable wa bit mov ecx,83h ;read hwcr (83h) rdmsr or eax,10h ;set bit 4 wrmsr

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