august 2000 copyright ?2000 alliance semiconductor. all rights reserved. ? as6va25616 8/31/00 alliance semiconductor 1 2.7v to 3.3v 256k 16 intelliwatt? low-power cmos sram with one chip enable features ? as6va25616 ? intelliwatt? active power circuitry ? industrial and commercial temperature ranges available ? organization: 262,144 words 16 bits ? 2.7v to 3.3v at 55 ns ? low power consumption: active - 132 mw at 3.3v and 55 ns ? low power consumption: standby - 66 w max at 3.3v ? 1.2v data retention ? equal access and cycle times ? easy memory expansion with cs , oe inputs ? smallest footprint packages - 48-ball fbga - 400-mil 44-pin tsop ii ? esd protection 3 2000 volts ? latch-up current 3 200 ma logic block diagram 256k 16 array (4,194,304) oe cs we column decoder row decoder a0 a1 a2 a3 a4 a6 a7 a8 v cc v ss a12 a5 a9 a10 a11 a14 a15 a16 a17 a13 control circuit i/o1Ci/o8 i/o9Ci/o16 ub lb i/o buffer pin arrangement (top view) 48-csp ball-grid-array package 123456 alb oe a0 a1 a2 nc bi/o9ub a3 a4 cs i/o1 c i/o10 i/o11 a5 a6 i/o2 i/o3 dv ss i/o12 a17 a7 i/o4 v cc ev cc i/o13 nc a16 i/o5 v ss f i/o15 i/o14 a14 a15 i/o6 i/o7 g i/o16 nc a12 a13 we i/o8 hnca8a9a10a11nc 5 6 7 8 9 10 11 12 13 14 15 16 17 1 8 19 20 i/o14 i/o13 v ss v cc i/o12 i/o11 i/o10 i/o9 nc a8 a9 a10 a11 a12 a0 cs i/o1 i/o2 i/o3 i/o4 v cc v ss i/o5 i/o6 i/o7 i/o 8 we a17 a16 a15 44-pin 400-mil tsop ii 21 22 a14 a13 ub lb i/o16 i/o15 2 a3 3 a2 4 a1 1 a4 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a6 a7 oe a5 note: a mode pad is to be placed between pins 33 and 34 and 11 and 12, shorted. the bonding of this pad to v cc or v ss configures the device. there should only be 44+2+2 pads on the chip. two extra v cc to separate out array from peripheral and two-mode pads. selection guide product v cc range speed (ns) power dissipation min (v) typ 2 (v) max (v) operating (i cc1 )standby (i sb2 ) max (ma) max ( m a) as6va25616 2.7 3.0 3.3 55 2 20
? 2 alliance semiconductor 8/31/00 as6va25616 functional description the as6va25616 is a low-power cmos 4,194,304 -bit static random access memory (sram) device organized as 262,144 words 16 bits. it is designed for memory applications where slow data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 55 ns are ideal for low-power applications. active high and low chip selects ( cs ) permit easy memory expansion with multiple-bank memory systems. when cs is high, or ub and lb are high, the device enters standby mode: the as6va25616 is guaranteed not to exceed 66 m w power consumption at 3.3v and 55ns. the device also returns data when v cc is reduced to 1.5v for even lower power consumption. a write cycle is accomplished by asserting write enable ( we ) and chip select (cs ) low, and ub and/or lb low. data on the input pins i/o1Co16 is written on the rising edge of we (write cycle 1) or cs (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable ( oe ) or write enable (we ). a read cycle is accomplished by asserting output enable ( oe ), chip select ( cs ), ub and lb low, with write enable ( we ) high. the chip drives i/o pins with the data word referenced by the input address. when either chip select or output enable is inactive, or write ena ble is active, or (ub ) and (lb ), output drivers stay in high-impedance mode. these devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. lb controls the lower bits, i/o1Ci/o8, and ub controls the higher bits, i/o9Ci/o16. all chip inputs and outputs are cmos-compatible, and operation is from either a single 2.7v to 3.3v supply. device is available in the jedec standard 400-ml, tsop ii, and 48-ball fbga packages. absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat i on is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table key: x = dont care, l = low, h = high. parameter device symbol min max unit volt age on v cc relative to v ss v tin C0.5 v cc + 0.5 v voltage on any i/o pin relative to gnd v ti/o C0.5 v power dissipation p d C1.0w storage temperature (plastic) t stg C65 +150 o c temperature with v cc applied t bias C55 +125 o c dc output current (low) i out C20ma cs we oe lb ub supply current i/o1Ci/o8 i/o9Ci/o16 mode hxxxx i sb high z high z standby (i sb ) lxxhh lhhxxi cc high z high z output disable (i cc ) lhl lh i cc d out high z read (i cc ) hl high zd out ll d out d out llx lh i cc d in high z write (i cc ) hl high zd in ll d in d in
? as6va25616 8/31/00 alliance semiconductor 3 recommended operating condition (over the operating range) capacitance (f = 1 mhz, t a = room temperature, v cc = nominal) 2 parameter description test conditions min max unit v oh output high voltage i oh = C2.1ma v cc = 2.7v 2.4 v v ol output low voltage i ol = 2.1ma v cc = 2.7v 0.4 v v ih input high voltage v cc = 2.7v 2.2 v cc + 0.5 v v il input low voltage v cc = 2.7v C0.5 0.8 v i ix input load current gnd < v in < v cc C1 +1 m a i oz output load current gnd < v o < v cc; outputs high z C1 +1 m a i cc v cc operating supply current cs = v il , v in = v il or v ih , i out = 0ma, f = 0 v cc = 3.3v 2 ma i cc1 @ 1mhz average v cc operating supply current at 1 mhz cs < 0.2v, v in < 0.2v or v in > v cc C 0.2v, f = 1 ms v cc = 3.3v 2 ma i cc2 average v cc operating supply current cs 1 v il , v in = v il or v ih , f = f max v cc = 3.3v (55 ns) 40 ma i sb cs power down current; ttl inputs cs > v ih or ub = lb > v ih , other inputs = v il or v ih , f = 0 v cc = 3.3v 100 m a i sb1 cs power down current; cmos inputs cs > v cc C 0.2v or ub = lb > v cc C 0.2v, other inputs = 0v C v cc , f = f max v cc = 3.3v 20 m a i sbdr data retention cs > v cc C 0.1v, ub = lb = v cc C 0.1v f = 0 v cc = 1.2v 2 m a parameter symbol signals test conditions max unit input capacitance c in a, cs , we , oe , lb , ub v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
? 4 alliance semiconductor 8/31/00 as6va25616 read cycle (over the operating range) 3,9 shaded areas indicate preliminary information. key to switching waveforms read waveform 1 (address controlled) 3,6,7,9 read waveform 2 (cs , oe , ub , lb controlled) 3,6,8,9 parameter symbol min max unit notes read cycle time t rc 55 C ns address access time t aa C55ns3 chip select ( cs ) access time t acs C55ns3 output enable ( oe ) access time t oe C25ns output hold from address change t oh 10 C ns 5 cs low t o output in low z t clz 10 C ns 4, 5 cs high to output in high z t chz 020ns4, 5 oe low to output in low z t olz 5 C ns 4, 5 ub /lb access time t ba C55ns ub /lb low to low z t blz 10 C ns 4, 5 ub /lb high to high z t bhz 020ns4, 5 oe high to output in high z t ohz 020ns4, 5 power up time t pu 0 C ns 4, 5 power down time t pd C55ns4, 5 undefined/dont care falling input rising input t oh t aa t rc t oh d out address data valid previous data valid data valid t rc t aa t blz t ba t oe t olz t oh t ohz t hz t bhz t acs t lz address oe cs lb , ub d out
? as6va25616 8/31/00 alliance semiconductor 5 write cycle (over the operating range) 11 shaded areas indicate preliminary information. write waveform 1 (we controlled) 10,11 write waveform 2 (cs controlled) 10,11 parameter symbol min max unit notes write cycle time t wc 55 C ns chip select to write end t cw 40 C ns 12 address setup to write end t aw 40 C ns address setup time t as 0 C ns 12 write pulse width t wp 35 C ns address hold from end of write t ah 0Cns data valid to write end t dw 25 C ns data hold time t dh 0 C ns 4, 5 write enable to output in high z t wz 020ns4, 5 output active from write end t ow 5 C ns 4, 5 ub /lb low to end of write t bw 35 C ns address cs lb , ub we d in d out t wc t cw t bw t aw t as t wp t dw t dh t ow t wz t ah data undefined high z data valid address cs lb , ub we d in t wc t cw t bw t wp t dw t dh t ow t wz t ah d out data undefined high z high z t as t aw data valid t clz
? 6 alliance semiconductor 8/31/00 as6va25616 data retention characteristics (over the operating range) 13,5 data retention waveform ac test loads and waveforms notes 1during v cc power-up, a pull-up resistor to v cc on cs is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions . 4t clz and t chz are specified with c l = 5pf as in figure c. transition is measured 500 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7cs and oe are low for read cy cle. 8 address valid prior to or coincident with cs transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 cs or we must be high during address transitions. either cs or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 n/a. 13 1.2v data retention applies to commercial and industrial temperature range operations. 14 c = 30pf, except at high z and low z parameters, where c = 5pf. parameter symbol test conditions min max unit v cc for data retention v dr v cc = 1.2v cs 3 v cc C 0.1v or ub = lb = > v cc C 0.1v v in 3 v cc C 0.1v or v in 0.1v 1.2v 3.3 v data retention current i ccdr C2ma chip deselect to data retention time t cdr 0Cns operation recovery time t r trc C ns parameters v cc = 3.0v v cc = 2.5v v cc = 2.0v unit r1 1105 16670 15294 ohms r2 1550 15380 11300 ohms r th 645 8000 6500 ohms v th 1.75v 1.2v 0.85v volts v cc cs t r t cdr data retention mode v cc v cc v dr 3 1.2v v ih v ih v dr v cc r1 r2 output 30 pf including jig and scope (a) v cc r1 r2 output 5 pf all input pulses (b) 10% 90% 10% 90% gnd v cc typ < 5 ns (c) thevenin equivalent: output r th v including jig and scope
? as6va25616 8/31/00 alliance semiconductor 7 typical dc and ac characteristics package diagrams and dimensions supply voltage (v) 1.7 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current supply voltage (v) 0.0 0.25 0.5 0.75 1.0 normalized t aa normalized access time vs. supply voltage vs. supply voltage ambient temperature (c) C 55 105 25 0.5 1.0 0.0 1.5 2.0 2.5 normalized i sb2 normalized standby current vs. ambient temperature v cc = v cc typ supply voltage (v) 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i sb normalized standby current vs. supply voltage i sb2 supply voltage (v) 0.10 0.50 1.0 1.5 normalized i cc normalized i cc vs. cycle time 2.2 2.7 3.2 3.7 1.7 2.2 2.7 3.2 3.7 t a = 25 c 3.0 C 0.5 v in = v cc typ 1 5 10 15 11.9 2.8 3.7 v in = v cc typ t a = 25 c v in = v cc typ t a = 25 c v cc = 3.3v t a = 25 c 44-pin tsop ii min (mm) max (mm) a1.2 a 1 0.05 a 2 0.95 1.05 b 0.25 0.45 c 0.15 (typical) d 18.28 18.54 e 10.06 10.26 h e 11.56 11.96 e 0.80 (typical) l 0.40 0.60 d h e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 44 43 42 41 40 39 38 37 36 35 34 33 32 31 15 16 30 29 17 18 19 20 28 27 26 25 c l a 1 a 2 e 44-pin tsop ii 0C5 21 24 22 23 e a b
? 8 alliance semiconductor 8/31/00 as6va25616 minimum typical maximum a C 0.75 C b 6.90 7.00 7.10 b1 C 3.75 C c 10.90 11 11.10 c1 C 5.25 C d 0.30 0.35 0.40 eCC1.20 e1 C 0.68 C e2 0.22 0.25 0.27 yCC0.08 notes 1. bump counts: 48 (8 row 6 column). 2. pitch: (x,y) = 0.75 mm 0.75 mm (typ). 3. units: millimeters. 4. all tolerance are 0.050 unless otherwise specified. 5. typ: typical. 6. y is coplanarity: 0.08 (max). 65432 1 48-ball fbga bottom view top view a b c d e f g h ball #a1 ball #a1 index c1 a a b1 b elastomer c sram die side view detail view die die a e2 e y 0.3/typ e1 e e2 d
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