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min gstar electronic corporatio n tft-lcd controller lsi (UPS015) preliminary specification model name: UPS015 the content of this technical information is subject to change without notice. please contact m in gs tar or its agent for further information. mi ng st ar copyright 199 9 all rights reserved, copying forbidden. spec. no. 233-220-053 version : 0 total pages: 21 date : 1998/07/20
contents : a. general description ........................................ p2 b. feature .................................................... p2 c. pin description ............................................. p3 d. dc characteristics .......................................... p5 1. absolute maximum ratings ................................. p5 2. recommended operating conditions ........................ p5 3. general dc characteristics ................................. p5 4. c urrent consumption for 5 volts operation ................... p5 e. ac characteristics .......................................... p 7 1. timing condition .......................................... p 7 ( i )220 x 280 reso l ution mode .............................. p7 a. input signal characteristics ........................... p 7 b. output signal characteristics .......................... p7 ( ii ) 234 x 480 resol ution mode .............................. p 8 a. input signal characteristics ........................... p8 b. output signal characteristics .......................... p8 ( iii )220 x 528 resolution mode ............................. p 9 a. input signal characteristics ........................... p9 b. output signal characteristics .......................... p9 spec no.:233-220-053 page : 1 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from min gs tar electronic corp.
( iv ) 234 x 960 r esol ution mode ............................. p 10 a. input signal characteristics ........................... p10 b. output signal characteristics .......................... p11 ( v )234 x 1152 r esol ution mode ............................. p 12 a. input signal characteristics ........................... p12 b. output signal characteristics .......................... p12 2. timing diagram ........................................... p13 f. test circuit .......................................... p14 g. package information .................................. p15 appendix fig.1 sampling clock timing .......................... p16 fig.2-(a) horizontal timing .............................. p17 fig.2-(b) detail horizontal timing ......................... p18 fig.3 vertical shift clock timing ........................ p19 fig.4-(a) vertical timing (udc="h") ....................... p20 fig.4-(b) vertical timing (udc="l") ....................... p21 spec no.:233-220-053 page : 2 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mi ng st ar electronic corp.
a.general description: this timing controller is a synchronizing signal controlling cmos array lsi for mi ng st ar lcd module. it provides all the necessary control timing signals to the lcd source and gate drivers. with external vco as the master clock, the controller has built-in phase locked loop system which can synchronize the master clock with the horizontal and vertical sync. signals from a classical tv system. the applicab le m in gs tar tft-lcd modul es are sm 261d series , mt l 0 20d01, m t l 0 25d01, m t l 0 40d01 , mt l 0 68d01, m tl 07 0 w 01 . b. feature: * programmable resolution mode. * low power consumption. * single supply : +5.0 volts. * 48 pins tqfp. * shift clocks signal for the source driver. (3 - clock) v * line inversion driving scheme. * ntsc tv standard system . * master clock frequency : 26 mhz max. * provides timing scan signals for left / right and up / down shift control. * display timing range = 49.6 s l spec no.:233-220-053 page : 3 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mi ng st ar electronic corp.
c.pin description: master system clock input. this input pin is connected to the external vco output for system clock timing & synchronization to the tv sync. signals through the phase locked loop block. i osc/i 26 inverted osc signal output o osc/o 25 vcc 24 ground gnd 23 note 2 resolution mode selecting pin b i rc1 22 note 1 test 21 note 1 test 20 source driver shift clock 3 . v o ck3a 19 source driver shift clock 2 . v o ck2a 18 source driver shift clock 1 . v o ck1a 17 gate driver shift clock. o ckv 16 negative polarity phase detector output. o npd 15 source driver start pulse. when (1).lrc=h, sthr is output pin of start pulse. (2).lrc=l, sthr is in high impedance state. o sthr 14 source driver start pulse. when (1).lrc=h, sthl is in high impedance state. (2).lrc=l, sthl is output pin of start pulse. o sthl 13 vcc 12 gate driver start pulse. when (1).udc=h, stv2 is in high impedance state. (2).udc=l, stv2 is output pin of start pulse. o stv2 11 gate driver start pulse. when (1).udc=h, stv1 is output pin of start pulse. (2).udc=l, stv1 is in high impedance state. o stv1 10 note 2 resolution mode selecting pin i i a18 9 s ample & hold sequence control signal for s our ce driver o q1ha 8 gr ound gnd 7 note 1 test 6 note 1 test 5 output enable control signal for source dr iver o oev 4 o utput enable control signal for source driver o oeh 3 inverter input i inv/i 2 inverter output o inv/o 1 remark description i/o symbol pin no spec no.:233-220-053 page : 4 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from m in gs t a r electronic corp.
vcc 48 compare pulse input. i cp/i 47 compare pulse output. o cp/o 46 test 45 polarity alternating signal for v com o pfrp 44 it should be pulled to vcc in normal operation. i npc 43 note 1 test 42 note 1 test 41 inverted lrc signal output. o lra 40 left / right scan control pin. i lrc 39 note 1 test 38 up / down scan control pin. i udc 37 ground gnd 36 positive polarity composite sync. input. i csync 35 negative polarity horizontal sync. output. o hsy/o 34 resolution mode selecti ng pin iii .i rc 233 g round gnd 32 inverted udc signal output. o ud 31 vertical synchronization signal input from the sync. separator of a tv system. it should be a negative polarity. i vsy/i 30 global reset. it should be connected to v cc in normal operation. if connected to gnd, the controller is in reset state. i gr 29 note 1 test 28 negative polarity vertical sync. output o vsy / o 27 remark description i/o symbol pin no note 1 : all the test pins should be electrically opened. note 2 : res olution setting : m t l 0 68d01, mtl070w01 234 x 1152 ll h m t l 0 25d 01 , m t l 0 4 0d01 234 x 480 hhh 234 x 960 h l h sm261d ser ies 220 x 280 hh l m t l 0 2 0 d01 220 x 528 h ll appicable mi ng st ar lcd res olutiion mode ( v xh) rc2 rc 1 a18 this chip can drive diff erent mi ng st ar' s lcd according to the above table . spec no.:233-220-053 page : 5 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from m in gs ta r electronic corp.
d .dc characteristics 1.absolute maximum ratings: o c -40 to 125 storage temperature t stg v -0.3 to vcc + 0.3 output voltage v out v -0.3 to vcc + 0.3 input voltage v in v -0.3 to 6.0 power supply v cc units rating parameter symbol 2.recommended operating conditions: o c 85 - -20 operating temperature t opr vv cc - 0 input voltage v in v 5.5 5.0 4.5 power supply v cc units max typ min parameter symbol 3.general dc characteristics: k w - 50 - v il =0v or v ih =v cc input pull up/down resistance r i v - - 3.5 i oh =4ma output high voltage v oh v 0.4 - - i ol =4ma output low voltage v ol note 1 v - 3.2 - cmos schmitt input h igh voltage v s ih v - - 0.7vcc cmos input h igh voltage v ih note 1 v - 1.76 - cmos schmitt input l ow voltage v s il v 0.3vcc - - cmos input l ow voltage v il pf 6 - 3 output capacitance c out pf - 3 - input capacitance c in a l 10 - -10 tri-state leakage current i oz a l 1 - -1 no pull-up or pull-down input high current i ih a l 1 - -1 no pull-up or pull-down input low current i il remark units max typ min conditions parameter symbol note 1 : the applicable pins are a18, osc/i, gr, vsy/i, csync, cp/i. 4. c urrent cons umption for 5 volts operati ng: mt l 0 68d01 ma 21159 234 x 960 mode ma 18138 mt l 0 4 0d 01 ma 1074 mt l 0 25d 01 ma 1074 mt l 0 2 0d 01 ma 1185 sm261d series ma 753 vcc=5v current consumption i in loading unit max typ min condition parameter symbol spec no.:233-220-053 page : 6 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from min gs tar electronic corp.
e. ac characteristics 1.timing condition ( i ) 220 x 280 resolution mode. a.input signal characteristics note 1 line 268 262.5 256 horizontal lines per field ns 700 -- t vf vsy/i falling ns 700 -- t vr vsy/i rising time t h 531 t vsy vsy/i pulse width ns 300 -- t cf csync falling time ns 300 -- t cr csync rising time s l 5.44.7 4 t csyn csync pulse width s l 65.563.561.5 t h csync period ns 183166150 t osc osc/i period remark unit. max. typ. min. symbol parameter note 1: please don't use odd horizontal lines to drive lcd panel for both odd and even field simultaneously. b.output signal characteristics t cph - 6 - t 4 hsy/o-cp/o timing difference t cph - 3 - t 3 hsy/o-oev timing difference t cph - 4 - t 2 hsy/o-ckv timing difference t cph - 5 - t 1 hsy/o-oeh timing difference t h - 1/2 - t wcp cp/o pulse duty t h - 1 - t cp cp/o period t cph - 11 - t ckv ckv pulse width t cph - 10 - t oev oev pulse width t cph - 16 - t dis1 sample & hold disable time t cph - 2 - t oeh oeh pulse width t cph - 9 - t hsy hsy/o pulse width t cph - 1 - t sth sth pulse width ns - t cph /2 - t suh sth setup time ns - t cph /3 - t c12 t c23 t c31 3 clock phase difference v ck1a~ck3a % 605040 t cwh clock pulse duty ck1a~ck3a t osc - 3 - t cph clock high and low level pulse width note 1 ns 10 -- t f falling time note 1 ns 10 -- t r rising time remark unit. max. typ. min. symbol parameter spec no.:233-220-053 page : 7 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from min gs tar electronic corp.
t h - 2 - t oes oeh-stv timing difference t h - 19 - t vs2 vsy/o-stv2 timing difference(udc="l") t h - 19 - t vs1 vsy/o-stv1 timing difference(udc="h") t h - 1 - t stv stv pulse width t cph - 2 - t suv stv setup time note 1: for all of the logic signals. ( i i ) 2 34 x 4 80 resolution mode. a.input signal characteristics note 1 line 268 262.5 256 horizontal lines per field ns 700 -- t vf vsy/i falling ns 700 -- t vr vsy/i rising time t h 531 t vsy vsy/i pulse width ns 300 -- t cf csync falling time ns 300 -- t cr csync rising time s l 5.44.7 4 t csyn csync pulse width s l 65.563.561.5 t h csync period ns 11410494 t osc osc/i period remark unit. max. typ. min. symbol parameter note 1: please don't use odd horizontal lines to drive lcd panel for both odd and even field simultaneously. b.output signal characteristics t cph - 20 - t ckv ckv pulse width t cph - 13 - t oev oev pulse width t cph - 27 - t dis1 sample & hold disable time t cph - 3 - t oeh oeh pulse width t cph - 15 - t hsy hsy/o pulse width t cph - 1 - t sth sth pulse width ns - t cph /2 - t suh sth setup time ns - t cph /3 - t c12 t c23 t c31 3 clock phase difference v ck1a~ck3a % 605040 t cwh clock pulse duty ck1a~ck3a t osc - 3 - t cph clock high and low level pulse width note 1 ns 10 -- t f falling time note 1 ns 10 -- t r rising time remark unit. max. typ. min. symbol parameter spec no.:233-220-053 page : 8 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from min gs tar electronic corp.
t h - 2 - t oes oeh-stv timing difference t h - 19 - t vs2 vsy/o-stv2 timing difference(udc="l") t h - 19 - t vs1 vsy/o-stv1 timing difference(udc="h") t h - 1 - t stv stv pulse width t cph - 3 - t suv stv setup time t cph - 10 - t 4 hsy/o-cp/o timing difference t cph - 2 - t 3 hsy/o-oev timing difference t cph - 6 - t 2 hsy/o-ckv timing difference t cph - 8 - t 1 hsy/o-oeh timing difference t h - 1/2 - t wcp cp/o pulse duty t h - 1 - t cp cp/o period note 1: for all of the logic signals. ( iii ) 220 x 528 resolution mode. a.input signal characteristics note 1 line 268 262.5 256 horizontal lines per field ns 700 -- t vf vsy/i falling ns 700 -- t vr vsy/i rising time t h 531 t vsy vsy/i pulse width ns 300 -- t cf csync falling time ns 300 -- t cr csync rising time s l 5.44.7 4 t csyn csync pulse width s l 65.563.561.5 t h csync period ns 1039485 t osc osc/i period remark unit. max. typ. min. symbol parameter note 1: please don't use odd horizontal lines to drive lcd panel for both odd and even field simultaneously. b.output signal characteristics ns - t cph /3 - t c12 t c23 t c31 3 clock phase difference v ck1a~ck3a % 605040 t cwh clock pulse duty ck1a~ck3a t osc - 3 - t cph clock high and low level pulse width note 1 ns 10 -- t f falling time note 1 ns 10 -- t r rising time remark unit. max. typ. min. symbol parameter spec no.:233-220-053 page : 9 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from min gs tar electronic corp.
t h - 2 - t oes oeh-stv timing difference t h - 19 - t vs2 vsy/o-stv2 timing difference(udc="l") t h - 19 - t vs1 vsy/o-stv1 timing difference(udc="h") t h - 1 - t stv stv pulse width t cph - 4 - t suv stv setup time t cph - 12 - t 4 hsy/o-cp/o timing difference t cph - 1 - t 3 hsy/o-oev timing difference t cph - 7 - t 2 hsy/o-ckv timing difference t cph - 8 - t 1 hsy/o-oeh timing difference t h - 1/2 - t wcp cp/o pulse duty t h - 1 - t cp cp/o period t cph - 24 - t ckv ckv pulse width t cph - 14 - t oev oev pulse width t cph - 27 - t dis1 sample & hold disable time t cph - 5 - t oeh oeh pulse width t cph - 18 - t hsy hsy/o pulse width t cph - 1 - t sth sth pulse width ns - t cph /2 - t suh sth setup time note 1: for all of the logic signals. ( iv ) 234 x 960 resolution mode. a.input signal characteristics note 1 line 268 262.5 256 horizontal lines per field ns 700 -- t vf vsy/i falling ns 700 -- t vr vsy/i rising time t h 531 t vsy vsy/i pulse width ns 300 -- t cf csync falling time ns 300 -- t cr csync rising time s l 5.44.7 4 t csyn csync pulse width s l 65.563.561.5 t h csync period ns 575247 t osc osc/i period remark unit. max. typ. min. symbol parameter note 1: please don't use odd horizontal lines to drive lcd panel for both odd and even field simultaneously. spec no.:233-220-053 page : 10 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mi ng st ar electronic corp.
b.output signal characteristics t h - 2 - t oes oeh-stv timing difference t h - 19 - t vs2 vsy/o-stv2 timing difference(udc="l") t h - 19 - t vs1 vsy/o-stv1 timing difference(udc="h") t h - 1 - t stv stv pulse width t cph - 6 - t suv stv setup time t cph - 20 - t 4 hsy/o-cp/o timing difference t cph - 4 - t 3 hsy/o-oev timing difference t cph - 12 - t 2 hsy/o-ckv timing difference t cph - 14 - t 1 hsy/o-oeh timing difference t h - 1/2 - t wcp cp/o pulse duty t h - 1 - t cp cp/o period t cph - 40 - t ckv ckv pulse width t cph - 26 - t oev oev pulse width t cph - 54 - t dis1 sample & hold disable time t cph - 7 - t oeh oeh pulse width t cph - 30 - t hsy hsy/o pulse width t cph - 1 - t sth sth pulse width ns - t cph /2 - t suh sth setup time ns - t cph /3 - t c12 t c23 t c31 3 clock phase difference v ck1a~ck3a % 605040 t cwh clock pulse duty ck1a~ck3a t osc - 3 - t cph clock high and low level pulse width note 1 ns 10 -- t f falling time note 1 ns 10 -- t r rising time remark unit. max. typ. min. symbol parameter note 1: for all of the logic signals. spec no.:233-220-053 page : 11 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mi ng st ar electronic corp.
( v ) 234 x 1152 resolution mode. a.input signal characteristics note 1 line 268 262.5 256 horizontal lines per field ns 700 -- t vf vsy/i falling ns 700 -- t vr vsy/i rising time t h 531 t vsy vsy/i pulse width ns 300 -- t cf csync falling time ns 300 -- t cr csync rising time s l 5.44.7 4 t csyn csync pulse width s l 65.563.561.5 t h csync period ns 474339 t osc osc/i period remark unit. max. typ. min. symbol parameter note 1: please don't use odd horizontal lines to drive lcd panel for both odd and even field simultaneously. b.output signal characteristics t h - 1 - t stv stv pulse width t cph - 8 - t suv stv setup time t cph - 26 - t 4 hsy/o-cp/o timing difference t cph - 12 - t 3 hsy/o-oev timing difference t cph - 14 - t 2 hsy/o-ckv timing difference t cph - 18 - t 1 hsy/o-oeh timing difference t h - 1/2 - t wcp cp/o pulse duty t h - 1 - t cp cp/o period t cph - 50 - t ckv ckv pulse width t cph - 40 - t oev oev pulse width t cph - 62 - t dis1 sample & hold disable time t cph - 9 - t oeh oeh pulse width t cph - 36 - t hsy hsy/o pulse width t cph - 1 - t sth sth pulse width ns - t cph /2 - t suh sth setup time ns - t cph /3 - t c12 t c23 t c31 3 clock phase difference v ck1a~ck3a % 605040 t cwh clock pulse duty ck1a~ck3a t osc - 3 - t cph clock high and low level pulse width note 1 ns 10 -- t f falling time note 1 ns 10 -- t r rising time remark unit. max. typ. min. symbol parameter spec no.:233-220-053 page : 12 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mi ng st ar electronic corp.
t h - 2 - t oes oeh-stv timing difference t h - 19 - t vs2 vsy/o-stv2 timing difference(udc="l") t h - 19 - t vs1 vsy/o-stv1 timing difference(udc="h") note 1: for all of the logic signals. 2.timing dia gram please refer to the attached drawing. from fig . 1 to fig . 4-(b). spec no.:233-220-053 page : 13 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mi ng st ar electronic corp.
spec no.: 233-220-053 page : 14/21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mi ng st ar electronic corp. f. test circuit - 10va +5vp vccu frp csyn vccu gnd gndu d[1:26] d14 d21 d10 d24 d17 d6 d23 d19 d4 d25 d15 d22 d9 d16 d11 d2 d1 d20 d7 d12 d3 d26 d5 d14 d13 d8 d6 d17 d18 d19 d7 d5 ck1a ck2a ckv d15 d16 ck3a d18 d9 d8 d12 c108 @104f r116 472f c109 c c106 c r113 r r114 101f c102 c d1 ma335 u3 njm2107f 1 2 3 4 5 + g _ o v r111 473f r105 105f r103 r r110 103f r107 vr103f c105 @104f r115 472f r109 473f l101 l r112 104f c101 @102b r106 823f r108 105f r122 103f r127 103f c111 @221c r125 204f r120 153f qm1 xn4501 6 5 4 1 2 3 e1 b1 c2 c1 b2 e2 r121 393f q101 2sb709a c110 @221c r126 302f r124 153f @225a r123 102f r154 153f c107 @104f r118 101f r158 101f r159 101f r161 101f r160 101f r162 101f jp2 elco26p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 s1 sw s4 sw s3 sw r117 101f s2 sw s5 sw r200 r r130 102f c112 @221c r129 vr503f u2 UPS015 43 42 41 40 44 39 38 37 7 8 9 10 11 12 13 14 47 46 45 4 5 6 2 1 24 23 18 16 15 22 21 20 19 17 25 26 27 28 29 30 31 32 33 34 35 36 48 3 npc tc /csync lra frp lrc pd_sw udc gnd q1ha a18 stv1 stv2 vcc sthl sthrcp/i cp/o np_sw oev d_mod fd inv/i inv/o vcc gnd ck2a ckv pd(-) rc1 ph2 ph1 ck3a ck1a osc/o osc/i vsy/o hsyw gr vsy/i /udc gnd rc2 hsy/o csync(+) gnd vcc oeh r157 101f r170 503 r156 r /pd (down) (up) (1) (2) 234 x 960 mode & 234 x 1152 mode other r156 r200 open open 101f 101f modes
g. package information spec no.: 233-220-053 page : 15/21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mi ng st ar electronic corp.
t t suh sth t t t t cph c23 c31 cwh 50% 50% ck3a ck1a ck2a sthl(r) t t t r f c12 90% 10% 10% 90% osc/ i osc/ o fig.1 sampling clock timing spec no.:233-220-053 page : 16 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mi ng st ar electronic corp.
spec no.: 233-220-053 page : 17/21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from min gs ta r electronic corp.
(csync) (cp/ i) hsy/o oeh sthl(r) ckv oev cp/o npd q1ha pfrp oev t t 4 2 ckv t t dis1 sth t t oeh 1 t t t hsy csyn t t h 3 t ? in 234 x 960 & 234 x 1152 resolution mode , q1ha always keeps low. fig.2-(b) detail horizontal timing spec no.:233-220-053 page : 18 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mingstar electronic corp.
fig.3 vertical shift clock timing stv 1(2) (c ) sync ckv spec no.:233-220-053 page : 19 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mingstar electronic corp.
(csync) (vsy/ i) stv1 q1ha pfrp(odd field) pfrp(even field) oeh t oes t vs1 t vsy ? in 234 x 960 & 234 x 1152 resolution mode , q1ha always keeps low. fig.4-(a) vertical timing (udc="h") spec no.:233-220-053 page : 20 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mingstar electronic corp.
(csync) (vsy/ i) stv2 q1ha pfrp(odd field) pfrp(even field) oeh t t oes vs2 ? in 234 x 960 & 234 x 1152 resolution mode , q1ha always keeps low. fig.4-(b) vertical timing (udc="l") spec no.:233-220-053 page : 21 /21 all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from mingstar electronic corp.
mingstar electronic corp. 365-a cloverleaf drive b a ld win park, ca 91706 fax : 62 6 -3 69 -1 655 tel :88 8 -3 14 - 11 26 m in gs ta r copyright 199 9 all rights reserved, copying forbidden.

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