View 20068_1035518.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this document contains information on a product under development at advanced micro devices, inc. the information is intended to help you evaluate this product. amd ? reserves the right to change or discontinue work on this proposed product without notice. publication #: 20068 rev. a amendment: /0 issue date: may 1997 am29240 eh, am29245 eh, and am29243 eh enhanced high-performance risc microcontrollers 5/2/97 ? ? ? preliminary distinctive characteristics all three microcontrollers in the am29240 ? eh micro- controller series have the following characteristics: completely integrated system for embedded applications full 32-bit architecture 4-kbyte, two-way set-associative instruction cache 4-gbyte virtual address space, 304-mbyte physical space implemented glueless system interfaces with on-chip wait state control 36 vax mips (million instructions per second) sustained at 25 mhz four banks of rom, each separately programmable for 8-, 16-, or 32-bit interface four banks of dram single-cycle rom burst-mode and dram page-mode access dram timing is software-programmable for 3/1 or 2/1 initial/burst access cycles 6-port peripheral interface adapter 16-line programmable i/o port bidirectional parallel port controller interrupt controller fully pipelined integer unit three-address instruction architecture 192 general purpose registers traceable cache ? technology instruction and data cache tracing ieee std 1149.1-1990 (jtag) compliant standard test access port and boundary scan architecture binary compatibility with all 29k ? family microprocessors and microcontrollers cmos technology/ttl compatible 208-pin plastic quad flat pack (pqfp) package 3.3-v power supply with 5-v-tolerant i/o am29240eh microcontroller the am29240eh microcontroller has the following addi- tional features: 2-kbyte, two-way set-associative data cache single-cycle 32-bit multiplier for faster integer math; two-cycle multiply accumulate (mac) function 16-entry on-chip memory management unit (mmu) with one translation look-aside buffer 4-channel double-buffered dma controller with queued reload two serial ports (uarts) bidirectional bit serializer/deserializer 20- and 25-mhz operating frequencies am29243eh microcontroller the am29243 ? eh data microcontroller is similar to the am29240eh microcontroller, without the video inter- face. it includes the following features: 2-kbyte, two-way set-associative data cache single-cycle 32-bit multiplier for faster integer math; two-cycle mac 32-entry on-chip mmu with dual tlbs 4-channel, double-buffered dma controller with queued reload two serial ports (uarts) 20- and 25-mhz operating frequencies dram parity am29245eh microcontroller the low-cost am29245 ? eh microcontroller is similar to the am29240eh microcontroller, without the data cache and 32-bit multiplier. it includes the following features: 16-entry on-chip mmu with one tlb two-channel dma controller one serial port (uart) bidirectional bit serializer/deserializer 16-mhz operating frequency
p r e l i m i n a r y 2 am29240 eh microcontroller series ? am29240eh microcontroller block diagram interrupts, traps dram space rom memory serial ports parallel port controller 4-channel dma controller programmable interrupt dram controller timer/counter i/o port controller serializer/ deserializer rom controller pia controller am29000 cpu peripherals 62432 pia chip selects address bus instruction/data bus 4 4 6 16 6 4/4 rom chip selects serial data printer/scanner video i/o 6 11 parallel port control/status lines dual 2k dcache 32x32 multiply mmu 4k icache 4 dreq 5 8 clock/ lines control jtag 4 stat memclk 4 dack greq /gack /tdma ras /cas am29245eh microcontroller block diagram interrupts, traps dram space rom memory serial port parallel port controller 2-channel dma controller programmable interrupt dram controller timer/counter i/o port controller serializer/ deserializer rom controller pia controller am29000 cpu peripherals 62432 pia chip selects address bus instruction/data bus 4 4 4 16 6 4/4 rom chip selects serial data printer/scanner video i/o 6 7 parallel port control/status lines single mmu 4k icache 2 dreq 5 8 clock/ lines control jtag 4 stat memclk 2 dack greq /gack /tdma ras /cas
p r e l i m i n a r y 3 am29240 eh microcontroller series ? am29243eh microcontroller block diagram interrupts, traps dram space rom memory serial ports parallel port controller 4-channel dma controller programmable interrupt dram controller timer/counter i/o port controller rom controller pia controller am29000 cpu peripherals 62432 pia chip selects address bus instruction/data bus 4 5 6 16 6 4/4 rom chip selects serial data i/o 6 11 parallel port control/status lines dual 2k dcache 32x32 multiply mmu 4k icache 4 dreq 8 clock/ lines control 4 stat memclk 4 dack greq /gack /tdma 36 32 ras /cas 5 jtag dram parity customer service amd's customer service network includes u.s. offices, international offices, and a customer training center. ex- pert technical assistance is available from amd's world- wide staff of field application engineers and support staff. for answers to technical questions, amd provides a toll-free number for direct access to our corporate ap- plications hotline. also available is the amd world wide web home page and ftp site, which provides the latest 29k family product information. corporate applications hotline (800) 222-9323, option 5 toll-free for u.s. 44-(0) 1276-803-299 u.k. and europe hotline engineering support lpd.support@amd.com e-mail world wide web home page and ftp site to access the amd home page on the web, go to: http:/www.amd.com. questions, requests, and input concerning amd's www pages can be sent via e-mail to webmaster@amd.com. to download documents and software, ftp to ftp.amd.com and log on as anonymous using your e-mail address as a password. or, with your web browser, go to ftp://ftp.amd.com. documentation and literature a simple phone call gets you free 29k family informa- tion such as data sheets, user's manuals, application notes, the fusion29k partner solutions catalog, and other literature. internationally, contact your local amd sales office for complete 29k family literature. literature ordering (800) 222-9323, option 3 toll-free for u.s. (512) 602-5651 direct dial worldwide (800) 222-9323, option 2 amd facts-on-demand ? fax information service toll-free for u.s., canada related documents the am29240eh, am29245eh, and am29243eh risc microcontrollers user's manual (order #17741) describes the technical features, programming inter- face, on-chip peripherals, register set, and instruction set for the am29240eh microcontroller series. programming the 29k risc family (order #19243) in- cludes comprehensive information about the 29k family for the software developer.
p r e l i m i n a r y 4 am29240 eh microcontroller series ? general description the am29240eh microcontroller series is an enhanced bus-compatible extension of the am29200 ? risc mi- crocontroller family, with two to four times the perfor- mance. the am29240eh microcontroller series includes the am29240eh microcontroller, the low-cost am29245eh microcontroller, and the am29243eh data microcontroller. the on-chip caches, mmu, faster inte- ger math, and extended dma addressing capability of the am29240eh microcontroller series allow the em- bedded systems designer to provide increasing levels of performance and software compatibility throughout a range of products (see table 1 on page 6). based on a low-voltage cmos-technology design, these devices offer a complete set of system peripherals and interfaces commonly used in embedded applica- tions. compared to cisc processors, the am29240eh microcontroller series offers better performance, more efficient use of low-cost memories, lower system cost, and complete design flexibility for the designer. coupled with hardware and software development tools from the amd fusion29k partners, the am29240eh microcon- troller series provides the embedded product designer with the cost and performance edge required by today's marketplace. for a complete description of the technical features, on- chip peripherals, programming interface, register set, and instruction set, please refer to the am29240eh, am29245eh, and am29243eh risc microcontrollers user's manual (order #17741). am29240eh microcontroller for general-purpose embedded applications, such as mass-storage controllers, communications, digital sig- nal processing, networking, industrial control, pen- based systems, and multimedia, the am29240eh microcontroller provides a high-performance solution with a low total-system cost. the memory interface of the am29240eh microcontroller provides even faster direct memory access than the am29200 microcontrol- ler. this performance improvement minimizes the effect of memory latency, allowing designers to use low-cost memory with simpler memory designs. on-chip instruc- tion and data caches provide even better performance for time-critical code. other on-chip functions include: a rom controller, dram controller, peripheral interface adapter control- ler, dma controller, programmable i/o port, parallel port controller, serial ports, and an interrupt controller. am29245eh microcontroller the low-cost am29245eh microcontroller is designed for embedded applications in which cost and space constraints, along with increased performance require- ments, are primary considerations. the am29245eh microcontroller also provides an easy upgrade path for am 29200, am29202 ? , and am29205 ? microcontro ller-based products. am29243eh microcontroller with dram parity support and a full mmu, the am29243eh data microcontroller is recommended for communications applications that require high-speed data movement and fast protocol processing in a fault- tolerant environment. both the am29243eh and am29240eh microcontrol- lers support fly-by dma at 100 mbytes/s for lans and switching applications, and a two-cycle multiply accu- mulate function for dsp applications. the low power re- quirements make either microcontroller a good choice for field-deployed devices. development support products the fusion29k program of partnerships for application solutions provides the user with a vast array of products designed to meet critical time-to-market needs. prod- ucts/solutions available from the amd fusion29k part- ners include the following: optimizing compilers for common high-level languages assembler and utility packages source- and assembly-level software debuggers target-resident development monitors simulators execution boards hardware development tools silicon products board-level products laser-printer solutions multiuser, kernel, and real-time operating systems graphics solutions networking and communication solutions manufacturing support custom software consulting, support, and training
p r e l i m i n a r y 5 am29240 eh microcontroller series ? ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. am29240eh 25 c temperature range c = commercial (t c = 0 c to +85 c) package type k = 208-lead plastic quad flat pack (pqr 208) speed option device number/description am29240eh enhanced risc microcontroller am29245eh enhanced risc microcontroller am29243eh enhanced risc data microcontroller valid combinations valid combinations lists configurations planned to be supported in volume. consult the local amd sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on amd standard military grade products. valid combinations 25 = 25 mhz 20 = 20 mhz 16 = 16 mhz k\w processing \w = trimmed and formed am29240eh20 kc\w am29243eh20 am29245eh16 kc\w am29240eh25 kc\w am29243eh25 related amd products 29k family devices product description am29000 32-bit risc microprocessor am29005 ? low-cost 32-bit risc microprocessor with no mmu and no branch target cache am29030 ? 32-bit risc microprocessor with 8-kbyte instruction cache am29035 ? 32-bit risc microprocessor with 4-kbyte instruction cache am29040 ? 32-bit risc microprocessor with 8-kbyte instruction cache and 4-kbyte data cache am29050 ? 32-bit risc microprocessor with on-chip floating point am29200 ? 32-bit risc microcontroller am29202 ? low-cost 32-bit risc microcontroller with ieee-1284-compliant parallel interface am29205 ? low-cost 32-bit risc microcontroller
p r e l i m i n a r y 6 am29240 eh microcontroller series ? table 1. product comparisoneam29200 microcontroller family feature am29205 ? controller am29202 ? controller am29200 ? controller am29245eh controller am29240eh controller am29243eh controller instruction cache e e e 4 kbytes 4 kbytes 4 kbytes data cache e e e e 2 kbytes 2 kbytes cache associativity e e e 2-way 2-way 2-way integer multiplier software software software software 32 x 32-bit 32 x 32-bit memory management unit (mmu) e e e 1 tlb 16 entry 1 tlb 16 entry 2 tlbs 32 entry data bus width internal external 32 bits 16 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits rom interface banks width rom size (max/bank) boot-up rom width burst-mode access 3 8, 16 bits 4 mbytes 16 bits not supported 4 8, 16, 32 bits 4 mbytes 8, 16, 32 bits not supported 4 8, 16, 32 bits 16 mbytes 8, 16, 32 bits supported 4 8, 16, 32 bits 16 mbytes 8, 16, 32 bits supported 4 8, 16, 32 bits 16 mbytes 8, 16, 32 bits supported 4 8, 16, 32 bits 16 mbytes 8, 16, 32 bits supported dram interface banks width size: 32-bit mode size: 16-bit mode video dram access cycles initial/burst dram parity 4 16 bits only e 8 mbytes/bank not supported 3/2 no 4 16, 32 bits 16 mbytes/bank 8 mbytes/bank not supported 3/2 no 4 16, 32 bits 16 mbytes/bank 8 mbytes/bank supported 3/2 no 4 32 bits 16 mbytes/bank not supported supported 2/1 or 3/1 no 4 32 bits 16 mbytes/bank not supported supported 2/1 or 3/1 no 4 32 bits 16 mbytes/bank not supported not supported 2/1 or 3/1 yes on-chip dma width (ext. peripherals) total number of channels externally controlled external master access external master burst external terminate signal 8, 16 bits 2 1 no no no 8, 16, 32 bits 2 1 no no no 8, 16, 32 bits 2 2 yes no yes 8, 16, 32 bits 2 2 yes yes yes 8, 16, 32 bits 4 4 yes yes yes 8, 16, 32 bits 4 4 yes yes yes low-voltage operation no no no yes yes yes peripheral interface adapter (pia) pia ports data width min. cycles access 2 8, 16 bits 3 2 8, 16, 32 bits 3 6 8, 16, 32 bits 3 6 8, 16, 32 bits 1 6 8, 16, 32 bits 1 6 8, 16, 32 bits 1 programmable i/o port (pio) signals signals programmable for interrupt generation 8 8 12 8 16 8 16 8 16 8 16 8 serial ports ports dsr /dtr 1 port pio signals 1 port pio signals 1 port supported 1 port supported 2 ports 1 port supported 2 ports 1 port supported interrupt controller external interrupt pins external trap and warn pins 2 0 2 0 4 3 4 3 4 3 4 3 parallel port controller 32-bit transfer ieee-1284 interface yes no no yes yes yes yes yes no yes yes no yes yes no yes yes no jtag debug support no yes yes yes yes yes serializer/deserializer yes yes yes yes yes no pin count and package 100 pqfp 132 pqfp 168 pqfp 208 pqfp 208 pqfp 208 pqfp operating voltage v cc i/o tolerance 5 v 5 v 5 v 5 v 5 v 5 v 3.3 v 5 v 3.3 v 5 v 3.3 v 5 v processor clock rate 12, 16 mhz 12, 16, 20 mhz 16, 20 mhz 16 mhz 20, 25 mhz 20, 25 mhz
p r e l i m i n a r y 7 am29240 eh microcontroller series ? key features and benefits the am29240eh microcontroller series extends the line of risc microcontrollers based on 29k family architec- ture, providing performance upgrades to the am29205 and am29200 microcontrollers. the risc microcontrol- ler product line allows users to benefit from the very high performance of the 29k family architecture, while also capitalizing on the very low system cost made possible by integrating processor and peripherals. the am29240eh microcontroller series expands the price/performance range of systems that can be built with the 29k family. the am29240eh microcontroller series is fully software compatible with the am29000, am29005, am29030, am29035, am29040, and am29050 microprocessors, as well as the am29200 and am29205 microcontrollers. it can be used in exist- ing 29k family microcontroller applications without soft- ware modifications. on-chip caches the am29240eh microcontroller series incorporates a 4-kbyte, two-way instruction cache that supplies most processor instructions without wait states at the proces- sor frequency. for best performance, the instruction cache supports critical-word-first reloading with fetch- through, so that the processor receives the required instruction and the pipeline restarts with minimum delay. the instruction cache has a valid bit per word to mini- mize the reload overhead. all cache array elements are visible to software for testing and preload. the am29240eh and am29243eh microcontrollers in- corporate a 2-kbyte, two-way set-associative data cache. the data cache appears in the execute stage of the processor pipeline, so that loaded data is available immediately to the next instruction. this provides the maximum performance for loads without requiring load scheduling. this minimizes the time the processor waits on external data as well as minimizing the reload time. the data cache uses a write-through policy with a two- entry write buffer. byte, half-word, and word reads and writes are supported. all cache array elements are vis- ible to software for testing and preload. single-cycle multiplier the am29240eh and am29243eh microcontrollers incorporate a full combinatorial multiplier that accepts two 32-bit input operands and produces a 32-bit result in a single cycle. the multiplier can produce a 64-bit re- sult in two cycles. the multiplier permits maximum per- formance without requiring instruction scheduling, since the latency of the multiply is the same as the la- tency of other integer operations. high-performance multiplication benefits imaging, signal processing, and state modeling applications. complete set of common peripherals the am29240eh microcontroller series minimizes sys- tem cost by incorporating a complete set of system facili- ties commonly found in embedded applications, eliminating the cost of additional components. the on- chip functions include: a rom controller, a dram con- troller, a peripheral interface adapter, a dma controller, a programmable i/o port, a parallel port, up to two serial ports, and an interrupt controller. a video interface is also included in the am29240eh and am29245eh mi- crocontrollers for printer, scanner, and other imaging ap- plications. these facilities allow many simple systems to be built using only the am29240eh microcontroller se- ries, external rom, and/or dram memory. rom controller the rom controller supports four individual banks of rom or other static memory, each with its own timing characteristics. each rom bank may be a different size and may be either 8, 16, or 32 bits wide. the rom banks can appear as a contiguous memory area of up to 64 mbytes in size. the rom controller also supports byte, half-word, and word writes to the rom memory space for devices such as flash eproms and srams. dram controller the dram controller supports four separate banks of dynamic memory. each bank may be a different size and must be 32 bits wide. the dram banks can appear as a contiguous memory area of up to 64 mbytes in size. the dram controller supports two- or three-cycle accesses (programmable by software), with single-cycle page- mode and burst-mode accesses. burst accesses are supported at two initial, one burst, or three initial, one burst. peripheral interface adapter the peripheral interface adapter (pia) permits glueless interfacing to as many as six external peripheral chips. the pia allows for additional system features imple- mented by external peripheral chips. dma controller the dma controller provides up to four channels for transferring data between the dram and internal or ex- ternal peripherals. fly-by dma transfers data directly between an external peripheral and dram or rom, permitting very high data bandwidth. the peripheral must support the timing of the memory (dram or rom). the transfer occurs at the rate of one 32-bit word per cycle, if dram page-mode accesses or rom burst-mode or single-cycle accesses are enabled. for page-mode dram, the tdma signal is asserted on the rising edge following the last access. for an initial access, tdma is asserted simultaneously with dack x. dma wait states and peripheral wait states are ignored
p r e l i m i n a r y 8 am29240 eh microcontroller series ? during fly-by transfers. a higher fly-by dma transfer can interrupt a lower fly-by transfer. refresh does not pre-empt a fly-by transfer. a dma transfer continues until either dreqx is deasserted, the transfer is interrupted by a higher priority dma, or the count terminate enable (cte) bit is set. no refreshes will occur until the fly-by transfer is completed, so fly-by transfers must be less than one refresh interval in length. the dreqx signal must be configured as level- sensitive in the dram control register. parity checking and generation cannot be performed during a fly-by transfer. note also that zero-wait-state rom cannot be used with fly-by dma. i/o port the i/o port permits direct access to 16 individually pro- grammable external input/output signals. eight of these signals can be configured to cause interrupts. parallel port the parallel port implements a bidirectional ibm pc- compatible parallel interface to a host processor. serial port the serial port implements up to two full-duplex uarts. serializer/deserializer the serializer/deserializer (video interface) on the am29240eh and am29245eh microcontrollers permits direct connection to a number of laser-marking engines, video displays, or raster input devices such as scanners. interrupt controller the interrupt controller generates and reports the status of interrupts caused by on-chip peripherals. wide range of price/performance points to reduce design costs and time-to-market, the product designer can use the am29200 microcontroller family and one basic system design as the foundation for an entire product line. from this design, numerous imple- mentations of the product at various levels of price and performance may be derived with minimum time, effort, and cost. the am29240eh risc microcontroller series supports this capability through various combinations of on-chip caches, programmable memory widths, programmable wait states, burst-mode and page-mode access sup- port, bus compatibility, and 29k family software compat- ibility. a system can be upgraded using various memory architectures without hardware and software redesign. the rom controller accommodates memories that are either 8, 16, or 32 bits wide, and the dram controller ac- commodates dynamic memories that are 32 bits wide. this unique feature provides a flexible interface to low- cost memory, as well as a convenient, flexible upgrade path. for example, a system can start with a 16-bit rom memory design and can subsequently improve perfor- mance by migrating to a 32-bit rom memory design. one particular advantage is the ability to add memory in half-megabyte increments. this provides significant cost savings for applications that do not require larger memory upgrades. the am29200, am29202, am29205, am29240, am29245, and am29243eh microcontrollers allow us- ers to address an extremely wide range of cost perfor- mance points, with higher performance and lower cost than existing designs based on cisc microprocessors. glueless system interfaces the am29240eh microcontroller series also minimizes system cost by providing a glueless attachment to exter- nal roms, drams, and other peripheral components. processor outputs have edge-rate control that allows them to drive a wide range of load capacitances with low noise and ringing. this eliminates the cost of external logic and buffering. bus and software compatibility compatibility within a processor family is critical for achieving a rational, easy upgrade path. processors in the am29240eh microcontroller series are all members of a bus-compatible family of risc microcontrollers. all members of this familyethe am29205, am29202, am29200, am29240, am29245, and am29243eh mi- crocontrollerseallow improvements in price, perfor- mance, and system capabilities without requiring that users redesign their system hardware or software. bus compatibility ensures a convenient upgrade path for fu- ture systems. the am29240eh microcontroller series is available in a 208-pin plastic quad flat-pack (pqfp) package. the am29240eh microcontroller series is signal-compatible with the am29200 and the am29205 microcontrollers. moreover, the am29240eh microcontroller series is binary compatible with existing risc microcontrollers and other members of the 29k family (the am29000, am29005, am29030, am29035, am29040, and am29050 microprocessors, as well as the am29200, am29202, and am29205 microcontrollers). the am29240eh microcontroller series provides a migra- tion path to low-cost, high-performance, highly inte- grated systems from other 29k family members, without requiring expensive rewrites of application software. debugging and testing the am29240eh microcontroller series provides de- bugging and testing features at both the software and hardware levels.
p r e l i m i n a r y 9 am29240 eh microcontroller series ? software debugging is facilitated by the instruction trace facility and instruction breakpoints. instruction tracing is accomplished by forcing the processor to trap after each instruction has been executed. instruction breakpoints are implemented by the halt instruction or by a software trap. the processor provides several additional features to assist system debugging and testing: the test/development interface is composed of a group of pins that indicate the state of the processor and control the operation of the processor. a traceable cache feature permits a hardware- development system to track accesses to the on- chip caches, permitting a high level of visibility into processor operation. an ieee std 1149.1-1990 (jtag) compliant stan- dard test access port and boundary-scan architec- ture. the test access port provides a scan interface for testing processor and system hardware in a pro- duction environment, and contains extensions that allow a hardware-development system to control and observe the processor without interposing hard- ware between the processor and system. performance overview the am29240eh microcontroller series offers a signifi- cant margin of performance over cisc microprocessors in existing embedded designs, since the majority of pro- cessor features were defined for the maximum achiev- able performance at very low cost. this section describes the features of the am29240eh microcontrol- ler series from the point of view of system performance. instruction timing the am29240eh microcontroller series uses an arith- metic/logic unit, a field shift unit, and a prioritizer to execute most instructions. each of these is organized to operate on 32-bit operands and provide a 32-bit result. all operations are performed in a single cycle. the performance degradation of load and store opera- tions is minimized in the am29240eh microcontroller series by overlapping them with instruction execution, by taking advantage of pipelining, by an on-chip data cache, and by organizing the flow of external data into the processor so that the impact of external accesses is minimized. pipelining instruction operations are overlapped with instruction fetch, instruction decode and operand fetch, instruction execution, and result write-back to the register file. pipeline forwarding logic detects pipeline dependencies and routes data as required, avoiding delays that might arise from these dependencies. pipeline interlocks are implemented by processor hardware. except for a few special cases, it is not necessary to rearrange programs to avoid pipeline dependencies, although this is some- times desirable for performance. on-chip instruction and data caches on-chip instruction and data caches satisfy most proces- sor fetches without wait states. the caches are pipelined for best performance. the reload policies minimize the amount of time spent waiting for reload, while optimizing the benefit of locality of reference. burst-mode and page-mode memories the am29240eh microcontroller series directly sup- ports burst-mode memories. the burst-mode memory supplies instructions at the maximum bandwidth, with- out the complexity of an external cache or the perfor- mance degradation due to cache misses. the processor can also use the page-mode capability of common drams to improve the access time in cases where page-mode accesses can be used. instruction set overview all 29k family members employ a three-address instruc- tion set architecture. the compiler or assembly-lan- guage programmer is given complete freedom to allocate register usage. there are 192 general-purpose registers, allowing the retention of intermediate calcula- tions and avoiding needless data destruction. instruc- tion operands may be contained in any of the general-purpose registers, and the results may be stored into any of the general-purpose registers. the am29240eh microcontroller series instruction set contains 117 instructions that are divided into nine classes. these classes are integer arithmetic, compare, logical, shift, data movement, constant, floating point, branch, and miscellaneous. the floating-point instruc- tions are not executed directly, but are emulated by trap handlers. all directly implemented instructions are capable of executing in one processor cycle, with the exception of interrupt returns, loads, and stores. data formats the am29240eh microcontroller series defines a word as 32 bits of data, a half-word as 16 bits, and a byte as 8 bits. the hardware provides direct support for word- integer (signed and unsigned), word-logical, word-bool- ean, half-word integer (signed and unsigned), and char- acter data (signed and unsigned). word-boolean data is based on the value contained in the most significant bit of the word. the values true and false are represented by the most significant bit values 1 and 0, respectively. other data formats, such as character strings, are sup- ported by instruction sequences. floating-point formats
p r e l i m i n a r y 10 am29240 eh microcontroller series ? (single and double precision) are defined for the proces- sor; however, there is no direct hardware support for these formats in the am29240eh microcontroller series. protection the am29240eh microcontroller series offers two mutu- ally exclusive modes of executionethe user and super- visor modesethat restrict or permit accesses to certain processor registers and external storage locations. the register file may be configured to restrict accesses to supervisor-mode programs on a bank-by-bank basis. memory management unit the am29240eh microcontroller series provides a memory-management unit (mmu) for translating virtual addresses into physical addresses. the page size for translation ranges from 1 kbyte to 16 mbytes in powers of 4. the am29245eh and am29240eh microcontrol- lers each have a single, 16-entry tlb. the am29243eh microcontroller has dual 16-entry tlbs, each capable of mapping pages of different size. interrupts and traps when the microcontroller takes an interrupt or trap, it does not automatically save its current state information in memory. this lightweight interrupt and trap facility greatly improves the performance of temporary inter- ruptions such as simple operating-system calls that re- quire no saving of state information. in cases where the processor state must be saved, the saving and restoring of state information is under the con- trol of software. the methods and data structures used to handle interruptseand the amount of state savedemay be tailored to the needs of a particular system. interrupts and traps are dispatched through a 256-entry vector table that directs the processor to a routine that handles a given interrupt or trap. the vector table may be relocated in memory by the modification of a proces- sor register. there may be multiple vector tables in the system, though only one is active at any given time. the vector table is a table of pointers to the interrupt and trap handlers, and requires only 1 kbyte of memory. the processor performs a vector fetch every time an inter- rupt or trap is taken. the vector fetch requires at least three cycles, in addition to the number of cycles required for the basic memory access. pin descriptions a23a0 address bus (output, synchronous) the address bus supplies the byte address for all ac- cesses, except for dram accesses. for dram ac- cesses, multiplexed row and column addresses are provided on a14a1. a2a0 are also used to provide a clock to an optional burst-mode eprom. bootw boot rom width (input, asynchronous) this input configures the width of rom bank 0, so the rom can be accessed before the rom configuration has been set by the system initialization software. the bootw signal is sampled during and after a processor reset. if bootw is high before and after reset (tied high), the boot rom is 32 bits wide. if bootw is low before and after reset (tied low), the boot rom is 16 bits wide. if bootw is low before reset and high after reset (tied to reset ), the boot rom is 8 bits wide. this signal has special hardening against metastable states, allow- ing it to be driven with a slow-rise-time signal and permit- ting it to be tied to reset . burst burst-mode access (output, synchronous) this signal is asserted to perform sequential accesses from a burst-mode device. cas 3cas 0 column address strobes, byte 30 (output, synchronous) a high-to-low transition on these signals causes the dram selected by ras 3ras 0 to latch the column ad- dress and complete the access. to support byte and half-word writes, column address strobes are provided for individual dram bytes. cas 3 is the column address strobe for the drams, in all banks, attached to id31id24. cas 2 is for the drams attached to id23id16, and so on. these signals are also used in other special dram cycles. cntl1cntl0 cpu control (input, asynchronous, internal pull-ups) these inputs specify the processor mode: load test instruction, step, halt, or normal. dack ddack a dma acknowledge d through a (output, synchronous) these signals acknowledge an external transfer on a dma channel. dma acknowledgments are not dedi- cated to a particular dma channeleeach channel spec- ifies which acknowledge line, if any, it is using. only one
p r e l i m i n a r y 11 am29240 eh microcontroller series ? channel at a time can use either dack d, dack c, dack b, or dack a, and the same channel uses the re- spective dreqddreqa signal for transfer requests. dma transfers can occur to and from internal peripher- als independent of these acknowledgments. the dack d and dack c signals are supported on the am29240eh and am29243eh microcontrollers only. dreqddreqa dma request d through a (input, asynchronous, pull-up resistors) these inputs request an external transfer on a dma channel. dma requests are not dedicated to a particular channeleeach channel specifies which request line, if any, it is using. only one channel at a time can use either dreqd, dreqc, dreqb, or dreqa. this channel ac- knowledges a transfer using the respective dack d dack a signal. these requests are individually program- mable to be either level- or edge-sensitive for either po- larity of level or edge. dma transfers can occur to and from internal peripherals independent of these requests. the dma request/acknowledge pairs dreqa/ dack a and dreqb/ dack b correspond to the am29200 micro- controller signals dreq0/dack 0 and dreq1/dack 1, respectively. the pin placement reflects this correspon- dence, and a processor reset dedicates these request/ acknowledge pairs to dma channels 0 and 1, respectively. this permits backward-compatible up- grade to an am29200 microcontroller. the dreqd and dreqc signals are supported on the am29240eh and am29243eh microcontrollers only. dsr a data set ready, port a (output, synchronous) this indicates to the host that the serial port is ready to transmit or receive data on serial port a. dtr a data terminal ready, port a (input, asynchronous) this indicates to the processor that the host is ready to transmit or receive data on serial port a. gack external memory grant acknowledge (output, synchronous) this signal indicates to an external device that it has been granted an access to the processor's rom or dram, and that the device should provide an address. the processor can be placed into a slave configuration that allows tracing of a master processor. in this configu- ration, gack is used to indicate that the processor pipe- line was held during the previous processor cycle. greq external memory grant request (input, synchronous, pull-up resistor) this signal is used by an external device to request an access to the processor's rom or dram. to perform this access, the external device supplies an address to the rom controller or dram controller. to support a hardware-development system, greq should be either tied high or held at a high-impedance state during a processor reset. id31id0 instruction/data bus (bidirectional, synchronous) the instruction/data bus (id bus) transfers instructions to, and data to and from the processor. idp3idp0 instruction/data parity (bidirectional, synchronous) if parity checking is enabled by the pce bit of the dram control register, idp3idp0 are parity bits for the id bus during dram accesses. idp3 is the parity bit for id31id24, idp2 is the parity bit for id23id16, and so on. if parity is enabled, the processor drives idp3idp0 with valid parity during dram writes, and expects idp3idp0 to be driven with valid parity during dram reads. these signals are supported on the am29243eh microcontroller only. inclk input clock (input) this is an oscillator input at twice the system operating frequency. intr 3intr 0 interrupt requests 30 (input, asynchronous, internal pull-up resistors) these inputs generate prioritized interrupt requests. the interrupt caused by intr 0 has the highest priority, and the interrupt caused by intr 3 has the lowest prior- ity. the interrupt requests are masked in prioritized or- der by the interrupt mask field in the current processor status register and are disabled by the da and di bits of the current processor status register. these signals have special hardening against metastable states, al- lowing them to be driven with slow-transition-time signals. lsync line synchronization (input, asynchronous) this signal indicates the start of a raster line. this si gnal is supported on the am29240eh and am29245eh mi- crocontrollers only.
p r e l i m i n a r y 12 am29240 eh microcontroller series ? memclk memory clock (output) memclk is an output clock only. it operates at the sys- tem operating frequency, which is half of the inclk fre- quency. most processor inputs and outputs are synchronous to memclk. note that memclk as an in- put is not supported on the am29240eh microcontroller series. memdrv memclk drive enable (input, internal pull-up resistor) the memdrv signal is reserved on the am29240eh microcontroller series. this pin should be either tied high or left unconnected. pack parallel port acknowledge (output, synchronous) this signal is used by the processor to acknowledge a transfer from the host or to indicate to the host that data has been placed on the port. pautofd parallel port autofeed (input, asynchronous) this signal is used by the host to indicate how line feeds should be performed or is used to indicate that the host is busy and cannot accept a data transfer. pbusy parallel port busy (output, synchronous) this indicates to the host that the parallel port is busy and cannot accept a data transfer. piacs 5piacs 0 peripheral chip selects, regions 50 (output, synchronous) these signals are used to select individual peripheral devices. dma channels may be programmed to use dedicated chip selects during an external peripheral access. piaoe peripheral output enable (output, synchronous) this signal enables the selected peripheral device to drive the id bus. piawe peripheral write enable (output, synchronous) this signal causes data on the id bus to be written into the selected peripheral. pio15pio0 programmable input/output (input/output, asynchronous) these signals are available for direct software control and inspection. pio15pio8 may be individually pro- grammed to cause processor interrupts. these signals have special hardening against metastable states, al- lowing them to be driven with slow-transition-time signals. the pio signals are sampled during a processor reset. after reset, the sampled value is held in the pio input register. this sampled value is supplied the first time this register is read, unless the read is preceded by write to the pio input register or by a read or write of any oth- er pio register. this may be used to indicate system configuration information to the processor during a reset. poe parallel port output enable (output, synchronous) this signal enables an external data buffer containing data from the host to drive the id bus. pstrobe parallel port strobe (input, asynchronous) this signal is used by the host to indicate that data is on the parallel port or to acknowledge a transfer from the processor. psync page synchronization (input/output, asynchronous) this signal indicates the beginning of a raster page. this signal is supported on the am29240eh and am29245eh microcontrollers only. pwe parallel port write enable (output, synchronous) this signal writes a buffer with data on the id bus. then, the buffer drives data to the host. r/w read/write (output, synchronous) during an external rom, dram, dma, or pia access, this signal indicates the direction of transfer: high for a read and low for a write. ras 3ras 0 row address strobe, banks 30 (output, synchronous) a high-to-low transition on one of these signals causes a dram in the corresponding bank to latch the row ad- dress and begin an access. ras 3 starts an access in dram bank 3, and so on. these signals also are used in other special dram cycles.
p r e l i m i n a r y 13 am29240 eh microcontroller series ? reset reset (input, asynchronous) this input places the processor in the reset mode. this signal has special hardening against metastable states, allowing it to be driven with a slow-rise-time signal. romcs 3romcs 0 rom chip selects, banks 30 (output, synchronous) a low level on one of these signals selects the memory devices in the corresponding rom bank. romcs 3 se- lects devices in rom bank 3, etc. the timing and access parameters of each bank are individually programmable. romoe rom output enable (output, synchronous) this signal enables the selected rom bank to drive the id bus. it is used to prevent bus contention when switch- ing between different rom banks or switching between a rom bank and another device or dram bank. rswe rom space write enable (output, synchronous) this signal is used to write an alterable memory in a rom bank (such as an sram or flash eprom). rxda receive data, port a (input, asynchronous) this input is used to receive serial data to serial port a. rxdb receive data, port b (input, asynchronous) this input is used to receive data to serial port b. this signal is supported on the am29240eh and am29243eh microcontrollers only. stat2stat0 cpu status (output, synchronous) these outputs indicate information about the processor or the current access for the purposes of hardware debug. tck test clock input (input, asynchronous, pull-up resistor) this input is used to operate the test access port. the state of the test access port must be held if this clock is held either high or low. this clock is internally synchro- nized to memclk for certain operations of the test ac- cess port controller, so signals internally driven and sampled by the test access port are synchronous to processor internal clocks. tdi test data input (input, synchronous to tck, pull-up resistor) this input supplies data to the test logic from an external source. it is sampled on the rising edge of tck. if it is not driven, it appears high internally. tdma terminate dma (input/output, synchronous) this signal is either an input or an output as controlled by the corresponding dma control register. as an input, this signal can be asserted during an external dma transfer (non-fly-by) to terminate the transfer after the current access. the tdma input is ignored during fly-by transfers. as an output, this signal is asserted to indicate the final transfer of a sequence. tdo test data output (three-state output, synchronous to tck) this output supplies data from the test logic to an exter- nal destination. it changes on the falling edge of tck. it is in the high-impedance state except when scanning is in progress. tms test mode select (input, synchronous to tck, pull-up resistor) this input is used to control the test access port. if it is not driven, it appears high internally. tr /oe video dram transfer/output enable (output, synchronous) this signal is used with video drams to transfer data to the video shift register. it is also used as an output en- able in normal video dram read cycles. this signal is supported on the am29240eh and am29245eh micro- controllers only. trap 1trap 0 trap requests 10 (input, asynchronous, internal pull-ups) these inputs generate prioritized trap requests. the trap caused by trap 0 has the highest priority. these trap requests are disabled by the da bit of the current processor status register. these signals have special hardening against metastable states, allowing them to be driven with slow-transition-time signals.
p r e l i m i n a r y 14 am29240 eh microcontroller series ? trist three-state control (input, asynchronous, pull-up resistor) this input is asserted to force all processor outputs into the high-impedance state. this signal is tied high through an internal pull-up resistor. trst test reset input (input, asynchronous, pull-up resistor) this input asynchronously resets the test access port. if trst is not driven, it appears high internally. trst must be tied to reset , even if the test access port is not being used. txda transmit data, port a (output, asynchronous) this output is used to transmit serial data from serial port a. txdb transmit data, port b (output, asynchronous) this output is used to transmit data from serial port b. this signal is supported on the am29240eh and am29243eh microcontrollers only. uclk uart clock (input) this is an oscillator input for generating the uart (seri- al port) clock. to generate the uart clock, the oscillator frequency may be divided by any amount up to 65,536. the uart clock operates at 16 times the serial port's baud rate. as an option, uclk may be driven with memclk or inclk. it can be driven with ttl levels. vclk video clock (input, asynchronous) this clock is used to synchronize the transfer of video data. as an option, vclk may be driven with memclk or inclk. it can be driven with ttl levels. this si gnal is supported on the am29240eh and am29245eh mi- crocontrollers only. vdat video data (input/output, synchronous to vclk) this is serial data to or from the video device. this si gnal is supported on the am29240eh and am29245eh mi- crocontrollers only. wait add wait states (input, synchronous, internal pull-up) external accesses are normally timed by the processor. however, the wait signal may be asserted during a pia, rom, or dma access to extend the access indefinitely. for external dma accesses, the number of wait states taken by the dram controller (this includes peripheral read and write wait states during dma transfers) is deter- mined by the actual value in the dmawait field of the dma control register or the number of wait states speci- fied by the iowait field in the pia control register, whichever is greater. warn warn (input, asynchronous, edge-sensitive, internal pull-up) a high-to-low transition on this input causes a non- maskable warn trap to occur. this trap bypasses the normal trap vector fetch sequence, and is useful in situa- tions where the vector fetch may not work (e.g., when data memory is faulty). this signal has special harden- ing against metastable states, allowing it to be driven with a slow-transition-time signal. warn must be held active for at least four system clocks for the processor to recognize it. we write enable (output, synchronous) this signal is used to write the selected dram bank. aearly writeo cycles are used so the dram data inputs and outputs can be tied to the common id bus. product enhancements programmable dram timing through bit 24 in the dram control register, the dram controller now supports programmable dram timing, for either two- or three-cycle simple accesses, with single-cycle page-mode accesses. the new bit defined below. bit 24: programmable dram timing (pdt)e a 1 in this bit sets the dram timing to 2/1, for two-cycle simple accesses and single-cycle page-mode accesses. a 0 in this bit sets the dram timing to 3/1, for three-cycle sim- ple accesses and single-cycle page-mode accesses. features no longer supported the following features are no longer supported on the am29240eh, am29245eh, and am29243eh micro- controllers: 33 mhz operating frequency scalable clocking ? technology (also known as turbo mode or clock doubling) 16-bit dram memory memdrv signal memclk as an input
p r e l i m i n a r y 15 am29240 eh microcontroller series ? connection diagram 208-pin pqfp top side view 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 am29240eh microcontroller series note: pin 1 is marked for orientation.
p r e l i m i n a r y 16 am29240 eh microcontroller series ? pqfp pin designations (pin number) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 reserved 53 reserved 105 reserved 157 reserved 2 memclk 54 v cc 106 v cc 158 v cc 3 memdrv 55 gnd 107 gnd 159 gnd 4 inclk 56 reserved 108 reserved 160 pio12 5 v cc 57 txdb 3 109 a23 161 pio11 6 gnd 58 rxdb 3 110 a22 162 pio10 7 id31 59 dtr a 111 a21 163 pio9 8 id30 60 rxda 112 a20 164 pio8 9 id29 61 uclk 113 a19 165 pio7 10 id28 62 dsr a 114 a18 166 pio6 11 id27 63 txda 115 a17 167 pio5 12 id26 64 romcs 3 116 a16 168 pio4 13 id25 65 romcs 2 117 gnd 169 gnd 14 id24 66 romcs 1 118 v cc 170 v cc 15 gnd 67 romcs 0 119 a15 171 pio3 16 v cc 68 v cc 120 a14 172 pio2 17 id23 69 gnd 121 a13 173 pio1 18 id22 70 burst 122 a12 174 pio0 19 id21 71 rswe 123 a11 175 tdo 20 id20 72 romoe 124 a10 176 stat2 21 id19 73 ras 3 125 a9 177 stat1 22 id18 74 ras 2 126 a8 178 stat0 23 id17 75 ras 1 127 gnd 179 vdat 2 24 id16 76 ras 0 128 v cc 180 psync 2 25 gnd 77 cas 3 129 a7 181 gnd 26 v cc 78 cas 2 130 a6 182 v cc 27 id15 79 v cc 131 a5 183 greq 28 id14 80 gnd 132 a4 184 dreqb 29 id13 81 cas 1 133 a3 185 dreqa 30 id12 82 cas 0 134 a2 186 tdma 31 id11 83 tr /oe 135 a1 187 trap 0 32 id10 84 we 136 a0 188 trap 1 33 id9 85 gack 137 gnd 189 intr 0 34 id8 86 piacs 5 138 v cc 190 intr 1 35 gnd 87 piacs 4 139 bootw 191 intr 2 36 v cc 88 piacs 3 140 wait 192 intr 3 37 id7 89 piacs 2 141 pautofd 193 gnd 38 id6 90 v cc 142 pstrobe 194 v cc 39 id5 91 gnd 143 pwe 195 warn 40 id4 92 piacs 1 144 poe 196 vclk 2 41 id3 93 piacs 0 145 pack 197 lsync 2 42 id2 94 piawe 146 pbusy 198 tms 43 id1 95 piaoe 147 gnd 199 trst 44 id0 96 r/ w 148 v cc 200 tck 45 gnd 97 dack b 149 pio15 201 tdi 46 v cc 98 dack a 150 pio14 202 reset 47 idp3 1, 3 99 dack d 3 151 pio13 203 cntl1 48 idp2 1, 3 100 dack c 3 152 dreqd 3 204 cntl0 49 idp1 1, 3 101 v cc 153 dreqc 3 205 trist 50 idp0 1, 3 102 gnd 154 gnd 206 v cc 51 gnd 103 reserved 155 v cc 207 gnd 52 reserved 104 reserved 156 reserved 208 reserved notes: 1. defined as no-connect on am29240eh microcontroller. 2. defined as no-connect on am29243eh microcontroller. 3. defined as no-connect on am29245eh microcontroller.
p r e l i m i n a r y 17 am29240 eh microcontroller series ? pqfp pin designations (pin name) pin name pin no. pin name pin no. pin name pin no. pin name pin no. a0 136 gnd 91 intr 0 189 reset 202 a1 135 gnd 102 intr 1 190 romcs 0 67 a2 134 gnd 107 intr 2 191 romcs 1 66 a3 133 gnd 117 intr 3 192 romcs 2 65 a4 132 gnd 127 lsync 2 197 romcs 3 64 a5 131 gnd 137 memclk 2 romoe 72 a6 130 gnd 147 memdrv 3 rswe 71 a7 129 gnd 154 pack 145 rxda 60 a8 126 gnd 159 pautofd 141 rxdb 3 58 a9 125 gnd 169 pbusy 146 stat0 178 a10 124 gnd 181 piacs 0 93 stat1 177 a11 123 gnd 193 piacs 1 92 stat2 176 a12 122 gnd 207 piacs 2 89 tck 200 a13 121 reserved 208 piacs 3 88 tdi 201 a14 120 greq 183 piacs 4 87 tdma 186 a15 119 id0 44 piacs 5 86 tdo 175 a16 116 id1 43 piaoe 95 tms 198 a17 115 id2 42 piawe 94 tr /oe 83 a18 114 id3 41 pio0 174 trap 0 187 a19 113 id4 40 pio1 173 trap 1 188 a20 112 id5 39 pio2 172 trist 205 a21 111 id6 38 pio3 171 trst 199 a22 110 id7 37 pio4 168 txda 63 a23 109 id8 34 pio5 167 txdb 3 57 bootw 139 id9 33 pio6 166 uclk 61 burst 70 id10 32 pio7 165 reserved 1 cas 0 82 id11 31 pio8 164 v cc 5 cas 1 81 id12 30 pio9 163 v cc 16 cas 2 78 id13 29 pio10 162 v cc 26 cas 3 77 id14 28 pio11 161 v cc 36 cntl0 204 id15 27 pio12 160 v cc 46 cntl1 203 id16 24 pio13 151 v cc 54 dack a 98 id17 23 pio14 150 v cc 68 dack b 97 id18 22 pio15 149 v cc 79 dack c 3 100 id19 21 poe 144 v cc 90 dack d 3 99 id20 20 pstrobe 142 v cc 101 dreqa 185 id21 19 psync 2 180 v cc 106 dreqb 184 id22 18 pwe 143 v cc 118 dreqc 3 153 id23 17 r/w 96 v cc 128 dreqd 3 152 id24 14 ras 0 76 v cc 138 dsr a 62 id25 13 ras 1 75 v cc 148 dtr a 59 id26 12 ras 2 74 v cc 155 gack 85 id27 11 ras 3 73 v cc 158 gnd 6 id28 10 reserved 52 v cc 170 gnd 15 id29 9 reserved 53 v cc 182 gnd 25 id30 8 reserved 56 v cc 194 gnd 35 id31 7 reserved 103 v cc 206 gnd 45 idp0 1, 3 50 reserved 104 vclk 2 196 gnd 51 idp1 1, 3 49 reserved 105 vdat 2 179 gnd 55 idp2 1, 3 48 reserved 108 wait 140 gnd 69 idp3 1, 3 47 reserved 156 warn 195 gnd 80 inclk 4 reserved 157 we 84 notes: 1. defined as no-connect on am29240eh microcontroller. 2. defined as no-connect on am29243eh microcontroller. 3. defined as no-connect on am29245eh microcontroller.
p r e l i m i n a r y 18 am29240 eh microcontroller series ? am29240eh microcontroller logic symbol 4 2 romcs 3romcs 0 stat2stat0 a23a0 id31id0 psync intr 3intr 0 reset inclk trap 1trap 0 3 24 tdo r/ w 32 4 romoe burst rswe ras 3ras 0 4 cas 3cas 0 4 we tr /oe piacs 5piacs 0 6 piaoe piawe trst tdi tck tms wait warn bootw dreqddreqa dack ddack a gack greq pio15pio0 pstrobe pautofd pbusy pack poe pwe uclk rxdbrxda txdbtxda dsr a dtr a vclk lsync vdat 16 memclk 2 memdrv trist cntl1cntl0 2 2 tdma 4 4 am29240eh microcontroller
p r e l i m i n a r y 19 am29240 eh microcontroller series ? am29245eh microcontroller logic symbol 4 2 romcs 3romcs 0 stat2stat0 a23a0 id31id0 psync intr 3intr 0 reset inclk trap 1trap 0 3 24 tdo r/ w 32 4 romoe burst rswe ras 3ras 0 4 cas 3cas 0 4 we tr /oe piacs 5piacs 0 6 piaoe piawe trst tdi tck tms wait warn bootw dreqbdreqa dack bdack a gack greq pio15pio0 pstrobe pautofd pbusy pack poe pwe uclk rxda txda dsr a dtr a vclk lsync vdat 16 memclk memdrv trist cntl1cntl0 2 tdma 2 2 am29245eh microcontroller
p r e l i m i n a r y 20 am29240 eh microcontroller series ? am29243eh microcontroller logic symbol 4 2 romcs 3romcs 0 stat2stat0 a23a0 id31id0 intr 3intr 0 reset inclk trap 1trap 0 3 24 tdo r/ w 32 4 romoe burst rswe ras 3ras 0 4 cas 3cas 0 4 we tr /oe piacs 5piacs 0 6 piaoe piawe trst tdi tck tms wait warn bootw dreqddreqa dack ddack a gack greq pio15pio0 pstrobe pautofd pbusy pack poe pwe uclk rxdbrxda txdbtxda dsr a dtr a 16 memclk 2 memdrv trist cntl1cntl0 2 2 tdma idp3idp0 4 4 4 am29243eh microcontroller
p r e l i m i n a r y 21 am29240 eh microcontroller series ? absolute maximum ratings storage temperature 65 c to +125 c . . . . . . . . . . . . voltage on any pin with respect to gnd 0.5 v to v cc +2.4 . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device reliability. operating ranges commercial (c) devices case temperature (t c )0 c to +85 c . . . . . . . . . . . . . . supply voltage (v cc ) +3 v to +3.6 v . . . . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges preliminary symbol parameter description test conditions min max unit v il input low voltage 0.5 0.8 v v ih input high voltage 2.0 v cc +2.4 v v ilinclk inclk input low voltage 0.5 0.8 v v ihinclk inclk input high voltage 2.4 5.5 v v ol output low voltage for all outputs except memclk i ol = 3.2 ma 0.5 v v oh output high voltage for all outputs except memclk i oh = 400 m a 2.4 v i li input leakage current 0.45 v v in v cc 0.45 v note 1 10 or +10/200 m a i lo output leakage current 0.45 v v out v cc 0.45 v 10 m a i ccop operating power-supply current with respect to memclk v cc = 3.6 v, outputs floating; holding reset active at 25 mhz 8 ma/mhz v olc memclk output low voltage i olc = 20 ma 0.6 v v ohc memclk output high voltage i ohc = 20 ma 2.4 v i osgnd memclk gnd short circuit current v cc = 3.3 v 100 ma i osvcc memclk v cc short circuit current v cc = 3.3 v 100 ma notes: 1. the low input leakage current for the inputs cntl1cntl0, intr 3intr 0 , trap 1trap 0, dreqddreqa, tck, tdi, reset , trst , tms, greq , warn , memdrv, wait , and trist is 200 m a. these pins have internal pull-up resistors. capacitance preliminary symbol parameter description test conditions min max unit c in input capacitance 15 pf c inclk inclk input capacitance 15 pf c memclk memclk capacitance fc = 10 mhz 20 pf c out output capacitance 20 pf c i/o i/o pin capacitance 20 pf note: limits guaranteed by characterization.
p r e l i m i n a r y 22 am29240 eh microcontroller series ? switching characteristics over commercial operating ranges preliminary 16 mhz 20 mhz 25 mhz no. parameter description test conditions 1 min max min max min max unit 1 inclk period (=0.5t) 30 50 25 50 20 50 ns 2 inclk high time 10 8 6 ns 3 inclk low time 10 8 6 ns 4 inclk rise time 0 5 0 5 0 5 ns 5 inclk fall time 0 5 0 5 0 5 ns 6 memclk delay from inclk note 1c, 3 1 7 1 7 1 7 ns 8 memclk high time note 1c 0.5t3 0.5t3 0.5t3 ns 9 memclk low time note 1c 0.5t3 0.5t3 0.5t3 ns 10 memclk rise time note 1c 1 4 1 4 1 4 ns 11 memclk fall time note 1c 1 4 1 4 1 4 ns 12a synchronous output valid delay from memclk rising edge pio15pio0, stat2stat0, piacs 5piacs 0, and ras 3ras 0 note 1a 1 13 1 12 1 11 ns cas 3cas 0 rising edge/ cas 3cas 0 falling edge notes 1b, 4b 1 17/11 1 15/9 1 13/7 ns all others note 1b 1 12 1 11 1 10 ns 12b synchronous output valid delay from memclk falling edge pio15pio0, stat2stat0, piacs 5piacs 0 note 1a 1 12 1 11 1 10 ns ras 3ras 0 note 1b 1 15 1 14 1 13 ns cas 3cas 0 falling edge notes 1b, 4b 1 11 1 9 1 7 ns all others note 1b 1 11 1 10 1 9 ns 13 synchronous output disable delay from memclk rising edge 1 12 1 11 1 10 ns 14 synchronous input setup time to memclk rising edge id31id0 and idp3idp0 for dram access parity enabled note 4a 18 16 15 ns id31id0 for dram access parity disabled note 4a 10 8 7 ns all others 10 8 7 ns 15 available cas access time (tcas t setup ) note 4b 25 24 19 ns 16a synchronous input hold time to memclk rising edge note 4a 0 0 0 ns 16b synchronous input hold time to cas rising edge note 4b 3 3 3 ns
p r e l i m i n a r y 23 am29240 eh microcontroller series ? switching characteristics over commercial operating ranges (continued) preliminary 25 mhz 20 mhz 16 mhz no. unit max min max min max min test conditions 1 parameter description 17 asynchronous input pulse width lsync and psync note 5 note 5 note 5 all others 4t 4t 4t ns 18 uclk period note 2 30 25 20 ns vclk period note 2 25 20 15 ns 19 uclk high time note 2 10 8 6 ns vclk high time note 2 8 6 4 ns 20 uclk low time note 2 10 8 6 ns vclk low time note 2 8 6 4 ns 21 uclk rise time note 2 0 5 0 5 0 5 ns vclk rise time note 2 0 3 0 3 0 3 ns 22 uclk fall time note 2 0 5 0 5 0 5 ns vclk fall time note 2 0 3 0 3 0 3 ns 23 synchronous output valid delay from vclk rise and fall note 6 1 16 1 14 1 14 ns 24 input setup time to vclk rise and fall notes 6, 7 10 9 9 ns 25 input hold time to vclk rise and fall notes 6, 7 0 0 0 ns 26 ras low time 50 50 50 ns 27 cas low time 13 13 13 ns notes: 1. all outputs driving 80 pf, measured at v ol = 1.5 v and v oh = 1.5 v using the switching test circuit shown on page 33. for higher capacitance loads: a. add 1 ns output delay per 15 pf loading above 80 pf, up to 150 pf total. the minimum delay from piaoe to piacs x is 0 ns if the capacitance loading on piacs x is equal to or higher than the capacitance loading on piaoe . b. add 1 ns output delay per 25 pf loading above 80 pf, up to 300 pf total. for 2/1 dram timing, in order to meet the setup time (t asr ) from a23a0 to ras 3ras 0 for dram, the capacitive loading of a23a0 must not exceed the capacitance loading of ras 3ras 0 by more than 150 pf. c. add 1 ns of output delay for memclk to drive an external load of 100 pf. 2. vclk and uclk can be driven with ttl inputs. uclk must be tied high if it is unused. 3. maximum inclk-to-memclk delay can be decreased by 0.5 ns for each 10 ma increase in i ol up to the maximum of 20 ma, i.e., 6 ns maximum delay at i ol = 20 ma. 4. id31id0 and idp3idp0 are sampled on the rising edge of memclk for all non-dram accesses, simple dram accesses, and the first access of a dram page-mode access. id31id0 and idp3idp0 are sampled on the rising edge of cas x for all dram page-mode accesses, except the first access of a dram page-mode access. (see figures 112 on pages 2532.) a. applies to id31id0 and idp3idp0 for simple dram accesses and the first access of a dram page-mode access. b. applies to id31id0 and idp3idp0 for dram page-mode accesses, except the first access of a dram page-mode access. when id31id0 and idp3idp0 are sampled on cas x, there is no additional setup time required for id31id0 and idp3idp0 when the parity is enabled. 5. lsync and psync minimum width is two bit-times. a bit-time is one period of the internal video clock, which is determined by the clkdiv field in the video control register and vclk. 6. active vclk edge depends on the clki bit in the video control register. 7. lsync and psync can be treated as synchronous signals by meeting the setup and hold times, though the synchronization delay still applies.
p r e l i m i n a r y 24 am29240 eh microcontroller series ? switching waveforms 16a 14 5 3 2 1 25 inclk memclk 4 0.8 v 1.5 v 2.0 v 10 9 8 0.8 v 1.5 v v cc 0.6 v 11 6 synchronous outputs synchronous inputs asynchronous inputs uclk, vclk 18 21 20 19 0.8 v 1.5 v 2.0 v 22 vclk-relative outputs vclk-relative inputs 1.5 v note: video timing may be relative to vclk falling edge if clk = 1. 13 17 23 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v note: during ac testing, all inputs are driven at v il = 0.4 v, v ih = 2.4 v. 24 cas x note: see note 4 on page 23. 12a 16b 1.5 v 12b 15
p r e l i m i n a r y 25 am29240 eh microcontroller series ? switching waveforms (continued) a14a1 column address 16a 14 1.5 v 1.5 v 1.5 v id31id0 idp3idp0 r/w memclk we tr /oe ras 3ras 0 cas 3cas 0 note: the ras 3ras 0 signals are asserted and deasserted on the falling edge of memclk . row address figure 1. simple 3/1 dram read cycle a14a1 id31id0 idp3idp0 memclk r/w we tr /oe ras 3ras 0 cas 3cas 0 row address column address data figure 2. simple 3/1 dram write cycle
p r e l i m i n a r y 26 am29240 eh microcontroller series ? switching waveforms (continued) a14a1 1.5 v column address +2/4 +4/8 +6/12 memclk r/w we tr /oe ras 3ras 0 cas 3cas 0 row address id31id0 idp3idp0 note: the ras 3ras 0 signals are asserted and deasserted on the falling edge of memclk . 1.5 v 1.5 v 1.5 v 16b 15 + t/2 15 16b 15 16b 15 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 16b 1.5 v figure 3. 3/1 dram page-mode read data id31id0 idp3idp0 memclk we tr /oe r/w ras 3ras 0 cas 3cas 0 row address column address +2/4 +4/8 +6/12 a14a1 data data data figure 4. 3/1 dram page-mode write
p r e l i m i n a r y 27 am29240 eh microcontroller series ? switching waveforms (continued) row addr memclk a14a1 ras 3ras 0 id31id0 idp3idp0 we column address cas 3cas 0 r/w tr /oe 1.5 v 16a 14 1.5 v 1.5 v figure 5. simple 2/1 dram read cycle row addr data column address memclk a14a1 id31id0 idp3idp0 we cas 3cas 0 r/w tr /oe ras 3ras 0 figure 6. simple 2/1 dram write cycle
p r e l i m i n a r y 28 am29240 eh microcontroller series ? switching waveforms (continued) row addr column address +2/4 +4/8 +6/12 memclk a14a1 ras 3ras 0 id31id0 ipd3idp0 we cas 3cas 0 r/w tr /oe 1.5 v 1.5 v 1.5 v 1.5 v 16b 15 + t/2 15 16b 15 16b 15 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v note : may be repeated up to 1-kbyte address boundary. 1.5 v 16b figure 7. 2/1 dram page-mode read cycle note : may be repeated up to 1-kbyte address boundary. data data column address +2/4 +4/8 +6/12 data data row addr memclk a14a1 ras 3ras 0 id31id0 idp3idp0 we cas 3cas 0 r/w tr /oe figure 8. 2/1 dram page-mode write cycle
p r e l i m i n a r y 29 am29240 eh microcontroller series ? switching waveforms (continued) row addr col addr col addr col addr memclk a14a1 ras x id31id0 we cas x r/w tr /oe dreqx dack x piacs x piaoe piawe row addr note : may be repeated up to 1-kbyte address boundary. data data data figure 9. fly-by dma reads (read peripheral, write dram)e3/1 dram accesses
p r e l i m i n a r y 30 am29240 eh microcontroller series ? switching waveforms (continued) row addr data data data col addr col addr col addr memclk a14a1 ras x id31id0 we cas x r/w tr /oe dreqx dack x piacs x piaoe piawe row addr note : may be repeated up to 1-kbyte address boundary. figure 10. fly-by dma writes (read dram, write peripheral)e3/1 dram accesses
p r e l i m i n a r y 31 am29240 eh microcontroller series ? switching waveforms (continued) row addr memclk a14a1 ras x id31id0 we cas x r/w tr /oe data dreqx dack x piacs x piaoe piawe data col addr col addr row addr col addr data note : may be repeated up to 1-kbyte address boundary. figure 11. fly-by dma reads (read peripheral, write dram)e2/1 dram accesses
p r e l i m i n a r y 32 am29240 eh microcontroller series ? switching waveforms (continued) row addr data data data col addr col addr row addr col addr memclk a14a1 ras x id31id0 we cas x r/w tr /oe dreqx dack x piacs x piaoe piawe note : may be repeated up to 1-kbyte address boundary. figure 12. fly-by dma writes (read dram, write peripheral)e2/1 dram accesses
p r e l i m i n a r y 33 am29240 eh microcontroller series ? switching test circuit v am29240eh microcontroller v l i ol = 3.2 ma * vref = 1.5 v i oh = 400 m a * c l v h pin under test note: *all outputs except memclk. memclk is tested with i ol = 20 ma and i oh = 20ma. thermal characteristics the am29240eh microcontroller series is specified for operation with case temperature ranges for a commercial temperature device. case temper ature is measured at the top center of the pqfp package as shown in figure 13. q ja q ca q jc t c q ja = q jc + q ca figure 13. thermal resistance e c/watt the various temperatures and thermal resistances can be determined using the equations shown in figure 14 along with information given in table 2. (the variable p is power in watts.) q ja = q jc + q ca p=i ccop ? freq ? v cc t j =t c +p ? q jc t j =t a +p ? q ja t c =t j p ? q jc t c =t a +p ? q ca t a =t j p ? q ja t a =t c p ? q ca figure 14. thermal characteristics equations table 2. thermal characteristics ( c/watt) surface mounted parameter c/watt q ja junction-to-ambient 38 q jc junction-to-case 8 q ca case-to-ambient 30
p r e l i m i n a r y 34 am29240 eh microcontroller series ? physical dimensions pqr 208, trimmed and formed plastic quad flat pack notes: all measurements are in millimeters unless otherwise noted. not to scale. for reference only. 30.40 30.80 27.90 28.10 25.50 ref. pin 156 pin 208 pin 52 pin 104 pin 1 i.d. 27.90 28.10 see detail x seating plane 0.50 basic 0.25 min. 3.20 3.60 3.95 max. s s a d b a c top view side view 25.50 ref. 30.40 30.80
p r e l i m i n a r y 35 am29240 eh microcontroller series ? pqr 208 (continued) 0.20 min. flat shoulder 7 typ. 0 min. 0.30 0.05 r gage plane 0.25 0.50 0.75 0 7 7 typ. detail x 0.18 0.30 0.13 0.20 3.95 max section ss 0.13 0.20 0.18 0.30 notes: all measurements are in millimeters unless otherwise noted. not to scale. for reference only.
p r e l i m i n a r y 36 am29240 eh microcontroller series ? physical dimensions (continued) solder land recommendationse208-lead pqfp 29.80 ref. 0.50 typ. 0.30 typ. 1.80 typ. 25.50 typ. 31.60 ref. 28.00 typ. notes: all measurements are in millimeters unless otherwise noted. not to scale. for reference only. trademarks copyright ? 1997 advanced micro devices, inc. all rights reserved. amd, the amd logo, am29000, minimon29k, and fusion29k are registered trademarks; 29k, amd facts-on-demand, am29005, am29030, am29035, am29040, am29050, am29200, am29202, am29205, am29240, am29243, am29245, and traceable cache are trademarks of ad- vanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

▲Up To Search▲

Price & Availability of 20068

	To Download 20068 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .