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infineon technologies 1 12.01 hys64/72d32000/64020gu unbuffered ddr-i sdram-modules 2.5 v 184-pin unbuffered ddr-i sdram modules 256 mbyte & 512 mbyte modules pc1600 & pc2100 the hys64/72d32000gu and hys64/72d64020gu are industry standard 184-pin 8-byte dual in- line memory modules (dimms) organized as 32m 64 and 64m 64 for non-parity and 32m x 72 and 64m x 72 for ecc main memory applications. the memory array is designed with 256mbit double data rate synchronous drams. a variety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. ? 184-pin unbuffered 8-byte dual-in-line ddr-i sdram non-parity and ecc-modules for pc and server main memory applications one bank 32m 64, 32m x 72 and two bank 64m x 64, 64m 72 organization jedec standard double data rate synchronous drams (ddr-i sdram) single + 2.5 v ( 0.2 v) power supply built with 256 mbit ddr-i sdrams organised as 32mb x 8 in 66-lead tsopii package programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs and outputs sstl_2 compatible serial presence detect with e 2 prom jedec standard mo-206 form factor: 133.35 mm 31.75 mm 4.00 mm max. jedec standard reference layout gold plated contacts performance: -7 -8 unit component speed grade ddr266a ddr200 module speed grade pc2100 pc1600 f ck clock frequency (max.) @ cl = 2.5 143 125 mhz f ck clock frequency (max.) @ cl = 2 133 100 mhz
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 2 12.01 ordering information type compliance code description sdram technology pc2100 (cl=2) : hys64d32000gu-7-a pc2100-20330-b1 one bank 256 mb dimm 256 mbit hys64d32000gu-7-b pc2100-20330-a1 one bank 256 mb dimm 256 mbit hys72d32000gu-7-a pc2100-20330-b1 one bank 256 mb ecc-dimm 256 mbit hys72d32000gu-7-b pc2100-20330-a1 one bank 256 mb ecc-dimm 256 mbit hys64d64020gu-7-a hys64d64020gu-7-b pc2100-20330-b1 two banks 512 mb dimm 256 mbit hys72d64020gu-7-a hys72d64020gu-7-b pc2100-20330-b1 two banks 512 mb ecc-dimm 256 mbit pc1600 (cl=2): HYS64D32000GU-8-A pc1600-20220-b1 one bank 256 mb dimm 256 mbit hys64d32000gu-8-b pc1600-20220-a1 one bank 256 mb dimm 256 mbit hys72d32000gu-8-a pc1600-20220-b1 one bank 256 mb ecc-dimm 256 mbit hys72d32000gu-8-b pc1600-20220-a1 one bank 256 mb ecc-dimm 256 mbit hys64d64020gu-8-a hys64d64020gu-8-b pc1600-20220-b1 two banks 512 mb dimm 256 mbit hys72d64020gu-8-a hys72d64020gu-8-b pc1600-20220-b1 two banks 512 mb ecc-dimm 256 mbit note: all part numbers end with a place code, designating the silicon-die revision. reference information available on request. example: hys 72d32000gu-8-a, indicating rev.a dies are used for the sdram components. the compliance code is printed on the module labels and describes the speed sort fe. ? pc2100 ? , the latencies (f.e. ? 20330 ? means cas latency = 2, trcd latency = 3 and trp latency =3 ) and the raw card used for this module.
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 3 12.01 pin definitions and functions a0 - a12 address inputs s0, s1 chip selects ba0, ba1 bank selects v dd power (+ 2.5 v) dq0 - dq63 data input/output v ss ground cb0 - cb7 check bits (x72 organization only) v ddq i/o driver power supply ras row address strobe v ddid vdd indentification flag cas column address strobe v ref i/o reference supply we read/write input v ddspd serial eeprom power supply cke0 - cke1 clock enable scl serial bus clock dqs0 - dqs8 sdram low data strobes sda serial bus data line clk0 - clk2, sdram clock (positive lines) sa0 - sa2 slave address select clk0 - clk2 sdram clock (negative lines) nc no connect dm0 - dm8 dqs9 - dqs17 sdram low data mask/ high data strobes note: s1 and cke1 are used on two bank modules only address format density organization memory banks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 256 mb 32m x 64 1 32m x 8 8 13/2/10 8k 64 ms 7.8 s 256 mb 32m x 72 1 32m x 8 9 13/2/10 8k 64 ms 7.8 s 512 mb 64m 64 2 32m x 8 16 13/2/10 8k 64 ms 7.8 s 512 mb 64m 72 2 32m x 8 18 13/2/10 8k 64 ms 7.8 s
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 4 12.01 pin configuration frontside frontside backside backside pin# symbol pin# symbol pin# symbol pin# symbol 1 vref 48 a0 93 vss 140 nc / dm8/dqs17 2 dq0 49 nc / cb2 94 dq4 141 a10 3 vss 50 vss 95 dq5 142 nc / cb6 4 dq1 51 nc / cb3 96 vddq 143 vddq 5 dqs0 52 ba1 97 dm0/dqs9 144 nc / cb7 6dq2 key 98 dq6 key 7 vdd 53 dq32 99 dq7 145 vss 8 dq3 54 vddq 100 vss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 nc 56 dqs4 102 nc 148 vdd 11 vss 57 dq34 103 nc 149 dm4/dqs13 12 dq8 58 vss 104 vddq 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 vss 15 vddq 61 dq40 107 dm1/dqs10 153 dq44 16 clk1 62 vddq 108 vdd 154 ras 17 clk1 63 we 109 dq14 155 dq45 18 vss 64 dq41 110 dq15 156 vddq 19 dq10 65 cas 111 cke1 157 s0 20 dq11 66 vss 112 vddq 158 s1 21 cke0 67 dqs5 113 nc (ba2) 159 dm5/dqs14 22 vddq 68 dq42 114 dq20 160 vss 23 dq16 69 dq43 115 nc / a12 161 dq46 24 dq17 70 vdd 116 vss 162 dq47 25 dqs2 71 nc 117 dq21 163 nc 26 vss 72 dq48 118 a11 164 vddq 27 a9 73 dq49 119 dm2/dqs11 165 dq52 28 dq18 74 vss 120 vdd 166 dq53 29 a7 75 clk2 121 dq22 167 nc (a13) 30 vddq 76 clk2 122 a8 168 vdd 31 dq19 77 vddq 123 dq23 169 dm6/dqs15 32 a5 78 dqs6 124 vss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 vss 80 dq51 126 dq28 172 vddq 35 dq25 81 vss 127 dq29 173 nc 36 dqs3 82 vddid 128 vddq 174 dq60 37 a4 83 dq56 129 dm3/dqs12 175 dq61 38 vdd 84 dq57 130 a3 176 vss 39 dq26 85 vdd 131 dq30 177 dm7/dqs16 40 dq27 86 dqs7 132 vss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 vss 88 dq59 134 nc / cb4 180 vddq 43 a1 89 vss 135 nc / cb5 181 sa0 44 nc / cb0 90 nc 136 vddq 182 sa1 45 nc / cb1 91 sda 137 ck0 183 sa2 46 vdd 92 scl 138 ck0 184 vddspd 47 nc / dqs8 139 vss note: pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are nc ( ? no-connects ? ) on x64 organised non-ecc modules. a12 is used for 256mbit based modules only
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 5 12.01 block diagram: one bank 32m x 64 ddr-i sdram dimm module hys64d32000gu using x8 organized sdrams dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0/dqs9 i/o 5 i/o 4 i/o 3 i/o 2 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 i/o 5 i/o 4 i/o 3 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 i/o 5 i/o 4 i/o 3 i/o 2 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 i/o 5 i/o 4 i/o 3 i/o 2 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4/dqs13 i/o 5 i/o 4 i/o 3 i/o 2 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 i/o 5 i/o 4 i/o 3 i/o 2 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 i/o 5 i/o 4 i/o 3 i/o 2 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 i/o 5 i/o 4 i/o 3 i/o 2 dm7/dqs16 a0 -a11, a12 a0 - a11,a12: sdrams d0 - d7 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda ras ras : sdrams d0 - d7 cas cas : sdrams d0 - d7 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d7 s 0 ba0 - ba1 ba0, ba1: sdrams d0 - d7 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 2 dqs dqs dqs dqs notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 2 sdrams 3 sdrams 3 sdrams * wire per clock loading table/w iring diagrams *ck2/ck2 v dd, v ss v ddq vref v ddid d0 - d7 d0 - d7 d0 - d7 cs cs cs cs cs cs cs cs
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 6 12.01 block diagram: two bank 64m x 64 ddr-i sdram dimm modules hys64d64020gu using x8 organized sdrams dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0/dqs9 dm d8 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 dm d9 i/o 5 i/o 4 i/o 3 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 dm d10 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 dm d11 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4/dqs13 dm d12 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 dm d13 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 dm d14 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 dm d15 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm7/dqs16 a0 - a12 a0 - a12: sdrams d0 - d15 a0 se rial pd a1 a2 sa0 sa1 sa2 scl sda ras ras : sdrams d0 - d15 cas cas : sdrams d0 - d15 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d15 s 0 s 1 cke1 cke: sdrams d8 - d15 ba0, ba1 ba0, ba1: sdrams d0, d15 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 2 i/o 5 dqs dqs dqs dqs dqs dqs dqs dqs dqs * clock w iring *ck0/ck0 clock input sdrams *ck1/ck1 4 sdrams 6 sdrams 6 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq v dd, v ss v ddq vref v ddid d0 - d15 d0 - d15 d0 - d15 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 7 12.01 block diagram: one bank 32m x 72 ddr-i sdram dimm module hys72d32000gu using x8 organized sdrams dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0/dqs9 i/o 5 i/o 4 i/o 3 i/o 2 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 i/o 5 i/o 4 i/o 3 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 i/o 5 i/o 4 i/o 3 i/o 2 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 i/o 5 i/o 4 i/o 3 i/o 2 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4/dqs13 i/o 5 i/o 4 i/o 3 i/o 2 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 i/o 5 i/o 4 i/o 3 i/o 2 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 i/o 5 i/o 4 i/o 3 i/o 2 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 i/o 5 i/o 4 i/o 3 i/o 2 dm7/dqs16 a0 - a11,a12 a0 - a11, a12: sdrams d0 - d8 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda ras ras : sdrams d0 - d8 cas cas : sdrams d0 - d8 cke0 cke: sdrams d0 - d8 we we : sdrams d0 - d8 s 0 ba0, ba1 ba0, ba1: sdrams d0 - d8 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 2 dqs dqs dqs dqs notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq * clock w iring *ck0/ck0 clock input sdrams *ck1/ck1 3 sdrams 3 sdrams 3 sdrams * wire per clock loading table/w iring diagrams *ck2/ck2 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm d8 dm8/dqs17 dqs8 dqs v dd, v ss v ddq vref v ddid d0 - d8 d0 - d8 d0 - d8 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 cs cs cs cs cs cs cs cs cs
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 8 12.01 block diagram: two bank 64m x 72 ddr-i sdram dimm modules hys72d64020gu using x8 organized sdrams dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0/dqs9 dm d9 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 dm d10 i/o 5 i/o 4 i/o 3 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 dm d11 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dm d12 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4/dqs13 dm d13 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 dm d14 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 dm d15 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 dm d16 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm7/dqs16 a0 - a12 a0 - a12: sdrams d0 - d17 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda ras ras : sdrams d0 - d17 cas cas : sdrams d0 - d17 cke0 cke: sdrams d0 - d8 we we : sdrams d0 - d17 s 0 s 1 cke1 cke: sdrams d9 - d17 ba0, ba1 ba0, ba1: sdrams d0 - d17 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 2 i/o 5 dqs dqs dqs dqs dqs dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 6 sdrams 6 sdrams 6 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm d8 dm dm8/dqs17 dqs8 dqs dqs v dd, v ss v ddq vref v ddid d0 - d17 d0 - d17 d0 - d17 cs cs cs cs cs cs cs cs cs cs i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 d17 cs cs cs cs cs cs cs cs
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 9 12.01 clock net wiring absolute maximum ratings parameter symbol limit values unit min. max. input / output voltage relative to v ss v in, v out ? 0.5 3.6 v power supply voltage on v dd /v ddq to v ss v dd, v ddq ? 0.5 3.6 v storage temperature range t stg -55 +150 o c power dissipation (per sdram component) p d ? 1w data out current (short circuit) i os ? 50 ma permanent device damage may occur if ? absolute maximum ratings ? are exceeded. functional operation should be restricted to recommended operation conditions. exposure to higher than recommended voltage for extended periods of time affect device reliability 4 dram loads dimm ck ck dram 1 dram2 dr am4 dr am5 dr am6 dram 1 cap. dram3 dr am5 cap. cap. dram 1 cap. dr am5 cap. cap. cap. dr am 1 dram5 cap. cap. dram3 dram2 dram6 co nnector co nnector dimm r = 120 r = 120 co nnector dimm co nnector dimm r =120 r =120 6 dram loads 3 dram loads 2 dram loads
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 10 12.01 supply voltage levels parameter symbol limit values unit notes min. nom. max. device supply voltage v dd 2.3 2.5 2.7 v ? output supply voltage v ddq 2.3 2.5 2.7 v 1) 1) under all conditions, v ddq must be less than or equal to v dd . input reference voltage v ref 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . termination voltage v tt v ref ? 0.04 v ref v ref +0.04 v 3) 3) v tt of the transmitting device must track v ref of the receiving device. eeprom supply voltage v ddspd 2.3 2.5 3.6 v dc operating conditions (sstl_2 inputs) ( v ddq =2.5v, t a =70 c, voltage referenced to v ss ) parameter symbol limit values unit notes min. max. dc input logic high v ih (dc) v ref +0.15 v ddq +0.3 v 1) 1) the relationship between the v ddq of the driving device and the v ref of the receiving device is what determines noise margins. however, in the case of v ih (max) (input overdrive), it is the v ddq of the receiving device that is referenced. in the case where a device is implemented such that it supports sstl_2 inputs but has no sstl_2 outputs (such as a translator), and therefore no v ddq supply voltage connection, inputs must tolerate input overdrive to 3.0 v (high corner v ddq + 300 mv). dc input logic low v il (dc) ? 0.30 v ref ? 0.15 v ? input leakage current i il ? 55 a 2) 2) for any pin under test input of 0 v v in v ddq + 0.3 v. values are shown per ddr-sdram component- output leakage current i ol ? 55 a 2)
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 11 12.01 operating, standby and refresh currents (pc1600) symbol parameter/condition HYS64D32000GU-8-A hys72d32000gu-8-a hys64d64020gu-8-a hys72d64020gu-8-a unit notes dram technology: 256mbit typ. typ. typ. typ. i dd0 operating current - one bank active - precharge ; t rc = t rc min ; t ck = 10 ns; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once per every two cycles 592 666 944 1062 ma 1,3 i dd1 operating current - one bank active / read / precharge ; burst = 4; reads; refer to the detailed test conditions in the component datasheet 568 639 920 1035 ma 1,3 i dd2p precharge power-down standby current : all banks idle; power-down mode; cke v il max ; t ck = 10 ns 88 99 176 198 ma 1,4 i dd2f precharge floating standby current : cs v ih min , all banks idle; cke v ih min ; t ck = 10 ns, address and other control inputs changing once per clock cycle, v in = v ref for dq, dqs and dm. 200 225 400 450 ma 1,4 i dd2q precharge quiet standby current : cs v ih min , all banks idle; cke v ih min ; t ck = 10 ns,address and other control inputs stable at v ih min or v il max ; v in = v ref for dq, dqs and dm. 192 216 383 432 ma 1,4 i dd3p active power-down standby current : one bank active; power-down mode; cke v il max ; t ck = 10 ns 88 99 176 198 ma 1,4 i dd3n active standby current : one bank; active / precharge;cs v ih min ; cke v ih min ; t rc = t ras max ; t ck = 10 ns; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 352 396 704 792 ma 1,4 i dd4r operating current - burst read: one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2; t ck = 10 ns; i out = 0ma 872 981 1224 1377 ma 1,3 i dd4w operating current - burst write: one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl = 2; t ck = 10 ns 872 981 1224 1377 ma 1,3 i dd5 auto-refresh current : t rc = t rfc min, distributed refresh 984 1107 1968 2214 ma 1,4 i dd6 self-refresh current : cke 0.2v 15.2 17.1 30.4 34.2 ma 1,2,4 i dd7 operating current - four bank operation ; four bank inter- leaving with bl=4; refer to the detailed test conditions in the component datasheet 1456 1638 1808 2034 ma 1,3 1. i dd currents are measured after the device is properly initialized. typical values are obtained from characteri- sation data measured at vdd = 2.5 v and r.t. with an input slew rate = 1v/ns. 2. enables on-chip refresh and address counters. 3. for two bank modules only : the other bank is in idd3n mode 4. for two bank modules only : both banks operate in the same current mode
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 12 12.01 operating, standby and refresh currents (pc2100) symbol parameter/condition hys64d32000gu-7-a hys72d32000gu-7-a hys64d64020gu-7-a hys72d64020gu-7-a unit notes dram technology: 256mbit typ. typ. typ. typ. i dd0 operating current - one bank active - precharge ; t rc = t rc min ; t ck = 7.5 ns; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once per every two cycles 680 765 1104 1242 ma 1,3 i dd1 operating current - one bank active / read / precharge ; burst = 4; reads; refer to the detailed test conditions in the component datasheet 704 792 1128 1269 ma 1,3 i dd2p precharge power-down standby current : all banks idle; power-down mode; cke v il max ; t ck = 7.5 ns 104 117 208 234 ma 1,4 i dd2f precharge floating standby current : cs v ih min , all banks idle; cke v ih min ; t ck = 7.5 ns, address and other control inputs changing once per clock cycle, v in = v ref for dq, dqs and dm. 232 261 464 522 ma 1,4 i dd2q precharge quiet standby current : cs v ih min , all banks idle; cke v ih min ; t ck = 7.5 ns,address and other control inputs stable at v ih min or v il max ; v in = v ref for dq, dqs and dm. 216 243 432 486 ma 1,4 i dd3p active power-down standby current : one bank active; power-down mode; cke v il max ; t ck = 7.5 ns 104 117 208 234 ma 1,4 i dd3n active standby current : one bank; active / precharge;cs v ih min ; cke v ih min ; t rc = t ras max ; t ck = 7.5 ns; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 424 477 848 954 ma 1,4 i dd4r operating current - burst read: one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2; t ck = 7.5 ns; i out = 0ma 1088 1224 1512 1701 ma 1,3 i dd4w operating current - burst write: one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl = 2; t ck = 7.5 ns 1112 1251 1536 1728 ma 1,3 i dd5 auto-refresh current : t rc = t rfc min, distributed refresh 1352 1521 2704 3042 ma 1,4 i dd6 self-refresh current : cke 0.2v 15.2 17.1 30.4 34.2 ma 1,2,4 i dd7 operating current - four bank operation ; four bank inter- leaving with bl=4; refer to the detailed test conditions in the component datasheet 1576 1773 2000 2250 ma 1,3 1. i dd currents are measured after the device is properly initialized. typical values are obtained from characteri- sation data measured at vdd = 2.5 v and r.t. with an input slew rate = 1v/ns. 2. enables on-chip refresh and address counters. 3. for two bank modules only : the other bank is in idd3n mode 4. for two bank modules only : both banks operate in the same current mode
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 13 12.01 electrical characteristics & ac timing for ddr-i components (for reference only) (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v) symbol parameter ddr266a -7 ddr200 -8 unit notes min max min max t ac dq output access time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4 t dqsck dqs output access time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4 t ch ck high-level width 0.45 0.55 0.45 0.55 t ck 1-4 t cl ck low-level width 0.45 0.55 0.45 0.55 t ck 1-4 t hp clock half period min (t cl, t ch) min (t cl, t ch) ns 1-4 t ck clock cycle time cl = 2.5 7 12 8 12 ns 1-4 t ck cl = 2.0 7.5 12 10 12 ns 1-4 t dh dq and dm input hold time 0.5 0.6 ns 1-4 t ds dq and dm input setup time 0.5 0.6 ns 1-4 t ipw control and addr. input pulse width (each input) 2.2 2.5 ns 1, 10 t dipw dq and dm input pulse width (each input) 1.75 2 ns 1-4, 11 t hz data-out high-impedence time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4, 5 t lz data-out low-impedence time from ck/ck ? 0.75 + 0.75 ? 0.8 + 0.8 ns 1-4, 5 t dqss write command to 1st dqs latching transition 0.75 1.25 0.75 1.25 t ck 1-4 t dqsq dqs-dq skew (for dqs & associated dq signals) + 0.5 + 0.6 ns 1-4 t qhs data hold skew factor + 0.75 + 1.0 ns 1-4 t qh data output hold time from dqs t hp -t qhs t hp -t qhs ns 1-4 t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 0.35 t ck 1-4 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 t ck 1-4 t dsh dqs falling edge hold time from ck (write cycle) 0.2 0.2 t ck 1-4 t mrd mode register set command cycle time 14 16 ns 1-4 t wpres write preamble setup time 0 0 ns 1-4, 7 t wpst write postamble 0.40 0.60 0.40 0.60 t ck 1-4, 6 t wpre write preamble 0.25 0.25 t ck 1-4 t is address and control input setup time fast slew rate 0.9 1.1 ns 2-4, 10,11 slow slew rate 1.0 1.1 ns t ih address and control input hold time fast slew rate 0.9 1.1 ns slow slew rate 1.0 1.1 ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck 1-4 t rpst read postamble 0.40 0.60 0.40 0.60 t ck 1-4 t ras active to precharge command 45 120,000 50 120,000 ns 1-4 t rc active to active/auto-refresh command period 65 70 ns 1-4
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 14 12.01 t rfc auto-refresh to active/auto-refresh command period 75 80 ns 1-4 t rcd active to read or write delay 20 20 ns 1-4 t rp precharge command period 20 20 ns 1-4 t rrd active bank a to active bank b command 15 15 ns 1-4 t wr write recovery time 15 15 ns 1-4 t dal auto precharge write recovery + precharge time (twr/tck) + (trp/tck) t ck 1-4,9 t wtr internal write to read command delay 1 1 t ck 1-4 t xsnr exit self-refresh to non-read command 75 80 ns 1-4 t xsrd exit self-refresh to read command 200 200 t ck 1-4 t refi average periodic refresh interval 128mbit based 15.6 15.6 s1-4, 8 256 mbit based 7.8 7.8 s1-4, 8 1. input slew rate >=1v/ns for ddr266 and = 1v/ns for ddr200. 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref. ck/ck slew rate are >= 1.0 v/ns. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac character- istics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parame- ters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifi- cations of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. for each of the terms, if not already an integer, round to the next highest integer. tck is equal to the actual system clock cycle time. 10. these parameters guarantee device timing, but they are not necessarily tested on each device 11. fast slew rate >= 1.0 v/ns , slow slew rate >= 0.5 v/ns and < 1v/ns for command/address and ck & ck slew rate >1.0 v/ns, measured between voh(ac) and vol(ac) electrical characteristics & ac timing for ddr-i components (for reference only) (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v) symbol parameter ddr266a -7 ddr200 -8 unit notes min max min max
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 15 12.01 spd codes for pc1600 modules ?-8? byte# description spd entry value hex 256mbyte one bank x64 256 mbyte one bank x72 512 mbyte two banks x64 512 mbyte two banks x72 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type ddr-sdram 07 3 number of row addresses 12 / 13 0d 4 number of column addresses 10 0a 5 number of dimm banks 1 / 2 01 01 02 02 6 module data width x64 / x72 40 48 40 48 7 module data width (cont ? d) 0 00 8 module interface levels sstl_2.5 04 9 sdram cycle time at cl = 2.5 8 ns 80 10 access time from clock at cl = 2.5 0.8 ns 80 11 dimm config non-ecc / ecc 00 02 00 02 12 refresh rate/type self-refresh, 7.8 s 82 13 sdram width, primary x8 08 14 error checking sdram data width na / x8 00 08 00 08 15 minimum clock delay for back-to-back random column address t ccd =1clk 01 16 burst length supported 2, 4 & 8 0e 17 number of sdram banks 4 04 18 supported cas latencies cas latency = 2 & 2.5 0c 19 cs latencies cs latency = 0 01 20 we latencies write latency = 1 02 21 sdram dimm module attributes unbuffered 20 22 sdram device attributes: general c0 23 min. clock cycle time at cas latency = 2 10.0 ns a0 24 access time from clock for cl = 2 0.8 ns 80 25 minimum clock cycle time at cl = 1.5 not supported 00 26 access time from clock at cl = 1.5 not supported 00 27 minimum row precharge time 20 ns 50 28 minimum row act. to row act. delay t rrd 15 ns 3c 29 minimum ras to cas delay t rcd 20 ns 50 30 minimum ras pulse width t ras 50 ns 32 31 module bank density (per bank) 256mbyte 40 32 addr. and command setup time 1.1 ns b0 33 addr. and command hold time 1.1 ns b0 34 data input setup time 0.6 ns 60 35 data input hold time 0.6 ns 60 36-40 superset information ? 00
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 16 12.01 41 minimum core cycle time trc 70 ns 46 42 min. auto refresh cmd cycle time trfc 80 ns 50 43 maximum clock cycle time tck 12 ns 30 44 max. dqs-dq skew tddsq 0.6 ns 3c 45 x-factor tqhs 1.0 ns a0 46-61 superset information - 00 62 spd revision revision 0.0 00 63 checksum for bytes 0 - 62 ? a7 b9 a8 ba 64 manufacturers jedec id code ? c1 65-71 manufacturer infineo(n) 72 module assembly location 73-90 module part number 91-92 module revision code 93-94 module manufacturing date 95-98 module serial number 99-127 128-255 open for customer use byte# description spd entry value hex 256mbyte one bank x64 256 mbyte one bank x72 512 mbyte two banks x64 512 mbyte two banks x72
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 17 12.01 spd codes for pc2100 modules ? -7 ? byte# description spd entry value hex 256mbyte one bank x64 256 mbyte one bank x72 512 mbyte two banks x64 512 mbyte two banks x72 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type ddr-sdram 07 3 number of row addresses 12/13 0d 4 number of column addresses 10 0a 5 number of dimm banks 1 / 2 01 01 02 02 6 module data width x64 / x72 40 48 40 48 7 module data width (cont ? d) 0 00 8 module interface levels sstl_2.5 04 9 sdram cycle time at cl = 2.5 7 ns 70 10 access time from clock at cl = 2.5 0.75 ns 75 11 dimm config non-ecc / ecc 00 02 00 02 12 refresh rate/type self-refresh, 7.8 s 82 13 sdram width, primary x8 08 14 error checking sdram data width na / x8 00 08 00 08 15 minimum clock delay for back-to-back random column address t ccd =1clk 01 16 burst length supported 2, 4 & 8 0e 17 number of sdram banks 4 04 18 supported cas latencies cas latency = 2 & 2.5 0c 19 cs latencies cs latency = 0 01 20 we latencies write latency = 1 02 21 sdram dimm module attributes unbuffered 20 22 sdram device attributes: general c0 23 min. clock cycle time at cas latency = 2 7.5 ns 75 24 access time from clock for cl = 2 0.75 ns 75 25 minimum clock cycle time at cl = 1.5 not supported 00 26 access time from clock at cl = 1.5 not supported 00 27 minimum row precharge time 20 ns 50 28 minimum row act. to row ac. delay t rrd 15 ns 3c 29 minimum ras to cas delay t rcd 20 ns 50 30 minimum ras pulse width t ras 45 ns 2d 31 module bank density (per bank) 256mbyte 40 32 addr. and command setup time 0.9 ns 90 33 addr. and command hold time 0.9 ns 90 34 data input setup time 0.5 ns 50 35 data input hold time 0.5 ns 50 36-40 superset information ? 00
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 18 12.01 41 minimum core cycle time trc 65 ns 41 42 min. auto refresh cmd cycle time trfc 75 ns 4b 43 maximum clock cycle time tck 12 ns 30 44 max. dqs-dq skew tddsq 0.5 ns 32 45 x-factor tqhs 0.75 ns 75 46-61 superset information - 00 62 spd revision revision 0.0 00 63 checksum for bytes 0 - 62 ? b2 c4 b3 c5 64 manufacturers jedec id code ? c1 65-71 manufacturer infineo(n) 72 module assembly location 73-90 module part number 91-92 module revision code 93-94 module manufacturing date 95-98 module serial number 99-127 128-255 open for customer use byte# description spd entry value hex 256mbyte one bank x64 256 mbyte one bank x72 512 mbyte two banks x64 512 mbyte two banks x72
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 19 12.01 package outlines - raw card b1 (one bank modules) ddr-sdram dimm module package l-dim-184-9 144 145 184 17.78 3 *) on ecc modules only 10.0 3 detail of contacts a 2.5 1 1.27 0.20 + 0.05 - + 0.20 - + 0.15 - 133.35 2.3 typ. 53 52 64.77 92 2.3 typ. 31.75 pin 1 + 0.13 - + 0.15 - 6.62 49.53 4.0 1.27 4.0 max. + 0.1 - pin 93 2.5d front view backside view detail of contacts b 3.8 typ. 2.175 6.35 1.8 0.9r *) *)
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 20 12.01 package outlines -raw card a1 (one bank modules) ddr-sdram dimm module package l-dim-184-29 144 145 184 17.78 3 *) on ecc modules only 10.0 3 detail of contacts a 2.5 1 1.27 0.20 + 0.05 - + 0.20 - + 0.15 - 133.35 2.3 typ. 53 52 64.77 92 2.3 typ. 31.75 pin 1 + 0.13 - + 0.15 - 6.62 49.53 4.0 1.27 4.0 max. + 0.1 - pin 93 2.5d front view backside view detail of contacts b 3.8 typ. 2.175 6.35 1.8 0.9r *)
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 21 12.01 package outlines - raw card b1 (two bank modules) ddr-sdram dimm module package two bank modules l-dim-184-9d 144 145 184 17.78 3 *) on ecc modules only 10.0 3 detail of contacts a 2.5 1 1.27 0.20 + 0.05 - + 0.20 - + 0.15 - 133.35 2.3 typ. 53 52 64.77 92 2.3 typ. 31.75 pin 1 + 0.13 - + 0.15 - 6.62 49.53 4.0 1.27 4.0 max. + 0.1 - pin 93 2.5d front view backside view detail of contacts b 3.8 typ. 2.175 6.35 1.8 0.9r *) *)
hys64/72d32000/64020gu unbuffered ddr-i sdram-modules infineon technologies 23 12.01

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