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?2008 scillc. all rights reserved. publication order number: may 2008 ? rev. 7 amis 52150/d amis-52150 low-power transceiver with clock and data recovery 1.0 introduction the amis-52150 is a cost-effective, ultra-low power single-chip wireless transceiver. it combines the proven amplitude shift ke y/on-off key (ask/ook) modulation technology of t he amis-52050 with data clock recovery. based on key features, such as dual indepe ndent receive channels, quick start crystal oscillator, sniff mode? signal acquisitio n, and data clock recovery, the amis-52150 is ideally suited for a wi de range of applications, includi ng point-to-point wireless data links, cost- optimized wireless monitor solutions, and very low power remote wireless sensors, among others. 2.0 key features ? data clock recovery ? auto slicing of data ? very low-power single-chip transceiver ? minimal external components ? low-power rc oscillator ? quick start crystal oscillator ? ultra-low power rf sniff mode?, with wake-up on rssi ? internal trim functions reduce external component requirements ? i 2 c control interface ? serial tx/rx data port ? clock generation for an external microprocessor ? wake-up on rssi ? antenna diversity dual receiver ? internal vco/pll tuning varactor ? wake-up interrupt to external controller
amis-52150 3.0 technical features ? operating frequency range: ? quick start, from 350mhz to 448mhz ? non-quick start, from 300mhz to 768mhz ? tx output power: +12dbm ? rx sensitivity: ? sniff mode: -93dbm minimum ? receive: -117dbm minimum @ 1kbps, with cdr ? data rate: ? 1-8kbps with manchester coding ? 1-16kbps with nrz data ? power requirements: ? receive: 7.5ma (continuous) ? transmit: 25ma @ full power (50 percent duty-cycle) ? sniff mode: 75ua (one percent duty-cycle) ? standby: 500na (rc oscillator running) ? operating voltage: 2.3v to 3.6v ? modulation: ask/ook ? xtal start time: 15us (quick start) ? sniff mode tm polling: 0.5ms to 16s (0.5ms or 64ms steps) ? pll lock time: <50us ? selectable data filter: up to 20khz ? internal trim functions: ? tx power (-3 to +12dbm) ? antenna impedance matching (two independent channels) ? xtal, for frequency and quick start ? rc oscillator frequency ? sniff mode tm , for data threshold ? data slice ? clock and data recovery (reduced data jitter) ? i 2 c interface: control bus ? serial interface: data input/output ? low frequency if ? internal if filtering ? package: 20-lead, 209mm ssop 4.0 functional block diagram the amis-52150 is a dual-channel receiver and a transmitter in a single, small outline package (fig. 1). the receiver provides for two independent receive channels with the signals combined in the data detection circuit. summing the signals allows the two channe ls to be used for antenna diversity optimization, without the need for complex protocols to select the strongest channel. the amis-52 150 can be programmed to be a single channel or a dual-channel receiver, re spectively. there exist internal trim functions for the rf r eceiver frequency, for tuning each input port, for setting the internal filt ers to match the data rate, and for setting the threshold l evel for acquiring an incoming signal, respectively. the receiver converts the received rf signal to a low frequency if. an rssi circuit determin es the strength of the received signal. a level detector samples the rssi signal level and compares that level to the slice threshold to recover the data. the slice threshold can be either set to a fixed level, or alternately, the transceiver can be configured to automati cally set the threshold level based on the incoming data. the transmitter is a high efficiency power amp lifier (pa) that is turned on or off by the serial data. the output power level i s adjustable. the frequency of the rf output can be tuned with an internal crysta l trim function, in order to conform to component and manufa cturing tolerances. in addition, the design of the tran sceiver is based on a number of unique features. the amis-52150 can be placed in a very low power state, with t he crystal oscillator being off wh ile the low power rc oscillator maintains the chip operation. in this low power state, the amis-52150 remains in the sleep mode until either the wake-up timer or an rev. 7 | page 2 of 25 | www.onsemi.com
amis-52150 external microcontroller wake up the device, respectively. the receiver can be also configured for operation in sniff mode tm , where by the device is programmed to wake up at regular intervals to sniff for received rf signals, returning to the sleep mode if a sig nal is not detected. the amis-52150 cont ains a quick start circuit as well, which results in full operation of the crystal oscillator in a n extremely short time, in turn leading to much lower power consumption as co mpared to other transceiver products available in the market. in the amis-52150, a programmable pll is used to synchronize the data clock to the received data. this feature enables reducing much o f the jitter in the data signal. these functions will be described in more detail later in the document. figure 1: amis-52150 block diagram 5.0 operating and maximum specifications table 1: operating conditions sym. parameter min. typ. max. units vdd positive supply 2.3 3 3.6 v vss ground 0.0 0.1 v temp temperature range 0 +25 +50 o c table 2: absolute maximum ratings sym. parameter min. max. units vdd positive supply +4 v rfin max rf input rx1/rx2 +10 dbm vss ground 0.0 0.1 v vin logical i/p voltage -0.3 vdd+ 0.3 v tstrg storage temperature -40 +120 o c rev. 7 | page 3 of 25 | www.onsemi.com
amis-52150 table 3: absolute maximum ratings idd (supply current) typ. max. units conditions transmitting 20 25 ma 50% duty cycle receiving 7.5 10 ma sniff mode 75 ua 1% sniff cycle off 500 na rc osc off table 4: electrical charac teristics; digital inputs parameter min. typ. max. units vih 0.7*vdd v vil 0.3*vdd v iih +1.0 ua iil -1.0 ua i 2 c internal pull-up 15 20 k ? table 5: electrical charac teristics; digital outputs parameter min. typ. max. units voh 0.8*vdd v vol 0.4 v ioh -1.0 ma iol +1.0 ma i 2 c internal pull-up 15 20 k ? table 6: electrical char acteristics; analog tx parameter min. typ. max. units comments frequency range 402 403.5 405 mhz targeted 300 768 mhz non-quick start 350 448 mhz quick start modulation 1 8 kbps manchester-coded data 1 16 kbps nrz data max. output power 11 12 13 dbm on/off ratio 70 db transmit vco gain 75 mhz/v kvco -95 dbc/hz 10khz pll phase noise -97 dbc/hz 100khz harmonics -35 dbc with typical matching components crystal freq. spurs -50 dbc 50khz pll loop bandwidth time tx to rx 1 ms table 7: electrical char acteristics; analog rx parameter min. typ. max. units comments frequency range 402 403.5 405 mhz targeted 300 768 mhz non-quick start 350 448 mhz quick start modulation 1 8 kbps manchester-coded data 1 16 kbps nrz data rf input -117 -10 dbm noise figure 4.5 rf detect time 100 us in sniff mode tm time rx to tx 1 ms rev. 7 | page 4 of 25 | www.onsemi.com
amis-52150 6.0 pin definitions this section describes the pins of the amis-52150 package. table 8: pin description pin# name type comments 1 rx1 rf rf receive rf input 1 2 rx2 rf rf receive rf input 2 3 vco2 ana voltage controlled oscillator 2 4 vco1 ana voltage controlled oscillator 1 5 lpfilt ana loop filter 6 rssi/ bandgap out ana analog rssi output or bandgap output 7 nc no electrical connection 8 cref ana current bias precision resistor 9 gnd ana analog/digital ground 10 clkout dig rc, xtal, or data clock output 11 x1 ana xtal input 12 x2 ana xtal output 13 iic data dig iic interface data i/o 14 nc no electrical connection 15 iic clock dig iic interface clock 16 tx/rx data dig data transmit, data receive or recovered data 17 vdd ana positive power supply 18 rfpwr ana regulated voltage output for rf transmitter circuitry 19 rfout rf rf transmit rf output 20 rfgnd ana rf ground 7.0 package outline figure 2: package outline rev. 7 | page 5 of 25 | www.onsemi.com
amis-52150 table 9: package dimensions ; 209mil ssop inches millimeters dm min. max. min. max. a 0.068 0.078 1.73 2.00 a1 0.002 .20 0.05 a2 0.065 0.073 1.65` 1.85 b 0.009 0.015 0.22 0.38 d 0.271 0.295 6.90 7.5 e 0.291 0.323 7.40 0.820 e1 0.197 0.221 5.00 0.560 e 0.026 bsc 0.65 bsc 8.0 pin descriptions 8.1 rx1, rx2, rf input pins rx1 and rx2 are the rf antenna inputs to t he amis-52150. the internal circuit designs are identical between these inputs. for t he amis-52150 receiver inputs, rx1 and rx2, external components ar e required in order to match the low noise amplifier (lna) to external devices such as antennas. the external componen ts must provide a dc voltag e path to the rf ground. figure 3 suggests an external circuit for the receiver inputs at 403mhz. each circuit? s input impedance can be trimmed internally to compensate for manufacturing and external component tolerances. the circuits empl oy an lna, internal filters, a low frequency, intermediate fr equency (if), and a received signal strength indica tion (rssi) circuit to recover the ask/ook m odulated data. the signals in the two in put channels are ?summed? before the data recovery circuit. the functions of the receive circuits are cont rolled by writing to the registers shown in table 10 . table 10: receiver control register description rx1 or rx2 receiver register control register (hex) name bits states comments 0x00 ant1 trim all inverse relationship register value to internal capacitance 0x01 ant2 trim all inverse relationship register value to internal capacitance 0 antenna port is off ant1 enable 0 1 antenna port is on 0 antenna port is off 0x0c ant2 enable 1 1 antenna port is on figure 3: typical input impedance match to 50 ? rev. 7 | page 6 of 25 | www.onsemi.com
amis-52150 8.2 vco1, vco2, voltage cont rolled oscillator pins the vco1 and vco2 pins connect a parallel combination of a capacit or and an inductor to the amis-52150 internal voltage control led oscillator (vco). the external lc (parallel inductor and capaci tor) circuit sets the frequency of the inte rnal vco. the vco fre quency must be set to twice the value of the desired tx or rx frequenc y. typical components for the tuning of the vco at 402mhz are sh own in figure 4. the range of the vco frequency is from 600mhz to 1536mhz. the voltage on these pins can be used to det ermine proper operation of the pll/vco circuits. for further details, refer to the application note titled ?first time users guide to working with the transceiver ic?. table 11: vco control registers vco/pll control registers register (hex) name bits states comments 00 20ua 01 25ua 10 50ua* charge pump 0,1 11 100ua 000 180ua 001 220ua 010 260ua 011 300ua 100 340ua* 101 380ua 110 420ua vco current 2,3,4 111 460ua 0 divider is 64 0x06 pll divider 7 1 divider is 128 *denotes the normal value figure 4: typical components for vco tuning at 402mhz rev. 7 | page 7 of 25 | www.onsemi.com
amis-52150 8.3 lpfilt, loop filter pin the lpfilt pin connects the amis-52150 internal phase lock loop (pll) frequency synthesizer to an external loop filter (fig. 5) . an external loop filter allows the system designer to optimize t he operation of the amis-52150 in or der to meet the requirements f or a specific end application. for further det ails, refer to the application note titled ?extending to frequencies outside of the 40 3mhz target?. figure 5: typical loop filter 8.4 rssi/bg, analog output pin the rssi/bg pin is used to output either the signal from the r ssi circuits, or to output the vo ltage from the bandgap voltage r eference or a bypass capacitor node, respectively. the rssi output is a tr ue analog representation of the received signal level. the pin can also be programmed to output the voltage of the bandgap voltage reference. when using the amis-52150 in the clock and data recovery mode, a capacitor needs to be connected from the rssi/bg pin to ground. a typical value for this capacitor is 2.2nf. additional information on the cdr function can be found later in this document. table 12 presents the registers that control the function of the rssi/bg pin. table 12: rssvbg pin control registers rssi pin definition control registers register (hex) name bits states comments 0x0e bandgap on rssi 3 0 normal operation 1 bg output on rssi* 0x1e rssi ext amp 4 0 tri-stated 1 rssi signal *note that device needs to be in rx, tx or crysta l-on mode for bandgap voltage to be present on pin. 8.5 cref, current reference bias pin a resistor must be connected to the cref pin to provide a current bias to the internal bandgap voltage reference circuit. it i s critical that this resistor value is 33.2k ? (with one percent or better tolerance) to achiev e proper operation of the bandgap voltage reference. rev. 7 | page 8 of 25 | www.onsemi.com
amis-52150 8.6 gnd, ground pin the gnd pin is the ground connection for the digital and analog circuits. 8.7 clkout, internal clock output pin the clkout pin is an output for the rc oscillator, crystal oscill ator signal or the recovered data clock, respectively. the cry stal oscillator signal output can be divided by 2, 3 or 4. the pin can also be programmed to output the signal from the recovered d ata clock function. for more information about the clock and data recovery (cdr) function of the amis-52150, refer to the section of thi s document on clock and data recovery. the clkout pin function control registers are shown in table 13 . table 13: oscillator ou tput control registers clkout pin definition control registers register (hex) name bits states comments 0x0c clkout enable 7 0 clkout is enabled 1 clkout is disabled 0x0d clkout select 4,5 00 automatic control 01 rc osc 10 xtal 11 off 0x0e xtal divide 0,1 00 divide by 4 01 divide by 3 10 divide by 2 11 divide by 1 8.8 x1, x2, external crystal reference pins x1 and x2 pins connect a parallel resonance oscillator crystal to the amis-52150 internal oscillator circuit. the external cry stal should meet the requirements as listed in table 14. however, the two load capacitors should be sized slightly smaller than the recomme nded value for the crystal, because of the added capacitance due to t he internal trim circuit. for further details, refer to the ap plication note titled ?quick start crystal oscillator circuit operati on and set-up?. the crystal parameters are shown in table 14 . table 14: external crystal parameters parameter min. typ. max. units conditions crystal frequency 12.56 12.65 mhz targeted 9.375 24.0 non-quick start 10.9 14.0 quick start crystal esr 70 ? crystal tolerance 10 ppm load capacitance load capacitors should be smaller than recommended for the crystal to allow for frequency tuning 8.9 i 2 cdata, i 2 cclk, i 2 c control interface bus pins the amis-52150 implements an i 2 c serial 8-bit bi-directional interface with the pins i 2 cdata and i 2 cclk. the device implements the protocol for a slave device. the clock for the interface is generated by the external master device. the interface will support the normal (0 ? 100 kbits/second) or the fast (0 ? 400kbits/second) data modes. the interface conforms to the phillips specification for t he i 2 c bus standard. the pins have internal pull-up resistors. see table 15 and table 16 for some parameters of this interface. in addition, table 17 shows the details of regi ster that controls the i 2 c address increment function. table 15: internal i 2 c pull-up resistors rev. 7 | page 9 of 25 | www.onsemi.com
amis-52150 pin function typ. units i 2 cdata internal pull-up r 15 k ? i 2 cclk internal pull-up r 15 k ? table 16: i 2 c bus device addressing device address (bin) hex function amis-52150 01101000 68 device write amis-52150 01101001 69 device read table 17: i 2 c control register i 2 c control register register (hex) name bits states comments 0 increment after write 0x0c i 2 c address increment 2 1 do not increment the i 2 cdata and i 2 cclk lines are also used to signal to an external controller certain internal activities of the transceiver. the receiver is activated upon detection of rf energy during sniff mode tm operation. the wake-up timer can also be configured to wake-up the device in order to alert an external c ontroller to perform specific tasks, as defined by the system designer. 8.10 tx/rx, data input/output pin the transmit/receive (tx/rx) pin can be programmed to be either an input for rf transmissions, or an output for rf reception, o r the output of the rc oscillator signal, or the output of the recovered data from the cdr circuits, respectively. in transmit mode, this pin is the digital data input to the am is-52150 rf transmit circuit. the digital data results in the on and off cycling of the output power amplifier (pa) . the amis-52150 does not perform any protocol conversion on the data bit stream; it is simply a serial bit stream. the state of the tx/rx pin either turns the output amplifier on (enabling rf transmission) or turns the output amplifier off (disabling rf transmission). the tx/rx input can be inverted which causes the state control of the rf output ampl ifier to be inverted as well. in receive mode, this pin is the digital data output from the am is-52150 receivers. the received data is recovered as a high/lo w (digital ones and zeros) serial bit stream; the amis-52150 does not modify the received data protocol. the data output state due to the presence of energy in the receiver can be programmed to be either a high level or a low level at the tx/rx pin. an external con troller is needed to decode the information in the recovered data bit stream. when programmed to be an oscillator output, the tx/rx pin outputs the signal from the rc oscillator. this signal can be used to monitor the frequency of the rc oscillator in order to trim the frequency to the desired value. the tx/rx pin can be programmed to output the recovered data obta ined from the clock and data recovery circuits. in this case, the device must be programmed in the cdr mode. more information on cdr will be provided in a later section of this datasheet. the functions of the tx/rx port ar e controlled by the values of the register settings, as shown in table 18 . table 18: tx/rx pin definition control registers register (hex) name bits states comments 0 rx/tx normal 0x0e rc osc on tx/rx 2 1 rc osc output 0 normal levels 0x1e tx/rx invert 5 1 inverted 8.11 vdd, supply voltage pin the vdd pin is the power supply pin for the amis-52150. the volt age on this pin is typically 3.0v. please refer to the section ?operating and maximum specific ations? of this document for the vdd operating conditions. rev. 7 | page 10 of 25 | www.onsemi.com
amis-52150 8.12 rfpwr, dc voltage output pin in the amis-52150, a regulated dc voltage is generated and outputt ed at the rfpwr pin. this vo ltage should be fed through a dc connection to the rfout pin in order to power the output stage of the rf pa. the voltage level is adjusted based on the value o f the register setting, as shown in table 19 . table 19: tx voltage control register rfpwr voltage control register register (hex) name bits states comments 0x02 rfpwr trim all 0xff is highest power 8.13 rfout, rf output signal pin in the amis-52150, a high efficiency non-linear output driver is used to produce the high power rf signal. this driver must be connected through a dc connection to the rfpwr pin. external components are required to match the output to a 50 ? ? load, or to an external antenna, respectively. figure 6 shows a typical matching circuit for the rfout pin. 8.14 rfgnd, rf ground pin the rfgnd pin is the ground connection for the rf circuits in the device. figure 6: typical rfout output impedance match to 50 ? (402mhz) rev. 7 | page 11 of 25 | www.onsemi.com
amis-52150 9.0 circuit functional description the functions of the amis-52150 are presented in this sect ion. these functions are: ? receiver ? transmitter ? sniff ? quick start ? data detection ? clock and data recovery ? application wakeup ? i 2 c protocol ? registers ? alternative wake-up ? power-on-reset/brown-out 9.1 receiver rf signals often suffer from reflections along the path of propagat ion. these reflected signals arrive at the receiver antenna with different phases or time delays. the different phases of the reflected signals cause the signal strength at the receiver to var y. this variation can be large enough to cause the receiver to miss in formation. the amis-52150 sums the signals from the dual receiver channels within the data detection circuits. this reduces the effe ct of multi-path reflections. proper operation requires a) tr imming aimed at minimizing the frequency tolerances, b)tuning of the oscillator frequency, c)sele ction of the data rate filters, and d)setti ng of a signal threshold, as shown in table 20 . table 21 lists some characteristic parameters for the receivers. figure 7 shows a typical received data waveform. table 20: receiver control registers rx1 or rx2 receiver register control register (hex) name bits states comments 0x00 ant1 trim all inverse relationship register value to internal capacitance 0x01 ant2 trim all inverse relationship register value to internal capacitance 0x05 rx xtal tune all 0x0a data threshold all reference level for detecting data logic state 0 antenna port is off ant1 enable 0 1 antenna port is on 0 antenna port is off ant2 enable 1 1 antenna port is on 0 receiver is off 0x0c rx enable 3 1 receiver is on 000 1.1khz 001 2.3khz 010 5.2khz 011 10.4khz 100 1.18khz 101 2.57khz 110 7.0khz 0x0f data filter 4,5,6 111 20.45khz 0 normal levels 0x1e tx/rx invert 5 1 inverted rev. 7 | page 12 of 25 | www.onsemi.com
amis-52150 table 21: rf input electrical characteristics specification settings conditions typ. max. units comments input resistance 2 k ? trim 0x00 min. tune 3 pfarads input capacitance trim 0xff max. tune 6 pfarads sensitivity 1 kbps -117 dbm w/cdr frequency 403.5 mhz target frequency max. input -10 dbm ip3 +8 dbm ip2 +66 dbm figure 7: received waveform 9.2 transmitter the rf transmitter is a non-linear open drain device. it requires a dc signal path to rfpwr, which is the output of the interna l power supply to the transmitter. the transmitter is switched on and off with the serial transmit data str eam. to achieve the desired output waveform, a tuned external resonant circuit is required. this resonant circuit should be designed to achieve the desired output frequency. this circuit includes a parallel lc tank (lp and cp) tuned to 402mhz (including internal capacitance), as well as a series lc (ls and cs) to produce a 403mhz output. the transmitter output is also to be filtered in order to reduce the harmonics to accep table levels. it is further required that the transmitter output powe r level is programmed, that the transmit frequency is tuned and that the data rate is selected, respectively (table 22). table 23 lists some characteristic parameters for the transmitter, whil e a typical transmitter output waveform is shown in fig. 8. table 22: transmitter control registers tx/rx definition control registers register (hex) name bits states comments 0x02 tx power all 0x04 tx xtal trim all 0 transmitter is off 0x0c tx enable 4 1 transmitter is on 000 1.1khz 001 2.3khz 010 5.2khz 011 10.4khz 100 1.18khz 101 2.57khz 110 7.0khz 0x0f data filter 4,5,6 111 20.45khz 0 normal levels 0x1e tx/rx invert 5 1 inverted rev. 7 | page 13 of 25 | www.onsemi.com
amis-52150 table 23: output impedance characteristics specification settings conditions min. typ. max. units resistance 22 ? output impedance capacitance 3 pfarads rfpwr 0x00 -26 dbm output power rfpwr 0xff 11 12 13 dbm harmonics ext. circuit -35 dbm target 402 405 mhz quick start 350 448 mhz frequency range full range 300 768 mhz modulation ask/ook on/off ratio tx output 70 dbm figure 8: transmit waveforms 9.3 sniff mode tm applications based on low power consumption require sniff mode tm operation of the amis-52150. this mode turns off the receiver and the crystal oscillator during programmable, regular time interval s. at the end of each time inte rval, the receiver wakes up and sniffs for the incoming rf energy. if energy is detected, the receiver transit ions to the full receive mode and starts data recovery from the rf carrier. if energy is not detected, the receiver retu rns to the low power or ?sleep? state. sniff mode tm operation is programmable; the ?sleep? time as well as multiple delay sequences can be fully programmed. table 24 lists the sniff mode tm control registers. typical timing waveforms for operation in sniff mode tm are shown in figure 9 and figure 10 . table 24: sniff function control registers control registers associated with the sniff function register (hex) name bits states comments 0x0b sniff threshold all reference level for detected rf 0 do not wake on rssi 0x0c wake on rssi 5 1 wake on rssi > threshold 0 resolution is set to 0.5ms per step 0x0d sniff timer res 3 1 resolution is set to 64ms per step 0x13 data filter all delay from rx wakeup to data sampled 0x16 irq delay all time i 2 c and tx/rx are active to indicate a wakeup 0x18 rssi delay all delay from wakeup to rssi being checked 0x19 sniff timer all time that receiver is off in sniff mode 0x1a offset dwell all time allowing receiver to power up (typically >40us) 0x1b data filter pre-divider all delay from data detection to pre-clock output rev. 7 | page 14 of 25 | www.onsemi.com
rev. 7 | page 15 of 25 | www.onsemi.com amis-52150 figure 9: receiver data acquisition in sniff mode tm
amis-52150 figure 10: sniff timing at rf energy detection 9.4 quick start there are two oscillators in the amis-52150, a low power 10 khz rc oscillator and a crystal oscillator, respectively. the rc oscillator is used to keep the amis-52150 running in the ul tra-low power mode. this oscillator is used to generate the c lock signals for the sniff mode tm timers as well as the wake-up timers. figure 11 shows a block diagram of t he clocks in t he amis-52150. the crystal oscillator provides the reference frequency which is used to generate the rf frequencies for transmission and recei ving of data. it is also the reference for all the timing functions in the amis-52150. the rc oscillator is in turn used to produce a ? kicker? signal when the quick start function of the crystal oscillator is needed. figure 11: internal clocks rev. 7 | page 16 of 25 | www.onsemi.com
amis-52150 a ?kicker? circuit stimulates the crystal o scillator circuit with oscillations close to the final frequency. this significantly reduces the time it takes for the oscillator to reach and lock to the final frequenc y. the quick start function is ne cessary for operation in sniff mode tm . table 25 lists the quick start control registers. for further details, refer to the applicat ion note titled ?quick start crystal oscill ator circuit operation and set-up?. table 25: quick start control registers quick start control registers register (hex) name bits states comments 0x03 kicker trim all trim the internal rc osc to form a kick-start to the xtal oscillator 0 common mode clamp disabled (startup) kick config1 4 1 common mode clamp enabled (normal) 0 normal operation 0x0e kick config2 5 1 continuous kick on 9.5 data detection the rssi circuit creates an analog voltage waveform (18mv/db) t hat follows the signal strength of the rf signal. the data slice circuit then samples that waveform to create the digitized data. the slic e circuit in the amis-52150 can be programmed to operate in on e of three modes; dac mode, average mode or peak mode. the dac mode co mpares a fixed slice threshold value to the level in the slice output. the digital data state is determined by the level of the slice output being above or below that fixed threshold. for fu rther details, refer to the application note titled ?setting up the amis-52150 data slicing modes?. figure 12 shows a typical waveform for the dac mode, while table 26 shows the control register s for the auto slice modes. figure 12: dac slice mode waveform in the average mode, the threshold value is generated automatically. this threshold value is then compared to the output of the slice circuit to re-create the digital data. the slice circuit along wi th an external capacitor are used to generate a charging time constant which is equal to charging to 95 percent of a bit level in two bit time periods. the data protocol should add a header to the d ata to allow the slice circuit to determine the average level. for further det ails, refer to the application note titled ?setting up the ami s-52150 data slicing modes?. figure 13 shows a typical waveform for the average mode. table 26 shows the control registers for the auto slice modes. rev. 7 | page 17 of 25 | www.onsemi.com
amis-52150 figure 13: average slice mode waveform in the peak mode, a threshold value is gene rated automatically as well. this threshold value is then compared to the output of the slice circuit to re-create the digital data. the operation of the slice circuit is based on an external capacitor with an internal pe ak detector, in order to arrive at the peak value of the data waveform. the thre shold value is set 6db below this peak value. the capacitor val ue should be selected so that the peak detector does not discharge during periods of continuous zeros, while being small enough to allow the peak detector to reach the peak value quickly. for further details, refer to the application note titled ?setting up the am is-52150 data slicing modes?. figure 14 shows a typical waveform for the peak mode. figure 14: peak slice mode waveform rev. 7 | page 18 of 25 | www.onsemi.com
amis-52150 table 26: auto slice control registers auto slice control registers register (hex) name bits states comments 0x0a data slice threshold all set a fixed reference level for the slice output to be compared to in the dac mode 00 0mv hysteresis used in the threshold circuit 01 20mv hysteresis used in the threshold circuit 10 50mv hysteresis used in the threshold circuit hysteresis 0,1 11 100mv hysteresis used in the threshold circuit 00 dac mode used for data detection (default) 01 average mode used for data detection 10 peak mode used for data detection 0x0f autoslice 2,3 11 dac mode used for data detection 9.6 data and clock recovery data recovered in a noisy environment or from a weak rf signal is usually jittery. the amis-52150 can remove much of that data jitter by recovering a synchronous clock signal from the incoming data. the device can be set to achieve auto slice data detection. th e clock and data recovery circuits can be programmed to generate a data clock for synchronously clocking the data output from the trans ceiver, removing much of the jitter in this process. the amis-52150 has an internal pll that must be programmed to the frequency of the data by setting the values in the fword register and setting the coe fficients of the filter. if these values are close to the data r ate, the device will recover the data clock from the in coming detected data. the cdr circuit can also be set to a given tolerance with r espect to the frequency difference between the target data rate and the act ual data rate, in order to improve the performance of the cdr function. the cdr circuit can also be configured to reset after a programmed number of data time periods if no data is received . this ?stop and check? function allows the cdr circuit to re-acquire the clock data when new data is received, maintaining better clo ck to data synchronization. table 27 lists the registers associated with the data and clock recove ry function. for further details, refer to the application note t itled ?amis-52150 clock and data recovery circuit operation and set-up?. rev. 7 | page 19 of 25 | www.onsemi.com
amis-52150 table 27: data and clock recovery control registers data and clock recovery associated registers register (hex) name bits states comments 0x07 fword lsb all 0x08 fword all 0x09 fword msb all sets the initial internal clock frequency for the clock and data recovery circuits 0 tx/rx normal signals data mux 6 1 recovered data on tx/rx 0 normal clkout signals 0x0d clkmux 7 1 recovered clock output on clkout 000 filter coefficient gain is 1 001 filter coefficient gain is 2 010 filter coefficient gain is 4 011 filter coefficient gain is 8 100 filter coefficient gain is 16 101 filter coefficient gain is 32 110 filter coefficient gain is 64 k 0 0,1,2 111 filter coefficient gain is 128 000 filter coefficient gain is 1 001 filter coefficient gain is 2 010 filter coefficient gain is 4 011 filter coefficient gain is 8 100 filter coefficient gain is 16 101 filter coefficient gain is 32 110 filter coefficient gain is 64 0x10 k 1 4,5,6 111 filter coefficient gain is 128 000 filter coefficient gain is 0.125 001 filter coefficient gain is 0.250 010 filter coefficient gain is 0.500 011 filter coefficient gain is 1.000 100 filter coefficient gain is 2 101 filter coefficient gain is 4 110 filter coefficient gain is 8 k 2 0,1,2 111 filter coefficient gain is 16 000 sample frequency divider is 2 001 sample frequency divider is 4 010 sample frequency divider is 8 011 sample frequency divider is 16 100 sample frequency divider is 20 101 sample frequency divider is 32 110 sample frequency divider is 40 0x11 fsdiv 4,5,6 111 sample frequency divider is 48 00 stopcheck bits: disabled 01 stopcheck bits: 2 10 stopcheck bits: 4 stop check 0,1 11 stopcheck bits: 8 00 loop clamp value is: +-baudclk/8 01 loop clamp value is: +-baudclk/16 10 loop clamp value is: +-baudclk/32 loopclamp 2,3 11 loop clamp value is: +-baudclk/64 0 phase alignment enabled freerun 4 1 phase alignment disabled 0 cdr reset disabled crd reset 5 1 cdr reset enabled 0 por reset (auto) auto/manual reset 6 1 cdr reset enabled (manual) 00 sampling starts with bit start edge 0x12 sample window 7 00 sampling centered around bit center the clock and data recovery function is dependent on the receiver ?s ability to recover the data from the incoming rf signal. th ere exists a technique to test the clock and data recovery function without having to set up the receiver to receive data. this is a test mode that allows an input data stream (square wave at 1 / 2 the data rate) on the rssi pin, with the recovered clock data appearing on the clkout pin and the recovered data appearing on the tx/rx pin, res pectively. once the amis-52150 is configured for clock and dat a rev. 7 | page 20 of 25 | www.onsemi.com
amis-52150 recovery (see the application note titled ?amis-52150 clock and data recovery circuit operation a nd set-up?), the register show n in table 28 can be used to define the test mode operation. table 28: clock and data recovery test mode clock and data recovery test control register register (hex) binary code hex code comments 0x1d 00001110 0x0e normal rssi digital input 00001111 0x0f cdr start bit digital input to rssi 9.7 wake-up function ultra-low power applications can take advan tage of the wake-up function of the amis- 52150. the amis-52150 can be placed in a lo w power or ?sleep? state until an interrupt based on the progra mmable wake-up timer is generated. this wakes up the transceiver, which then flags the external microcontroller to perform the required ap plication-specific operations. the wake-up interrupt is also generated based on detection of rf energy (sniff mode tm ). communication with the microcontroller takes place via the i 2 c bus. in addition, when the amis-52150 is in the ?sleep?? state, the wake-up signal can be generated by the microcontroller. table 29 lists the registers associated with the wake-up function. table 29: application wake-up control registers application wakeup control registers register (hex) name bits states comments 0x14 aw timer div all divides the rc oscillator to form a clock for the aw 0x15 aw timer all number of aw clock periods before a aw wakeup 0x17 pre/post aw delay all number of clkout clock periods before the tx/rx pin goes low for a aw cycle 9.8 i 2 c interface the i 2 c is a two pin bi-directional serial interface communication bus , with a data line and a clock line, respectively. serial data on the data pin is clocked into or out of the amis-52150 by the clock pin. the amis-52150 is implemente d as a slave device, which mean s that the external controller is the mast er device. the clock signal for all transmissions between the master (controller) and t he slave (amis-52150) is generated by the controller. the serial communicati on bit rate can be as high as 400kbps. a communication link is initiated based on a start sequence. bi-directional communication co ntinues as long as the master and slave acknowledge the wri te or read sequences, and is terminated with a st op sequence. this is illustrated in figure 15 , figure 16 and figure 17 , respectively. rev. 7 | page 21 of 25 | www.onsemi.com
amis-52150 figure 15: 1 2 c valid control waveforms figure 16: 1 2 c protocol in a write 68 (hex) or a data write request rev. 7 | page 22 of 25 | www.onsemi.com
amis-52150 figure 17: 1 2 c write and read protocol 9.9 registers the amis-52150 is comprised of 31 registers. for further details, refer to the applic ation note titled ?amis-52150 register def initions and functions?. 9.10 power-on-reset/brown-out detection the por/brown-out detection circuit ensures that the amis-52150 will be in a reset state when vdd drops below a certain thresho ld voltage, and remains in this state until vdd rises above another threshold voltage. the characte ristics of the por circuit are shown in figure 18 . gure 18 . figure 18: power-on-reset characteristics rev. 7 | page 23 of 25 | www.onsemi.com
amis-52150 9.11 alternative wake-up functions figure 19: wakeup circuits the amis-52150 will wake up from the low power mode upon a) reception of rf energy, b) an interrupt generated by the wake-up timer, or c) an interrupt generated by the external controller. in this low power mode, the rf circuits, the crystal oscillator , and the clkout circuits are shut off, and only th e rc oscillator a nd the wake-up divider circuitry ar e active. once the amis-52150 rece iver detects rf energy and wakes up, the rx/tx pin is set ?low? while the i 2 cdata and i 2 cclk pins can remain ?high?. in addition, when the wake-up timer wakes up the amis-52150 to in turn flag the external controller, the tx/rx and i 2 cdata pins are set ?low? while the i 2 cclk pin can remain ?high?. the external controller can also signal the amis-52150 to wake up by setting both the i 2 cdata and i 2 cclk lines low. these functions are shown in table 30 . table 30: wakeup truth table wakeup truth table wakeup source tx/rx i 2 cdata i 2 cclk clkout comments sniff 0 1 1 xtal out wake on rf energy detect hk cycle 0 0 1 rc oscillator wake due to hk timer timeout external 1 0 0 don?t care wake due to external controller 10.0 ordering information part number package type shipping configuration temperature range AMIS-52150-XTD 20-pin ssop (209 mil, shrink small outline package) tube/tray 0c to 50c amis-52150-xtp 20-pin ssop (209 mil, shrink small outline package) tape & reel 0c to 50c 11.0 revision history revision date modification rev. 7 | page 24 of 25 | www.onsemi.com
rev. 7 | page 25 of 25 | www.onsemi.com amis-52150 6 april 2007 update to new amis template 7 may 2008 update to new on semiconductor template on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes witho ut further notice to any products herein. scillc makes no warranty, representation or guarantee regardin g the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any pr oduct or circuit, and specific ally disclaims any and all liability, including without li mitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actu al performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surg ical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal op portunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-3 -3867 toll free usa/canada 44 email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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