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| ? 1996 microchip technology inc. preliminary ds40146c-page 1 m features security programmable 28/32-bit serial number programmable 64-bit encryption key each transmission is unique 67-bit transmission code length 32-bit hopping code 35-bit ?ed code (28/32-bit serial number, 4/0-bit function code, 1-bit status, 2-bit crc) encryption keys are read protected operating 2.0-6.6v operation four button inputs - 15 functions available selectable baud rate automatic code word completion battery low signal transmitted to receiver nonvolatile synchronization data pwm and vpwm modulation other easy to use programming interface on-chip eeprom on-chip oscillator and timing components button inputs have internal pulldown resistors current limiting on led output minimum component count enhanced features over hcs300 48-bit seed vs. 32-bit seed 2-bit crc for error detection 28/32-bit serial number select two seed transmission methods pwm and vpwm modulation wake-up signal in vpwm mode ir modulation mode typical applications the HCS361 is ideal for remote keyless entry (rke) applications. these applications include: automotive rke systems automotive alarm systems automotive immobilizers gate and garage door openers identity tokens burglar alarm systems package types HCS361 block diagram description the HCS361 is a code hopping encoder designed for secure remote keyless entry (rke) systems. the HCS361 utilizes the k ee l oq code hopping technology, which incorporates high security, a small package outline and low cost, to make this device a perfect solution for unidirectional remote keyless entry systems and access control systems. the HCS361 combines a 32-bit hopping code generated by a nonlinear encryption algorithm, with a 28/32-bit serial number and 7/3 status bits to create a 67-bit transmission stream. the length of the transmission eliminates the threat of code scanning and the code hopping mechanism makes each transmission unique, thus rendering code capture and resend (code grabbing) schemes useless. 1 2 3 4 8 7 6 5 s0 s1 s2 s3 v dd led pwm v ss pdip, soic HCS361 v ss v dd oscillator reset circuit led driver controller power latching and switching button input port 32-bit shift register encoder eeprom pwm led s 3 s 2 s 1 s 0 k ee l oq is a trademark of microchip technology inc. *code hopping encoder patents issued in europe, u. s. a., r. s. a. ?us: 5,517,187; europe: 0459781 HCS361 code hopping encoder*
HCS361 ds40146c -page 2 preliminary ? 1996 microchip technology inc. the encr yption k e y , ser ial n umber , and con gur ation data are stored in eepr om which is not accessib le via an y e xter nal connection. this mak es the HCS361 a v er y secure unit. the HCS361 pro vides an easy to use ser ial interf ace f or prog r amming the necessar y secur ity k e ys , system par ameters , and con gur ation data. the encr yption k e ys and code combinations are pro- g r ammab le b ut read-protected. the k e ys can only be v er i ed after an automatic er ase and prog r amming oper ation. this protects against attempts to gain access to k e ys and manipulate synchronization v alues . the HCS361 oper ates o v er a wide v oltage r ange of 2.0v to 6.6v and has f our b utton inputs in an 8-pin con gur ation. this allo ws the system designer the freedom to utiliz e up to 15 functions . the only components required f or de vice oper ation are the b ut- tons and rf circuitr y , allo wing a v er y lo w system cost. 1.0 system o ver vie w 1.1 k e y t erms man uf acturer s code ?a 64-bit w ord, unique to each man uf acturer , used to produce a unique encr yption k e y in each tr ansmitter (encoder). encr yption k e y ?a unique 64-bit k e y gener ated and prog r ammed into the encoder dur ing the man uf actur ing process . the encr yption k e y controls the encr yption algor ithm and is stored in eepr om on the encoder de vice . lear n t he hcs product f amily f acilitates se v er al lear n ing str ategies to be implemented on the decoder . the f ollo wing are e xamples of what can be done . nor mal lear ning the receiv er uses the same inf or mation that is tr ansmitted dur ing nor mal oper ation to der iv e the tr ansmitter s secret k e y , decr ypt the discr imination v alue and the synchronization counter . secure lear n* the tr ansmitter is activ ated through a special b ut- ton combination to tr ansmit a stored 48-bit v alue (r andom seed) that can be used f or k e y gener a- tion or be par t of the k e y . t r ansmission of the r an- dom seed can be disab led after lear ning is completed. the HCS361 is a code hopping encoder de vice that is designed speci cally f or k e yless entr y systems , pr imar ily f or v ehicles and home gar age door openers . it is meant to be a cost-eff ectiv e , y et secure solution to such systems . the encoder por tion of a k e yless entr y system is meant to be held b y the user and oper ated to gain access to a v ehicle or restr icted area. the HCS361 requires v er y f e w e xter nal components ( figure 2-1 ). most k e yless entr y systems tr ansmit the same code from a tr ansmitter e v er y time a b utton is pushed. the relativ e n umber of code combinations f or a lo w end sys- tem is also a relativ ely small n umber . these shor tcomings pro vide the means f or a sophisticated thief to create a de vice that ? r abs a tr ansmission and retr ansmits i t later or a de vice that scans all possib le combinations until the correct one is f ound. the HCS361 emplo ys the k ee l oq code hopping tech- nology and an encr yption algor ithm to achie v e a high le v el of secur ity . code hopping is a method b y which the code tr ansmitted from the tr ansmitter to the receiv er is diff erent e v er y time a b utton is pushed. this method, coupled with a tr ansmission length of 67 bits , vir tually eliminates the use of code ? r ab bing or code scanning? as indicated in the b loc k diag r am on page one , the HCS361 has a small eepr om arr a y which m ust be loaded with se v er al par ameters bef ore use . the most impor tant of these v alues are: a 28/32-bit ser ial n umber which is meant to be unique f or e v er y encoder an encr yption k e y that is gener ated at the time of production a 16-bit synchronization v alue the ser ial n umber f or each tr ansmitter is prog r ammed b y the man uf acturer at the time of production. the gener ation of the encr yption k e y is done using a k e y gener ation algor ithm ( figure 1-1 ). t ypically , inputs to the k e y gener ation algor ithm are the ser ial n umber of the tr ansmitter or seed v alue , and a 64-bit man uf ac- turer s code . the man uf acturer s code is chosen b y the system man uf acturer and m ust be carefully controlled. the man uf acturer s code is a piv otal par t of the o v er all system secur ity . the 16-bit synchronization v alue is the basis f or the tr ansmitted code changing f or each tr ansmission, and is updated each time a b utton is pressed. because of the comple xity of the code hopping encr yption algo- r ithm, a change in one bit of the synchronization v alue will result in a large change in the actual tr ansmitted code . there is a relationship ( figure 1-2 ) betw een the k e y v alues in eepr om and ho w the y are used in the encoder . once the encoder detects that a b utton has been pressed, the encoder reads the b utton and updates the synchronization counter . the synchroniza- tion v alue is then combined with the encr yption k e y in the encr yption algor ithm and the output is 32 bits of encr ypted inf or mation. this data will change with e v er y b utton press , hence , it is ref erred to as the hopping por tion of the code w ord. the 32-bit hopping code is combined with the b utton inf or mation and the ser ial n umber to f or m the code w ord tr ansmitted to the receiv er . the code w ord f or mat is e xplained in detail in section 4.2 . an y type of controller ma y be used as a receiv er , b ut it is typically a microcontroller with compatib le r mw are that allo ws the receiv er to oper ate in conjunction with a tr ansmitter , based on the HCS361 . section 7.0 pro vides more detail on integ r ating the HCS361 into a total system. *secure lear ning patents pending. HCS361 ? 1996 microchip technology inc. preliminary ds40146c -page 3 bef ore a tr ansmitter can be used with a par ticular receiv er , the tr ansmitter m ust be ?ear ned b y the receiv er . upon lear ning a tr ansmitter , inf or mation is stored b y the receiv er so that it ma y tr ac k the tr ansmitter , including the ser ial n umber of the tr ansmitter , the current synchronization v alue f or that tr ansmitter and the same encr yption k e y that is used on the tr ansmitter . if a receiv er receiv es a message of v alid f or mat, the ser ial n umber is chec k ed and, if it is from a lear ned tr ansmitter , the message is decr ypted and the decr ypted synchronization counter is chec k ed against what is stored. if the synchronization v alue is v er i ed, then the b utton status is chec k ed to see what oper ation is needed. figure 1-3 sho ws the relationship betw een some of the v alues stored b y the receiv er and the v al- ues receiv ed from the tr ansmitter . figure 1-1: creation and stora g e of encr yption k e y during pr oduction figure 1-2: basic operation of transmitter ( encoder) figure 1-3: basic operation of receiver (decoder) t r ansmitter man uf acturer s ser ial number or code encr yption k e y k e y gener ation algor ithm ser ial number encr yption k e y sync counter . . . HCS361 eepr om arr a y seed k ee l oq algor ithm button press inf or mation encr yption eepr om arr a y 32 bits of encr ypted data ser ial number t r ansmitted inf or mation dec r yption k e y sync counter ser ial number button press inf or mation eepr om arr a y dec r yption k e y 32 bits of encr ypted data ser ial number receiv ed inf or mation decr ypted synchronization counter chec k f or match chec k f or match k ee l oq algor ithm de cr yption sync counter ser ial number man uf acturer code HCS361 ds40146c -page 4 preliminary ? 1996 microchip technology inc. 2.0 de vice operation as sho wn in the typical application circuits ( figure 2-1 ), the HCS361 is a simple de vice to use . it requires only the addition of b uttons and rf circuitr y f or use as the tr ansmitter in y our secur ity application. a descr iption of each pin is descr ibed in t ab le 2-1 . figure 2-1: typical cir cuits t able 2-1 pin descriptions the high secur ity le v el of the HCS361 is based on the patented k ee l oq technology . a b loc k cipher type of encr yption algor ithm based on a b loc k length of 32 bits and a k e y length of 64 bits is used. the algor ithm obscures the inf or mation in such a w a y that e v en if the tr ansmission inf or mation (bef ore coding) diff ers b y only one bit from the inf or mation in the pre vious tr ansmis- sion, the ne xt coded tr ansmission will be totally diff er- ent. statistically , if only one bit in the 32-bit str ing of inf or mation changes , appro ximately 50 percent of the coded tr ansmission will change . the HCS361 will w ak e up upon detecting a s witch closure and then dela y appro ximately 6.5 ms f or s witch debounce ( figure 2-2 ). the synchroniz ation i nf or mation, x ed inf or mation, and s witch inf or mation will be encr ypted to f or m the hopping code . the encr ypted or hopping code por tion of the tr ansmission will change e v er y time a b utton is pressed, e v en if the same b utton is pushed again. k eeping a b utton pressed f or a long time will result in the same code w ord being tr ansmitted until the b utton is released or time-out o ccurs . a code that has been tr ansmitted will not occur again f or more than 64k tr ansmissions . this will pro vide more than 18 y ears of typical use bef ore a code is repeated based on 10 oper- ations per da y . ov er o w inf or mation prog r ammed into the encoder can be used b y the decoder to e xtend the n umber of unique tr ansmissions to more than 128 k . if in the tr ansmit process it is detected that a ne w b ut- ton(s) has been pressed, a reset will immediately be f orced and the code w ord will not be completed. please note that b uttons remo v ed will not ha v e an y eff ect on the code w ord unless no b uttons remain pressed in which case the current code w ord will be completed and the po w er do wn will occur . v dd b0 tx out s0 s1 s2 s3 led v dd pwm v ss 2 b utton remote control b1 v dd tx out s0 s1 s2 s3 led v dd pwm v ss 5 b utton remote control (note) b4 b3 b2 b1 b0 note: up to 15 functions can be implemented b y pressing more than one b utton sim ul- name pin number description s0 1 switch input 0 s1 2 switch input 1 s2 3 switch input 2/can also be cloc k pin when in prog r amming mode s3 4 switch input 3/cloc k pin when in prog r amming mode v ss 5 ground ref erence connection pwm 6 pulse width modulation (pwm) output pin/data pin f or prog r amming mode led 7 cathode connection f or directly dr iving led dur ing tr ansmission v dd 8 p ositiv e supply v oltage connection HCS361 ? 1996 microchip technology inc. preliminary ds40146c -page 5 figure 2-2: encoder operation 3.0 eepr om memor y or ganization the HCS361 contains 192 bits (12 x 16-bit w ords) of eepr om memor y ( t ab le 3-1 ). this eepr om arr a y is used to store the encr yption k e y inf or mation, synchronization v alue , etc. fur ther descr iptions of the memor y arr a y is giv en in the f ollo wing sections . t able 3-1 eepr om memor y map 3.1 k e y_0 - k e y_3 (64-bit encr yption k e y) the 64-bit encr yption k e y is used b y the tr ansmitter to create the encr ypted message tr ansmitted to the receiv er . this k e y is created and prog r ammed at the time of production using a k e y gener ation algor ithm. inputs to the k e y gener ation algor ithm are the ser ial n umber f or the par ticular tr ansmitter being used and a secret man uf acturer s code . while the k e y gener ation algor ithm supplied from microchip is the typical method used, a user ma y elect to create their o wn method of k e y gener ation. this ma y be done pro viding that the decoder is prog r ammed with the same means of creat- ing the k e y f or decr yption pur poses . if a seed is used, the seed will also f or m par t of the input to the k e y gen- er ation algor ithm. p o w er up r eset and debounce dela y ( 6.5 m s) sample inputs update sync inf o encr ypt with load t r ansmit register button s added ? all buttons released ? (a b utton has been pressed) t r ansmit stop no y es no y es encr yption k e y complete code w ord t r ansmission w ord address mnemonic description 0 key_0 64-bit e ncr yptio n k e y ( w ord 0) 1 key_1 64-bit encr yptio n k e y ( w ord 1) 2 key_2 64-bit encr yptio n k e y ( w ord 2) 3 key_3 64-bit encr yptio n k e y ( w ord 3) 4 sync_a 16-bit synchroni- zation v alue 5 sync_b /seed _ 2 16-bit synchroni- zation or seed v alue (w ord 2) 6 reser ved set to 0000h 7 se ed_ 0 seed v alue ( w ord 0) 8 se ed_ 1 seed v alue ( w ord 1) 7 se r_ 0 de vice ser ial nu mb er ( w ord 0) 10 se r_ 1 de vice ser ial number ( w ord 1) 11 config con gur ation w ord HCS361 ds40146c -page 6 preliminary ? 1996 microchip technology inc. 3.2 sync_a, sync_b (sync hr onization counter) this is the 16-bit synchronization v alue that is used to create the hopping code f or tr ansmission. this v alue will be changed after e v er y tr ansmission. a second syn- chronization v alue can be used to sta y synchroniz ed with a second receiv er . 3.3 seed_0, seed_1, and seed_2 (seed w or d) this is the t hree w ord ( 48 b its) seed code that will be tr ansmitted when seed tr ansmission is selected. this allo ws the system designer to implement the secure lear n f eature or use this x ed code w ord as par t of a dif- f erent k e y gener ation/tr ac king process or purely as a x ed code tr ansmission . 3.4 ser_0, ser_1 (encoder serial number) ser_0 and ser_1 are the lo w er and upper w ords of the de vice ser ial n umber , respectiv ely . there are 32 bits allocated f or the ser ial n umber and a selectab le con g- ur ation bit deter mines whether 32 or 28 bits will be tr ansmitted. the ser ial n umber is meant to be unique f or e v er y tr ansmitter . 3.5 config (con guration w or d) the con gur ation w ord is a 16-bit w ord stored in eepr om arr a y that is used b y the de vice to store inf or mation used dur ing the encr yption process , as w ell as the status of option con gur ations . fur ther e xplanations of each of the bits are descr ibed in the f ollo wing sections . t able 3-2 configuration w or d 3.5.1 ba cw: blank alter nate code w ord ba cw = 1 s elects the encoder to tr ansmit e v er y sec- ond code w ord. this can be used to reduce the a v er age po w er tr ansmitted o v er a 100ms windo w and thereb y tr ansmit a higher peak po w er . 3.5.2 f ast : select f ast t r ansmission f ast selects the baud r ate . if f ast = 1, the baud r ate is nominally 1667 bits per second and with f ast = 0, 833 bits per second. 3.5.3 txw ak: bit f or mat select o r w ak eup in pwm mode , this bit selects the bit f or mat. if txw ak = 1, the pwm pulse is 1/6;2/6 and f or txw ak = 0, 1/ 3;2/3 ( figure 4-1 , vpwm = 0). in vpwm mode , this bit enab les the w ak e-up signal. with txw ak = 1, tr ansmission of the w ak e-up and dead time sequence is enab led ( figure 4-2 , vpwm = 1). w ak eup is tr ansmitted b ef ore the rst code w ord of each tr ansmission only . f or txw ak = 0, the tr ansmis- sion will skip w ak e-up and star t tr ansmitting the pream- b le por tion of the code w ord ( figure 4-2 , vpwm = 1). 3.5.4 spm: sync pulse modulation select modulation mode of sync pulse . if spm = 1, the sync pulse is modulated ( figure 4-1 and figure 4-2 ). bit number symbol bit description 0 ba cw blank alter nate code w ord 1 f ast baud rate selection 2 txw ak pwm mode: 1/6, 2/6 or 1/3, 2/3 select vpwm mod e : w ak eup enab le 3 spm sync pulse modulation 4 seed seed t r ansmission enab le 5 delm dela y mode enab le 6 timo time out enab le 7 ind independent mode enab le 8 usra0 user bit 9 usra1 user bit 10 usrb0 user bit 11 usrb1 user bit 12 xser extended ser ial n umber enab le 13 tmpsd t empor ar y seed tr ansmis- sion enab le 14 vpwm vpwm select 15 o vr ov er o w bit HCS361 ? 1996 microchip technology inc. preliminary ds40146c -page 7 3.5.5 seed: enab le seed t r ansmission if seed = 0, seed tr ansmission is disab led. the inde- pendent counter mode can only be used with seed tr ansmission disab led since seed_2 is shared with the second synchronization counter . w ith seed = 1, seed tr ansmission is enab led. the appropr iate b utton code(s) m ust be activ ated to tr ans- mit the seed inf or mation. in this mode , the seed inf or- mation (seed_0, seed_1, and seed_2) and the upper 12- or 16-bits of the ser ial n umber (ser_1) a re tr ansmitted instead of the hop code . seed tr ansmission is a v ailab le f or function codes ( t ab le 3-7 ) s[3:0] = 1001 and s[3:0] = 0011 (dela y ed). this tak es place regardless of the setting of the ind bit. the tw o seed tr ansmissions are sho wn in figure 3-1 . figure 3-1: seed t ransmission all e xamples sho wn with xser = 1, seed = 1 when s[3:0] = 1001, dela y is not applicab le . crc+ v low ser_1 seed_2 seed_1 seed_0 data tr ansmission direction f or s[3:0] = 0x3 bef ore dela y: 16-bit data w ord 16-bit counter encr ypt crc+ v low ser_1 ser_0 encr ypted data f or s[3:0] = 0011 after dela y (note 1, note 2): crc+ v low ser_1 seed_2 seed_1 seed_0 data tr ansmission direction data tr ansmission direction note 1: f or seed t r ansmission, seed_2 is tr ansmitted instead of ser_0. 2: f or seed t r ansmission, the setting of delm has no eff ect. HCS361 ds40146c -page 8 preliminary ? 1996 microchip technology inc. 3.5.6 delm: dela y mode if delm = 1, dela y tr ansmission is enab led. a dela y ed tr ansmission is indicated b y in v er ting the lo w er nib b le of the discr imination v alue . the dela y mode is pr imar ily f or compatibility with pre vious k ee l oq de vices . i f delm = 0, dela y tr ansmission is disab led ( t ab le 3-3 ). t able 3-3 t ypical dela y times 3.5.7 t imo: time-out if timo = 1, the time-out is enab led. time-out can be used to ter minate accidental contin uous tr ansmission s . w hen time-out occurs , the pwm output is set lo w and the led is tur ned off . current consumption will b e higher than in standb y mode since current will o w through the activ ated input resistors . this state can be e xited only after all inputs are tak en lo w . t imo = 0 , will enab le contin uous tr ansmission ( t ab le 3-4 ). t able 3-4 t ypical time-out times 3.5.8 ind: independent mode the independent mode can be used where one encoder is used to control t w o receiv ers . t w o counters ( sync_a a nd sync_b ) are used in independent mode . as indicated in t ab le 3-7 , function codes 1 to 7 use s ync_ a and 8 to 1 5 sync_ b . the independent mode also select s ir mode . in ir mode function codes 12 to 15 will use counter b . the pwm output signal is modulated with a 40 khz carr ier . it m ust be pointed out the 40 khz is der iv ed from the inter nal cloc k and will theref ore v ar y with the same percentage as the baud r ate . if ind = 0, sync_a i s used f or all function codes . if ind = 1, independent mode is enab led and counters f or functions are used according to t ab le 3-7 . f or ind = 1 and s[3:0] o 0xc , 0xd , 0xe, 0xf , basic pulse width modulation becomes: t able 3-5 ir modulation 3.5.9 usra,b : user bits user bits f or m par t of the discr imination v alue . the use r bits together with the ind bit can be used to identify the counter that is used in independent mode . 3.5.10 xs er: extended ser ial number if xse r = 1, the full 32-bit ser ial n umber [ser_1, s er _0] is tr ansmitted. if xser = 0, the f our most sig- ni cant bits of the ser ial n umber are substituted b y s[ 3:0] and is compatib le with the hcs200/300/301. 3.5.11 tmpsd: t empor ar y seed t r ansmission the tempor ar y seed tr ansmission can be used to dis- ab le lear ning after the tr ansmitter has been used f or a prog r ammab le n umber of oper ation s . this f eature can be used to implement v er y secure systems . after lear n- ing is disab led, the seed inf or mation cannot be accessed e v en if ph ysical access to the tr ansmitter is possib le . if tmpsd = 1 the seed tr ansmission will be disab led after a n umber of c ode hopping tr ansmissions . t he n umber of tr ansmissions bef ore seed tr ansmission is disab led , can be prog r ammed b y setting the synchro- nization counter (sync_a or sync_b) to a v alue as sho wn in t ab le 3-6 . t able 3-6 sync hr onous counter initialization v alues txw ak f ast number of code w or ds bef ore dela y mode time bef ore dela y mode (vpwm = 0) 0 0 28 ? 2.8s 0 1 56 ? 2.9s 1 0 28 ? 2.6s 1 1 56 ? 2.8 s txw a k f ast maxim um n umber of code w or d s t ransmitted time bef ore time-out (vpwm = 0) 0 0 256 ? 25.6s 0 1 512 ? 27.2s 1 0 256 ? 23.8s 1 1 512 ? 25.4 s tx w ak f ast basic puls e 0 0 0 1 1 0 1 1 sync hr onous counter v alues number of t ransmission s 0000h 128 0060h 64 005 0 h 32 0048h 16 (400 m s) (16x) (200 m s) (8x) p er iod = 25 m s (100 m s) (8x) HCS361 ? 1996 microchip technology inc. preliminary ds40146c -page 9 t able 3-7 function codes 3.5.12 vpwm: v ar iab le pulse width modulation vpwm selects betw een vpwm modulation and pwm modulation. if vpwm = 1, vpwm modulation is selected as w ell as the f ollo wing: 1. en ab les the txw ak bit to select the w akeup tr ansmissio n . 2. e xtends the guard time . if vpwm = 0, pwm modulation is selected. 3.5.13 o vr: ov erflo w t he o v er o w bit is used to e xtend the n umber of possi- b le synchronization v alues . the synchronization counter is 16 bits in length, yielding 65,536 v alues bef ore the cycle repeats . under typical use of 10 oper ations a da y , this will pro vide near ly 18 y ears of use bef ore a repeated v alue will be used. should the system designer conclude that is not adequate , then the o v er o w bit can be utiliz ed to e xtend the n umber of unique v alues . this can be done b y prog r amming o vr t o 1 at the time of production. the encoder will automat- ically clear o vr t he rst time that the tr ansmitted s yn- chronization v alue wr aps from 0xffff to 0x0000. once cleared, o vr c annot be set again, thereb y creat- ing a per manent record of the counter o v er o w . this pre v ents f ast cycling of 64k counter . if the decoder sys- tem is prog r ammed to tr ac k the o v er o w bits , then the eff ectiv e n umber of unique synchronization v alues can be e xtended to 128k. if prog r ammed to z ero , the sys- tem will be compatib le with the ntq104/5/6 de vices (i.e ., no o v er o w with discr imination bits set to z ero). s3 s2 s1 s0 ind = 0 ind = 1 comments counter 1 0 0 0 1 a a 2 0 0 1 0 a a 3 0 0 1 1 a a if seed = 1, tr ansmit seed after dela y . 4 0 1 0 0 a a 5 0 1 0 1 a a 6 0 1 1 0 a a 7 0 1 1 1 a a 8 1 0 0 0 a b 9 1 0 0 1 a b if seed = 1, tr ansmit seed immediately . 10 1 0 1 0 a b 11 1 0 1 1 a b 12 1 1 0 0 a b ir mode 13 1 1 0 1 a b ir mode 14 1 1 1 0 a b ir mode 15 1 1 1 1 a b ir mode HCS361 ds40146c -page 10 preliminary ? 1996 microchip technology inc. 4.0 t ransmitted w or d 4.1 t ransmission format (pwm) the HCS361 tr ansmission is made up of se v er al par ts ( figure 4-1 and figure 4-2 ). each tr ansmission is begun with a preamb le and a header , f ollo w ed b y the encr ypted and then the x ed data. the actual data is 67 bits which consists of 32 bits of encr ypted data and 3 5 b its of x ed data. each tr ansmission is f ollo w ed b y a guard per iod bef ore another tr ansmission can begin. ref er to t ab le and t ab le f or tr ansmission timing spec- i cations . the encr ypted por tion pro vides up to f our bil- lion changing code combinations and includes the function b its (based on which b uttons w ere activ ated) along with the synchronization counter v alue and d is- cr imination v alue . the n o n-encr ypted p or tion is com- pr ised of the crc bits , v low b its , the function bits and the 28/32-bit ser ial n umber . the encr ypted a nd non- encr ypted sections combined increase the n umber of combinations to 1.47 x 10 20 . 4.2 code w or d or ganization the HCS361 tr ansmits a 67-bit code w ord when a b ut- ton is pressed. the 67-bit w ord is constr ucted from a fix ed code por tion and an encr ypted code por tion ( figure 4-3 ). the encr ypted data is gener ated from 4 function b its , 2 user b its , o v er o w bit, independent mode bit, and 8 ser ial n umber bits , and the 16-bit synchronization v alue ( figure 8-4 ). the non-encr ypted code data is made up of v low bit, 2 crc bits , 4 function bits , and the 28-bit ser ial n umber . if the e xtended ser ial n umber (32 bits) is selected, the 4 function code bits will not be tr ansmit- ted. figure 4-1: t ransmission format?pwm = 0 t bp logic "1" code w ord bit t e guard time txw ak=1 txw ak=0 spm=1 spm=0 preamb le header encr ypted data fix ed code data bit logic "0" txw ak=1 txw ak=0 t bp code w ord: transmission seq uence: preamb le sync encr ypt fix ed guard 1 code w ord preamb le sync encr ypt HCS361 ? 1996 microchip technology inc. preliminary ds40146c -page 11 figure 4-2: t ransmission format ? pwm = 1 figure 4-3: c ode w or d organiza tio n (right-most bit is c loc ked-out fir st) guard time spm=1 spm=0 preamb le header encr ypted data fix ed code data logic "0" t e code w ord: t o t al transmission: w akeup (option) preamb le sync encr ypt fix ed guard x84 dead time 1 code w ord preamb le sync encr ypt t e logic "1" transition t e code w ord lsb msb fix ed code data encr ypted code data 67 bits of data t r ansmitted msb ls b crc (2 bit) v low (1 bit) button status (4 bits) 28-bit ser ial number button status (4 bits) discr imination bits (12 bits) 16-bit synch v alue crc (2 bit) v low bit + ser ial number and button status (32 bits) + 32 bits of encr ypted data HCS361 ds40146c -page 12 preliminary ? 1996 microchip technology inc. 5.0 special fea tures 5.1 code w or d completion code w ord completion is an automatic f eature that ens ure s that the entire code w ord is tr ansmitted, e v en if the b utton is released bef ore the tr ansmission is com- plete and that a minim um of tw o w ords are completed. the HCS361 encoder po w ers itself up when a b utton is pushed and po w ers itself do wn after the current t r ans- mission is nished, if the user has already released the b utton. if the b utton is held do wn be y ond the time f or tw o tr ansmissions , then m ultiple tr ansmissions will result. the HCS361 tr ansmits at least tw o tr ansmis- sions b ef ore po w er ing do wn. if another b utton is acti- v ated dur ing a tr ansmission, the activ e tr ansmission will be abor ted and the ne w code will be gener ated using the ne w b utton inf or mation. 5.2 blank alternate code w or d f eder al comm unications commission (fcc) par t 15 r ules specify the limits on fundamental po w er and har monics that can be tr ansmitted. p o w er is calculated on the w orst case a v er age po w er tr ansmitted in a 100ms windo w . it is theref ore adv antageous to minimiz e the duty cycle of the tr ansmitted w ord. this can be achie v ed b y minimizing the duty cycle of the individual bits and b y b lanking out consecutiv e w ords . blank alter nate code w ord (ba cw) is used f or reducing the a v er age po w er of a tr ansmission ( figure 5-1 ). this is a selectab le f eature . using the ba cw allo ws the user to tr ansmit a higher amplitude tr ansmission if the tr ansmission length is shor ter . the fcc puts constr aints on the a v er age po w er that can be tr ansmitted b y a de vice , and ba cw eff ectiv ely pre v ents contin uous tr ansmission b y only allo wing the tr ansmis- sion of e v er y second w ord. this reduces the a v er age po w er tr ansmitted and hence , assists in fcc appro v al of a tr ansmitter de vice . 5.3 crc (cyc le redundanc y chec k) bits the crc bits are calculated on the 65 pre viously tr ans- mitted bits . the crc bits can be used b y the receiv er to chec k the data integ r ity bef ore processing star ts . the crc can detect all single bit and 66 % o f doub le bit errors . the crc is computed as f ollo ws: eq u a tion 0-1: crc calculation and with and di n the nth tr ansmission bit 0 n 64 5.4 secure learning in order to increase the le v el of secur ity in a system, it is possib le f or the receiv er to implement what is kno wn as a secure lear n ing function. this can be done b y uti- lizing the seed v alue on the HCS361 which is stored in eepr om . instead of the nor mal k e y gener ation method being used to create the encr yption k e y , this seed v alue is used and there should n ot be an y mathe- matical relationship betw een ser ial n umbers and seeds f or the best secur ity . 5.5 a uto-shutoff t he a uto-shutoff function automatically stops the de vice from tr ansmitting if a b utton inadv er tently gets pressed f or a long per iod of time . this will pre v ent the de vice from dr aining the batter y if a b utton gets pressed while the tr ansmitter is in a poc k et or purse . this func- tion can be enab led or disab led and is selected b y set- ting or clear ing the time-out bit ( section 3.5.7 ). setting this bit w ill enab le the function (tur n a uto-shutoff func- tion on) and clear ing t he bit w ill disab le the function. time-out per iod is appro ximately 25 seconds . 5.6 v low : v olta g e lo w indicator the v low bit is tr ansmitted with e v er y tr ansmission ( figure 4-2 ) and will be tr ansmitted as a one if the oper ating v oltage has dropped belo w the lo w v oltage tr ip point , typically 3.8v at 25 c . t his v low signal is tr ansmitted so the receiv er can giv e an indicat ion t o the user that the tr ansmitter batter y is lo w . 5.7 led output operation dur ing nor mal tr ansmission the led output is lo w . if the supply v oltage drops belo w the lo w v oltage tr ip point, the led output will be toggled at appro ximately 1hz dur ing the tr ansmission. figure 5-1: blank alternate code w or d c r c 1 [ ] n 1 + c r c 0 [ ] n d i n = c r c 0 [ ] n 1 + c r c 0 [ ] n d i n ( ) c r c 1 [ ] n = c r c 1 0 , [ ] 0 0 = one code w ord ba cw disab led (all w ords tr ansmitted) ba cw enab led (1 out of 2 tr ansmitted) a 2a 100ms 100ms 100ms 100ms amplitude time min tx length HCS361 ? 1996 microchip technology inc. preliminary ds40146c -page 13 6.0 p r ogramming the HCS361 when using the HCS361 in a system, the user will ha v e to prog r am some par ameters into the de vice including the ser ial n umber and the secret k e y bef ore it can be used. the prog r amming cycle allo ws the user to input all 192 bits in a ser ial data stream, which are then stored inter nally in eepr om. prog r amming will be initiated b y f orcing the pwm line high, after the s3 line has been held high f or the appropr iate length of time . s 0 a nd s1 should be held lo w dur ing the entire prog r am cycle ( t ab le 6-1 and figure 6-1 ). the de vice can then be prog r ammed b y cloc king in 16 bits at a time , f ollo w ed b y the w ord s complement u sing s3 or s2 as the cloc k line and pwm as the data in line . after each 16-bit w ord is loaded, a prog r amming dela y is required f or the inter nal prog r am cycle to complete . a n ac kno wledge bit can be read bac k after the prog r amming dela y ( t wc ). after the rst w ord and its complement ha v e been do wnloaded, an automatic b ulk wr ite is perf or med. t his dela y can tak e up to t wc. at the end of the prog r am- ming cycle , the de vice can be v er i ed ( figure 6-2 ) b y reading bac k the eepr om. reading is done b y cloc k- ing the s3 line and reading the data bits on pwm. f or secur ity reasons , it is not possib le to e x ecute a v er ify function without rst prog r amming the eepr om. a verify operation can onl y be done once , immedi- atel y f ollo wing the pr ogram c yc le . figure 6-1: pr ogramming w a vef orms figure 6-2: v erify w a vef orms t able 6-1 pr ogramming/verify timing requirements v dd = 5.0v 10% 25 c 5 c p arameter symbol min. max. units prog r am mode setup time t 2 0 4. 9 ms hold time 1 t 1 9.0 ms prog r amming dela y t wc 3 0 ms cloc k lo w time t clkl 25 m s cloc k high time t clkh 25 m s data setup time t ds 0 m s data hold time t dh 18 m s data out v alid time t dv 24 m s pwm enter prog r am mode (data) (cloc k) bit 0 bit 1 bit 2 bit 3 bit 14 bit 15 bit 16 bit 17 t 1 t 2 repeat 12 times f or each w ord t clkh t clkl t wc t ds s2/ s3 data f or w ord 0 (key_0) data f or w ord 1 t dh bit 0 bit 1 bit 2 bit 3 bit 14 bit 15 note 1: un used b utton inputs to be held to g round dur ing the entire prog r amming sequence . 2: the v dd pin m ust be tak en to g round after a prog r am/v er ify cycle . ac kno wledge pwm (cloc k) (data) note: if a v er ify oper ation is to be done , then it m ust immediately f ollo w the prog r am cycle . end of prog r amming cycle begin v er ify cycle here bit 1 bit 2 bit 3 bit 15 bit 14 bit 16 bit 17 bit190 bit191 t wc data in w ord 0 t dv s2/ s3 bit 0 bit191 bit190 HCS361 ds40146c -page 14 preliminary ? 1996 microchip technology inc. 7.0 integrating the HCS361 into a system use of the HCS361 in a system requires a compatib le decoder . this decoder is typically a microcontroller with compatib le r mw are . f ir mw are routines that accept tr ansmissions from the HCS361 and decr ypt the hopping code por tion of the data stream are a v ailab le . these routines pro vide system designers the means to de v elop their o wn decoding system. 7.1 learning a t ransmitter to a receiver in order f or a tr ansmitter to be used with a decoder , the tr ansmitter m ust rst be ?ear ned? se v er al lear ning str ategies can be f ollo w ed in the decoder implementa- tion. when a tr ansmitter is lear ned to a decoder , it is suggested that the decoder stores the ser ial n umber and current synchronization v alue in eepr om. the decoder m ust k eep tr ac k of these v alues f or e v er y tr ansmitter that is lear ned ( figure 7-1 ). the maxim um n umber of tr ansmitters that can be lear ned is only a function of ho w m uch eepr om memor y stor age is a v ailab le . the decoder m ust also store the man uf ac- turer s code in order to lear n a tr ansmission tr ansmitter , although this v alue will not change in a typical system so it is usually stored as par t of the microcontroller r om code . stor ing the man uf acturer s code as par t of the r om code is also better f or secur ity reasons . it m ust be stated that some lear ning str ategies ha v e been patented and care m ust be tak en not to infr inge . figure 7-1: typical learn sequence enter lear n mode w ait f or reception of a v alid code gener ate k e y from ser ial number use gener ated k e y to decr ypt compare discr imination v alue with fix ed v alue equal w ait f or reception of second v alid code compare discr imination v alue with fix ed v alue use gener ated k e y to decr ypt equal counters encr yption k e y ser ial n umber synchronization counter sequential ? ? ? exit lear n successful store: lear n unsuccessful no no no y es y es y es HCS361 ? 1996 microchip technology inc. preliminary ds40146c -page 15 7.2 decoder operation in a typical decoder oper ation ( figure 7-2 ), the k e y gen- er ation on the decoder side is done b y taking the ser ial n umber from a tr ansmission and combining that with the man uf acturer s code to create the same secret k e y that w as used b y the tr ansmitter . once the secret k e y is obtained, the rest of the tr ansmission can be decr ypted. the decoder w aits f or a tr ansmission and immediately can chec k the ser ial n umber to deter mine if it is a lear ned tr ansmitter . if it is , it tak es the encr ypted por tion of the tr ansmission and decr ypts it using the stored k e y it uses the discr imination bits to deter mine if the decr yption w as v alid. if e v er ything up to this point is v alid, the synchronization v alue is e v aluated. figure 7-2: typical decoder operation 7.3 sync hr onization with decoder the k ee l oq technology f eatures a sophisticated synchronization technique ( figure 7-3 ) which does not require the calculation and stor age of future codes . if the stored counter v alue f or that par ticular tr ansmitter and the counter v alue that w as just decr ypted are within a f or matted windo w of sa y 16, the counter is stored and the command is e x ecuted. if the counter v alue w as not within the single oper ation windo w , b ut is within the doub le oper ation windo w of sa y 32k windo w , the tr ans- mitted synchronization v alue is stored in tempor ar y location and it goes bac k to w aiting f or another tr ans- mission. when the ne xt v alid tr ansmission is receiv ed, it will chec k the ne w v alue with the one in tempor ar y stor age . if the tw o v alues are sequential, it is assumed that the counter had just gotten out of the single oper a- tion ?indo w? b ut is no w bac k in sync , so the ne w syn- chronization v alue is stored and the command e x ecuted. if a tr ansmitter has someho w gotten out of the doub le oper ation windo w , the tr ansmitter will not w or k and m ust be relear ned. since the entire windo w rotates after each v alid tr ansmission, codes that ha v e been used are par t of the ? loc k ed (32k) codes and are no longer v alid. this eliminates the possibility of g r ab- bing a pre vious code and retr ansmitting t o gain entr y . figure 7-3: sync hr onization windo w ? t r ansmission receiv ed does ser ial number match ? decr ypt t r ansmission is decr yption v alid ? is counter within 16 ? is counter within 32k ? update counter ex ecute command sa v e counter in t emp location star t no no no no y es y es y es y es y es no and no note: the synchronization method descr ibed in this section is only a typical implementation and because it is usually implemented in r mw are , it can be altered to t the needs of a par ticular system bloc k ed entire windo w rotates to eliminate use of pre viously used codes current p osition (32k codes) doub le oper ation (32k codes) single oper ation windo w (16 codes) HCS361 ds40146c -page 16 preliminary ? 1996 microchip technology inc. 8.0 electrical chara cteristics t able 8-1 absolute maximum ra tings t able 8-2 dc chara cteristics symbol item rating units v dd supply v oltage -0.3 to 6. 9 v v in input v oltage -0.3 to v dd + 0.3 v v out output v oltage -0.3 to v dd + 0.3 v i out max output current 25 ma t stg stor age temper ature -55 to +125 c (note) t lsol lead solder ing temp 300 c (note) v esd esd r ating 4000 v note: stresses abo v e those listed under ?bsolute maximum ra tings ma y cause per manent damage to the de vice . commercial (c): t amb = 0 c to +70 c industr ial (i): t amb = -40 c to +85 c 2.0v < v dd < 3. 3 3.0 < v dd < 6. 6 p arameter sym. min t yp 1 max min t y p 1 max unit conditions oper ating current (a vg) i cc 0.3 1. 2 0.7 1. 6 ma v dd = 3.3v v dd = 6.6v standb y current i ccs 0.1 1.0 0.1 1.0 m a a uto-shutoff current 2,3 i ccs 40 75 160 350 m a high le v el input v oltage v ih 0. 55 v dd v dd +0.3 0. 55v dd v dd +0.3 v lo w le v el input v oltage v il -0.3 0.15 v dd -0.3 0. 15 v dd v high le v el output v oltage v oh 0. 7v dd 0. 7v dd v i oh = -1.0ma, v dd = 2.0v i oh = - 2.0ma, v dd = 6.6v lo w le v el output v oltage v ol 0.08 v dd 0.08 v dd v i ol = 1.0ma, v dd = 2.0v i ol = 2.0ma, v dd = 6.6v led sink current i led 0.15 1.0 4.0 0.15 1.0 4.0 ma vled = 1.5v , v dd = 6.6v resistance; s0-s3 r s 0-3 40 60 80 40 60 80 k w v dd = 4.0v resistance; pwm r pwm 80 120 1 60 80 120 160 k w v dd = 4.0v note 1: t ypical v alues are at 25 c . 2: a uto-shutoff current speci cation does not include the current through the input pulldo wn resistors . 3: a uto-shutoff current is per iodically sampled and not 100% tested. HCS361 ? 1996 microchip technology inc. preliminary ds40146c -page 17 figure 8-1: p o wer up and transmit timing t able 8-3 po wer up and transmit timing requirements figure 8-2: pwm f ormat summar y ( vpwm = 0 ) v dd = +2.0 to 6.6v commercial (c): t amb = 0 c to +70 c industr ial (i): t amb = -40 c to +85 c p arameter symbol min max unit remarks time to second b utton press t bp 10 + code w ord time 26 + code w ord time ms ( note 1 ) t r ansmit dela y from b utton detect t td 4.5 26 ms ( note 2 ) debounce dela y t db 4 13 ms a uto-shutoff time-out per iod t to 15 35 s ( note 3 ) note 1: t bp is the time in which a second b utton can be pressed without completion of the rst code w ord and the intention w as to press the combination of b uttons . 2: t r ansmit dela y max im um v alue if the pre vious tr ansmission w as successfully tr ansmitted. 3: the auto shutoff timeout per iod is not tested. button press sn detect t db pwm t td code w ord t r ansmission t to code w ord 1 code w ord 2 code w ord 3 code w ord n t bp logic ? logic ? preamb le header encr ypted p or tion of t r ansmission fix ed por tion o f t r ansmission guard time t p t h t hop t fix t g t bp t e t e t e txwak = 0 t bp txwak = 1 logic ? logic ? HCS361 ds40146c -page 18 preliminary ? 1996 microchip technology inc. figure 8-3: pwm preamb le/header f ormat figure 8-4: pwm data w or d f ormat figure 8-5: vpwm format s ummar y (vpwm = 1) figure 8-6: vpwm w akeup format figure 8-7: vpwm preamb le/header format figure 8-8: vpwm data w or d format preamb le spm = 0 header spm = 1 10t e 30t e 10t e bit 0 bit 1 header bit 30 bit 31 bit 32 bit 33 bit 58 bit 59 fix ed code data encr ypted data guard lsb lsb msb msb s3 s0 s1 s2 v low crc0 crc1 time ser ial number function code status bit 60 bit 61 bit 62 bit 63 bit 64 bit 65 crc bit 66 w ak eup dead time preamb le encr ypt ser ial number function header v low crc w ak eup dead time 252 t e 256 t e t e preamb le spm = 0 header spm = 1 10t e 30t e 10t e 1 0 0 1 0 1 2 3 1 0 1 1 28 29 30 31 1 0 0 1 28 29 30 31 1 0 0 1 56 57 58 59 1 0 0 1 60 61 62 63 1 0 64 65 1 66 encr ypted data ser ial number function code v low crc note: the bit v alues are only sho wn as an e xample . bit HCS361 ? 1996 microchip technology inc. preliminary ds40146c -page 19 figure 8-9: HCS361 normaliz ed t e vs. t emp 0.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.7 0.6 t e min. t e max. v dd legend = 2.0v = 3.0v = 6.0v t ypical t e t emper ature c -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 t able 8-4 code w or d t ransmission timing p arameter s pwm mode (txw ak = 0) v dd = +2.0 to 6.6v commercial (c): t amb = 0 c to +70 c industr ial (i): t amb = -40 c to +85 c code w or ds t ransmitted f ast = 0, txw ak = 0 f ast = 1, txw ak = 0 symbol characteristic number of t e min t yp. max. number of t e min. t yp. max. units t e basic pulse element 1 260 400 620 1 130 200 310 m s t bp pwm bit pulse width 3 780 1200 1860 3 390 600 930 m s t p preamb le dur ation 28 7.3 11.2 17.4 28 3.6 5.6 8.7 ms t h header dur ation 10 2.6 4.0 6.2 10 1.3 2.0 3.1 ms t hop hopping code dur ation 96 25.0 38.4 59.5 96 12.5 19.2 29.8 ms t fix fix ed code dur ation 105 27.3 42.0 65.1 105 13.7 21.0 32.6 ms t g guard time 16 4.2 6.4 9.9 32 4.2 6.4 9.9 ms ? t otal t r ansmit time 255 66.3 102.0 158.1 271 35.2 54.2 84.0 ms ? pwm data r ate ? 1282 833 538 ? 2564 1667 1075 bps note: the timing par ameters are not tested b ut der iv ed from the oscillator cloc k. pwm mode (txw ak = 1) v dd = +2.0 to 6.6v commercial (c): t amb = 0 c to +70 c industr ial (i): t amb = -40 c to +85 c code w or ds t ransmitted f ast = 0, txw ak = 1 f ast = 1, txw ak = 1 symbol characteristic number of t e min t yp. max. number of t e min. t yp. max. units t e basic pulse element 1 130 200 310 1 65 100 155 m s t bp pwm bit pulse width 6 780 1200 1860 6 390 600 930 m s t p preamb le dur ation 28 3.6 5.6 8.7 28 1.8 2.8 4.3 ms t h header dur ation 10 1.3 2.0 3.1 10 0.7 1.0 1.6 ms t hop hopping code dur ation 192 25.0 38.4 59.5 192 12.5 19.2 29.8 ms t fix fix ed code dur ation 210 27.3 42.0 65.1 210 13.7 21.0 32.6 ms t g guard time 32 4.2 6.4 9.9 64 4.2 6.4 9.9 ms ? t otal t r ansmit time 472 61.4 94.4 146.3 504 32.8 50.4 78.1 ms ? pwm data r ate 1282 833 538 2564 1667 1075 bps note: the timing par ameters are not tested b ut der iv ed from the oscillator cloc k. HCS361 ds40146c -page 20 preliminary ? 1996 microchip technology inc. t able 8-5 code w or d t ransmission timing p arameter s vpwm mode (f ast = 0) v dd = +2.0 to 6.6v commercial (c): t amb = 0 c to +70 c industr ial (i): t amb = -40 c to +85 c code w or ds t ransmitted f ast = 0, shor test f ast = 0, long est symbol characteristic number of t e min t yp. max. number of t e min. t yp. max. units t e basic pulse element 1 260 400 620 1 260 400 620 m s t p preamb le dur ation 28 7.3 11.2 17.4 28 7.3 11.2 17.4 ms t h header dur ation 10 2.6 4.0 6.2 10 2.6 4.0 6.2 ms t hop hopping code dur ation 32 8.3 12.8 19.8 64 16.6 25.6 39.7 ms t fix fix ed code dur ation 35 9.1 14.0 21.7 70 18.2 28.0 43.4 ms t g guard time 112 29.1 44.8 69.4 112 29.1 44.8 69.4 ms ? t otal t r ansmit time 217 56.4 86.8 134.5 284 73.8 113.6 176.1 ms ? vpwm data r ate ? 3846 2500 1613 ? 3846 2500 1613 ms note: the timing par ameters are not tested b ut der iv ed from the oscillator cloc k. vpwm mode (f ast = 1) v dd = +2.0 to 6.6v commercial (c): t amb = 0 c to +70 c industr ial (i): t amb = -40 c to +85 c code w or ds t ransmitted f ast = 1, shor test f ast = 1, long est symbol characteristic number of t e min t yp. max. number of t e min. t yp. max. units t e basic pulse element 1 130 200 310 1 130 200 310 m s t p preamb le dur ation 28 3.6 5.6 8.7 28 3.6 5.6 8.7 ms t h header dur ation 10 1.3 2.0 3.1 10 1.3 2.0 3.1 ms t hop hopping code dur ation 32 4.2 6.4 9.9 64 8.3 12.8 19.8 ms t fix fix ed code dur ation 35 4.6 7.0 10.9 70 9.1 14.0 21.7 ms t g guard time 224 29.1 44.8 69.4 224 29.1 44.8 69.4 ms ? t otal t r ansmit time 329 42.8 65.8 102.0 396 51.5 79.2 122.8 ms ? vpwm data r ate ? 7692 5000 3226 ? 7692 5000 3226 bps note: the timing par ameters are not tested b ut der iv ed from the oscillator cloc k. HCS361 ? 1996 microchip technology inc. preliminary ds40146c -page 21 notes: HCS361 ds40146c -page 22 preliminary ? 1996 microchip technology inc. notes: HCS361 ? 1996 microchip technology inc. preliminary ds40146c -page 23 HCS361 pr oduct identification system t o order or obtain inf or mation, e .g., on pr icing or deliv er y , ref er to the f actor y or the listed sales of ce . sales and suppor t p ac ka g e: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body) , 8-lead t emperature blank = 0 ? c to +70 ? c rang e: i = ?0 ? c to +85 ? c de vice: HCS361 code hopping encoder HCS361 t code hopping encoder (t ape and reel) HCS361 /p data sheets products suppor ted b y a preliminar y data sheet ma y ha v e an err ata sheet descr ibing minor oper ational diff erences and recom- mended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: 1. y our local microchip sales of ce (see last page) 2. the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277 3. the microchip s bulletin board, via y our local compuser v e n umber (compuser v e membership no t required). please specify which de vice , re vision of silicon and data sheet (include liter ature #) y ou are using. information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip s products as critical components in life sup port systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the m icrochip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds40146c-page 24 preliminary ? 1997 microchip technology inc. w orldwide s ales & s ervice americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602-786-7200 fax: 602-786-7277 technical support: 602 786-7627 web: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 708-285-0071 fax: 708-285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 972-991-7177 fax: 972-991-8588 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 714-263-1888 fax: 714-263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516-273-5305 fax: 516-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia paci? rm 3801b, tower two metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 india microchip technology india no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-299-4036 fax: 91-80-559-9840 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?n road west, hongiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 singapore microchip technology taiwan singapore branch 200 middle road #10-03 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2-717-7175 fax: 886-2-545-0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44-1628-851077 fax: 44-1628-850259 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 m?chen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleone palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-39-6899939 fax: 39-39-6899883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81-4-5471- 6166 fax: 81-4-5471-6122 1/14/97 printed on recycled paper. all rights reserved. ?1997, microchip technology incorporated, usa. 1/97 m |
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