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lan?sc520 microcontroller customer development platform user?s manual order #22450C acdp.book page 1 wednesday, april 4, 2001 10:57 am
lan?sc520 microcontroller customer development platform user?s manual ? copyright 2001 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set fo rth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a partic ular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. no support obligation: amd is not obligated to furnish, support, or make any further information, software, technical information, know-how, or show-how available to you. amd, the amd logo, combinations thereof, am186, amdebug, amd-k6, e86, lan, and pcnet are trademarks, am486 is a registered trademark, and fusione86 is a service mark of advanced micro devices, inc. mmx is a trademark of intel corporation. windows and windows nt are registered trademarks of microsoft corporation. netware is a registered trademark of novell, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. acdp.book page ii wednesday, april 4, 2001 10:57 am
if you have questions, we ? re here to help you. the amd customer service network includes u.s. offices, international offices, and a customer training center. expert technical assistance is available from the amd worldwide staff of field application engineers and factory support staff to answer e86 ? family hardware and software development questions. frequently accessed numbers are listed below. additional contact information is listed on the back of this manual. amd ? s www site lists the latest phone numbers. technical support answers to technical questions are available online, through e-mail, and by telephone. go to amd ? s home page at www.amd.com and follow the support link for the latest amd technical support phone numbers, software, and frequently asked questions. for technical support questions on all embedded system products, send e-mail to epd.support@amd.com (in the us and canada) or euro.tech@amd.com (in europe and the uk). you can also call the amd corporate applications hotline at: (800) 222-9323 toll-free for u.s. and canada 44-(0) 1276-803-299 u.k. and europe hotline www support for specific information on e86 products, access the amd home page at www.amd.com and follow the embedded processors link. these pages provide information on upcoming product releases, overviews of existing products, information on product support and tools, and a list of technical documentation. support tools include online benchmarking tools and codekit software ? tested source code example applications. many of the technical documents are available online in pdf form. questions, requests, and input concerning amd ? s www pages can be sent via e-mail to web.feedback@amd.com . documentation and literature support data books, user ? s manuals, data sheets, application notes, and product cds are free with a simple phone call. internationally, contact your local amd sales office for product literature. to order literature, go to www.amd.com/support/literature.html or, in the u.s. and canada, call (800) 222-9323. third-party support amd fusione86 sm partners provide an array of products designed to meet critical time-to-market needs. products and solutions available include emulators, hardware and software debuggers, board-level products, and software development tools, among others. the www site and the e86? family products development tools cd , order #21058, describe these solutions. in addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. acdp.book page iii wednesday, april 4, 2001 10:57 am
acdp.book page iv wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual v contents about the lan ? sc520 microcontroller customer development platform features............................................................................................................... xii documentation .................................................................................................. xiii about this manual......................................................................................... xiii suggested reference material ...................................................................... xiv documentation conventions ........................................................................xv chapter 1 quick start setting up the lan ? sc520 microcontroller cdp.......................................... 1-2 set-up requirements .................................................................................... 1-3 set-up procedure .......................................................................................... 1-5 starting from a floppy disk........................................................................ 1-14 starting from an ide hard disk drive ....................................................... 1-15 acdp.book page v wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual vi chapter 2 features and functions block diagram and component locations........................................................ 2-2 descriptions ....................................................................................................... 2-6 lan ? sc520 microcontroller ...................................................................... 2-6 10/100baset ethernet controller.................................................................. 2-7 super i/o ....................................................................................................... 2-8 pci card slots ............................................................................................. 2-10 isa card slots (general-purpose bus slots) .............................................. 2-10 test interface port (tip) connector ............................................................ 2-10 logic analyzer connector .......................................................................... 2-10 high-speed uart ...................................................................................... 2-11 low-speed uart....................................................................................... 2-11 hexadecimal led display.......................................................................... 2-11 memory ....................................................................................................... 2-12 amdebug ? tool........................................................................................ 2-17 in-circuit emulator (ice) connector.......................................................... 2-17 synchronous serial interface....................................................................... 2-17 integrated drive electronics (ide) ............................................................. 2-17 optional daughter modules ........................................................................ 2-18 acdp.book page vi wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual vii appendix a jumper and dip switch settings jumper settings ................................................................................................ a-1 jumper jp2 ................................................................................................... a-2 jumper jp3 ................................................................................................... a-3 jumper jp4 ................................................................................................... a-4 jumper jp5 ................................................................................................... a-5 isa dma selection, jumpers jp6 ? jp9 ....................................................... a-6 jumpers jp10, jp11, jp12, jp13, and jp14.................................................a-11 jumper jp18 ............................................................................................... a-12 jumper jp20 ............................................................................................... a-13 dip switch settings........................................................................................ a-14 dip switch s3 ............................................................................................ a-14 dip switch s4 ............................................................................................ a-15 dip switch s5 ............................................................................................ a-16 appendix b resource assignments chip select resource assignments ...................................................................b-2 gpirq resource assignments..........................................................................b-3 gpdma resource assignments .......................................................................b-4 pio resource assignments ...............................................................................b-5 uart resource assignments...........................................................................b-7 index index ........................................................................................................... index-1 acdp.book page vii wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual viii list of figures figure 1-1. jumper jp20....................................................................................................... 1- 8 figure 1-2. older type of 34-pin floppy disk cable........................................................ 1-10 figure 1-3. newer type of 34-pin floppy disk cable ...................................................... 1-11 figure 1-4. wiring connection changes on 34-pin ribbon cable .................................... 1-13 figure 2-1. lan ? sc520 microcontroller cdp block diagram ........................................ 2-3 figure 2-2. lan ? sc520 microcontroller cdp board layout ........................................... 2-4 figure 2-3. connectors on the lan ? sc520 microcontroller cdp .................................... 2-5 figure 2-4. on-board 10/100 mbit/s ethernet controller block diagram .......................... 2-7 figure 2-5. super i/o block diagram .................................................................................. 2-9 figure 2-6. sdram configuration diagram..................................................................... 2-13 figure 2-7. flash memory configuration for lan ? sc520 microcontroller cdp .......... 2-15 figure 2-8. flash memory configuration block diagram................................................. 2-16 figure a-1. jumper jp2 default setting .............................................................................. a-2 figure a-2. jumper jp3 default setting .............................................................................. a-3 figure a-3. jumper jp4 default setting .............................................................................. a-4 figure a-4. jumper jp5 default setting .............................................................................. a-5 figure a-5. jumper jp6, jp7, jp8, and jp9 pin numbering ................................................ a-6 figure a-6. jumper jp6 default routing............................................................................. a-7 figure a-7. jumper jp7 default routing............................................................................. a-8 figure a-8. jumper jp8 default routing............................................................................. a-9 figure a-9. jumper jp9 default routing........................................................................... a-10 figure a-10. jumper jp18 default setting .......................................................................... a-12 figure a-11. jumper jp20.................................................................................................... a-13 figure a-12. dip switch s3 default setting ....................................................................... a-14 figure a-13. dip switch s4 default setting ....................................................................... a-15 figure a-14. dip switch s5 default setting ....................................................................... a-16 acdp.book page viii wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual ix list of tables table 0-1. notational conventions ......................................................................................xv table 2-1. dma channels and irqs reserved for super i/o ........................................... 2-8 table 2-2. sdram signals .............................................................................................. 2-12 table 2-3. chip select (cs) decoder address space....................................................... 2-16 table a-1. dip switch s3 settings .................................................................................. a-14 table a-2. dip switch s4 settings .................................................................................. a-15 table a-3. dip switch s5 settings .................................................................................. a-16 table b-1. chip select resource assignments ...................................................................b-2 table b-2. gpirq resource assignments..........................................................................b-3 table b-3. gpdma resource assignments .......................................................................b-4 table b-4. pio resource assignments ...............................................................................b-5 table b-5. uart resource assignments...........................................................................b-7 acdp.book page ix wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual x acdp.book page x wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual xi about the lan ? sc520 microcontroller customer development platform the lan ? sc520 microcontroller customer development platform (cdp) provides a robust evaluation and development platform for the lansc520 microcontroller. using the lansc520 microcontroller, sdram, am79c973 ethernet controller, and pci bus, the lansc520 microcontroller cdp serves as a platform for embedded product development. within the lansc520 microcontroller cdp, the embedded pci bus controller works well with other pci- ready peripherals (audio, video, etc.). the lansc520 microcontroller cdp uses an on-board 10/100 mbit/s ethernet based on the am79c973 pcnet ? - fast iii device. in addition, the lansc520 microcontroller cdp uses an ali super i/o for additional interface functionality including serial (two), parallel, irda, floppy, keyboard, and mouse devices. the lansc520 microcontroller cdp contains 16-mbytes of flash memory that is expandable to an additional 32 mbytes through a daughter module (with a flexible 8- and 16-bit configuration on the gp-bus or 8-, 16-, or 32-bit on a sdram data bus), system configuration jumpers, and pci and isa expansion connectors. the lansc520 microcontroller cdp uses an atx form factor. the lansc520 microcontroller cdp enables you to: develop firmware and application code for the lansc520-based embedded microcontroller benchmark embedded, network-ready applications on the high performance lansc520 microcontroller make power measurements experiment with design trade-offs and assemble an lansc520 microcontroller system using off-the-shelf components. acdp.book page xi wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual xii features the lansc520 microcontroller cdp contains the following features: 10/100baset ethernet super i/o peripheral chip containing: - floppy device - two serial devices (one irda shared with serial port 2) - one parallel device - keyboard -mouse three pci card slots two isa card slots test interface port (tip) connector high-speed uart port low-speed uart port hex led display logic analyzer connector (amp mictor type) sdram (two 168-pin dimm sockets) 16-mbyte on-board flash memory amdebug ? (jtag-compliant) test interface tool (connector pod1 or pod2) in-circuit emulator (ice) connector (j10) support using a prom ice device synchronous serial interface (ssi) integrated drive electronics (ide) acdp.book page xii wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual xiii documentation the lan ? sc520 microcontroller customer development platform user ? s manual provides information about the system, features, functions, and interfaces. additional information can be found in ? suggested reference material ? on page xiv. about this manual chapter 1, ? quick start ? , describes how to quickly set up and begin using the lansc520 microcontroller cdp. chapter 2, ? features and functions ? , describes the features and functions of the lansc520 microcontroller cdp. appendix a, ? jumper and dip switch settings ? , describes the various jumpers, switches, and settings. appendix b, ? resource assignments ? , describes the resource assignments for chip select, gpirq, gpdma, pio, and uart. a standard index is also included. acdp.book page xiii wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual xiv suggested reference material the following amd documentation may be of interest: lan ? sc520 microcontroller register set manual , order #22005 lan ? sc520 microcontroller user ? s manual , order #22004 lan ? sc520 microcontroller data sheet , order #22003 am486 ? microprocessor software user ? s manual , order #18497 amd test interface port board user ? s manual , order #22505a am79c973/am79c975 pcnet ? -fast iii single-chip10/100 mbps pci ethernet controller with onnow support , order #21510 e86 ? family products development tools cd , order #21058 for current application notes and technical bulletins, see our world wide web page at www.amd.com . the following non-amd documentation may also be of interest to you: pci local bus specification , production version, revision 2.1, june 1, 1995, pci special interest group, 800-433-5177 (us, 503-693-6232 (international), www.pcisig.com . ieee std 1148\9.1-1990 standard test access port and boundary-scan architecture (order #sh16626-nyf), institute of electrical and electronic engineers, inc., 800-678-4333, www.ieee.org . pci system architecture , mindshare, inc., third edition. reading, ma: addison-wesley, 1995, isbn 0-201-40993-3. isa system architecture , mindshare, inc., third edition. reading, ma: addison-wesley, 1995, isbn 0-201-40996-8. the indispensable pc hardware book , hans-peter messmer, third edition. wokingham, england: addison-wesley, 1995, isbn 0-201-40399-4. acdp.book page xiv wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual xv documentation conventions the lan ? sc520 microcontroller customer development platform user ? s manual uses the notational conventions shown in table 0-1 (unless otherwise noted). table 0-1. notational conventions symbol usage boldface indicates that characters must be entered exactly as shown, except that the alphabetic case is only significant when indicated. italic indicates a descriptive term to be replaced with a user-specified term. typewriter face indicates computer text input or output in an example or listing. exe indicates a dos executable file. hex indicates an intel extended hex file. <> encloses a required parameter. to include the information described within the angle brackets, type only the parameters, not the angle brackets themselves. [] encloses an optional parameter. to include the information described within the brackets, type only the parameter, not the brackets themselves. | separates alternate choices in a list. only one of the choices can be entered. acdp.book page xv wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual xvi acdp.book page xvi wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-1 chapter 1 quick start this chapter provides information to enable you to quickly set up and start using the lansc520 microcontroller customer development platform (cdp). the following sections describe how to connect, power up, and begin using the board. the lansc520 microcontroller is shipped with a bios that has been configured specifically for the chipset used on this platform. the bios contains the code that enables the lansc520 microcontroller to function as a standard at-compatible pc, using at-compatible displays, display adapters, mouse, and keyboards. details on the bios can be found in the online bios documentation shipped with your kit. the lansc520 microcontroller can run at-compatible operating system software. you can start the system with either a bootable floppy disk or an ata (ide) hard disk drive that has the pre-installed operating system. embedded bios software typically supports the configuration of onboard flash memory as a resident flash disk (rfd) that can also be set up as a boot device. see the online bios manual included with your kit. for information on how to: set up the lansc520 microcontroller cdp, refer to ? set-up procedure ? on page 1-5. boot the lansc520 microcontroller cdp from a floppy disk, refer to ? starting from a floppy disk ? on page 1-14. boot the lansc520 microcontroller cdp from a hard disk drive, refer to ? starting from an ide hard disk drive ? on page 1-15. modify the promice interface cable for booting the lansc520 microcontroller cdp, refer to ? modifying the promice interface cable for booting the lansc520 microcontroller cdp ? on page 1-8. this procedure should be used only with cdp board versions 1.0 ? 1.2. additonal information and utilities are available as codekit software included with your kit. codekit software can also be found at www.amd.com . acdp.book page 1 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-2 setting up the lan ? sc520 microcontroller cdp caution: as with all computer equipment, the lansc520 microcontroller cdp may be damaged by electrostatic discharge (esd). please take proper esd precautions when handling any board. warning: read the following before using the lan ? sc520 microcontroller cdp. before applying power, the following precautions should be taken to avoid damage or misuse of the board: make sure the power connector jp1 (atx power) is plugged into the lansc520 microcontroller cdp correctly. - refer to figure 2-2 on page 2-4 for the jp1 (atx power) connector location. check the materials that were shipped with your kit for readme or errata documentation. read all the information carefully before continuing. for current application notes and technical bulletins, refer to the amd world wide web page at www.amd.com and follow the link to embedded systems. ! acdp.book page 2 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-3 set-up requirements the following items are provided with the lansc520 microcontroller cdp. lansc520 microcontroller (pre-installed) cr2032 lithium battery (pre-installed) 64-mbyte sdram dimm module general software bios (pre-installed) 34-pin ribbon cable with header (for floppy disk drive) 40-pin ribbon cable with header (for ide drive) pci video card you must provide the following items: ps/2 keyboard ps/2 mouse floppy disk drive ide hard disk drive atx power supply (any wattage) color vga monitor (any size) to boot from a floppy disk, you must provide at least the following: a pc/at-compatible 3.5-inch or 5.25-inch floppy disk drive a bootable dos floppy disk to boot from a hard disk drive, you must provide at least the following: an ide hard disk drive pc/at-compatible operating system (pre-installed on the hard disk drive) (dos, microsoft windows) acdp.book page 3 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-4 for correct configuration, the jumper and dip switch settings must be set to the default settings. verify these settings before operating the lansc520 microcontroller cdp; refer to appendix a, ? jumper and dip switch settings ? . if you install both a floppy disk drive and a hard disk drive, you can boot from either device. only one boot disk image (floppy disk or hard disk) is required. for example, you can boot from the floppy disk drive, and then install the operating system on a blank hard disk drive. caution: use the configuration described here when you first start the lansc520 microcontroller cdp. before using other features, read the appropriate sections in chapter 2, ? features and functions. ? ! acdp.book page 4 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-5 set-up procedure note: for block diagram information, refer to figure 2-1 on page 2-3. for layout and connector locations, refer to figure 2-2 on page 2-4. caution: ensure that all connections and settings are correct before powering up the lansc520 microcontroller cdp. incorrect connections or settings can damage the lansc520 microcontroller cdp. perform the following steps to set up the lansc520 microcontroller cdp: 1. remove the lansc520 microcontroller cdp from the shipping carton, and inspect the it to verify that it was not damaged during shipping. the lansc520 microcontroller cdp contains several jumpers. the following steps assume all jumpers are set to the factory default configuration (settings are listed in ? jumper and dip switch settings ? on page a-1). 2. if you are installing a floppy disk drive, perform the following steps: a. inspect the 34-wire, floppy disk drive cable. the red wire along one edge of the ribbon cable indicates wire 1. most cables have a connector for the board at one end and two or more connectors along the length. there may be two different drive connectors at each location to accommodate different drive types. b. connect one end of the floppy disk drive cable to the 34-pin connector (connector p13) on the lansc520 microcontroller cdp (with wire 1 oriented towards the led displays). if there is a twist in one span of the cable, connect the opposite end to the board. note the pin-1 position. c. connect the other connector on the floppy disk drive cable to the floppy disk drive, just as you would for a standard pc installation. if there is a twist in the cable, the position you use determines whether the drive responds as a or b (typically drive a connects to the end of the cable, beyond the twist). the connector ? s orientation should be indicated in the drive documentation, or marked near the connector on the drive. usually wire 1 is oriented towards the drive ? s power cable connector. d. find one of the 4-wire power connectors from the pc power supply and attach it to the 4-pin connector on the floppy disk drive just as you would for a standard pc installation. ! acdp.book page 5 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-6 3. if you are installing a hard disk drive, perform the following steps: a. connect the 40-pin hard disk drive cable into the ide box header (p3). note the pin-1 position. the red wire along one edge of the ribbon cable indicates wire 1. b. connect one end of the 40-wire ide cable to the hard disk drive just as you would for a standard pc installation. the connector ? s orientation should be indicated in the drive documentation, or marked near the connector on the drive. usually wire 1 is oriented towards the drive ? s power cable connector. c. connect the other end of the 40-wire ide cable to the first 40-pin connector (connector p3) on the lansc520 microcontroller cdp (with wire 1 oriented towards the led displays). d. find one of the 4-wire power connectors from the pc power supply and attach it to the 4-pin connector on the hard disk drive just as you would for a standard pc installation. 4. connect the monitor cable from the monitor to the d-connector on the video card just as you would for a standard pc. 5. connect the isa vga or pci video card into one of the isa or pci slots. 6. connect the sdram dimm module into either j2 or j3. 7. the lansc520 microcontroller is pre-installed in the lansc520 microcontroller cdp. if the microcontroller is mounted in a zif socket and you need to re-seat or replace the microcontroller, perform the following steps: a. lift the lever-bar of the socket to the vertical position. b. place the lansc520 microcontroller over the zif socket, and then align the golden arrow on the lansc520 microcontroller with the upper-left corner (pin-a1) of the socket. c. place the lansc520 microcontroller flat on the zif socket, and then lock the lever-bar by pushing it down to the horizontal position. 8. connect the ps/2 keyboard cable into the j1 lower-socket. note: the keyboard and mouse socket positions have changed in board revision 1.4. they were reversed in previous board versions. 9. connect the ps/2 mouse cable into the j1 upper-socket. 10. connect the atx power connector into the jp1 connector. acdp.book page 6 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-7 configuring the system setup (bios) setting perform the following steps to configure the system setup (bios) setting: 1. in the drive assignment order: a. set drive a: to floppy drive 0. b. set drive c: to ide 0 (master 1). 2. in the boot order block: a. set boot 1st to drive a:. b. set boot 2nd to drive c:. 3. in the ide drive geometry block, set device ide0 to ? auto config, physical ? (typically for drives smaller than 1 gbyte) or ? auto config, lba ? (typically for drives 1 gbyte and larger). if only one ide device exists, set the other ide devices to ? not installed. ? 4. in the floppy disk drive type block, set floppy 0: to 1.44 mbyte, 3.5. acdp.book page 7 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-8 modifying the promice interface cable for booting the lan ? sc520 microcontroller cdp note: for cdp board versions 1.3 or 1.4, use either of the following jumper settings on jumper jp20, according to your promice setup. if your cdp board version is 1.3 or 1.4, skip ? modifying the promice interface cable procedure ? on page 1-9. setting jumper jp20 according to your promice setup use either of the following jumper settings on jumper jp20 according to your promice setup. for the location of jumper jp20, refer to ? lan ? sc520 microcontroller cdp board layout ? on page 2-4. when using flash memory or a modified promice cable, jumper pins 1 and 3 and jumper pins 2 and 4. when using promice with the original cable (requiring no cable modifications), jumper pins 3 and 5 and jumper pins 4 and 6. figure 1-1. jumper jp20 1 2 3 4 5 6 acdp.book page 8 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-9 modifying the promice interface cable procedure note: this procedure applies only to cdp board versions 1.0 ? 1.2. the lansc520 microcontroller cdp enables you to boot either from a rom/flash device in a 32-pin dip socket u17, or from a promice (or compatible rom emulator) that is connected to the 34-pin connector labeled prom ice (located adjacent to the diskette 34-pin connector). the boot device is selected by positioning jp18 to pins 1 and 2 for the dip socket, and to pins 2 and 3 for the promice. the promice interface for the rev 1.2 lansc520 microcontroller cdp is designed in strict accordance with pinouts given in the promice user ? s manual, version 3.4. however, this reference refers to uv-eprom instead of the more popularly used eeprom and flash memory devices, making the lansc520 microcontroller cdp incompatible. to fix this condition, perform one of the following tasks: modify a 34-pin floppy disk cable. to modify a 34-pin floppy disk cable, perform step 1 on the following pages. step 1 describes how to remove the extra connectors prior to making the wiring connection changes in step 2. step 1 is optional, but is recommended. make a standard 34-pin cable by using a cable press to attach a berg connector to both ends of a ribbon cable. after making the standard 34-pin ribbon cable, perform step 2 to change the wiring connections. acdp.book page 9 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-10 1. to modify a 34-pin floppy disk cable, perform the following steps: the floppy disk cable contains extra connectors that are not required for this application. after cutting off the extra connectors, the modified cable contains the correct connectors that are properly keyed for the promice application. note: if you are using a newer type of floppy disk cable (not containing any card- edge interface connectors), perform step 1.b. instead of step 1.a. a. if you are using an older type of floppy disk cable (containing card-edge interface connectors), use a razor knife or scissors to cut the cable as shown in figure 1-2, and then proceed to step 2 to make the required wiring connection changes. after cutting the cable, make sure none of the exposed wires at the edge of the cut cable are touching. figure 1-2. older type of 34-pin floppy disk cable cable twist berg connector cut the cable here berg connector berg connector (this connector plugs into the board) 34-pin cable after modification acdp.book page 10 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-11 b. if you are using a newer type of floppy disk cable (not containing any card- edge interface connectors), use a razor knife or scissors to cut the cable as shown in figure 1-3, and then proceed to step 2 to make the required wiring connection changes. after cutting the cable, make sure none of the exposed wires at the edge of the cut cable are touching. figure 1-3. newer type of 34-pin floppy disk cable note: the information provided in step 2 and figure 1-4 assumes that you are supporting the emulation of a 256k flash device, because address lines a18 and a19 are tied high. 2. to change the wiring connections on the 34-pin cable, perform the following steps: a. being careful not to cut into the insulation of the wires, use a razor knife to separate wires 2, 3, 4 and 5 from each other and from the other cable wires, as shown in figure 1-4. b. cut wires 2, 3, 4, and 5, as shown in figure 1-4. cable twist berg connector cut the cable here berg connector berg connector (this connector plugs into the board) 34-pin cable after modification acdp.book page 11 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-12 c. remove about a half-inch of insulation from the ends of the following wires: wires 2, 3, 4, and 5 on the side of the cable that connects to the promice wire 4, on the side of the cable that connects to the lansc520 microcontroller cdp. note: do not remove the insulation from wires 2, 3, and 5 located on the side of the cable that connects to the lansc520 microcontroller cdp. d. connect exposed wires 2, 3, and 4 by twisting the wire-ends together. e. this connection provides a pull-up for a18 and a19 to vcc because they are not used in addresses 256k ? 1 and below. f. connect exposed wire 4 to exposed wire 5 by twisting the wire-ends together. g. this connection fixes the compatibility issue originating in the promice user ? s manual. h. to ensure that the exposed connected wires do not touch other wires, use electrical tape to cover the exposed wires. acdp.book page 12 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-13 figure 1-4. wiring connection changes on 34-pin ribbon cable wire 1 (red) exposed wires 2, 3, and 4 twisted together promice connector lansc520 microcontroller cdp connector exposed wires 4 and 5 twisted together 2 3 4 5 4 acdp.book page 13 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-14 starting from a floppy disk use the following steps to start the lansc520 microcontroller cdp from a bootable floppy disk: 1. make sure you have installed the lansc520 microcontroller cdp correctly as described in ? set-up procedure ? on page 1-5. caution: failure to verify the power supply connections can result in total destruction of the lansc520 microcontroller cdp. 2. plug the vga monitor into an electrical outlet and turn it on. 3. insert a bootable dos floppy disk (not included) in the floppy disk drive. 4. apply power to the lansc520 microcontroller cdp by connecting the pc power supply to an electrical outlet. if the power supply is equipped with a switch, turn it on. then turn on the power switch on the cdp. the power supply fan should start running, and the port 80h and 680h leds should start to display power-on self-test (post) status codes. then the speaker should beep and the monitor should start displaying startup information. 5. the first time you start the system, the bios might display a message reporting a cmos error or some other bios configuration problem. follow the instructions shown on the screen to enter the setup utility. once you are in the setup utility, you can set the system ? s date, time, startup drive, and other options. for more information on the included bios, including power-on status codes, see the online bios manual included with your kit. 6. save and exit the setup utility. 7. the system should now boot from the dos floppy disk just like a standard pc. ! acdp.book page 14 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-15 starting from an ide hard disk drive use the following steps to start up the lansc520 microcontroller cdp from an ide hard disk drive on which you have pre-installed an operating system (while it was connected to another pc): 1. make sure you have installed the lansc520 microcontroller cdp correctly as described in ? set-up procedure ? on page 1-5. caution: failure to verify the power supply connections can result in total destruction of the lansc520 microcontroller cdp. 2. plug the vga monitor into an electrical outlet and turn it on. 3. if a floppy disk drive is installed, make sure it is empty. 4. apply power to the lansc520 microcontroller cdp by connecting the pc power supply to an electrical outlet. if the power supply is equipped with a switch, turn it on. then turn on the power switch on the cdp. the power supply fan and hard disk should start running, and the port 80h and port 680h leds should start to display power-on self-test (post) status codes. then the speaker should beep and the monitor should start displaying startup information. 5. the first time you start the system, the bios might display a message reporting a cmos error or some other bios configuration problem. follow the instructions shown on the screen to enter the setup utility. once you are in the setup utility, you can set the system ? s date, time, startup drive, and other options. for more information on the included bios, including power-on status codes, see the online bios manual included with your kit. 6. save and exit the setup utility. 7. the system should now boot using the operating system on the hard disk drive. ! acdp.book page 15 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 1-16 acdp.book page 16 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-1 chapter 2 features and functions the lansc520 microcontroller customer development platform (cdp) is designed for validating features and functionality, qualifying specifications on the lansc520 microcontroller, and for developing customer applications. for more information about the components of the lansc520 microcontroller cdp, refer to the following sections: lansc520 microcontroller, page 2-6 10/100baset ethernet, page 2-7 super i/o and serial ports, page 2-8 - floppy device - two serial devices - one parallel device - keyboard -mouse pci card slots, page 2-10 isa card slots, page 2-10 test interface port (tip) connector, page 2-10 logic analyzer connector, page 2-10 high-speed uart, page 2-11 low-speed uart, page 2-11 hexadecimal led display, page 2-11 sdram, page 2-12 16-mbyte onboard flash memory, page 2-14 amdebug ? (jtag-compliant) test interface, page 2-17 acdp.book page 1 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-2 in-circuit emulator (ice) connector support using prom ice, page 2-17 synchronous serial interface (ssi), page 2-17 integrated drive electronics (ide), page 2-17 daughter modules: 32-mbyte flash memory module and tip module, page 2-18 block diagram and component locations the following figures show the features and layout of the lansc520 microcontroller customer development platform: figure 2-1 on page 2-3 shows a block diagram and a summary of the functions of the features. figure 2-2 on page 2-4 shows the board layout and the locations of the components. figure 2-3 on page 2-5 shows the connectors on the lansc520 microcontroller cdp. acdp.book page 2 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-3 figure 2-1. lan?sc520 microcontroller cdp block diagram mouse lansc520 microcontroller hs uart transceiver ls uart transceiver hs/ls uarts sdram dimm slot 2 system clock reset decoupling atx power cfg straps ssi devices mw/spi ssi jtag amdebug jtag/amdebug pci slot 1 pci slot 2 pci slot 3 pcnet ? - fast iii pci local bus pci local bus sdram bus data/ address gp address gp data gp buffer expansion flash card connector data super i/o uart 1 transceiver uart 2 transceiver parallel ide floppy keyboard tip connector isa slot 1 isa slot 2 hex led display dip flash hp headers - gp bus ni header - gp bus gp bus data/address gp bus data/address gp bus data/address gp bus data/address gp bus data/address gp bus data/address sdram dimm slot 1 acdp.book page 3 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-4 figure 2-2. lan ? sc520 microcontroller cdp board layout daq header sdram header pci connector (slt3) isa 0 connector dimm socket atx power am79c973 m512x flash exp dimm socket isa 1 connector pci connector (slt4) pci connector (slt5) flash exp sdram header pci bus header test header test header test header ide floppy pci bus header dip flash tsop-ii rj-45 flash daughter card (32 mbyte) vccpwr cpu interface serial/parallel ports ide cpu interface ms/kb pci interface pci interface pci interface line interface led driver battery prom ice data addr transformer sp503 jp10 jp13 jp11 jp12 jp14 jp2 jp17 jp3 jp4 jp5 jp18 jp9 jp8 jp7 jp6 s3 s4 s5 pod2 pod1 (jtag) tip mouse keyboard hsuart (top, j5) lsuart (bottom, j6) super i/o parallel port (top, j7) super i/o serial ports (bottom, j8, j9) p1 p2 reset lansc520 microcontroller 388-bga gp bus leds leds bank 0 bank 1 jp1 p3 p13 j10 p4 p11 p8 p12 j3 j2 p7 p10 (jtag) (ssi) jp19 power switch jp20 ls1 j12 j13 acdp.book page 4 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-5 figure 2-3. connectors on the lan ? sc520 microcontroller cdp atx-style headers are provided near the ide connector for the following chassis connections: reset switch jp19, speaker ls1, power status led j12, and hd (ide) status led j13. super i/o serial port 1 (com 3, j8) keyboard mouse super i/o parallel port j7 super i/o serial port 2 (com 4, j9) lansc520 microcontroller serial port 0, high-speed uart (com 1, j5, rs-422a) lansc520 microcontroller serial port 1 low-speed uart (com 2, j6, rs-232) board note: the mouse and keyboard connector positions are reversed (keyboard connector on top) in cdp board versions 1.3 and earlier. acdp.book page 5 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-6 descriptions this chapter describes the features and functions of the lansc520 microcontroller cdp. for additional information about the lansc520 microcontroller cdp, refer to the following sections: appendix a, ? jumper and dip switch settings ? for information about jumper and switch settings. appendix b, ? resource assignments ? for information about chip select, gpirq, gpdma, pio on cdp, and uart assignments. for component layout and locations, refer to figure 2-2 on page 2-4. lan ? sc520 microcontroller the lan ? sc520 microcontroller is a full-featured microcontroller developed for the general embedded market. designed for medium- to high-performance applications in the telecommunications, data communications, and information appliance markets, the lansc520 microcontroller is particularly well suited for applications requiring high throughput combined with low latency and low cost. the lansc520 microcontroller utilizes a high-performance, industry-standard, 33-mhz, 32-bit pci bus for high-bandwidth i/o peripherals. the microcontroller also contains a simple 8- and 16-bit general-purpose (gp) bus for a glueless connection to low-bandwidth peripherals. the gp bus supports most legacy isa peripherals. the lansc520 microcontroller utilizes the industry-standard x86 architecture instruction set that enables compatibility across a variety of performance levels from the low-end 16-bit am186 processors to the high-end amd-k6e ? family processors. software written for the x86 architecture family is compatible with the lansc520 microcontroller. with the amdebug technology, the lansc520 microcontroller provides a full- featured, high-performance in-circuit emulation capability that enables you to test and debug your software earlier in the design cycle. acdp.book page 6 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-7 in addition to these features, the lansc520 microcontroller provides a high- performance sdram controller, rom/flash controller, flexible address-mapping hardware, general-purpose bus interface, clock generation, integrated peripherals, jtag boundary scan test interface, and various system test and debug features. for more information about the lansc520 microcontroller, refer to the lan ? sc520 microcontroller data sheet , lan ? sc520 microcontroller user ? s manual , and the lan ? sc520 microcontroller register set manual , which are included in your kit. 10/100baset ethernet controller the lansc520 microcontroller cdp contains the am79c973 pcnet ? - fa s t iii ethernet controller chip. the high-performance 10/100baset ethernet port enables the lansc520 microcontroller cdp to connect to a high-bandwidth lan. external magnetics for a built-in transceiver (phy) are utilized for a full-duplex implementation with an rj45 10/100baset connector. the am79c973 device logically resides on the pci bus and is wired for full bus- mastering capability. the pci address bit 27 is used for the idsel pin of the am79c973 device. the am79c973 registers can be configured by either the pci configuration space mechanism, or by downloading the configuration information from a dedicated serial eeprom (part u30). a 4k serial eeprom is used so that other board-level configuration information can be stored with the am79c973 device configuration parameters. codekit software is provided to read and write the serial eeprom so it can be used for a wide variety of applications. figure 2-4 shows a block diagram of the 10/100baset ethernet. figure 2-4. on-board 10/100 mbit/s ethernet controller block diagram pci bus magnetics rj45 pe-h1081 pcnet ? - fast iii am79c973 acdp.book page 7 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-8 super i/o the ali super i/o chip (acer laboratories, inc., p/n m512x) provides two 16550 compatible uarts (serial ports) that operate at baud rates up to 1.15 mbit/s, one parallel port, a floppy disk interface, irda interface (shared with com4), and a keyboard/mouse controller. note: the two serial ports (com3 and com4) of the super i/o are not the same as the two serial ports (com1 and com2) of the lansc520 microcontroller. the two serial ports facilitate software development and other communications. external transceivers are needed for the serial ports and irda interface. leds indicate tx and rx activity on both serial ports. both serial ports are routed to industry-standard db9 and rs-232 connectors on the lansc520 microcontroller cdp and are named as com3 and com4. note: the bios included with cdp version 1.4 maps the super i/o uarts to com3 and com4. earlier bios versions, used on boards with microcontroller revisions a0 and a1, disabled the microcontroller ? s uarts and mapped the super i/o uarts to com1 and com2 instead. the epp-supported parallel port is routed to an industry-standard db25 connector. the keyboard and mouse use ps/2 connectors. table 2-1 shows the dma channels and the irqs for the super i/o devices. figure 2-5 on page 2-9 shows the block diagram of the super i/o configuration. table 2-1. dma channels and irqs reserved for super i/o devices dma channels reserved for super i/o irqs reserved for super i/o fdd drq0/dack0 irq6 epp (parallel port) drq0/dack 0 irq7 sio1 ? irq4 sio2 ? irq3 kb (keyboard) ? irq1 mouse ? irq12 acdp.book page 8 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-9 figure 2-5. super i/o block diagram super i/o chip floppy disk connector at keyboard connector ps/2 mouse connector serial port 1 connector serial port 2 connector parallel port connector m512x irda transceiver ide connector xcvr xcvr gp bus acdp.book page 9 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-10 pci card slots three industry-standard pci card slots are provided to enable you to plug in most pci-v2.2-compliant peripheral cards to speed up their design process and to reduce development time for your product. the lansc520 microcontroller cdp supports up to five pci masters. the pci card slots are 5v-capable (only). isa card slots (general-purpose bus slots) two industry-standard isa card slots enable you to plug in a variety of off-the- shelf, low-cost isa peripheral cards to achieve design simplicity and reduced development time. test interface port (tip) connector the 60-pin, test interface port (tip) connector enables you to use the optional module to develop software and debug hardware. the tip board contains a rich set of peripherals used for debugging, diagnostics, evaluation, and reference design. the tip board is available through your amd sales contact. logic analyzer connector the logic analyzer connector enables you to use a logic analyzer to debug the application design. all signals from the lansc520 microcontroller are connected to the logic analyzer connectors, except for crystals, clkpciout (pci clocks), and clkmemout (sdram clocks). amd supports the hewlett packard (hp) and tektronix logic analyzer connector without shrouds and the hp connector with shrouds. both types of connectors attach to a specific mictor connector on the lansc520 microcontroller cdp, depending on what feature is being tested. acdp.book page 10 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-11 high-speed uart the high-speed uart (port 0, com1) is embedded in the lansc520 microcontroller. the high-speed uart port enables you to communicate at a speed of up to 1.152 mbit/s through balanced rs-422a-compliant serial ports with other serial communication equipment, for a longer distance and faster speed. you can make the high-speed uart port pin-compatible with the rs-232 by setting the external pin strap. for connector location, refer to figure 2-2 on page 2-4 and figure 2-3 on page 2-5. note: the bios included with cdp version 1.4 maps the microcontroller ? s uarts to com1 and com2. earlier bios versions, used on boards with microcontroller revisions a0 and a1, disabled the microcontroller ? s uarts and mapped the super i/o uarts to com1 and com2 instead. low-speed uart the low-speed uart (port 1, com2) is embedded in the lansc520 microcontroller. the low-speed uart port enables you to communicate at a lower speed of up to 460 kbit/s through a single-ended rs-232-compliant serial port. the low-speed uart is capable of high-speed, like the high-speed uart port, but is restricted through a low-speed transceiver that limits this high-speed uart channel to a lower speed for the purpose of communicating with specific serial communication equipment. note: the bios included with cdp version 1.4 maps the microcontroller ? s uarts to com1 and com2. earlier bios versions, used with microcontroller revisions a0 and a1, disabled the microcontroller ? s uarts and mapped the super i/o uarts to com1 and com2 instead. hexadecimal led display the hexadecimal led display is a single-byte (two digits) hexadecimal led address at 80h and 680h. the hexadecimal led display (error code display) provides indications for cpu status as well as debugging status, which improves the debugging process. acdp.book page 11 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-12 memory the memory on the lansc520 microcontroller cdp consists of sdram and flash memory. sdram the lansc520 microcontroller cdp can have a maximum of four rows on two dimms that connect into two industry-standard, 168-pin dimm sockets. the dimms are 64-bit wide main memory, using 16/64-mbit x 8 sdram chips. note that the sdram dimms used are 64-bits wide only because they are configured as two rows each. error correction code (ecc) is not supported on the full sdram dimms; the ecc supports only half of the dimm capacity. figure 2-6 on page 2-13 shows the sdram configuration diagram. the two dimm sockets are wired to enable you to install a combination of single- or double-sided dimms. this configuration yields a total of four rows of sdram memory, using the two dimm sockets. you can adjust the timing of the sdram interface by using the registers in the lansc520 microcontroller. table 2-2 shows the sdram signals and the descriptions. table 2-2. sdram signals sdram signal description cs0 ? cs3 chip select signal for each row on dimm ma0 ? ma12 memory address signals md0 ? md31 memory data signals ba0 ? ba1 memory bank select signal for each memory chip dqm0 ? dqm3 data byte masks acdp.book page 12 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-13 figure 2-6. sdram configuration diagram dram bus sdram sockets dqm3 ? dqm0 ba1 ? ra0 md31 ? md0 ma12 ? ma0 cs3 cs1 cs2 cs0 socket 2 (j3) socket 1 (j2) 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 2mx8x4 acdp.book page 13 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-14 flash memory the on-board flash memory uses the amd am29lv017b and consists of following configuration: two 8-mbyte banks in a 32-bit data width consisting of eight 2-mbit x 8 devices the flash memory is used for the bios and/or execute-in-place memory that interfaces to the lansc520 microcontroller only through the sdram data bus md31 ? md0 or the residential flash disk (rfd). an additional two banks of flash/rom is optionally available on a 32-mbyte daughter module that can be configured to interface to either the 32-bit sdram md bus (with 8/16/32-bit data width (x32 is only available when data bus is selected on sdram md31 ? md0 and selected by bootcs , romcs1 , or romcs2 )) or with the 16-bit gp bus (with 8- or 16-bit selectable). bootcs can be assigned to each flash bank. romcs1 and romcs2 can be assigned to the 16-mbytes on-board flash bank and/or the 32-mbyte flash daughter card. flash roms are configured as 32-bit wide on both the on-board and daughter modules. if the flash memory is set as 8-bit or 16-bit data width, the higher bytes are not accessible on the lansc520 microcontroller cdp. the lansc520 microcontroller cdp demonstrates the ability of only sizing the data width for rom access. the user can configure it in any bus size to access the entire rom space by rearranging the address bus for bootcs , romcs1 , and romcs2 . the flash rom x8 dip is connected on the gp bus and can be selected only by bootcs . the flash rom x32 onboard memory is connected only on sdram md31 ? md0, and it can be selected by bootcs , romcs1 , and romcs2 . the flash rom daughter module contains configuration jumpers. users can configure the module as x8, x16, x32 data width on the gp bus (gpd15 ? gpd0) or the sdram bus (md31 ? md0). figure 2-7 on page 2-15 shows the flash memory configuration supported by the lansc520 microcontroller cdp. figure 2-8 on page 2-16 shows a flash memory configuration block diagram. table 2-3 on page 2-16 shows the signals, inputs, and outputs for each type of memory. acdp.book page 14 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-15 figure 2-7. flash memory configuration for lan ? sc520 microcontroller cdp expand flash module - romcs2 on-board flash - romcs1 on-board flash - bootcs 0x0000000 0x0ffffff 0x1000000 0x0000000 0x0000000 0x1ffffff 0x2000000 0x3ffffff 0x00001ff 0x0000200 0x3ffffff 0x3ffffff on-board dip on-board tsop-ii flash daughter board (2mx8 x 8) (2mx16 x 8) (max 64mb) acdp.book page 15 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-16 figure 2-8. flash memory configuration block diagram table 2-3. chip select (cs ) decoder address space signal name number of outputs inputs associated with sdram scs3 ? scs0 3 ? 0 ? flash/rom bootcs 1gpa25 ? gpa0, bootcs , cfg2 ? cfg0 romcs1 1gpa25 ? gpa0, romcs1 , cfg2 ? cfg0 romcs2 1gpa25 ? gpa0, romcs2 , cfg2 ? cfg0 512kx8 dip/5v 1mx16 tsop/3v exp flash 1mx16 tsop/3v 1mx16 tsop/3v 1mx16 tsop/3v 1mx16 tsop/3v 1mx16 tsop/3v 1mx16 tsop/3v 1mx16 tsop/3v gp bus dram bus buffer x32 buffer x32 connector acdp.book page 16 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-17 amdebug ? tool this in-system test feature is a standard jtag-compliant test interface. the jtag utilizes two types of 2-mm connectors ? one 20-pin full version (pod1) and one 12-pin simple version (pod2). both connectors are used for the amdebug tool. in-circuit emulator (ice) connector the in-circuit emulator (ice) connector (j10) is used to speed up the design development of application software. the ice connector is a 34-pin, 1/10-inch box header and is supported by prom ice. synchronous serial interface the microcontroller ? s synchronous serial interface (ssi) is populated with a 6-pin, 1/10-inch center sip connector (jp17) that can communicate with an external device. in addition, two on-board eeprom devices are populated on the ssi: one synchronous peripheral interface (spi), and one microwire ? peripheral. these eeprom devices contain no relevant data when the cdp is shipped. they are provided to demonstrate the use of the ssi port with these device types. they can be freely written to or read using the ssi codekit software included with your kit, or downloaded from www.amd.com . integrated drive electronics (ide) one ide channel supports two ide devices: one master and one slave. usually, the bootable device is set on the master and all other devices reside on the slave. the ide uses the gp-bus. header j13 is provided near the ide connector to allow connection of an external drive status led. acdp.book page 17 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual 2-18 optional daughter modules the lansc520 microcontroller cdp can interface with two optional daughter modules: the 32-mbyte flash memory module and the test interface port (tip) module. the 32-mbyte flash memory module provides additional memory for developing and testing applications. the tip provides an additional resource for testing and debugging applications, diagnostics, and hardware. the tip module is available through your amd sales contact. acdp.book page 18 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-1 appendix a jumper and dip switch settings each section in this appendix provides information about settings and operating state descriptions for the respective components. for locations of the various jumpers and dip switches, refer to figure 2-2 on page 2-4. jumper settings the following information provides the jumper settings and pin locations for the various jumpers. acdp.book page 1 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-2 jumper jp2 the following settings indicate the possible configurations for jumper jp2. figure a-1 shows the jumper pins and the default setting for jumper jp2. to set to on or connect to chassis power supply, jumper pins 1 and 2. when using the on-board power supply, pins 1 and 2 are not jumpered. note: jumper jp2 is not meant to be used as an external power switch connector. if it is used to connect to an external switch, an on/off toggle switch must be used (not the momentary-contact type typically used in an atx chassis). figure a-1. jumper jp2 default setting 1 2 to ps-on on jp1 (atx power) to switch s2 acdp.book page 2 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-3 jumper jp3 the following settings indicate the possible configurations for jumper jp3. figure a-2 shows the jumper pins and the default setting for jumper jp3. note: when a row of jumper pins (either pins 1 and 2, pins 3 and 4, or pins 5 and 6) are jumpered on jp3, jumper pins on the same row of jp4 and jp5 cannot be jumpered. for example, if pins 1 and 2 of jp3 are jumpered, then pins 1 and 2 of jp4 and jp5 cannot be jumpered. only one pair (row) of jumper pins can be jumpered on jp3. to boot from the on-board flash bank 0, jumper pins 1 and 2. to boot from the on-board flash bank 1, jumper pins 3 and 4. to boot from the expansion flash board, jumper pins 5 and 6. to boot from the dip flash memory, jumper pins 7 and 8 (shown in figure a-2). figure a-2. jumper jp3 default setting 1 2 3 4 5 6 7 8 acdp.book page 3 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-4 jumper jp4 the following settings indicate the possible configurations for jumper jp4. figure a-3 shows the jumper pins and the default setting for jumper jp4. note: when a row of jumper pins (either pins 1 and 2, pins 3 and 4, or pins 5 and 6) are jumpered on jp4, jumper pins on the same row of jp3 and jp5 cannot be jumpered. for example, if pins 1 and 2 of jp4 are jumpered, then pins 1 and 2 of jp3 and jp5 cannot be jumpered. to select romcs1 for accessing the on-board flash bank 0, jumper pins 1 and 2 (shown in figure a-3). to select romcs1 for accessing the on-board flash bank 1, jumper pins 3 and 4. to select romcs1 for accessing the expansion flash board, jumper pins 5 and 6. figure a-3. jumper jp4 default setting 1 3 5 2 6 4 acdp.book page 4 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-5 jumper jp5 the following settings indicate the possible configurations for jumper jp5. figure a-4 shows the jumper pins and the default setting for jumper jp5. note: when a row of jumper pins (either pins 1 and 2, pins 3 and 4, or pins 5 and 6) are jumpered on jp5, jumper pins on the same row of jp3 and jp4 cannot be jumpered. for example, if pins 1 and 2 of jp5 are jumpered, then pins 1 and 2 of jp3 and jp4 cannot be jumpered. to select romcs2 for accessing the on-board flash bank 0, jumper pins 1 and 2. to select romcs2 for accessing the on-board flash bank 1, jumper pins 3 and 4 (shown in figure a-4). to select romcs2 for accessing the expansion flash board, jumper pins 5 and 6. figure a-4. jumper jp5 default setting 1 3 5 2 6 4 acdp.book page 5 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-6 isa dma selection, jumpers jp6 ? jp9 the lansc520 microcontroller supports two dma channels via its gpdrq0, gpdack0 , gpdrq1, and gpdack1 signals. the isa-compatible signaling on the isa interface provides paths for seven dma channels (0 ? 3 and 5 ? 7), which are shared by attached devices. jumpers jp6, jp7, jp8, and jp9 allow you to route any one isa-bus dma channel to either of the microcontroller ? s two dma channels. figure a-5 shows the pin numbering for these jumpers. figure a-5. jumper jp6, jp7, jp8, and jp9 pin numbering 13 11 9 7 5 3 1 1412108642 acdp.book page 6 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-7 jumper jp6 jumper jp6 is used to route one isa-compatible drqn channel from the pc/ 104-plus connector to the microcontroller ? s gpdrq0 input. the following settings indicate the possible configurations for jumper jp6. to route isa drq0 to microcontroller gpdrq0, jumper pins 1 and 2. to route isa drq1 to microcontroller gpdrq0, jumper pins 3 and 4. to route isa drq2 to microcontroller gpdrq0, jumper pins 5 and 6. to route isa drq3 to microcontroller gpdrq0, jumper pins 7 and 8. to route isa drq5 to microcontroller gpdrq0, jumper pins 9 and 10. to route isa drq6 to microcontroller gpdrq0, jumper pins 11 and 12. to route isa drq7 to microcontroller gpdrq0, jumper pins 13 and 14. jumper jp7 must be used to route the corresponding dackx signal (i.e., the selected channel number must match, for example drq0 and dack0 ). also, the channel number selected must be different from the channel selected by jp8 and jp9 (if any). figure a-6 shows the default signal routing for jumper jp6, with isa drq5 routed to gpdrq0. figure a-6. jumper jp6 default routing isa connectors lan ? sc520 microcontroller jp7 drq0 drq1 drq2 drq3 drq5 drq6 drq7 dack0 dack1 dack2 dack3 dack5 dack6 dack7 jp9 jp8 jp6 gpdack0 gpdack1 gpdrq0 gpdrq1 isadrq1 isadrq0 isadack1 isadack0 acdp.book page 7 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-8 jumper jp7 jumper jp7 is used to route one isa-compatible dackn channel from the pc/ 104-plus connector to the microcontroller ? s gpdack0 input. the following settings indicate the possible configurations for jumper jp7. to route isa dack0 to microcontroller gpdack0 , jumper pins 1 and 2. to route isa dack1 to microcontroller gpdack0 , jumper pins 3 and 4. to route isa dack2 to microcontroller gpdack0 , jumper pins 5 and 6. to route isa dack3 to microcontroller gpdack0 , jumper pins 7 and 8. to route isa dack5 to microcontroller gpdack0 , jumper pins 9 and 10. to route isa dack6 to microcontroller gpdack0 , jumper pins 11 and 12. to route isa dack7 to microcontroller gpdack0 , jumper pins 13 and 14. jumper jp6 must be used to route the corresponding drqx signal (i.e., the selected channel number must match, for example drq0 and dack0 ). also, the channel number selected must be different from the channel selected by jp8 and jp9 (if any). figure a-7 shows the default signal routing for jumper jp7, with isa dack5 routed to gpdack0 . figure a-7. jumper jp7 default routing isa connectors lan ? sc520 microcontroller jp7 drq0 drq1 drq2 drq3 drq5 drq6 drq7 dack0 dack1 dack2 dack3 dack5 dack6 dack7 jp9 jp8 jp6 gpdack0 gpdack1 gpdrq0 gpdrq1 isadrq1 isadrq0 isadack1 isadack0 acdp.book page 8 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-9 jumper jp8 jumper jp8 is used to route one isa-compatible drqn channel from the pc/ 104-plus connector to the microcontroller ? s gpdrq1 input. the following settings indicate the possible configurations for jumper jp8. to route isa drq0 to microcontroller gpdrq1, jumper pins 1 and 2. to route isa drq1 to microcontroller gpdrq1, jumper pins 3 and 4. to route isa drq2 to microcontroller gpdrq1, jumper pins 5 and 6. to route isa drq3 to microcontroller gpdrq1, jumper pins 7 and 8. to route isa drq5 to microcontroller gpdrq1, jumper pins 9 and 10. to route isa drq6 to microcontroller gpdrq1, jumper pins 11 and 12. to route isa drq7 to microcontroller gpdrq1, jumper pins 13 and 14. jumper jp9 must be used to route the corresponding dackx signal (i.e., the selected channel number must match, for example drq0 and dack0 ). also, the channel number selected must be different from the channel selected by jp6 and jp7 (if any). figure a-8 shows the default signal routing for jumper jp8, with isa drq6 routed to gpdrq1. figure a-8. jumper jp8 default routing isa connectors lan ? sc520 microcontroller jp7 drq0 drq1 drq2 drq3 drq5 drq6 drq7 dack0 dack1 dack2 dack3 dack5 dack6 dack7 jp9 jp8 jp6 gpdack0 gpdack1 gpdrq0 gpdrq1 isadrq1 isadrq0 isadack1 isadack0 acdp.book page 9 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-10 jumper jp9 jumper jp9 is used to route one isa-compatible dackn channel from the pc/ 104-plus connector to the microcontroller ? s gpdack1 input. the following settings indicate the possible configurations for jumper jp9. to route isa dack0 to microcontroller gpdack1 , jumper pins 1 and 2. to route isa dack1 to microcontroller gpdack1 , jumper pins 3 and 4. to route isa dack2 to microcontroller gpdack1 , jumper pins 5 and 6. to route isa dack3 to microcontroller gpdack1 , jumper pins 7 and 8. to route isa dack5 to microcontroller gpdack1 , jumper pins 9 and 10. to route isa dack6 to microcontroller gpdack1 , jumper pins 11 and 12. to route isa dack7 to microcontroller gpdack0 , jumper pins 13 and 14. jumper jp8 must be used to route the corresponding drqx signal (i.e., the selected channel number must match, for example drq0 and dack0 ). also, the channel number selected must be different from the channel selected by jp6 and jp7 (if any). figure a-9 shows the default signal routing for jumper jp9, with isa dack6 routed to gpdack1 . figure a-9. jumper jp9 default routing isa connectors lan ? sc520 microcontroller jp7 drq0 drq1 drq2 drq3 drq5 drq6 drq7 dack0 dack1 dack2 dack3 dack5 dack6 dack7 jp9 jp8 jp6 gpdack0 gpdack1 gpdrq0 gpdrq1 isadrq1 isadrq0 isadack1 isadack0 acdp.book page 10 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-11 jumpers jp10, jp11, jp12, jp13, and jp14 jumpers jp10, jp11, jp12, jp13, and jp14 are used for reqn /gntn tests and are used for amd internal use only. acdp.book page 11 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-12 jumper jp18 select the boot device either from dip memory or from prom ice when jp3 is set on pin 7 and 8. the following settings indicate the possible configurations for jumper jp18. figure a-10 shows the jumper pins and the default setting for jumper jp18. to boot from dip memory, jumper pins 1 and 2 (shown in figure a-10). to boot from prom ice, jumper pins 2 and 3. figure a-10. jumper jp18 default setting 1 3 2 dipfcs dipcs promcs acdp.book page 12 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-13 jumper jp20 use either of the following jumper settings on jumper jp20 according to your promice setup. when using flash memory or a modified promice cable, jumper pins 1 and 3 and jumper pins 2 and 4. when using promice with the original cable (requiring no cable modifications), jumper pins 3 and 5 and jumper pins 4 and 6. figure a-11. jumper jp20 1 2 3 4 5 6 acdp.book page 13 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-14 dip switch settings this section provides the switch settings for the three dip switches. dip switch s3 dip switch s3 is a single, three-circuit, slide-actuated, single-pole single-throw (spst) dip switch for the system boot pinstrap. the default switch setting is shown in figure a-12. a description of the dip switch settings and functions are shown in table a-1. for the layout location, refer to figure 2-2 on page 2-4. figure a-12. dip switch s3 default setting table a-1. dip switch s3 settings cfg0 cfg1 cfg2 function off off x bootcs data width = 8 bit on off x bootcs data width = 16 bit off on x bootcs data width = 32 bit x x off bootcs data bus = gp data bus x x on bootcs data bus = sdram data bus o n cfg0 cfg1 cfg2 acdp.book page 14 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-15 dip switch s4 dip switch s4 is a slide-actuated dip switch for the system boot pinstrap. the default switch setting is shown in figure a-13. the dip switch settings (positions 2 - 8) vary according to the user-defined applications. you must define the switch settings according to the applications being used. for the layout location on the lansc520 microcontroller cdp, refer to figure 2-2 on page 2-4. table a-2 shows the switch settings on switch s4. figure a-13. dip switch s4 default setting table a-2. dip switch s4 settings switch setting description 1on off normal safe; resets cmos settings on bios 2xdon ? t care 3xdon ? t care 4on off bios splash displayed at startup memory/pci info displayed at startup 5xdon ? t care 6xdon ? t care 7xdon ? t care 8xdon ? t care 1 23 o n 4 5 6 7 8 acdp.book page 15 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual a-16 dip switch s5 dip switch s5 is a single three-circuit, slide-actuated dip switch for the system boot pinstrap. the default switch setting is shown in figure a-14. a description of the dip switch settings and functions are shown in table a-3. for the layout location, refer to figure 2-2 on page 2-4. figure a-14. dip switch s5 default setting table a-3. dip switch s5 settings switch 1 - debug_enter setting function off normal operation on amdebug tool enabled switch 2 - inst_trce setting function off normal operation on trace controller enabled to output trace records switch 3 - debug_dis setting function off normal operation on amdebug tool is disabled and cannot be enabled by software 1 2 3 o n acdp.book page 16 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual b-1 appendix b resource assignments this section provides information about the resource assignments for the chip selects, gpirq, gpdma, pio, and uart. the following information applies to the following five resource assignment tables in this appendix: all pios are configured for alternate pin functions except pio27, which is default to input and works as isa iochchk. cbar aliases mmcr at df00:0. echo mode is default to off. gpcs3 -gpcs7 are chip selects, the default setting of pitgate2, tmrin1, tmrin0, tmrout1, and tmrout0. clktest pin is default to output 1.8432 mhz. bootcs , romcs1 , and romcs2 are default to non-page mode (seven wait states). acdp.book page 1 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual b-2 chip select resource assignments table b-1 provides the resource assignments for the devices listed. table b-1. chip select resource assignments chip select settings bootcs for jp3 and jp18, select either: first 2m x 32 sdram bus bank second 2m x 32 sdram bus bank flash memory expansion connector 512k x 8 dip eprom/flash memory flash memory expansion connector romcs1 for jp4, select either: first 2m x 32 sdram bus bank second 2m x 32 sdram bus bank flash memory expansion connector romcs2 for jp5, select either: first 2m x 32 sdram bus bank second 2m x 32 sdram bus bank flash memory expansion connector gpcs3 64k x 16 sram on gpbus (word access) gpcs4 unused - for use as tmrin1 set to input gpcs5 unused - for use as tmrin0 set to input gpcs6 ide hard drive cs0 gpcs7 ide hard drive cs1 acdp.book page 2 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual b-3 gpirq resource assignments table b-2 provides the resource assignments for the devices listed. table b-2. gpirq resource assignments note: 1. the bios included with cdp version 1.4 maps the super i/o uarts to com3 and com4. earlier bios versions, used on boards with microcontroller revisions a0 and a1, disabled the microcontroller ? s uarts and mapped the super i/o uarts to com1 and com2 instead. isa slt1 isa slt2 super i/o tip ide hard drive gpirq0 irq11 irq11 irq11 ?? gpirq1 ?? irq1 (keyboard) ?? gpirq2 irq12 irq12 irq12 (mouse) ?? gpirq3 irq3 irq3 irq3 (com4 1 ) ?? gpirq4 irq4 irq4 irq4 (com3 1 ) ?? gpirq5 irq5 irq5 irq5 (lpt2) (not in use) ?? gpirq6 irq6 irq6 irq6 (fdc) ?? gpirq7 irq7 irq7 irq7 (lpt1) serirq0 r109 ? gpirq8 ?? irq8 (rtc) (not in use) serirq1 r107 ? gpirq9 irq9 irq9 irq9 parirq r106 ? gpirq10 irq10 irq10 irq10 enetirq r105 irq14 acdp.book page 3 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual b-4 gpdma resource assignments table b-3 provides the resource assignments for the devices listed. table b-3. gpdma resource assignments isa slt1 isa slt2 super i/o ide hard drive gpdrq0 gpdack0 drq/dack, 0, 1, 2, 3, 5, 6, 7, jp6, jp7 drq/dack, 0, 1, 2, 3, 5, 6, 7, jp6, jp7 ?? gpdrq1 gpdack1 drq/dack, 0, 1, 2, 3, 5, 6, 7, jp8, jp9 drq/dack, 0, 1, 2, 3, 5, 6, 7, jp8, jp9 ?? gpdrq2 gpdack2 ?? drq0/ dack0 ? gpdrq3 gpdack3 ??? dmareq/ dma_ack r17, r18 acdp.book page 4 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual b-5 pio resource assignments table b-4 provides the resource assignments for the devices listed. table b-4. pio resource assignments pin cdp probe 1 cdp use pio input pio output pio0 gpale p8 d14 drives isa ale via buffer u20 na na pio1 gpbhe p8 d12 drives isa bhe via buffer u20 na na pio2 gprdy p8 d15 driven by isa iochrdy, ide hard drive iochrdy, super i/o iochrdy, and tip iochrdy. wired or with 1k pullup to 5v. na na pio3 gpaen p8 p11 drives isa, super i/o, and tip and via buffer u20. gpaen used by pals u4 and u6 for gp bus decode. na na pio4 gptc p3 d10 drives isa and super i/o tc via buffer u20 na na pio5 gpdrq3 p4-16 ide hard drive dmareq via r17 na na pio6 gpdrq2 p4-11 super i/o drq0 for sio na na pio7 gpdrq1 p4-14 isa drq0, 1, 2, 3, 5, 6, 7; selected by jp8 na na pio8 gpdrq0 p4-11 isa drq0, 1, 2, 3, 5, 6, 7; selected by jp6 na na pio9 gpdack3 p4-20 ide hard drive dma_ack via r18 na na pio10 gpdack2 p4-17 super i/o dack0 for sio na na pio11 gpdack1 p4-18 isa dack0 , 1, 2, 3, 5, 6, 7; selected by jp9 na na pio12 gpdack0 p4-15 isa dack0 , 1, 2, 3, 5, 6, 7; selected by jp7 na na pio13 gpirq10 p4-12 driven by isa irq10, super i/o irq10, ide hard drive irq, and tip enetirq via r015; has pullup 4k7 to 5v. na na pio14 gpirq9 p4-9 driven by isa irq9, super i/o irq9, and tip parirq via r106; has pullup 4k7 to 5v. na na pio15 gpirq8 p4-10 driven by super i/o irq8 and tip serirq1 via r107; has pullup 4k7 to 5v. na na acdp.book page 5 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual b-6 note: 1. the probe column indicates the probe point on the cdp as the pin name (px dxx) or the number (px-xx). pio16 gpirq7 p4-7 driven by isa irq7, super i/o irq7 and tip serirq0 via r109; has pullup 4k7 to 5v. na na pio17 gpirq6 p4-8 driven by isa irq6, super i/o irq6 and tip mainirq via r108; has pullup 4k7 to 5v. na na pio18 gpirq5 p4-5 driven by isa irq5 and super i/o irq5; has pullup 4k7 to 5v. na na pio19 gpirq4 p4-6 driven by isa irq4 and super i/o irq4; has pullup 4k7 to 5v. na na pio20 gpirq3 p4-3 driven by isa irq3 and super i/o irq3; has pullup 4k7 to 5v. na na pio21 gpirq2 p4-4 driven by isa irq12 and super i/o irq12; has pullup 4k7 to 5v. na na pio22 gpirq1 p4-1 driven by super i/o irq1; has pullup 4k7 to 5v. na na pio23 gpirq0 p4-2 driven by isa irq11 and super i/o irq11; has pullup 4k7 to 5v. na na pio24 gpdbufoe p8 d9 enables gp data bus buffer and 512 kbyte sram rd strobe na na pio25 gpiocs16 p11 d15 driven by isa iocs16 and ide hard drive io16 ; used by pal u4 for gp bus decode; has pullup 1k to 5v. na na pio26 gpmemcs16 p11 d14 driven by isa memcs16 ; has pullup 1k to 5v. na na pio27 pio27 input p4-22 driven by isa iochck ; has pullup 4k7 to 5v. input na pio28 cts2 p4-40 driven by com2 transceiver u34 (cts) na na pio29 dsr2 p4-46 driven by com2 transceiver u34 (dsr) na na pio30 dcd2 p4-38 driven by com2 transceiver u34 (dcd) na na pio31 rin2 p4-48 driven by com2 transceiver u34 (ri) na na table b-4. pio resource assignments (continued) pin cdp probe 1 cdp use pio input pio output acdp.book page 6 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual b-7 uart resource assignments table b-5 provides the resource assignments for the devices listed. table b-5. uart resource assignments device setting uart1 com1 dte on db25m r70 and r173, or r71 and r172 selects rs422 or rs232 1.15 mbit/s maximum speed uart2 com2 dte rs232 on db9m 120 kbit/s maximum speed ssi three devices selected by super i/o signals: cio14: expansion connector jp17 cio15: microwire eeprom cio16: spi eeprom acdp.book page 7 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual b-8 acdp.book page 8 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual index-1 numerics 10/100baset ethernet, 2-7 a amdebug ? tool, 2-17 b block diagram, 2-3 c chip select decoder address space, 2-16 chip select resource assignments, b-2 codekit software, iii component locations, 2-4 connector logic analyzer, 2-10, 2-12 connectors locations, 2-5 conventions, documentation, xv d daughter modules, 2-18 description lansc520 microcontroller cdp, xi dip switches s3, a-14 s4, a-15 s5, a-16 display, 2-11 dma channels reserved for super i/o, 2-8 dma routing, isa, a-6 documentation conventions, xv reference material, xiv support, iii e lansc520 microcontroller, 2-6 lansc520 microcontroller cdp, xi setting up, 1-2 set-up procedure, 1-5 ethernet, 2-7 index acdp.book page 1 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual index-2 f features, 2-1 10/100baset ethernet, 2-7 amdebug, 2-17 descriptions, 2-6 lansc520 microcontroller, 2-6 flash memory, 2-14 hexadecimal led display, 2-11 high-speed uart, 2-11 in-circuit emulator (ice), 2-17 integrated drive electronics (ide), 2-17 isa card slots, 2-10 logic analyzer connector, 2-12 low-speed uart, 2-11 memory, 2-12 optional daughter modules, 2-18 pci card slots, 2-10 sdram, 2-12 super i/o, 2-8 synchronous serial interface (ssi), 2-17 test interface port (tip) connector, 2-10 flash memory, 2-14 configuration block diagram, 2-16 configuration diagram, 2-15 floppy disk starting from, 1-14 g gpdma resource assignments, b-4 gpirq resource assignments, b-3 h hard disk drive starting from, 1-15 hd header j13, 2-17 hd status led connector j13, 2-5 hexadecimal led display, 2-11 high-speed uart, 2-11 i ice, 2-17 ide hard disk drive starting from, 1-15 in-circuit emulator (ice), 2-17 integrated drive electronics (ide), 2-17 irqs reserved for super i/o, 2-8 isa card slots (gp bus slots), 2-10 isa-compatible signals dma routing, a-6 j j12 header, 2-5 j13 header, 2-5, 2-17 jp10, a-11 jp11, a-11 jp12, a-11 jp13, a-11 jp14, a-11 jp18, a-12 jp19, 2-5 jp2, a-2 jp20, a-13 jp3, a-3 jp4, a-4 jp5, a-5 acdp.book page 2 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual index-3 jp6 ? jp9 jumper, a-7 ? a-10 jtag, 2-17 jumpers jp10, a-11 jp11, a-11 jp12, a-11 jp13, a-11 jp14, a-11 jp18, a-12 jp2, a-2 jp20, a-13 jp3, a-3 jp4, a-4 jp5, a-5 l layout, 2-4 led, 2-11 literature support, iii locations components, 2-4 logic analyzer connector, 2-10 low-speed uart, 2-11 ls1, 2-5 m memory, 2-12 chip select decoder address space, 2-16 flash, 2-14 sdram, 2-12 microcontroller, 2-6 modules daughter, 2-18 test interface port (tip), 2-18 p pci card slots, 2-10 pinout jumpers jp1 ? jp4, a-6 pio resource assignments, b-5 power led connector j12, 2-5 promice interface cable, 1-8 setting jumper jp20, 1-8 q quick start, 1-1 r reference material, xiv reset switch connector jp19, 2-5 resource assignments chip select, b-2 gpdma, b-4 gpirq, b-3 pio, b-5 uart, b-7 s s3, a-14 s4, a-15 s5, a-16 setting up, 1-2 lansc520 microcontroller cdp, 1-2 procedure, 1-5 requirements, 1-3 speaker connector ls1, 2-5 acdp.book page 3 wednesday, april 4, 2001 10:57 am
lan ? sc520 microcontroller customer development platform user ? s manual index-4 starting from floppy disk, 1-14 ide hard disk drive, 1-15 super i/o, 2-8 block diagram, 2-9 support, iii synchronous serial interface (ssi), 2-17 t technical support, iii reference material, xiv test interface port (tip) connector, 2-10 third-party support, iii u uart high-speed, 2-11 low-speed, 2-11 resource assignments, b-7 url amd, iii literature ordering, iii w www.amd.com, iii acdp.book page 4 wednesday, april 4, 2001 10:57 am

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