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e datasheet addendum 82371ab (piix4) pci isa ide xcelerator timing specifications order number: 290548-001 september 1997
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 82371ab (piix4) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-4725 or call 1-800-548-4725 copyright ? intel corporation, 1997 cg-041493
e 82371ab (piix4) pci isa ide xcelerator timing specifications 1 preliminary supported kits for both pentium and pentium pro microprocessors ? ? 82430tx isa kit ? ? 82440lx isa/dp kit multifunction pci to isa bridge ? ? supports pci at 30 mhz and 33 mhz ? ? supports pci rev 2.1 specification ? ? supports full isa or extended i/o (eio) bus ? ? supports full positive decode or subtractive decode of pci ? ? supports isa/eio at 1/4 of pci frequency supports both mobile and desktop deep green environments ? ? 3.3v operation with 5v tolerant buffers ? ? ultra-low power for mobile environments ? ? power-on suspend and soft-off for desktop environment ? ? all registers readable/restorable for proper resume from 0v suspend power management logic ? ? global and local device management ? ? suspend/resume logic ? ? supports thermal alarm ? ? support for external microcontroller ? ? full support for advanced configuration and power interface (acpi) specification and os directed power management integrated ide controller ? ? independent timing of up to 4 drives ? ? pio mode 4 transfers up to 14 mbytes/sec ? ? supports ? ultra dma/33 ? synchronous dma mode transfers up to 33 mbytes/sec ? ? integrated 8 x 32-bit buffer for ide pci burst transfers ? ? supports glue-less ? swap-bay ? option with full electrical isolation enhanced dma controller ? ? two 82c37 dma controllers ? ? supports pci dma with 3 pc/pci channels and distributed dma protocols (simultaneously) ? ? fast type-f dma for reduced pci bus usage interrupt controller based on two 82c59 ? ? 15 interrupt support ? ? independently programmable for edge/level sensitivity ? ? supports optional i/o apic ? ? serial interrupt input timers based on 82c54 ? ? system timer, refresh request, speaker tone output usb ? ? two usb 1.0 ports for serial transfers at 12 or 1.5 mbit/sec ? ? supports legacy keyboard and mouse software with usb-based keyboard and mouse ? ? supports uhci design guide revision 1.1 interface smbus ? ? host interface allows cpu to communicate via smbus ? ? slave interface allows external smbus master to control resume events real-time clock ? ? 256-byte battery-back cmos sram ? ? includes date alarm ? ? two 8-byte lockout ranges 82371ab (piix4) pci isa ide xcelerator features
82371ab (piix4) pci isa ide xcelerator timing specifications e 2 preliminary microsoft windows* 95 compliant 324 mbga package reference information: the information in this document is provided as a supplement to the standard package datasheets published for the intel 82371ab (piix4) pci isa ide xcelerator. please refer to the standard package datasheet (order number 290562 for the piix4) for product information and specifications not found in this document. notice: this document contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. the 82371ab (piix4) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request.
e 82371ab (piix4) pci isa ide xcelerator timing specifications 3 preliminary contents page 1.0. introduction ................................ ................................ ................................ ............................... 5 2.0. electrical characteristics ................................ ................................ ................................ ... 5 2.1. absolute maximum ratings ................................ ................................ ................................ ............ 5 2.2. d.c. characteristics ................................ ................................ ................................ ...................... 6 2.3. a.c. characteristics ................................ ................................ ................................ .................... 10 2.4. clock, reset, isa bus, x-bus and host timing diagrams ................................ ............................. 29 2.5. pci timing diagrams ................................ ................................ ................................ ................... 48 2.6. ide timing diagrams ................................ ................................ ................................ ................... 51 2.7. usb timing diagrams ................................ ................................ ................................ .................. 53 2.8. ioapic timing diagrams ................................ ................................ ................................ ............. 54 2.9. smbus timing diagrams ................................ ................................ ................................ .............. 55 2.10. ultra dma/33 timing diagrams ................................ ................................ ................................ .. 56 figures figure 1. test load ................................ ................................ ................................ ............................ 29 figure 2. clock timing ................................ ................................ ................................ ........................ 29 figure 3. reset inactive timing ................................ ................................ ................................ ........... 30 figure 4. reset active pulse width ................................ ................................ ................................ ..... 30 figure 5. smi#, extsmi# and stpclk# timing ................................ ................................ .................. 31 figure 6. input to pciclk setup/hold times ................................ ................................ ....................... 31 figure 7. hclkin to output valid delay ................................ ................................ .............................. 32 figure 8. 8-bit isa memory slave timing (piix4 as master) ................................ ................................ . 32 figure 9. 16- bit isa memory slave timing (piix4 as master) ................................ ............................... 33 figure 10. 8-bit isa i/o slave timing (piix4 as master) ................................ ................................ ...... 34 figure 11. 16-bit i/o slave timing (piix4 as master) ................................ ................................ ........... 35 figure 12. isa master accessing pci memory timing ................................ ................................ ......... 36 figure 13. isa master accessing piix4 register timing ................................ ................................ ...... 37 figure 14. nmi timing ................................ ................................ ................................ ........................ 37 figure 15. interrupt timing ................................ ................................ ................................ .................. 38 figure 16. isa master miscellaneous timing ................................ ................................ ....................... 38 figure 17. isa master data swap timing ................................ ................................ ............................ 39 figure 18. dma compatible timing (memory read) ................................ ................................ ............. 40 figure 19. dma compatible timing (memory write) ................................ ................................ ............. 41 figure 20. dma compatible timing (data swap) ................................ ................................ .................. 42 figure 21. dma type f timing ................................ ................................ ................................ ............ 43 figure 22. piix4-initiated refresh timing ................................ ................................ ............................ 44 figure 23. isa master-initiated refresh timing ................................ ................................ .................... 45 figure 24. piix4 and isa master access to x-bus timing ................................ ................................ .... 46
82371ab (piix4) pci isa ide xcelerator timing specifications e 4 preliminary figure 25. coprocessor error and mouse support timing ................................ ................................ ..... 47 figure 26. real time clock timing (rtcale generation) ................................ ................................ .... 47 figure 27. speaker timing ................................ ................................ ................................ .................. 48 figure 28. propagation delay ................................ ................................ ................................ .............. 48 figure 29. valid dela y from rising clock edge ................................ ................................ ................... 49 figure 30. setup and hold times ................................ ................................ ................................ ......... 49 figure 31. float delay ................................ ................................ ................................ ......................... 50 figure 32. pulse width ................................ ................................ ................................ ........................ 50 figure 33. output enable delay ................................ ................................ ................................ ........... 50 figure 34. ide pio mode ................................ ................................ ................................ .................... 51 figure 35. ide multiword dma mode ................................ ................................ ................................ ... 52 figure 36. data signal rise and fall time ................................ ................................ ............................ 53 figure 37. data jitter ................................ ................................ ................................ .......................... 53 figure 38. eop width timing ................................ ................................ ................................ .............. 54 figure 39. piix4 to ioapic timing ................................ ................................ ................................ ...... 54 figure 40. smbus timing ................................ ................................ ................................ .................... 55 figure 41. smbus timeout timing ................................ ................................ ................................ ....... 55 figure 42. ultra dma/33 drive initiating a dma burst for a read command ................................ .......... 56 figure 43. ultra dma/33 sustained synchronous dma burst ................................ ................................ 57 figure 44. ultra dma/33 sustained synchronous dma burst ................................ ................................ 58 figure 45. ultra dma/33 host terminating a dma bu rst during a write command ................................ 58 tables table 1. package thermal resistance ................................ ................................ ................................ ... 5 table 2. dc characteristics ................................ ................................ ................................ .................. 6 table 3. dc characteristic signal association ................................ ................................ ....................... 8 table 4. dc current characteristics ................................ ................................ ................................ ...... 9 table 5. clock/reset timings ................................ ................................ ................................ .............. 10 table 6. isa bus and x-bus timings ................................ ................................ ................................ ... 12 table 7. pci interface timing ................................ ................................ ................................ .............. 23 table 8. pci bus ide timing ................................ ................................ ................................ ............... 24 table 9. universal serial bus timing ................................ ................................ ................................ ... 26 table 10. ioapic bus timing ................................ ................................ ................................ .............. 27 table 11. smbus timing ................................ ................................ ................................ .................... 27 table 12. serial irq timing ................................ ................................ ................................ ................ 28 table 13. ultra dma/33 timing ................................ ................................ ................................ ............ 28 table 14. a.c. test loads ................................ ................................ ................................ ................... 29
e 82371ab (piix4) pci isa ide xcelerator timing specifications 5 preliminary 1. 0. introduction this document contains the electrical and the thermal specification (ets) for the 82371ab (piix4). piix4 is a multi-function pci device implementing a pci-to-isa bridge function, a pci ide function, a universal serial bus host/hub function, and a power management function. the contents of this document are based on simulation and parametric data. this information may be modified as more data is available. references the ets assumes that the reader is familiar with the following documents: 82371ab piix4 external design specification universal serial bus specification universal host controller interface (uhci) design guide system management bus specification serialized irq support for pci systems specification distributed dma support for pci systems specification 2. 0. electrical characteristics 2.1. absolute maximum ratings case temperature under bias ................................ ............ 0 o c to +85 o c storage temperature ................................ ......................... -55 o c to +150 o c voltage on any pin with respect to ground ........................ -0.3 to v cc + 0.3v 3.3v supply voltage with respect to vss ............................ -0.3 to +4.6v 5.0v supply voltage with respect to vss (v ref ) ................. -0.3 to +5.5v maximum power dissipation ................................ .............. 1.0w warning: stressing the device beyond the ? absolute maximum ratings ? may cause permanent damage. these are stress ratings only. operating beyond the ? operating conditions ? is not recommended and extended exposure beyond ? operating conditions ? may affect reliability. the 82371ab piix4 (bga) is designed for operation at case temperatures between 0 o c and 85 o c. the thermal resistances of the package are given in table 1. table 1 . package thermal resistance parameter air flow meters/second (linear feet per minute) 0 (0) 1.0 (196.9) theta ja ( o c/watt) 29 24.5 theta jc ( o c/watt) 9.0
82371ab (piix4) pci isa ide xcelerator timing specifications e 6 preliminary 2.2. d.c. characteristics table 2 . dc characteristics functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) symbol parameter min max unit notes v cc (rtc) battery voltage 2.0 3.6 v v cc (sus) standby voltage 3.0 3.6 v v il1 input low voltage -0.5 0.3 v cc v 1 v ih1 input high voltage 0.5 v cc v cc + 0.5 v 1 v il2 input low voltage -0.3 0.6 v 1 v ih2 input high voltage 1.4 v cc + 0.3 v 1 v il3 input low voltage -0.5 0.8 v 1 v ih3 input high voltage 2.0 v cc 5 + 0.5 v 1 v ol1 output low voltage 0.4 v 1 v oh1 output high voltage v cc - 0.5 v 1 v ol2 output low voltage 0.3 v 1, 2 v oh2 output high voltage 2.8 3.6 v 1, 2 v ol3 output low voltage 0.5 v 1 v oh3 output high voltage v cc - 0.5 v 1 v ol4 output low voltage 0.45 v 1 v oh4 output high voltage v cc - 0.5 v 1 v di differential input sensitivity 0.2 v |(usbpx+, usbpx-)| v cm differential common mode range 0.8 2.5 v includes v di v se single ended rcvr threshold 0.8 2.0 v i ol1 output low current 4 ma 1, @ v ol1 i oh1 output high current -1 ma 1, @ v oh1 i ol2 output low current 10 ma 1, @ v ol4 i oh2 output high current -3 ma 1, @ v oh4 i ol3 output low current 3 ma 1, @ v ol1 i oh3 output high current -2 ma 1, @ v oh1 i ol4 output low current 6 ma 1, @ v ol1 i oh4 output high current -2 ma 1, @ v oh1 i ol5 output low current 2 ma 1, @ v ol2 i oh5 output high current -0.25 ma 1, @ v oh2
e 82371ab (piix4) pci isa ide xcelerator timing specifications 7 preliminary table 2 . dc characteristics functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) symbol parameter min max unit notes i ol6 output low current 6 ma 1, @ v ol1 i oh6 output high current -2 ma 1, @ v oh1 i ol7 output low current 7 ma 1, @ v ol1 i oh7 output high current -2 ma 1, @ v oh1 i ol8 output low current 11 ma 1, @ v ol3 i oh8 output high current -2 ma 1, @ v oh3 i li1 input leakage current 1 a i li2 hi-z state data line leakage -10 +10 a (0v< v in < 3.3v) c in input capacitance 12 pf f c =1 mhz c out output capacitance 12 pf f c =1 mhz c i/o i/o capacitance 12 pf f c =1 mhz c l crystal load capacitance 7.5 15 pf notes: 1. refer to table 3. for the signals associated with this specification. 2. v ol2 assumes r l of 1.5 kohms to 3.6v and v oh2 assumes r l of 15 kohms to gnd.
82371ab (piix4) pci isa ide xcelerator timing specifications e 8 preliminary table 3 . dc characteristic signal association symbol associated signals v il1 /v ih1 v ref =5.0v: (all 3.3v only inputs except smbclk & smbdata) pwrok, rsmrst#, rtcx1, test, batlow#, config[1:2], extsmi#, gpi[1], irq8#, lid, ri#, smbalert#, pwrbtn#, usbp[1:0]+, usbp[1:0]-, ferr# v ref =3.3v: (all inputs except smbclk & smbdata) pwrok, rsmrst#, rtcx1, test, batlow#, config[1:2], extsmi#, gpi[1], irq8#, lid, ri#, smbalert#, pwrbtn#, usbp[1:0]+, usbp[1:0]-, ferr#, ad[31:0], c/be[3:0]#, clkrun#, devsel#, frame#, idsel, irdy#, phlda#, serr#, stop#, trdy#, iochk#, iochrdy, iocs16#, ior#, iow#, la[23:17], memcs16#, memr#, memw#, refresh#, sa[19:0], sbhe#, sd[15:0], zerows#, a20gate, rcin#, dreq[0:3, 5:7], req[a:c]#, apicreq#, irq[1, 3:7, 9:12, 14:15], pirq[a:d], serirq, clk48, pciclk, osc, pdd[15:0], pddreq, piordy, sdd[15:0], sddreq, siordy, oc[1:0]#, pcireq[a:d],thrm# v il2 /v ih2 smbclk, smbdata v il3 /v ih3 v ref =5.0v: (all 5v tolerant inputs) ad[31:0], c/be[3:0]#, clkrun#, devsel#, frame#, idsel, irdy#, phlda#, serr#, stop#, trdy#, iochk#, iochrdy, iocs16#, ior#, iow#, la[23:17], memcs16#, memr#, memw#, refresh#, sa[19:0], sbhe#, sd[15:0], zerows#, a20gate, rcin#, dreq[0:3, 5:7], req[a:c]#, apicreq#, irq[1, 3:7, 9:12, 14:15], pirq[a:d], serirq, clk48, pciclk, osc, pdd[15:0], pddreq, piordy, sdd[15:0], sddreq, siordy, oc[1:0]#, pcireq[a:d],thrm# v ol1 /v oh1 pda[2:0], pdcs1#, pdcs3#, pdd[15:0], pddack#, pdior#, pdiow#, sda[2:0], sdcs1#, sdcs3#, sdd[15:0], sddack#, sdior#, sdiow#, cpu_stp#, extsmi#, zz, gpo8, pci_stp#, smbclk, smbdata, sus[a:c]#, sus_stat[1:2]#, a20m#, cpurst, ignne#, init, intr, nmi, smi#, stpclk#, bioscs#, kbccs#, mccs#, pcs0#, pcs1#, rtcale, rtccs#, xdir#, xoe#, susclk, rtcx2, smbclk, smbdata, apicack#, apiccs#, irq[0, 8], spkr, gnt[a:c], gpo[0, 8, 27, 28, 30], irq9out#, ad[31:0], c/be[3:0]#, clkrun#, devsel#, frame#, irdy#, par, pcirst#, phold#, serr#, stop#, trdy#, serirq v ol2 /v oh2 usbp[1:0]+, usbp[1:0]- v ol3 /v oh3 slp# v ol4 /v oh4 isa/eio output signals: aen, bale, iochrdy, ior#, iow#, la[23:17], memcs16#, memr#, memw#, refresh#, rstdrv, sa[19:0], sbhe#, sd[15:0], smemr#, smemw#, sysclk, dack[0:3, 5:7]#, tc i ol1 /i oh1 ide output signals: pda[2:0], pdcs1#, pdcs3#, pdd[15:0], pddack#, pdior#, pdiow#, sda[2:0], sdcs1#, sdcs3#, sdd[15:0], sddack#, sdior#, sdiow# i ol2 /i oh2 isa/eio output signals: aen, bale, iochrdy, ior#, iow#, la[23:17], memcs16#, memr#, memw#, refresh#, rstdrv, sa[19:0], sbhe#, sd[15:0], smemr#, smemw#, sysclk, dack[0:3, 5:7]#, tc
e 82371ab (piix4) pci isa ide xcelerator timing specifications 9 preliminary table 3 . dc characteristic signal association symbol associated signals i ol3 /i oh3 power management signals: cpu_stp#, extsmi#, zz, gpo8, pci_stp#, smbclk, smbdata, sus[a:c]#, sus_stat[1:2]# cpu interface signals: a20m#, cpurst, ignne#, intr, nmi x-bus interface signals: bioscs#, kbccs#, mccs#, pcs0#, pcs1#, rtcale, rtccs#, xdir#, xoe#, susclk, rtcx2 other signals: smbclk, smbdata, apicack#, apiccs#, irq[0, 8], spkr, gnt[a:c], gpo[0, 8, 27, 28, 30], irq9out# i ol4 /i oh4 pci bus signals: ad[31:0], c/be[3:0]#, clkrun#, devsel#, frame#, irdy#, par, pcirst#, phold#, serr#, stop#, trdy#, serirq i ol5 /i oh5 usb signals: usbp[1:0]+, usbp[1:0]- i ol6 /i oh6 smi#, stpclk# i ol7 /i oh7 init# i ol8 /i oh8 slp# table 4 . dc current characteristics functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) symbol parameter typ max unit notes i cc (3v) v cc supply current 110 155 ma i cc (sus) on suspend well supply current ? full on 3 5 ma i cc (sus) pos/str suspend well supply current ? power on suspend or suspend to ram 30 150 m a i cc (sus) std/soff suspend well supply current ? suspend to disk or soft off 9 150 m a icc(rtc) battery standby current 6 8 m a v cc (rtc)=3.0v mech off state
82371ab (piix4) pci isa ide xcelerator timing specifications e 10 preliminary 2.3. a.c. characteristics table 5 . clock/reset timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units notes figure pci clock timings pciclk t1a period 30 33.3 ns 2 t1b high time 12.0 ns 2 t1c low time 12.0 ns 2 t1c rise time 3.0 ns 2 t1d fall time 3.0 ns 2 isa clock timings sysclk t1f period 120 133.3 ns 2 t1g high time 49 ns 2 t1h low time 49 ns 2 t1i rise time 4 ns 2 t1j fall time 4 ns 2 oscillator clock timings osc t1l osc period 67 70 ns 2 t1m high time 20 2 t1n low time 20 ns 2 usb clock timings f clk48 operating frequency 48 mhz t1p frequency tolerance 2500 ppm 1 2 t1q high time 7 ns 2 t1r low time 7 ns 2 t1s rise time 1.2 ns 2 t1t fall time 1.2 ns 2 suspend clock timings f susclk susclk operating frequency 32 khz t1v high time 10 m s t1w low time 10 m s
e 82371ab (piix4) pci isa ide xcelerator timing specifications 11 preliminary table 5 . clock/reset timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units notes figure smbus clock f smb smclk operating frequency 10 16 khz t2b high time 4.0 50 m s 40 t2c low time 4.7 m s 40 t2d clock/data rise time 1000 ns 40 t2e clock/data fall time 300 ns 40 reset timings t2f pcirst#, rstdrv driven inactive after sus_statx# is driven inactive. 1 rtcclk 3 t2g cpurst, pcirst#, rstdrv active pulse width. initiated via the rc register. 1 ms 4 t2h cpurst driven inactive after pcirst# is driven inactive. 1 rtcclk 3 t2i cpurst valid delay from pciclk rising 2 25 ns 29 t2j pwrok, rsmrst# rise time 10 ns 3 smi# t3a valid delay from pciclk 2 25 ns 7 t3b active pulse width 3 pciclk 5 t3c inactive pulse width 4 pciclk 5 extsmi# t3d active pulse width 2 pciclk 5 t3e inactive pulse width 4 pciclk 5 t3f valid setup to pciclk 10 ns 6 t3g valid hold from pciclk 4 ns 6 stpclk# t3h valid delay from pciclk 2 25 ns 7 t3i stpclk# inactive pulse width 5 pciclk 5 notes: 1. the usbclk is a 48 mhz that expects a 40/60% duty cycle. 2. the maximum high time (t2b max) provide a simple guaranteed method for devices to detect bus idle conditions. 3. t2j is measured as a transition time through the threshold region vol=0.8v and voh=2.0v.
82371ab (piix4) pci isa ide xcelerator timing specifications e 12 preliminary table 6 . isa bus and x-bus timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units type size notes figure piix4 as master timings bale t4a bale pulse width 50 ns m,i/o 8,16 8,9,10, 11 t4b bale driven active from memx#, iox# inactive 44 ns m,i/o 8,16 8,9,10, 11 la[23:17] t5a la[23:17] valid setup to bale inactive 150 ns m 8,16 7 8,9 t5b la[23:17] valid hold from bale inactive 26 ns m 8,16 8,9 t5c la[23:17] valid setup to memx# active 150 ns m 16 9 t5d la[23:17] valid setup to memx# active 173 ns m 8 8 t5e la[23:17] invalid from memx# active 39 ns m 16 9 t5f la[23:17] invalid from memx# active 39 ns m 8 8 sa[19:0], sbhe# t6a sa[19:0], sbhe# valid setup to memx# active 34 ns m 16 13,15 9 t6b sa[19:0], sbhe# valid setup to iox# active 100 ns i/o 16 11 t6c sa[19:0], sbhe# setup to memx#, iox# active 100 ns m,i/o 8 9 t6d sa[19:0], sbhe# valid setup to bale inactive 37 ns m,i/o 8,16 13,15 8,9,10, 11 t6e sa[19:0], sbhe# valid hold from memx#, iox# inactive 41 ns m,i/o 8,16 8,9,10, 11 memr#, memw#, ior# and iow# t7a memx# active pulse width (std) 225 ns m 16 9 t7b iox# active pulse width (std) 160 ns i/o 16 11 t7c memx# active pulse width (nws) 105 ns m 16 1 9 t7d memx# or iox# active pulse width (std) 520 ns m,i/o 8 8,10 t7e memx# or iox# active pulse width (nws) 160 ns m,i/o 8 1 8,10 t7f memx# inactive pulse width 103 ns m 16 9
e 82371ab (piix4) pci isa ide xcelerator timing specifications 13 preliminary table 6 . isa bus and x-bus timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units type size notes figure t7g memx# inactive pulse width 163 ns m 8 8 t7h iox# inactive pulse width 163 ns i/o 8,16 10,11 t7i memx#, iox# driven inactive from iochrdy active 120 ns m,i/o 8,16 8,9,10, 11 smemr# and smemw# t8a smemr# & smemw# propagation delay from memr# and memw# 16 ns m 8,16 8,9 read data t9a read data driven from memr#, ior# active 0 ns m,i/o 8,16 8,9,10, 11 t9b read data valid setup to memr#, ior# 24 ns m,i/o 8,16 8,9,10, 11 t9c read data valid hold from memr#, ior# inactive 0 ns m,i/o 8,16 8,9,10, 11 t9d read data tri-stated from memr# and ior# inactive 41 ns m,i/o 8,16 8,9,10, 11 write data t10a write data valid setup to memw# active write data valid setup to iow# active write data valid setup to iow# active -40 -40 +23 ns ns ns m,i/o m,i/o m,i/o 8,16 8 16 8,9,10, 11 t10b write data valid hold from memw#, iow# inactive 45 ns m,i/o 8,16 8,9,10, 11 t10c write data tri-stated from memw#, iow# inactive 105 ns m,i/o 8,16 8,9,10, 11 t10d write data driven valid after read memr#, ior# inactive 41 ns m,i/o 8,16 8,9,10, 11 memcs16# t11a memcs16# driven active from la[23:17] valid 94 ns m 16 9 t11b memcs16# inactive from la[23:17] valid 91 ns m 8 8 t11c memcs16# valid hold from la[23:17] invalid 0 ns m 16 9
82371ab (piix4) pci isa ide xcelerator timing specifications e 14 preliminary table 6 . isa bus and x-bus timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units type size notes figure t11d memcs16# driven active from sa[19:2] valid 35 ns m 16 9 iocs16# t12a iocs16# driven active from valid sa[19:0] 123 ns i/o 16 11 t12b iocs16# inactive from valid sa[19:0] 91 ns i/o 8 10 t12c iocs16# valid hold from sa[19:0] invalid 0 ns i/o 16 11 t12d iocs16# driven active from iox active 80 ns i/o 16 11 zerows# t13a zerows# driven active from memx# active 16 ns m 16 9 t13b zerows# driven active from memx#, iox# active 80 ns m,i/o 8 8 t13c zerows# driven active from la[23:17] valid 180 ns m 16 9 t13d zerows# driven active from la[23:17] valid 300 ns m 8 8 zerows# t13e zerows# driven active from sa[19:0], sbhe# valid 80 ns m 16 9 t13f zerows# driven active from sa[19:0], sbhe# valid 200 ns m,i/o 8 8,10 aen t14a aen valid setup to iox# driven active 111 ns i/o 8,16 10,11 t14b aen valid setup to bale driven inactive 111 ns i/o 8,16 10,11 t14c aen valid hold from iox# driven inactive 41 ns i/o 8,16 10,11 iochrdy t15a iochrdy driven valid from memx#, iox# active 78 ns m,i/o 16 9,11 t15b iochrdy driven valid from memx#, iox# active 366 ns m,i/o 8 8,10
e 82371ab (piix4) pci isa ide xcelerator timing specifications 15 preliminary table 6 . isa bus and x-bus timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units type size notes figure t15e iochrdy inactive pulse width 0.12 15.6 m s m,i/o 8,16 8,9,10, 11 piix4 as slave timings la[23:17] t16a la[23:17] valid setup to memx# active 23 ns m 16 12 sa[19:0],sbhe# t17a sa[19:0],sbhe# setup to memx# active 23 ns m 16 12 t17b sa[19:0],sbhe# setup to iox# active 89 ns i/o 8 13 t17c sa[19:0],sbhe# valid hold from memx#, iox# inactive 30 ns m,i/o 8,16 12,13 memr#, memw#, ior#, iow# t18a memx# active pulse width 214 ns m 16 12 t18b iox# active pulse width 509 ns i/o 8 13 t18c memx# inactive pulse width 92 ns m 16 12 t18d iox# inactive pulse width 152 ns i/o 8 13 read data t19a read data valid from iochrdy active 69 ns m,i/o 8,16 12,13 t19b read data valid from ior# active 69 ns i/o 8 11 13 t19c read data valid hold from memr#, ior# inactive 0 ns m,i/o 8,16 12,13 t19d read data tri-state from memr#, ior# inactive 55 ns m,i/o 8,16 12,13 write data t20a write data valid setup to memw#, iow# active -54 ns m,i/o 8,16 12,13 t20b write data valid hold from memw#, iow# inactive 14 ns m,i/o 8,16 12,13 memcs16# t21a memcs16# driven active from valid la[23:17] 65 ns m 16 12 t21b memcs16# float from valid la[23:17] 31 ns m 16 12
82371ab (piix4) pci isa ide xcelerator timing specifications e 16 preliminary table 6 . isa bus and x-bus timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units type size notes figure t21c memcs16# valid hold from la[23:17] invalid 0 ns m 16 12 iochrdy t22a iochrdy inactive from memx#, iox# active 50 ns m,i/o 8,16 12,13 t22b iochrdy float from iochrdy rising 85 ns m,i/o 8,16 4 12,13 t22c iochrdy inactive pulse width 0.12 2.5 m s m,i/o 8,16 12,13 interrupt and nmi timings nmi timing t23a serr#, iochk# active to nmi driven active 200 ns 14 interrupt timing t24a irqx inactive pulse width 100 ns 15 isa bus master timings dack# t26a dack#, inactive from dreq inactive 240 ns 16 tri-stating and driving the bus t27a piix4 tri-states address, data, and control signals from dack#, active 30 ns 16 t27b piix4 drives address, data, and control signals from dack#, inactive 71 ns 16 smemr# and smemw# t28a smemr# and smemw# active (falling edge) from memr# and memw# active (falling edge) 25 ns 16 t28b smemr# and smemw# inactive (rising edge) from memr# and memw# inactive (rising edge) 35 ns 16 data swap logic timing (isa master to isa slave) t29a sd[7:0] to sd[15:8] propagation delay 26 ns 17 t29b sd[15:8] to sd[7:0] propagation delay 26 ns 17
e 82371ab (piix4) pci isa ide xcelerator timing specifications 17 preliminary table 6 . isa bus and x-bus timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units type size notes figure t29c piix4 drives data bus from ior#, iow#, memr# or memw# active 26 ns 2 17 t29d piix4 tri-states bus from ior#, memr#, or smemr# inactive 2 55 ns 2,3 17 t29e piix4 tri-states bus from iow#, memw#, or smemw# inactive 2 60 ns 2,3 17 dma compatible timings dreq t30a dreq active hold from ior# active 558 ns 5 19 t30b dreq active hold from iow# active 315 ns 5 18 dack# t31a dack# active to ior# active 73 ns 19 t31b dack# active to iow# active 312 ns 18 t31c dack# active hold from ior# inactive 100 ns 19 t31d dack# active hold from iow# inactive 155 ns 18 aen and bale t32a aen active to iox# active 111 ns 18,19 t32b aen and bale inactive from iox# inactive 41 ns 18,19 la[23:19], sa[19:0], sbhe# t33a la[23:19],sa[19:0], sbhe# valid setup to memx# active 99 ns 18,19 t33b la[23:19],sa[19:0], sbhe# valid hold from memx# inactive 51 ns 18,19 memr#, memw#, ior#, iow# t34a iow# and memw# active pulse width 465 ns 18,19 t34b memr# active pulse width 495 ns 18 t34c ior# active pulse width 760 ns 19 t34d iow# inactive pulse width (continuous) 465 ns 18 t34e ior# inactive pulse width (continuous) 160 ns 19 t34f ior# active to memw# active 230 ns 19 t34g memr# active to iow# active -26 ns 18
82371ab (piix4) pci isa ide xcelerator timing specifications e 18 preliminary table 6 . isa bus and x-bus timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units type size notes figure t34h memr# active hold from iow# inactive 40 ns 18 t34i ior# active hold from memw# inactive 40 ns 19 t34j memx# active hold from iochrdy active 120 ns 18,19 smemr# & smemw# t35a smemr# & smemw# valid from memr# and memw# valid 15 ns 18,19 read data t36a read data valid from ior# active 237 ns 19 t36b read data valid hold from ior# inactive 0 ns 19 t36c read data float from ior# inactive 61 ns 19 write data t37a write data valid setup to iow# inactive 225 ns 18 t37b write data valid hold from iow# inactive 36 ns 18 data swap logic timing (isa to isa transaction) t38a sd[7:0] to sd[15:8] propagation delay 26 ns 20 t38b sd[15:8] to sd[7:0] propagation delay 26 ns 20 t38c piix4 drives data bus from ior# or memr# active 26 ns 2 20 t38d piix4 tri-states bus from ior# or memr# inactive 55 ns 2 20 tc t39a tc active setup to iox# inactive 511 ns 6 18,19 t39b tc active hold from iox# inactive 71 ns 6 18,19 t39h tc pulse width 700 ns 18,19 iochrdy t40b iochrdy valid from memx# active 315 ns 18,19 t40c iochrdy inactive pulse width 125 ns 18,19
e 82371ab (piix4) pci isa ide xcelerator timing specifications 19 preliminary table 6 . isa bus and x-bus timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units type size notes figure dma type ? f ? timings dreq t55a dreq active hold from ior# active 82 ns 5,16 21 t55b dreq active hold from iow# active 82 ns 5,16 21 dack# t56a dack# active to ior# active 77 ns 16 21 t56b dack# active to iow# active 77 ns 16 21 t56c dack# active hold from ior# inactive 30 ns 16 21 t56d dack# active hold from iow# inactive 30 ns 16 21 aen and bale t57a aen active to iox# active 111 ns 21 t57b aen and bale inactive from iox# inactive 41 ns 21 ior# and iow# t58a ior# active pulse width 110 ns 21 t58b iow# active pulse width 110 ns 21 t58c ior# inactive pulse width (continuous) 115 ns 21 t58d iow# inactive pulse width (continuous) 115 ns 21 read data t59a read data valid from ior# active 96 ns 21 t59b read data valid hold from ior# inactive 2 ns 21 t59c read data float from ior# inactive 61 ns 21 write data t60a write data valid setup to iow# inactive 70 ns 21 t60b write data valid hold from iow# inactive 31 ns 21 tc t61a tc active setup to ior# inactive 40 ns 6 21
82371ab (piix4) pci isa ide xcelerator timing specifications e 20 preliminary table 6 . isa bus and x-bus timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units type size notes figure t61b tc active setup to iow# inactive 40 ns 6 21 t61c tc active hold from iox# inactive 0 ns 6 21 isa refresh timings refresh# t62a refresh# active setup to memr# active 120 ns 22,23 t62b refresh# active hold from memr# inactive 31 260 ns 22,23 t62c refresh# driven active to sa[15:0] valid 11 ns 22,23 t62d refresh# active hold from sa[15:0] invalid 11 ns 22,23 aen t63a aen driven active to memr# active 11 ns 22,23 t63b aen hold from memr# inactive 11 ns 22,23 sa[15:0] t64a sa[15:0] valid setup to memr# active 72 ns 22,23 t64b sa[15:0] valid hold from memr# inactive 35 ns 22,23 t64c sa[15:0] valid float from memr# inactive 46 120 ns 8 23 memr#, smemr# t65a memr# active pulse width 225 ns 22,23 t65b memr# tri-state from memr# inactive 36 120 ns 22,23 t65c memr# driven inactive from iochrdy active 120 ns 22,23 t65d smemr# propagation delay from memr# 25 ns 22,23 iochrdy t66a iochrdy inactive from memr# active 76 ns 22,23 t66b iochrdy valid from memr# active 76 ns 22,23 t66c iochrdy inactive pulse width 120 ns 22,23
e 82371ab (piix4) pci isa ide xcelerator timing specifications 21 preliminary table 6 . isa bus and x-bus timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units type size notes figure piix4 driving bus from refresh# t67a piix4 drives control and address from refresh# active 5 ns 8 23 piix4 and isa master accesses to the x-bus bioscs#, kbccs#, rtccs#, and pcs0#, pcs1#, mccs# t68a cs# driven active from sa[19:0], la[23:17] valid (except bioscs#) 35 ns 24 t68b cs# driven inactive from sa[16:0], la[23:17] invalid (except bioscs#) 35 ns 24 xdir# and xoe# t69a xdir# active from ior#, memr# active ? pci-initiated access ? isa-initiated access 25 30 ns ns 24 t69b bioscs#, xoe# active from iox#, memx# active 29 ns 24 t69c xdir# active setup to xoe# active 2 12 ns 24 t69d bioscs#, xoe# inactive from iox#, memx# inactive 35 60 ns 9 24 t69f bioscs#, xoe# setup to xdir# inactive 2 15 ns 9 24 t69g xoe# inactive from ior#, memr# inactive 2 140 ns 10 24 t69i xoe# inactive setup to xdir# inactive 2 12 ns 10 24 miscellaneous x-bus timings mouse timing support t71a irq12/m and irq1 minimum active pulse width (for mouse function and keyboard) 180 ns 25 coprocessor error support t73a ignne# active from iow# active from port f0h access 220 ns 25
82371ab (piix4) pci isa ide xcelerator timing specifications e 22 preliminary table 6 . isa bus and x-bus timings functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units type size notes figure t73b ignne# inactive from ferr# inactive 230 ns 25 real time clock timing (rtcale) t75a rtcale pulse width 200 300 ns 26 t75b rtcale active from iow# active ? pci-initiated access ? isa-initiated access 85 156 ns ns 26 speaker timing t76a spkr valid delay from osc rising 200 ns 27 notes: 1. no-wait-state (zerows#) asserted. 2. this applies to the byte lane that the data has been swapped to. 3. data is tri-stated from the standard memory commands (smemr# or smemw#), when they are generated. 4. this specification includes both the time the piix4 drives iochrdy active and the time it takes thepiix4 to float iochrdy. 5. this applies to the last cycle of a demand mode dma transfer. 6. output from piix4. 7. 36 ns has been added to the isa spec to meet zerows# setup requirements. 8. this applies to isa master initiated refresh only. 9. piix4 as a master cycles only. 10. isa master cycles only. 11. this applies to the piix 4 cycles that iochrdy is not driven low. 12. this applies to all dack# signals. 13. 56 ns has been added to the isa spec to meet memcs16# setup requirements. isa devices are not suppose to use the sa address as part of their memcs16# decode. however, some devices do use sa as part of memcs16# decode. 14. x-bus read. 15. for back-to-back ? sub cycles ? generated as a result of byte assembly or disassembly, this spec is 34 ns. 16. type f transfers are selected via the mbdmax register.
e 82371ab (piix4) pci isa ide xcelerator timing specifications 23 preliminary table 7 . pci interface timing functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units notes figure t77 ad[31:0] valid delay 2 11 ns min: 0 pf max: 50 pf 29 t78 ad[31:0] setup time 7 ns 30 t79 ad[31:0] hold time 0 ns 30 t80 c/be[3:0]#, frame#, trdy#, irdy#, stop#, par, serr#, idsel, devsel# clockrun#, gnt[a:c]# valid delay from pciclk rising 2 11 ns min: 0 pf max: 50 pf 29 t81 c/bes[3:0]#, frame#, trdy#, irdy#, stop#, par, serr#, idsel, devsel# clockrun#, gnt[a:c]# output enable delay from pciclk rising 2 ns 33 t82 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, idsel, devsel# clockrun#, float delay from pciclk rising 2 28 ns 31 t83 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, idsel, devsel# clockrun#, req[a:c]# setup time to pciclk rising 7 ns 30 t84 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, idsel, devsel# clockrun#, req[a:c]#, hold time from pclkin rising 0 ns 30 t85 phld# valid delay from pciclk rising 2 12 ns 0 pf 29 t86 phlda# setup time to pciclk rising 10 ns 30 t87 phlda# hold time from pciclk rising 0 ns 30 t91 pirq[d:a]# setup time to pciclk rising 1 30 t92 pirq[d:a]# hold time from pciclk rising 1 30 t96 rst# low pulse width 1 ms 32 notes: 1. this signal is internally synchronized.
82371ab (piix4) pci isa ide xcelerator timing specifications e 24 preliminary table 8 . pci bus ide timing functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units notes figure primary ide timing t102 pdiow# active from pciclk rising 2 20 ns 34,35 t103 pdiow# inactive from pciclk rising 2 20 ns 34,35 t104 pdior# active from pciclk rising 2 20 ns 34,35 t105 pdior# inactive from pciclk rising 2 20 ns 34,35 t106 pda[2:0] valid delay from pciclk rising 2 30 ns 34 t107 pdcs1#, pdcs3# active from pciclk rising 2 30 ns 34 t108 pdcs1#, pdcs3# inactive from pciclk rising 2 30 ns 34 t113 pddack# active from pciclk rising 2 20 ns 35 t114 pddack# inactive from pciclk rising 2 20 ns t114a pddreq setup time to pciclk rising 7 ns 35 t114b pddreq hold from pciclk rising 7 ns 35 t115 pdd[15:0] valid delay from pciclk rising 2 30 ns 34,35 t115a pdd[15:0] setup time to pciclk rising 10 ns 34,35 t115b pdd[15:0] hold from pciclk rising 8 ns 34,35 t116 piordy setup time to pciclk rising 7 ns 1 34 t117 piordy hold from pciclk rising 7 ns 1 34 t117a piordy inactive pulse width 48 ns 34 t118 piordy sample point from diox# assertion pciclk 2,3 34 t119 pdiox# active pulse width pciclk 2,3 34,35 t120 pdiox# inactive pulse width pciclk 3,4 34,35 secondary ide timing t102 sdiow# active from pciclk rising 2 20 ns 34,35 t103 sdiow# inactive from pciclk rising 2 20 ns 34,35 t104 sdior# active from pciclk rising 2 20 ns 34,35 t105 sdior# inactive from pciclk rising 2 20 ns 34,35 t106 sda[2:0] valid delay from pciclk rising 2 30 ns 34 t107 sdcs1#, pdcs3# active from pciclk rising 2 30 ns 34 t108 sdcs1#, pdcs3# inactive from pciclk rising 2 30 ns 34
e 82371ab (piix4) pci isa ide xcelerator timing specifications 25 preliminary table 8 . pci bus ide timing functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units notes figure t113 sddack# active from pciclk rising 2 20 ns 35 t114 sddack# inactive from pciclk rising 2 20 ns t114a sddreq setup time to pciclk rising 7 ns 35 t114b sddreq hold from pciclk rising 7 ns 35 t115 sdd[15:0] valid delay from pciclk rising 2 30 ns 34,35 t115a sdd[15:0] setup time to pciclk rising 10 ns 34,35 t115b sdd[15:0] hold from pciclk rising 8 ns 34,35 t116 siordy setup time to pciclk rising 7 ns 1 34 t117 siordy hold from pciclk rising 7 ns 1 34 t117a piordy inactive pulse width 48 ns 34 t118 siordy sample point from diox# assertion pciclk 2,3 34 t119 sdiox# active pulse width pciclk 2,3 34,35 t120 sdiox# inactive pulse width pciclk 3,4 34,35 notes: 1. iordy is internally synchronized. this timing is to guarantee recognition on the next clock. 2. this parameter is programmable from 2 ? 5 pci clocks when the drive mode is mode 2 or greater. refer to the isp field in the ide timing register. 3. the cycle time is the compatible timing when the drive mode is mode 0/1. refer to the tim0/1 field in the ide timing register. 4. this parameter is programmable from 1 ? 4 pci clocks when the drive mode is mode 2 or greater. refer to the rct field in the ide timing register.
82371ab (piix4) pci isa ide xcelerator timing specifications e 26 preliminary table 9 . universal serial bus timing functional operating range (v ref =5v 5%, v cc =3.3v 0.3v, t case =0c to +85c) sym parameter min max units notes fig full speed source (note 7) t122 usbpx+, usbpx- driver rise time 4 20 ns 1, c l =50 pf 36 t123 usbpx+, usbpx- driver fall time 4 20 ns 1, c l =50 pf 36 t124 source differential driver jitter ? to next transition ? for paired transitions -2 -1 2 1 ns ns 2,3 37 t125 source eop width 160 175 ns 4 38 t126 differential to se0 transition skew -2 5 ns 5 t127 receiver data jitter tolerance ? to next transition ? for paired transitions -20 -10 20 10 ns ns 3 37 t128 eop width ? must reject as eop ? mu st accept as eop 40 85 ns ns 4 38 t126 differential to se0 transition skew -2 5 ns 5 low speed source (note 8) t127 usbpx+, usbpx- driver rise time 75 300 ns ns 1,6=50 pf c l =350 pf 36 t128 usbpx+, usbpx- driver fall time 75 300 ns ns 1,6 c l =50 pf c l =350 pf 36 t129 source differential driver jitter ? to next transition ? for paired transitions -2 -1 2 1 ns ns 2,3 37 t130 source eop width 160 175 ns 4 38 t131 differential to se0 transition skew -2 5 ns 5 t132 receiver data jitter tolerance ? to next transition ? for paired transitions -20 -10 20 10 ns ns 3 37 t133 eop width ? must reject as eop ? must accept as eop 40 85 ns ns 4 38 t134 differential to se0 transition skew -2 5 ns 5
e 82371ab (piix4) pci isa ide xcelerator timing specifications 27 preliminary notes: 1. driver output resistance under steady state drive is spec?ed at 28 ohms at minimum and 43 ohms at maximum. 2. timing difference between the differential data signals. 3. measured at crossover point of differential data signals. 4. measured at 50% swing point of data signals. 5. measured from last crossover point to 50% swing point of data line at leading edge of eop. 6. measured from 10% to 90% of the data signal. 7. full speed data rate has minimum of 11.97 mbps and maximum of 12.03 mbps. 8. low speed data rate has a minimum of 1.48 mbps and a maximum of 1.52 mbps. table 10 . ioapic bus timing functional operating range (v ref =5v 5%, v cc =3.3v 0.3v t case =0c to +85c) sym parameter min max units notes fig t136 apiccs# setup to memx# 2 pciclk 1 39 t137 sa[19:0] setup to apiccs# 2 pciclk 1 39 t138 apicack# valid delay from pciclk 2.0 12.0 ns 29 t139 apicreq# valid setup to pciclk 10.0 ns 30 t140 apicreq# valid hold from pciclk 0.0 ns 30 notes: 1. with these exceptions, the apic configuration cycles conform to the 8-bit isa memory slave timing where piix4 is the master. table 11 . smbus timing functional operating range (v ref =5v 5%, v cc =3.3v 0.3v t case =0c to +85c) sym parameter min max units notes fig t141 bus free time between stop and start condition 4.7 m s 40 t142 hold time after (repeated) start condition. after this period, the first clock is generated 4.0 m s 40 t143 repeated start condition setup time 4.7 m s 40 t144 stop condition setup time 4.0 m s 40 t145 data hold time 300 ns 40 t146 data setup time 250 ns 40 t147 device time out 25 35 ms 1 t148 cumulative clock low extend time (slave device) 25 ms 2 41 t149 cumulative clock low extend time (master device) 10 ms 3 41
82371ab (piix4) pci isa ide xcelerator timing specifications e 28 preliminary notes: 1. a device will timeout when any clock low exceeds this value. 2. t148 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to stop. if a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 3. t149 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack, or ack-to-stop. table 12 . serial irq timing functional operating range (v ref =5v 5%, v cc =3.3v 0.3v t case =0c to +85c) sym parameter min max units notes fig t151 serirq setup time to pciclk rising 7 ns 30 t152 serirq hold time from pciclk rising 0 ns 30 table 13 . ultra dma/33 timing functional operating range (v ref =5v 5%, v cc =3.3v 0.3v t case =0c to +85c) mode 0 (ns) mode 1 (ns) mode 2 (ns) sym parameter (1) min max min max min max figure t154 cycle time (tcyc) (2) 114 75 55 43 t155 two cycle time (t2cyc) 235 156 117 43 t156 data setup time (tds) 15 10 7 43 t157 data hold time (tdh) 5 5 5 43 t158 data valid setup time (tdvs) 70 48 34 43 t159 data valid hold time (tdvh) 6 6 6 43 t160 limited interlock time (tli) 0 150 0 150 0 150 45 t161 interlock time w/minimum (tmli) 20 20 20 45 t162 envelope time (tenv) 20 70 20 70 20 70 42 t163 ready to pause time (trp) 160 125 100 44 t164 dmack setup/hold time (tack) 20 20 20 42,45 notes: 1. the specification symbols in parenthesis correspond to the ultra dma/33 specification name. 2. these cycle timings are based on the strobe period as indicated in figure 44. however, table 13 in the piix4 datasheet refers to cycle time strobe periods as 120 ns, 90 ns and 60 ns for mode 0, 1, and 2 respectively. the datasheet timings are different because they are based on the number of pci clocks per cycle, not the actual period between the rise and fall of strobe.
e 82371ab (piix4) pci isa ide xcelerator timing specifications 29 preliminary table 14 . a.c. test loads capacitive load signals 120 pf refresh#, tc, sd[15:0], sa[19:0], sbhe#, la[23:17], i0cs16#, memcs16#, memr#, memw#, smemr#, smemw#, ior#, iow#, aen, bale, iochrdy, zerows#, rstdrv, sysclk 50 pf dack#[7:5,3:0], spkr, intr, nmi, bioscs#, kbccs#, rtccs#, pcs[1:0]#, mccs#, rtcale, xdir#, xoe#, ignne#, pdd[15:0], sdd[15:0], , apiccs#, dior#, diow#, pddack#, sddack#, pdcs1# pdcs3#, sdcs1#, sdcs3 cc , pda[2:0], sda[2:0]. c l includes all parasitic capacitance output c l testload figure 1 . test load 2.4. clock, reset, isa bus, x-bus and host timing diagrams pciclk, sysclk, osc 2.0v 0.8v period high time low time fall time rise time clk_tm figure 2 . clock timing
82371ab (piix4) pci isa ide xcelerator timing specifications e 30 preliminary sus_stat[1:2]# reset2.vsd t2f pcirst#, rstdrv t2h active inactive inactive active cpurst figure 3 . reset inactive timing 048821_2.vsd cpurst, pcirst#, rstdrv (write to rc register) t2g active figure 4 . reset active pulse width
e 82371ab (piix4) pci isa ide xcelerator timing specifications 31 preliminary s m i # 048823.drw (m) p c i c l k e x t s m i # s t p c l k # t 3 b t 3 c t 3 d t 3 e t 3 i p c i c l k p c i c l k figure 5 . smi#, extsmi# and stpclk# timing t 3 f p c i c l k e x t s m i # 0 4 8 8 2 4 . d r w ( m ) t 3 g figure 6 . input to pciclk setup/hold times
82371ab (piix4) pci isa ide xcelerator timing specifications e 32 preliminary p c i c l k s m i # , e x t s m i # , s t p c l k # 0 4 8 8 2 5 . d r w ( m ) t 3 a , t 3 h figure 7 . hclkin to output valid delay b a l e l a [ 2 3 : 1 7 ] s a [ 1 9 : 0 ] , s b h e # m e m r # , m e m w # s m e m x # m e m c s 1 6 # z e r o w s # i o c h r d y s d [ 7 : 0 ] r s d [ 7 : 0 ] w t 4 a t 5 a t 6 d t 5 d t 6 c t 1 1 b t 8 a t 1 3 d t 1 3 f t 9 a t 1 5 b t 1 3 b t 1 0 b , t 1 0 c t 1 0 d t 9 c , t 9 d t 9 b t 7 i t 1 5 e t 8 a t 7 g t 7 d , t 7 e t 6 e t 4 b t 5 f t 5 b t 1 0 a 0 4 8 8 2 6_2.vsd figure 8 . 8-bit isa memory slave timing (piix4 as master)
e 82371ab (piix4) pci isa ide xcelerator timing specifications 33 preliminary bale la[23:17] sa[15:0],sbhe# memr#, memw# smemw#, smemr# memcs16# zerows# iochrdy sd[15:0] r t5a t4a t6d t5c t6a t11d t11a t13e t13c t8a t5b t6e t5e t7a, t7c t13a t15a t10a t7i t9b t10b, t10c t9c, t9d t8a t11c t7f t4b 048827_2.vsd sd[15:0] w t10d t15e figure 9 . 16-bit isa memory slave timing (piix4 as master)
82371ab (piix4) pci isa ide xcelerator timing specifications e 34 preliminary bale sa[19:0], sbhe# ior#, iow# iocs16# zerows# iochrdy sd[7:0] r aen t14a t14b t4a t6d t6c t12b t13f t13b t10a t9a t15b t15e t10b, c t10d t9c,t9d t9b t7i t7d, t7e t7h t4b t6e t14c 048828_2.vsd sd[7:0] w figure 10 . 8-bit isa i/o slave timing (piix4 as master)
e 82371ab (piix4) pci isa ide xcelerator timing specifications 35 preliminary bale sa[19:0], sbhe# ior#, iow# iocs16# iochrdy sd[15:0] r sd[15:0] w aen t4a t14b t14a t6d t6b t12a t12d t15a t15e t10a t9a t7i t9d, t9c t10b, c t10d t12c t7h t4b t6e t7b t14c 048829_2.vsd figure 11 . 16-bit i/o slave timing (piix4 as master)
82371ab (piix4) pci isa ide xcelerator timing specifications e 36 preliminary bale la[23:17] sa[19:0], sbhe# memr#, memw# iochrdy memcs16# sd[7:0] r sd[7:0] w t17a t16a t22a t21a t19c, t19d t20b t21b, t21c t19a t22b t22c t18a t17c t20a 048830_2.vsd t18c figure 12 . isa master accessing pci memory timing
e 82371ab (piix4) pci isa ide xcelerator timing specifications 37 preliminary aen bale sa[19:0], sbhe# ior#, iow# iochrdy sd[7:0] r sd[7:0] w t17b t22a t22c t19a t22b t18b t17c t18d t19c, t19d t20b t20a 048831.drw low high t19b figure 13 . isa master accessing piix4 register timing serr#, iochk# 048832.vsd t23a nmi figure 14 . nmi timing
82371ab (piix4) pci isa ide xcelerator timing specifications e 38 preliminary irqx 048833.vsd t24a figure 15 . interrupt timing dack# s d [ 1 5 : 0 ] s a [ 1 5 : 0 ] l a [ 2 3 : 1 9 ] b h e # t 2 7 a t 2 6 a t 2 7 b t 2 8 a t 2 8 b 0 4 8 8 3 4_2.vsd m e m r # , m e m w # i o r # , i o w # s m e m r # , s m e m w # m e m r # , m e m w # a e n dreq figure 16 . isa master miscellaneous timing
e 82371ab (piix4) pci isa ide xcelerator timing specifications 39 preliminary sd[7:0] ior#, iow# memr#, memw# ior#, memr#, or smemr# iow#, memw#, or smemw# sd[15:8] sd[7:0] or sd[15:8] 048835_2.vsd sd[7:0] or sd[15:8] sd[7:0] or sd[15:8] t29e t29c t29a t29b t29d figure 17 . isa master data swap timing
82371ab (piix4) pci isa ide xcelerator timing specifications e 40 preliminary dreq a e n dack# l a [ 2 3 : 1 7 ] s a [ 1 5 : 0 ] i o c h r d y i o w # m e m r # s m e m r # s d [ 1 5 : 0 ] t c t 3 2 a t 3 1 b t 3 0 b t 3 4 j t 3 4 a t 3 4 b t 3 3 a t 3 4 g t 3 5 a t 3 5 a t34d t 3 3 b t 3 7 a t 3 9 a t 3 9 b t 3 4 h t 4 0 b t 4 0 c t 3 2 b t 3 1 d 0 4 8 8 3 6_2.vsd t 3 9 h t 3 7 b figure 18 . dma compatible timing (memory read)
e 82371ab (piix4) pci isa ide xcelerator timing specifications 41 preliminary d y dreq a e n dack# l a [ 2 3 : 1 7 ] s a [ 1 9 : 0 ] i o c h r i o r # m e m w # s m e m w # s d [ 1 5 : 0 ] t c t30a t32a t31a t33a t35a t34a t35a t 3 4 c t34e t36a t39a t 3 9 b t 3 6 b , t 3 6 c t 4 0 b t40c t 3 4 j t 3 4 i t 3 4f t 3 3 b t31c t 3 2 b 0 4 8 8 3 7 t 3 9 h figure 19 . dma compatible timing (memory write)
82371ab (piix4) pci isa ide xcelerator timing specifications e 42 preliminary sd[7:0] 048838.vsd t38a sd[15:8] t38b t38c t38d ior#, memr# sd[7:0], or sd[15:8] figure 20 . dma compatible timing (data swap)
e 82371ab (piix4) pci isa ide xcelerator timing specifications 43 preliminary dreq iow# memr# aen t57a t55b t56b t58b t58d t60a t60b t56a t57a t55a t58c ior# t58a t59a t59c, t59b tc t61a t61c t61c t61b t56c t56d t57b t57b dma_f2.vsd sd[15:0] sd[15:0] dack# memw# figure 21 . dma type f timing
82371ab (piix4) pci isa ide xcelerator timing specifications e 44 preliminary smemr# t63b t62b t62d t64b t65c t66c t65a t66a,b t65d t63a t64a t62c t62a 048839_2.vsd t65d memr# iochrdy sa[15:0] refresh# bale aen t65b figure 22 . piix4-initiated refresh timing
e 82371ab (piix4) pci isa ide xcelerator timing specifications 45 preliminary aen t62a t62c t64a t67a t65d t66a,b t66c t65c t65d t63a t63b t62b t62d t64b t65a t64c t65b 048840_2.vsd bale refresh# memr# smemr# sa[15:0] iochrdy high figure 23 . isa master-initiated refresh timing
82371ab (piix4) pci isa ide xcelerator timing specifications e 46 preliminary 048841.vsd la[23:17] sa[16:0] sa[16:0] sa[16:0] t68a t69b t68b t69a t69c t69d t69f t69a t69b t69c t69g t69i isa master piix4 as master bale pccs[1:4]#, kbcs#, mccs#, rtccs# memr#, memw#, ior#, iow# bioscs#, xoe# xdir# xoe# xdir# figure 24 . piix4 and isa master access to x-bus timing
e 82371ab (piix4) pci isa ide xcelerator timing specifications 47 preliminary 048844.vsd t73a ferr# irq13 t73b t71a iow# (write to f0h) ignne# irq12/m, irq1 figure 25 . coprocessor error and mouse support timing 048845.vsd t75a iow# t75b rtcale figure 26 . real time clock timing (rtcale generation)
82371ab (piix4) pci isa ide xcelerator timing specifications e 48 preliminary osc 048846.vsd t76a spkr figure 27 . speaker timing 2.5. pci timing diagrams input prop_del.vsd propagation delay output vt vt figure 28 . propagation delay
e 82371ab (piix4) pci isa ide xcelerator timing specifications 49 preliminary clock val_del.vsd 1.5v valid delay vt output figure 29 . valid delay from rising clock edge clock sethold.vsd vt input hold time setup time vt 1.5v figure 30 . setup and hold times
82371ab (piix4) pci isa ide xcelerator timing specifications e 50 preliminary input floatdel.vsd vt output float delay figure 31 . float delay pulsewid.vsd vt pulse width vt figure 32 . pulse width clock outendel.vsd output output enable delay vt 1.5v figure 33 . output enable delay
e 82371ab (piix4) pci isa ide xcelerator timing specifications 51 preliminary 2.6. ide timing diagrams t106,t107 t106,t107 idepio_2.vsd da[2:0], cs1#, cs3# t118 t115 t115 t115a t115b t116 t117 t103,t105 read data pciclk diox# dd[15:0] write dd[15:0] read iordy t103,t105 t119 t120 write data sample point t117a figure 34 . ide pio mode
82371ab (piix4) pci isa ide xcelerator timing specifications e 52 preliminary pciclk idedma.vsd t114a ddreq[1:0] ddack[1:0] t113 diox# dd[15:0] read dd[15:0] write t102,t104 t103,t105 t119 t120 t115a t115b t115 t115 read data write data write data read data t114b figure 35 . ide multiword dma mode
e 82371ab (piix4) pci isa ide xcelerator timing specifications 53 preliminary 2.7. usb timing diagrams usb_1.vsd full speed: 4 to 20 ns at c l =50 pf differential data lines 90% 10% 10% 90% tr tf rise time fall time los speed: 75 ns at c l =50 pf, 300 ns at c l =350 pf c l c l figure 36 . data signal rise and fall time differential data lines consecutive transitions paired transitions crossover points tperiod usb_2.vsd figure 37 . data jitter
82371ab (piix4) pci isa ide xcelerator timing specifications e 54 preliminary differential data lines eop width data crossover level tperiod usb_3.vsd figure 38 . eop width timing 2.8. ioapic timing diagrams sa[19:0] apic_01.vsd t137 apiccs# memx# t136 figure 39 . piix4 to ioapic timing
e 82371ab (piix4) pci isa ide xcelerator timing specifications 55 preliminary 2.9. smbus timing diagrams clk smbtm_2.vsd t2c data t141 t142 t145 t146 t2d t2e t143 t2b t144 figure 40 . smbus timing smbusto.vsd start stop t148 clk ack clk ack t149 t149 smb clk smb figure 41 . smbus timeout timing
82371ab (piix4) pci isa ide xcelerator timing specifications e 56 preliminary 2.10. ultra dma/33 timing diagrams dmarq (drive) udma1.vsd t164 t162 t162 t164 dmack# (host) stop (host) dmardy# (host) strobe (drive) dd[15:0] da[2:0], cs[1:0] figure 42 . ultra dma/33 drive initiating a dma burst for a read command
e 82371ab (piix4) pci isa ide xcelerator timing specifications 57 preliminary strobe @ sender t154 data @ sender t159 t158 t159 t158 t154 t155 t159 udma2.vsd strobe @ receiver data @ receiver t157 t156 t157 t156 t157 figure 43 . ultra dma/33 sustained synchronous dma burst
82371ab (piix4) pci isa ide xcelerator timing specifications e 58 preliminary t163 udma3.vsd strobe data stop (host) dmardy# figure 44 . ultra dma/33 sustained synchronous dma burst t161 udma4.vsd strobe (drive) dmardy# (host) data (drive) dmack# (host) t164 t160 dmarq (drive) crc figure 45 . ultra dma/33 host terminating a dma burst during a write command
united states, intel corporation 2200 mission college blvd., p.o. box 58119, santa clara, ca 95052-8119 tel: +1 408 765-8080 japan, intel japan k.k. 5-6 tokodai, tsukuba-shi, ibaraki-ken 300-26 tel: + 81-29847-8522 france, intel corporation s.a.r.l. 1, quai de grenelle, 75015 paris tel: +33 1-45717171 united kingdom, intel corporation (u.k.) ltd. pipers way, swindon, wiltshire, england sn3 1rj tel: +44 1-793-641440 germany, intel gmbh dornacher strasse 1 85622 feldkirchen/ muenchen tel: +49 89/99143-0 hong kong, intel semiconductor ltd. 32/f two pacific place, 88 queensway, central tel: +852 2844-4555 canada, intel semiconductor of canada, ltd. 190 attwell drive, suite 500 rexdale, ontario m9w 6h8 tel: +416 675-2438

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