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isd51 16 single-chip voice record/pla y back device up t o 16 minute dura tion with digit a l st orage cap ability publ i c at i on rel e ase dat e : oct ober, 2002 - 1 - revi si on 2.1
isd5116 1. general description the isd5116 chipcorder ? product provides high quality, fully int egrated, single-chip record / p l a y b a ck solutions for 8- to 16-minute messaging applicati ons that are ideal for use in cellular phones, automotive communications, gps/navigation sy stems and other portable products. the isd5116 product is an enhancement of the isd5000 ar chitecture, providing: 1) the i 2 c serial port - address, control and duration selection are accomplished through an i 2 c interface to minimize pin count (only two control lines required); 2) the capability of stor ing digital data, in addition to analog, information. these features allow customers to store phone book numbers, system conf iguration parameters and message address pointers for message management capability. analog functions and audio gating have also been int egrated into the isd5116 product to allow easy interface with integrated digital cellular chip sets on the market. audio paths have been designed to enable full duplex conversation record, voice memo, answering machine (including outgoing message playback) and call screening features. this product enables playback of messages while the phone is in standby, and both simplex and duplex pl ayback of messages while on a phone call. additional voice storage features for digital cellular phones include: 1) a personalized outgoing message can be sent to the person by getting caller-id information from the host chipset 2) a private call announce while on call can be heard from the host by giving caller-id on call waiting information from the hos t c h ips e t. logic interface options of 2.0v and 3.0v are supported by the isd5116 to accommodate portable communication products customers (2.0- and 3.0-volt required). like other chipcorder ? products, the isd5116 integrates t he sampling clock, anti-aliasing and smoothing filters, and the multi-le vel storage array on a single-chip. for enhanced voice features, the isd5116 eliminates external circuitry by int egrating automatic gain c ontrol (agc), a power amplifier/speaker driver, volume control, summing amplifiers, analog switches, and a car kit interface. input level adjustable amplifiers are also included, providing a flexible interface for multiple applications. recordings are stored into on-chip nonvolatile me mory cells, providing zero-power message storage. this unique, single-chip solution is made po ssible through winbond?s patented multilevel storage technology. voice and audio signals are stored directly into solid-state memory in their natural, uncompressed form, providing superio r quality voice and music reproduction. - 2 -
isd5116 2. features fully -integrated solution x single-chip voice record/playback solution x dual storage of digital and analog information low pow e r consumption x + 2 .7 to + 3 .3v (v cc ) supply voltage x supports 2.0v and 3.0v interface logic x operating current: i cc play = 15 ma (typical) i cc rec = 30 ma (typical) i cc feedthrough = 12 ma (typical) x standby current: i sb = 1 p a (ty p ical) x most stages can be individually powered down to minimize power consumption enhanced voice features x one or two-way conversation record x one or two-way message playback x voice memo record and playback x private call screening x in-terminal answering machine x personalized outgoing message x private call announce while on call digital memory features x up to 4 mb available x storage of phone numbers, system configuration parameters and message address table in cellular application easy -to-use and control x no compression algorithm development required x user-controllable sampling rates x programmable analog interface x standard & fast mode i 2 c serial interface (100khz ? 400 khz) x fully addressable to handle multiple messages high quality solution x high quality voice and music reproduction x winbond?s standard 100-year mess age retention (typical) x 100k record cycles (typical) for analog data x 10k record cycles (typical) for digital data options x available in die form, bga (available upon request), tsop and soic and pdip x extended (-20 to +70c) and industrial (-40 to +85c) available, besides commercial (0 to +70c) publ i c at i on rel e ase dat e : oct ober, 2002 - 3 - revi si on 2.1
isd5116 3. block diagram isd5116 b l ock d i agram au x in am p 1.0 / 1 . 4 / 2.0 / 2 . 8 ag c s u m1 mu x vol m u x fi lt e r mu x lo w p ass f ilter su m 1 fth ru in p a na o u t m u x vo l su m 2 ana i n vo l sp+ sp- spea ker au x out ana out- an a ou t+ mic + mi c - a g cca p m i cr o p ho ne au x in xc lk ana in v ssa v cc a v ss a v ssd v ss d v ccd v ccd 64- bi t / s a mp. ar ra y o u tp ut m u x arra y in pu t mu x i n pu t s o ur ce m u x ar r a y i / o m u x fi lto su m 1 in p ana i n su m 2 fi lto su m 2 s u m 1 su m m in g am p a na in am p 0.625 / 0 . 8 8 3 / 1 . 2 5 / 1.76 6db su m2 su m m i n g am p ou t p u t mu x vol u m e contr o l mi c in au x i n fi lt o ana i n su m 1 a na i n fi lto su m 2 ( anal o g ) array in p sum1 mux ct rl ( d ig it al ) 64 - b i t /s amp. ar ray ou t ( anal o g ) a rray o u t ( d ig it al ) ar ray sp kr. am p aux ou t amp p o w e r c ond iti oni ng ra c int sd a sc l a1 a0 devi ce c o n t r o l in t e r n al cl o c k m u lt ilev e l/ dig i t a l st or ag e ar r a y ana ou t amp 2 ( ) vls0 vls1 2 ( ) aig 0 aig 1 2 ( ) axg 0 axg 1 2 ( ) s1s0 s1s1 2 ( ) s1m 0 s1m 1 2 ( ) s2 m 0 s2 m 1 ( ) o pa0 o pa1 2 ( ) o ps0 o ps1 2 ( ) fl d 0 fl d 1 2 (i ns 0 ) 1 1 ( axpd ) 1 (a gp d ) 1 (fl p d ) 1 ( f ls0) 1 (a i p d) 1 (a o p d) ( ) 3 aos 0 aos 1 aos 2 3 ( ) vol0 vol1 vol2 1 (v lp d ) - 4 -
isd5116 4. table of contents 1. general d escript ions ........................................................................................................ ....... 2 2. features .................................................................................................................... ..................... 3 3. block diagram ............................................................................................................... ............... 4 4. table of cont ents ........................................................................................................... ........... 5 5. pin conf igurati on ........................................................................................................... ............ 7 6. pin des cription ............................................................................................................. ................ 8 7. functional descript ion ...................................................................................................... ...... 9 7.1. ov erview ................................................................................................................. ................... 9 7.1.1. speec h/sound q uality.................................................................................................. .... 9 7.1.2. durati on .............................................................................................................. .............. 9 7.1.3. fl as h st orage ......................................................................................................... .......... 9 7.1.4. mic r oc ont roller inte rfac e ............................................................................................. ...... 9 7.1.5. progra mming ........................................................................................................... ....... 10 7.2. func tion de tails ......................................................................................................... .............. 10 7.2.1. inte rnal re s i ters ..................................................................................................... ........ 11 7.2.2. memo ry organi zation ................................................................................................... .. 11 7.3. operational modes descr iption ............................................................................................ ... 12 7.3.1. i 2 c interf ac e .................................................................................................................... 12 7.3.2. i 2 c control r egis t er s ...................................................................................................... 16 7.3.3 op code su mmary ......................................................................................................... .. 17 7.3.4. da ta bytes ............................................................................................................ .......... 19 7.3.5. configurati on regis t er bytes ......................................................................................... 2 0 7.3.6. po wer-up s equence ..................................................................................................... .. 21 7.3.7. f eed through mode ..................................................................................................... .. 22 7.3.8. call re c o rd ........................................................................................................... .......... 24 7.3.9. me mo re c o rd ........................................................................................................... ...... 25 7.3.10. memo and call play back ............................................................................................. 26 7.3.11. me ssage c ueing ....................................................................................................... ... 27 7.4. a nalog m ode .............................................................................................................. .............. 28 7.4.1. aux in and ana in descr iption ........................................................................................ 2 8 7.4.2. analog struc t ure (left half) de s c r ipti on .......................................................................... 30 7.4.3. analog struc t ure (right half) de s c r ipti on ........................................................................ 31 7.4.4. volume c ontrol des c r iption ........................................................................................... 3 2 7.4.5. speaker and aux out descr iption .................................................................................. 33 publ i c at i on rel e ase dat e : oct ober, 2002 - 5 - revi si on 2.1
isd5116 7.4.6. ana out des c r iption ................................................................................................... .... 34 7.4.7. a nalog i nputs ......................................................................................................... ........ 34 7.5. digi tal m ode ............................................................................................................. ................ 37 7.5.1. er as ing data .......................................................................................................... ......... 37 7.5.2. writing data .......................................................................................................... .......... 37 7.5.3. reading data .......................................................................................................... ....... 38 7.5.4. exampl e command s equence ...................................................................................... 38 7.6. pi n deta ils .............................................................................................................. .................. 49 7.6.1. digi tal i/o pins ...................................................................................................... .......... 49 7.6.2. a nalog i/o pins ....................................................................................................... ....... 51 7.6.3. powe r and ground pins ................................................................................................. 55 7.6.4. samp le pc layout ...................................................................................................... ... 55 8. timing diagrams ............................................................................................................. ............. 56 8.1. i 2 c timing diagr am ............................................................................................................... ... 56 8.2. playback and stop cy cle .................................................................................................. ....... 58 8.3. example of power-up command (first 12 bits ) ...................................................................... 59 9. absolute maxi mum ratings .................................................................................................... 60 10. electrical cha racteris tics ............................................................................................... 62 10.1. general parame ters ...................................................................................................... ........ 62 10.2. timing parame ters ....................................................................................................... ......... 63 10.3. analog parame ters ....................................................................................................... ......... 65 10.4. characteristics of the i 2 c serial in terfac e .............................................................................. 69 10.5. i 2 c prot oc ol ..................................................................................................................... ....... 72 11. typical applic ation ci rcuit ................................................................................................ . 74 12. package spec ification ...................................................................................................... .... 75 12.1. plastic thin small outline package (tsop) type e dimens ions ......................................... 75 12.2. plas tic small outline interg rated circ uit (soi c) dimens ions ................................................ 76 12.3. plastic dual inline package (pdip) dimensi ons ................................................................... 77 12.4. die bonding physical layout ............................................................................................. .... 78 13. ordering informat ion ....................................................................................................... .... 80 14. version history ............................................................................................................ ........... 81 - 6 -
isd5116 5. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 21 20 19 18 17 16 15 13 14 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc au x o u t au x i n an a i n v cca sp+ v ssa sp- ac ap an a o u t - an a o u t + mi c - mi c + v ssa v ccd sc l a1 sd a a0 v ssd v ssd nc nc v ssa ra c in t xc lk v ccd v ccd v ccd xclk int ra c v ssa nc nc au x o u t au x i n an a i n v cca sp+ v ssa isd5116 isd5116 scl a 1 sd a a 0 v ssd v ssd nc mic+ v ss a mic- a na out+ an a o u t - a ca p sp- 28-pin tsop soic/pdip publ i c at i on rel e ase dat e : oct ober, 2002 - 7 - revi si on 2.1
isd5116 6. pin description pin name pin no . 28-pin ts op pin no . 28-pin soic/pdip functionality rac 3 24 row address clock; an open drain output. the rac pin goes low t ra cl o 1 before the end of each row of memory and returns high at ex actly the end of each row of memory. int 4 25 interrupt output; an open drain output that indicates that a set eom bit has been found during playback or that the chip is in an overflow (ovf) condition. this pin remains low until a read status command is ex ecuted. xclk 5 26 this pin allow s the internal clock of the device to be driven ex ternally for enhanced timing precision. this pin is grounded for most applications. scl 8 1 serial clock line is part of the i 2 c interface. it is used to clock the data into and out of the i 2 c interface. sda 10 3 serial data line is part of the i 2 c interface. data is passed betw een devices on the bus over this line. a0 11 4 input pin that supplies the lsb for the i 2 c slave address. a1 9 2 input pin that supplies the lsb +1 bit for the i 2 c slave address. mic+ 16 8 differential positive input to the microphone amplifier. mic- 17 10 differential negative input to the microphone amplifier. ana out+ 18 11 differential positive analog output for ana out of the device. ana out- 19 12 differential negative analog output for ana out of the device. acap 20 13 agc capacitor connection. required for the on-chip agc amplifier. sp+ 23 16 differential positive speaker driver output. sp- 21 14 differential negative speaker driver output. when the speaker outputs are in use, the aux out output is disabled. ana in 25 18 analog input. this is one of the gain adjustable analog inputs of the device. aux in 26 19 aux iliary input. this is one of the gain adjustable analog inputs of the device. aux out 27 20 aux iliary output. this is one the analog outputs of the device. when this output is in use, the sp+ and sp- outputs are disabled. v c c d 6,7 27,28 positive digital supply pins. these pins carry noise generated by internal clocks in the chip. they must be carefully bypassed to digital ground to insure correct device operation. v ssd 1 2 , 1 3 5 , 6 digital g r o u n d p i n s . v s s a 2 , 1 5 , 2 2 9 , 1 5 , 2 3 analog ground p i n s . v cca 24 1 7 positive analog supply pin. this pin supplies the low level audio sections of the device. it should be carefully bypassed to analog ground to insure correct device operation. n c 1 , 1 4 , 2 8 7 , 2 1 , 2 2 no c o n n e c t . 1 see the param e ters sectio n of on page 63 - 8 -
isd5116 7. functional description 7.1. overview 7.1.1 speech/sound quality the isd5116 chipcorder product can be configured via so ftware to operate at 4.0, 5.3, 6.4 or 8.0 khz sampling frequencies, allowing the user a choice of speech quality. increasing the duration decreases the sampling frequency and bandwidth, which affects s ound quality. the table in the following section compares filter pass band and product durations. 7.1.2. duration to meet end-system requirements, the isd5116 device is a single-chip solution, which provides from 8 to 16 minutes of voice record and playback, depending on the sample rates defined by customer software. input sample rate (khz) duration 1 ty pical filter knee (khz) 8.0 8 min 44 sec 3.4 6.4 10 min 55 sec 2.7 5.3 13 min 6 sec 2.3 4.0 17 min 28 sec 1.7 1. minus any pages selected for digital storage 7.1.3. flash technology one of the benefits of winbond?s chipcorder technol ogy is the use of on-chip nonvolatile memory, which provides zero-power message storage. the me ssage is retained for up to 100 years (typically) without power. in addition, the device can be re-reco rded over 10,000 times (typically) for the digital data and over 100,000 times (typically) for the analog messages. a new feature has been added that allows memory s pace in the isd5116 to be allocated to either digital or analog storage when recorded. the fact that a section has been assigned digital or analog data is stored in the message address table by t he system microcontroller when the recording is made. 7.1.4. microcontroller interface the isd5116 is controlled through an i 2 c 2-wire interface. this synchronous serial port allows commands, configurations, address data, and digital data to be loaded to the device, while allowing status, digital data and current address information to be read back from the device. in addition to the serial interface, two other pins can be connected to the microcontroller for enhanced interface. these publ i c at i on rel e ase dat e : oct ober, 2002 - 9 - revi si on 2.1
isd5116 are the rac timing pin and the int pin for interrupts to the controller. communications with all the internal registers are through the serial bus, as well as digital memory read and write operations. 7.1.5. programming the isd5116 is also ideal for playback-only applicat ions, where single or multiple messages may be played back when desired. playback is controlled through the i 2 c interface. once the desired message configuration is created, duplicates can easily be generated via a third-party programmer. for more information on available application tools and programmers, please see the winbond web s i te at www.winbond-usa.com 7.2. functional details the isd5116 is a single chip solution for voice and analog storage that also includes the capability to store digital data in the memory array. the array may be divided between analog and digital storage, as the user chooses, when configuri ng the device. the device consists of several sections that will be described in the following paragraphs. looking at the block diagram below, one can see t hat the isd5116 may be very easily designed into a cellular phone. placing the device between t he microphone and the existing voice encoder chip takes care of the transmit path. the ana in is connected between one of the speaker leads on the voice decoder chip and the speaker is connected to the speaker pins of the isd5116. two pins are needed for the i 2 c digital control and digital information for storage. baseband isd5116 microphone ke y board earpiece au x i n a u x ou t car kit s da , sc l a na in mic+ mic- sp+ sp- a na out + a na out - bb codec 12 3 4 56 7 8 microcontrolle r dsp sp o u t- sp o u t+ vb codec mic in+ mic in- rf section dis p la y - 10 -
isd5116 starting at the microphone inputs, the signal from the microphone can be routed directly through the chip to the ana out pins through a 6 db amplifier stage (feed through mode). or, the signal can be passed through the agc amplifier and directed to the ana out pins, directed to the storage array, or mixed with voice from the receive pat h coming from ana in and be directed to the same places. in addition, if the phone is inserted into a "hands -free" car kit, then the signal from the pickup microphone in the car can be passed through to the same places from the aux in pin and the phone's microphone is switched off. under this situat ion, the other party's voice from the phone is played into ana in and passed through to the aux out pin that drives the car kit's loudspeaker. depending upon whether one desires recording one si de (simplex) or both sides (duplex) of a conversation, the various paths will also be switched through to the low pass filter (for anti-aliasing) and into the storage array. later, the cell phone owner can playback the messages from the array. when this happens, the array output mux is connect ed to the volume control through the output mux to the speaker amplifier. for applications other than a cell phone, the audio paths can be switched into many different configurations, providing greater flexibility. 7.2.1. internal registers the isd5116 has multiple internal registers that are used to store the address information and the configuration or set-up of the device. the two 16- bit configuration register s control the audio paths through the device, the sample frequency, the va rious gains and attenuations, power up and down of different sections, and the volume settings. these registers are discussed in detail in section 7.3.5 on page 20. 7.2.2. memory organization the isd5116 memory array is arranged as 2048 pages (or rows) of 2048 bits for a total memory of 4,194,304 bits. the primary addressing for the 2048 pages is handled by 11 bits of address input in the analog mode. at the 8 khz sample rate, each page contains 256 milliseconds of audio. thus at 8 khz there is actually room for 8 minutes and 44 seconds of audio. a memory page is 2048 bits organized as thirty-two 64-bit "blocks" when used for digital storage. the contents of a page are either analog or digital. this is determined by instructi on (op code) at the time the data is written. a record of where is analog and where is digital, is stored in a message address table (mat) by the system microcont roller. the mat is a table kept in the microcontroller memory that defines the status of each message ?page?. it can be st ored back into the isd5116 if the power fails or the system is turned off. using this table allo ws for efficient message management. segments of messages can be stored wherever there is available s pace in the memory array. [this is explained in detail for the isd5008 in applications note #9 and w ill be similarly described in a later note for the isd5116.] publ i c at i on rel e ase dat e : oct ober, 2002 - 11 - revi si on 2.1
isd5116 when a page is used for analog storage, the same 32 blocks are present but there are 8 eom (end- of-message) markers. this means that for each 4 blocks there is an eom marker at the end. thus, when recording, the analog recording will stop at any one of eight positions. at 8 khz, this results in a resolution of 32 msec when ending an analog recording. beginning an analog recording is limited to the 256 msec resolution provided by the 11-bit address. a recording does not immediately stop when the stop command is given, but continues until the 32 millis econd block is filled. then a bit is placed in the eom memory to develop the inte rrupt that signals a message is finished playing in the playback mode. digital data is sent and rece ived serially over the i 2 c interface. the data is se rial-to-parallel converted and stored in one of two alternating (commutating) 64-bi t shift registers. when an input register is full, it becomes the register that is parallel written into the array. the prior write register becomes the new serial input register. a mechanism is built-in to ensur e there is always a register available for storing new data. storing data in the memory is accomplished by accepting data one byte at a time and issuing an acknowledge. if data is coming in faster than it can be written, the chip issues an acknowledge to the host microcontroller, but holds scl low until it is ready to accept more data. the read mode is the opposite of the write mode. data is read into one of two 64-bit registers from the array and serially sent to the i 2 c i n t e r f a c e . ( s e e section 7.5 on page 37 for details). 7.3. operational modes description 7.3.1. i 2 c interface to use more than four isd5116 devices in an applicat ion requires some external switching of the i 2 c interface. i 2 c interface important note: the rest of this data sheet will assum e that the reader is fam iliar with the i 2 c serial interface. additional inform ation on i 2 c m a y be found in section 10 on page 72 of this docum ent. if you are not fam iliar with this serial protocol, please read this section to fam iliarize yourself with it. a large am ount of additional inform ation on i 2 c can also be found on the philips web page at http://www.philips.com/ . i 2 c slav e address the isd5116 has a 7-bit slave address of <100 00xy> where x and y are equal to the state, respectively, of the external address pins a1 and a0. because all data bytes are required to be 8 bits, the lsb of the address byte is the read/write se lection bit that tells the slave whether to transmit or receive data. therefore, there are 8 possi ble slave addresses for the isd5116. these are: - 12 -
isd5116 pinout ta ble a 1 a 0 s l a v e address r/w bit hex value 0 0 <100 0 0 0 0 > 0 8 0 0 1 <100 0 0 0 1 > 0 8 2 1 0 <100 0 0 1 0 > 0 8 4 1 1 <100 0 0 1 1 > 0 8 6 0 0 <100 0 0 0 0 > 1 8 1 0 1 <100 0 0 0 1 > 1 8 3 1 0 <100 0 0 1 0 > 1 8 5 1 1 <100 0 0 1 1 > 1 8 7 isd5116 i 2 c operation definitions there are many control functions used to operate the isd5116. among them are: 7.3.1.1. read status command : the read status command is a read request from the host processor to the isd5116 without delivering a co mmand byte. the host supplies all the clocks (scl). in each case, the entity sending the dat a drives the data line (s da). the read status command is executed by the following i 2 c sequence. 1. host executes i 2 c start 2. send slave address with r/w bit = ?1? (read) 81h 3. slave (isd5116) responds back to host an ack nowledge (ack) followed by 8-bit status word 4. host sends an acknowledge (ack) to slave 5. wait for scl to go high 6. slave responds with upper address byte of internal address register 7. host sends an ack to slave 8. wait for scl to go high 9. slave responds with lower address byte of inte rnal address register (a[4:0] will always return s e t to 0.) 10. host sends a no ack to slave, then executes i 2 c stop publ i c at i on rel e ase dat e : oct ober, 2002 - 13 - revi si on 2.1
isd5116 note that the processor could have sent an i 2 c stop after the status word data transfer and aborted the transfer of the address bytes. conv entions used in i 2 c data transfer diagrams = start condition = stop condition = 8 - b i t d a t a t r a n s f e r = ? 1 ? i n t h e r / w b i t = ? 0 ? i n t h e r / w b i t = ack (acknowledge) = n o a c k w r n p data a slave address the box color indicates the direction of data flow = 7-bit slave address s a graphical representation of this operation is found below. see the caption box above for more explanation. = hos t to slave (gray) = slave t o h ost (white) a a data p r data data a n hi g h addr. low addr. status slave address s - 14 -
isd5116 7.3.1.2. load command byte register (single byte load ): a single byte may be written to the command byte register in order to power up the device, start or stop analog record (if no address information is needed), or do a message cueing function. the command byte register is loaded as follows: publ i c at i on rel e ase dat e : oct ober, 2002 1. host executes i 2 c start 2. send slave address with r/w bit = ?0? (write) [80h] 3. slave responds back with an ack. a command byte w p data a slave address s 4. wait for scl to go high 5. host sends a command byte to slave 6. slave responds with an ack 7. wait for scl to go high 8. host executes i 2 c stop 7.3.1.3. load command byte register (address load): for the normal addressed mode the registers are loaded as follows: 1. host executes i 2 c start 2. send slave address with r/w bit = ?0? (write) 3. slave responds back with an ack. 4. wait for scl to go high 5. host sends a byte to slave - (command byte) 6. slave responds with an ack 7. wait for scl to go high 8. host sends a byte to slave - (high address byte) 9. slave responds with an ack 10. wait for scl to go high 11. host sends a byte to slave - (low address byte) 12. slave responds with an ack 13. wait for scl to go high 14. host executes i 2 c stop a p w c o mmand data a data a data a hi g h addr. low addr. slave address s - 15 - revi si on 2.1
isd5116 7.3.2. i 2 c control registers the isd5116 is controlled by loading commands to, or, reading from, the internal command, configuration and address registers. the command byte sent is used to start and stop recording, write or read digital data and perform other functions necessary for the oper ation of the device. com m a nd by te control of the isd5116 is implemented through an 8- bit command byte, sent after the 7-bit device address and the 1-bit read/write selection bit. the 8 bits are: global power up bit dab bit: determines whether device is performing an analog or digital function 3 function bits: these determine which functi on the device is to perform in conjunction with the dab bit. 3 register address bits: these determine if and when data is to be loaded to a register c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 p u d a b f n 2 f n 1 f n 0 r g 2 r g 1 r g 0 function bits register bits pow e r up bit function bits the command byte function bits are detailed in the table to the right. c6, the dab bit, determines whether the device is performing an analog or digital function. the other bits are decoded to produce the individual commands. not all decode combinations are currently used, and are reserved for future use. out of 16 possible codes, the isd5116 uses 7 for normal operation. the other 9 are undefined function bits c 6 c 5 c 4 c 3 d a b f n 2 f n 1 f n 0 function 0 0 0 0 stop (or do nothing) 0 1 0 1 a n a l o g p l a y 0 0 1 0 analog r e c o r d 0 1 1 1 a n a l o g m c 1 1 0 0 digital r e a d 1 0 0 1 digital w r i t e 1 0 1 0 erase ( r o w ) - 16 -
isd5116 register bits the register load may be used to modify a command sequence (such as load an address) or used with the null command sequence to load a configuration or test register. not all registers are accessible to the user. [rg2 is always 0 as the four additional combinations are undefined.] r g 2 r g 1 r g 0 c 2 c 1 c 0 function 0 0 0 no a c t i o n 0 0 1 load a d d r e s s 0 1 0 load c f g 0 0 1 1 load c f g 1 7.3.3. opcode summary opcode command description the following commands are used to access the chip through the i 2 c interface. play: analog play command record: analog record command message cue: analog message cue command read: digital read command write: digital write command erase: digital page and block erase command power up: global power up/down bit. (c7) load address: load address register (is incorpor ated in play, record, read and write commands) load cfg0: load configuration register 0 load cfg1: load configuration register 1 read status: read the interrupt status and addr ess register, including a hardwired device id publ i c at i on rel e ase dat e : oct ober, 2002 - 17 - revi si on 2.1
isd5116 opcode command byte table pw r func tion bits re gis t e r bits o p c o d e h e x p u da b f n 2 f n 1 f n 0 r g 2 r g 1 r g 0 comma nd bit number cmd c7 c6 c5 c4 c3 c2 c1 c0 pow e r up 80 1 0 0 0 0 0 0 0 pow e r dow n 00 0 0 0 0 0 0 0 0 st op (do not h ing) st ay on 80 1 0 0 0 0 0 0 0 st op (do not h ing) st ay of f 00 0 0 0 0 0 0 0 0 load address 81 1 0 0 0 0 0 0 1 load cf g0 82 1 0 0 0 0 0 1 0 load cf g1 83 1 0 0 0 0 0 1 1 record analog 90 1 0 0 1 0 0 0 0 record analog @ addr 91 1 0 0 1 0 0 0 1 play analog a8 1 0 1 0 1 0 0 0 play analog @ addr a9 1 0 1 0 1 0 0 1 msg cue analog b8 1 0 1 1 1 0 0 0 msg cue analog @ addr b9 1 0 1 1 1 0 0 1 ent e r digit al mode c0 1 1 0 0 0 0 0 0 ex it digit al mode 40 0 1 0 0 0 0 0 0 digit al erase page d0 1 1 0 1 0 0 0 0 digit al erase page @ addr d1 1 1 0 1 0 0 0 1 digit al writ e c8 1 1 0 0 1 0 0 0 digit al writ e @ addr c9 1 1 0 0 1 0 0 1 digit al read e0 1 1 1 0 0 0 0 0 digit al read @ addr e1 1 1 1 0 0 0 0 1 read st at us 1 n / a n / a n / a n / a n/ a n / a n / a n / a n / a 1 . s e e section 7.2 on page 11 for details. - 18 -
isd5116 7.3.4. data by tes in the i 2 c write mode, the device can accept data sent after the command byte. if a register load option is selected, the next two bytes are loaded into the selected register. the format of the data is msb firs t, the i 2 c standard. thus to load data<15:0> into t he device, data<15:8> is sent first, the byte is acknowledged, and data<7:0> is sent next. t he address register consists of two bytes. the format of the address is as follows: address<15:0> = page_address< 10:0>, block_address<4:0> note: if an analog function is selected, the block address bits must be set to 0000. digital read and write are block addressable. when the device is polled with the read status command, it will return three bytes of data. the first byte is the status byte, the next the upper address byte and the la st the lower address byte. the status register is one byte long and its bit function is: status< 7 :0> = eom, ovf, read y, pd, prb, device_id< 2:0> lower address byte will always return the block addre ss bits as zero, either in digital or analog mode. the functions of the bits are: eom bit 7 indicates whether an eom interrupt has occurred. ovf bit 6 indicates whether an ov erflow interrupt has occurred. ready bit 5 indicates the internal stat us of the device ? if ready is low no new commands should be sent to device. pd bit 4 device is power ed down if pd is high. prb bit 3 play/record mode indicator. high=play/low=record. device_id bit 0, 1, 2 an internal device id. this is 001 for the isd5116. it is recommended that you read the st atus register after a write or record operation to ensure that the device is ready to accept new commands. depending upon the design and the number of pins available on the controller, the polling overhead can be reduced. if int and rac are tied to the microcontroller, it does not have to poll as fr equently to determine the st atus of the isd5116. publ i c at i on rel e ase dat e : oct ober, 2002 - 19 - revi si on 2.1
isd5116 7.3.5. configuration resiter by tes the configuration register bytes are def ined, in detail, in the drawings of section 7.4 on page 28. the drawings display how each bit enables or disables a function of the audio paths in the isd5116. the tables below give a general illustration of the bits . there are two configuration registers, cfg0 and cfg1, so there are four 8-bit bytes to be loaded during the set-up of the device. d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 c o nfigurat ion r e gist er 0 (c fg 0) ai g 1 ai g 0 ai p d ax g 1 a x g 0 a xpd i n s0 a o s2 ao s1 ao s 0 aopd o ps1 o p s 0 o p a 1 o p a 0 v l pd v o l u m e con t rol p o w er d o wn s p k r & au x o u t con t rol ( 2 b i t s) out p ut m u x se le c t (2 bits ) ana ou t p o we r dow n aux ou t m u x se le c t (3 bits ) inp u t s o ur ce mux s e lect ( 1 b i t ) aux i n p o we r dow n aux i n am p g a in se t (2 bits ) ana i n p o we r dow n ana i n am p g a in se t (2 bits ) d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 c o nfigurat ion r e gist er 0 (c fg 0) ai g 1 ai g 0 ai p d ax g 1 a x g 0 a xpd i n s0 a o s2 ao s1 ao s 0 aopd o ps1 o p s 0 o p a 1 o p a 0 v l pd v o l u m e con t rol p o w er d o wn s p k r & au x o u t con t rol ( 2 b i t s) out p ut m u x se le c t (2 bits ) ana ou t p o we r dow n aux ou t m u x se le c t (3 bits ) inp u t s o ur ce mux s e lect ( 1 b i t ) aux i n p o we r dow n aux i n am p g a in se t (2 bits ) ana i n p o we r dow n ana i n am p g a in se t (2 bits ) - 20 -
isd5116 agc amp p o wer down f i lt er p o wer d o wn sam p l e rate (& f i lt e r ) s e t up (2 bit s ) f i lte r mux s e l e ct su m 2 su m m i n g a m p c o ntr o l (2 bi ts ) sum 1 s u m m ing amp co nt rol ( 2 b i t s ) sum 1 m ux s e le c t ( 2 bits ) volume contr o l ( 3 bi t s ) volume cont. m ux sel e ct (2 bi t s ) c onfiguration r e gister 1 (c fg 1) v l s 1 v l s 0 v o l 2 v o l 1 v o l 0 s 1 s 1 s 1 s 0 s 1 m1 s 1 m 0 s 2 m 1 s 2 m 0 fl s 0 f l d 1 fl d 0 fl p d a g p d d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 agc amp p o wer down f i lt er p o wer d o wn sam p l e rate (& f i lt e r ) s e t up (2 bit s ) f i lte r mux s e l e ct su m 2 su m m i n g a m p c o ntr o l (2 bi ts ) sum 1 s u m m ing amp co nt rol ( 2 b i t s ) sum 1 m ux s e le c t ( 2 bits ) volume contr o l ( 3 bi t s ) volume cont. m ux sel e ct (2 bi t s ) c onfiguration r e gister 1 (c fg 1) v l s 1 v l s 0 v o l 2 v o l 1 v o l 0 s 1 s 1 s 1 s 0 s 1 m1 s 1 m 0 s 2 m 1 s 2 m 0 fl s 0 f l d 1 fl d 0 fl p d a g p d d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 v l s 1 v l s 0 v o l 2 v o l 1 v o l 0 s 1 s 1 s 1 s 0 s 1 m1 s 1 m 0 s 2 m 1 s 2 m 0 fl s 0 f l d 1 fl d 0 fl p d a g p d d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 v l s 1 v l s 0 v o l 2 v o l 1 v o l 0 s 1 s 1 s 1 s 0 s 1 m1 s 1 m 0 s 2 m 1 s 2 m 0 fl s 0 f l d 1 fl d 0 fl p d a g p d d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 7.3.6. pow e r-up sequence this sequence prepares the isd5116 for an operation to follow, waiting the tpud time before sending the next command sequence. 1. send i 2 c power up 2. send one byte 10000000 {slave address, r/w = 0} 80h 3. slave ack 4. wait for scl high 5. send one byte 10000000 {command byte = power up} 80h 6. slave ack 7. wait for scl high 8. send i 2 c stop play back mode the command sequence for an analog playback operation can be handled several ways. one technique would be to do a load address (81h), which requires sending a total of four bytes, and then sending a play analog, which would be a comm and byte (a8h) proceeded by the slave address byte. this is a total of six bytes plus the times for start, ack, and stop. publ i c at i on rel e ase dat e : oct ober, 2002 - 21 - revi si on 2.1
isd5116 another approach would be to incorporate both into a single four byte exchange, which consists of the slave address (80h), the command byte (a9h) fo r play analog @ address, and the two address bytes. record mode the command sequence for an analog record would be a four byte sequence consisting of the slave address (80h), the command byte (91h) for record analog @ address, and the two address bytes. see ?load command byte register (a ddress load)? in section 7.3.2 on page 16. 7.3.7. feed through mode the previous examples were dependent upon the device already being powered up and the various paths being set through the device for the desired oper ation. to set up the device for the various paths requires loading the two 16-bit configuration regi sters with the correct dat a. for example, in the feed through mode the device only needs to be powered up and a few paths selected. this mode enables the isd5116 to connect to a cellular or cordless base band phone chip set without affecting the audio source or destination. there are two paths involved, the transmit path and the receive path. the transmit path connects the winbond chip?s microphone source through to the microphone input on the base band chip set. the receive path connects the base band chip set?s speaker output through to the speaker driver on the winbond chip. this allows the winbond chip to substitute for those functions and incidentally gai n access to the audio to and from the base band chip s e t. to set up the environment described above, a series of commands need to be sent to the isd5116. first, the chip needs to be powered up as described in this section. then the configuration registers must be filled with the specific data to connect the paths desired. in the case of the feed through mode, most of the chip can remain pow ered down. the following figure illustrates the affected paths. an a i n chip set chip set an a o u t + a na out- s p eake r sp+ sp- output mux an a i n am p 6 d b a na out mux fthru inp filt o su m 1 su m 2 2 [ops1,ops0] 2 [aig1,aig0] 1 [apd ] 3 [aos2,aos1,aos0] 1 [aopd] 2 [opa1,opa0] su m 2 filto an a i n am p v ol vol mi c + mi c - microphone - 22 -
isd5116 the figure above shows the part of the isd5116 blo ck diagram that is used in feed through mode. the rest of the chip will be powered down to conser ve power. the bold lines highlight the audio paths. note that the microphone to ana out +/? path is differential. to select this mode, the following control bits must be configured in the isd5116 configuration registers. to set up the transmit path: 1. select the fthru path through the ana out mux?bits aos0, aos1 and aos2 control the state of the ana out mux. these are the d6, d7 and d8 bits respectively of configuration register 0 (cfg0) and they should a ll be zero to select the fthru path. 2. power up the ana out amplifier?bit aopd cont rols the power up state of ana out. this is bit d5 of cfg0 and it should be a zero to power up the amplifier. to set up the receive path: 1. set up the ana in amplifier for the correct gain?bits aig0 and aig1 control the gain settings of this amplifier. these are bits d14 and d15 res pectively of cfg0. the input level at this pin determines the setting of this gain stage. the ana in am plifier gain settings table on page 36 will help determine this setting. in this exampl e, we will assume that the peak signal never goes above 1 volt p-p single ended. that would enabl e us to use the 9 db attenuation setting, or where d14 is one and d15 is zero. 2. power up the ana in amplifier?bit aipd contro ls the power up state of ana in. this is bit d13 of cfg0 and should be a zero to power up the amplifier. 3. select the ana in path through the output mux?bits ops0 and ops1 control the state of the output mux. these are bits d3 and d4 re spectively of cfg0 and they should be set to the state where d3 is one and d4 is zero to select the ana in path. 4. power up the speaker amplifier?bits opa0 and opa1 control the state of the speaker and aux amplifiers. these are bits d1 and d2 res pectively of cfg0. they should be set to the state where d1 is one and d2 is zero. this powers up the speaker amplifier and configures it for its higher gain setting for us e with a piezo speaker element and also powers down the aux output stage. the status of the rest of the functions in the isd5116 chip must be defined before the configuration registers settings are updated: 1. power down the volume control element ? bit vlpd controls the power up state of the volume control. this is bit d0 of cfg0 and it should be set to a one to power down this stage. 2. power down the aux in amplifier ? bit axpd controls the power up state of the aux in input amplifier. this is bit d10 of cfg0 and it s hould be set to a one to power down this stage. 3. power down the sum1 and sum2 mixer amplifiers ? bits s1m0 and s1m1 control the sum1 mixer and bits s2m0 and s2m1 control the sum2 mixer. these are bits d7 and d8 in cfg1 and bits d5 and d6 in cfg1 respectively. all 4 bits should be set to a one to power down these two amplifiers. publ i c at i on rel e ase dat e : oct ober, 2002 - 23 - revi si on 2.1
isd5116 4. power down the filter stage ? bit flpd controls the power up state of the filter stage in the device. this is bit d1 in cfg1 and s hould be set to a one to power down the stage. 5. power down the agc amplifier ? bit agpd controls the power up state of the agc amplifier. this is bit d0 in cfg1 and should be se t to a one to power down this stage. 6. don?t care bits ? the following stages are not used in feed through mode. their bits may be set to either level. in this example, we will set all the following bits to a zero. (a). bit ins0, bit d9 of cfg0 controls the input source mux. (b). bits axg0 and axg1 are bits d11 and d12 respectively in cfg0. they control the aux in amplifier gain setting. (c). bits fld0 and fld1 are bits d2 and d3 respectively in cfg1. t hey control the sample rate and filter band pass setting. (d). bit fls0 is bit d4 in cfg1. it cont rols the filter mux. (e). bits s1s0 and s1s1 are bits d9 and d10 of cfg1. they control the sum1 mux. (f). bits vol0, vol1 and vol2 are bits d11, d12 and d13 of cfg1. they control the setting of the volume control. (g). bits vls0 and vls1 are bits d14 and d15 of cfg1 . they control the volume control mux. the end result of the above set up is cfg0=0100 0100 0000 1011 (hex 440b) and cfg1=0000 0001 1110 0011 (hex 01e3). since both registers are being loaded, cfg0 is l oaded, followed by the loading of cfg1. these two registers must be loaded in this order. the internal set up for both registers will take effect synchro- nously with the rising edge of scl. 7.3.8. call record the call record mode adds the ability to record an incoming phone call. in most applications, the isd5116 would first be set up for feed through mode as described above. when the user wishes to record the incoming call, the setup of the chip is modified to add that ability. for the purpose of this explanation, we will use the 6.4 kh z sample rate during recording. the block diagram of the isd5116 s hows that the multilevel storage array is always driven from the sum2 summing amplifier. the path traces ba ck from there through the low pass filter, the filter mux, the sum1 summing amplifier, the su m1 mux, then from the ana in amplifier. feed through mode has already powered up the ana in amp so we only need to power up and enable the path to the multilevel storage array from that point: 1. select the ana in path through the sum1 mux? bits s1s0 and s1s1 control the state of the sum1 mux. these are bits d9 and d10 respecti vely of cfg1 and they should be set to the state where both d9 and d10 are zero to select the ana in path. 2. select the sum1 mux input (only) to t he s1 summing amplifier?bits s1m0 and s1m1 control the state of the sum1 summing amplifie r. these are bits d7 and d8 respectively of - 24 -
isd5116 cfg1 and they should be set to the state where d7 is one and d8 is zero to select the sum1 mux (only) path. 3. select the sum1 summing amplifier path th rough the filter mux?bit fls0 controls the state of the filter mux. this is bit d4 of cfg1 and it must be set to zero to select the sum1 summing amplifier path. 4. power up the low pass filter?bit flpd c ontrols the power up s t ate of the low pass filter stage. this is bit d1 of cfg1 and it must be set to zero to power up the low pass filter stage. 5. select the 6.4 khz sample rate ? bits fld0 and fld1 select the low pass filter setting and sample rate to be used during record and playback. these are bits d2 and d3 of cfg1. to enable the 6.4 khz sample rate, d2 must be set to one and d3 set to zero. 6. select the low pass filter input (only) to the s2 summing amplifier ? bits s2m0 and s2m1 control the state of the sum2 summi ng amplifier. these are bits d5 and d6 respectively of cfg1 and they should be set to the state where d5 is zero and d6 is one to s e lec t the low pass filter (only) path. in this mode, the elements of the original pass through mode do not change. the sections of the chip not required to add the record path remain powered down. in fact, cfg0 does not change and remains cfg0=0100 0100 0000 1011 (hex 440b). cfg1 changes to cfg1=0000 0000 1100 0101 (hex 00c5). since cfg0 is not changed, it is only necessary to load cfg1. note that if only cfg0 was changed, it would be necessary to load both registers. 7.3.9. memo record the memo record mode sets the chip up to record from the local microphone into the chip?s multilevel storage array. a connected cellular telephone or cordless phone chip set may remain powered down and is not active in this mode. the path to be us ed is microphone input to agc amplifier, then through the input source mux to the sum1 summing am plifier. from there the path goes through the filter mux, the low pass filter, the sum2 summing amplifier, then to the multilevel storage array. in this instance, we will select t he 5.3 khz sample rate. the rest of the chip may be powered down. 1. power up the agc amplifier?bit agpd contro ls the power up state of the agc amplifier. this is bit d0 of cfg1 and must be set to zero to power up this stage. 2. select the agc amplifier through the input source mux?bit ins0 controls the state of the input source mux. this is bit d9 of cf g0 and must be set to a zero to select the agc amplifier. 3. select the input source mux (only ) to the s1 summing amplifier ? bits s1m0 and s1m1 control the state of the sum1 summing amplifie r. these are bits d7 and d8 respectively of publ i c at i on rel e ase dat e : oct ober, 2002 - 25 - revi si on 2.1
isd5116 cfg1 and they should be set to the state where d7 is zero and d8 is one to select the input source mux (only ) path. 4. select the sum1 summing amplifier path th rough the filter mux?bit fls0 controls the state of the filter mux. this is bit d4 of cfg1 and it must be set to zero to select the sum1 summing amplifier path. 5. power up the low pass filter ? bit flpd c ontrols the power up s t ate of the low pass filter stage. this is bit d1 of cfg1 and it must be set to zero to power up the low pass filter stage. 6. select the 5.3 khz sample rate?bits fld0 and fld1 select the low pass filter setting and sample rate to be used during record and playback. these are bits d2 and d3 of cfg1. to enable the 5.3 khz sample rate, d2 must be set to zero and d3 set to one. 7. select the low pass filter input (only) to the s2 summing amplifier ? bits s2m0 and s2m1 control the state of the sum2 summi ng amplifier. these are bits d5 and d6 respectively of cfg1 and they should be set to the state where d5 is zero and d6 is one to s e lec t the low pass filter (only) path. to set up the chip for memo record, the conf iguration registers are set up as follows: cfg0=0010 0100 0010 0001 (hex 2421). cfg1=0000 0001 0100 1000 (hex 0148). only those portions necessary for this mode are powered up. 7.3.10. memo and call play back this mode sets the chip up for local playback of messages recorded earlier. the playback path is from the multilevel storage array to the filter mux, then to the low pass filter stage. from there, the audio path goes through the sum2 summing amplifier to the volume mux, through the volume control then to the speaker output stage. we will assume that we are driving a piezo speaker element. this audio was prev iously recorded at 8 kh z. all unnecessary stages will be powered down. 1. select the multilevel storage array path through the filter mux ? bit fls0, the state of the filter mux. this is bit d4 of cfg1 and must be set to one to select the multilevel storage array. 2. power up the low pass filter ? bit flpd c ontrols the power up s t ate of the low pass filter stage. this is bit d1 of cfg1 and it must be set to zero to power up the low pass filter stage. 3. select the 8.0 khz sample rate?bits fld0 and fld1 select the low pass filter setting and sample rate to be used during record and playback. these are bits d2 and d3 of cfg1. to enable the 8.0 khz sample rate, d2 and d3 must be set to zero. 4. select the low pass filter input (only) to the s2 summing amplifier ?bits s2m0 and s2m1 control the state of the sum2 summi ng amplifier. these are bits d5 and d6 respectively of cfg1 and they should be set to the state where d5 is zero and d6 is one to s e lec t the low pass filter (only) path. - 26 -
isd5116 5. select the sum2 summing amplifier path through the volume mux ? bits vls0 and vls1 control the state volume mux. these bits ar e bits d14 and d15, respectively of cfg1. they should be set to the state where d14 is one and d15 is zero to select the sum2 summing amplifier. 6. power up the volume control level ? bit vlpd controls the power-up state of the volume control attenuator. this is bit d0 of cfg0. this bit must be set to a zero to power-up the volume control. 7. select a volume control level?bits vo l0, vol1, and vol2 control the state of the volume control level. these are bits d11, d12, and d13, respectively, of cfg1. a binary count of 000 through 111 controls the amount of attenuation through t hat state. in most cases, the software will select an attenuation le vel according to the desires of the current users of the product. in this example, we will assume the user wants an attenuation of ?12 db. for that setting, d11 should be set to one, d12 should be set to one, and d13 should be set to a zero. 8. select the volume control path through the output mux ? these are bits d3 and d4, respectively, of cfg0. they should be set to t he state where d3 is zero and d4 is a zero to select the volume control. 9. power up the speaker amplifier and select the high gain mode ? bits opa0 and opa1 control the state of the speaker (sp+ and sp? ) and aux out outputs. these are bits d1 and d2 of cfg0. they must be set to the state w here d1 is one and d2 is zero to power-up the speaker outputs in the high gain mode and to power-down the aux out. to set up the chip for memo or call playback, t he configuration registers are set up as follows: cfg0=0010 0100 0010 0010 (hex 2422). cfg1=0101 1001 1101 0001 (hex 59d1). only those portions necessary for this mode are powered up. 7.3.11. message cueing message cueing allows the user to skip through anal og messages without knowi ng the actual physical location of the message. this operation is used dur ing playback. in this mode, the messages are skipped 512 times faster than in normal playback m ode. it will stop when an eom marker is reached. then, the internal address counter will be pointing to the next message. publ i c at i on rel e ase dat e : oct ober, 2002 - 27 - revi si on 2.1
isd5116 7.4. analog mode 7.4.1. aux in and ana in description the aux in is an additional audio input to the is d5116, such as from the microphone circuit in a mobile phone ?car kit.? this input has a nominal 694 mv p-p level at its minimum gain setting (0 db). see the aux in amplifier gain settings table on page 36. additional gain is available in 3 db steps (controlled by the i 2 c serial interface) up to 9 db. internal to the device rb ra c coup = 0 .1 f aux in in p ut aux in in p ut am p lifie r note: f cutoff = 1 2 rac coup internal to the device rb ra c coup = 0.1 f aux in in p ut am p lifie r aux in in p ut note: f cutoff = 1 2 rac coup - 28 -
isd5116 the ana in pin is the analog input from the tel ephone chip set. it can be switched (by the serial bus) to the speaker output, the array input or to vari ous other paths. this pin is designed to accept a nominal 1.11 vp-p when at its mini mum gain (6 db) setting. see the ana in am plifier gain settings table on page 36. there is additional gain availabl e in 3 db steps controlled from the i 2 c interface, if required, up to 15 db. internal to the device rb ra c coup = 0 .1 f ana in in p ut ana in in p ut am p lifie r note: f cutoff = 1 2 rac coup publ i c at i on rel e ase dat e : oct ober, 2002 - 29 - revi si on 2.1
isd5116 7.4.2. isd 5116 analog structure (left half) description inp in p u t ag c am p s um 1 2 ( s 1m 1, s 1 m 0 ) s ou r c e mu x su m 1 s um m i n g am p au x i n am p fi lto s um 1 mu x an a i n a m p ar r a y 2 ( s 1 s 1, s 1 s 0 ) (i n s 0 ) s 1 m 1 s 1 m 0 s o u r c e 0 0 b o t h 0 1 sum1 mux only 1 0 i n p only 1 1 pow e r dow n i n s o s o u r c e 0 a g c a m p 1 aux in amp s 1 s 1 s 1 s 0 s o u r c e 0 0 a n a i n 0 1 array 1 0 f i l t o 1 1 n / c 1 5 14 1 3 12 1 1 10 9 8 7 6 5 4 3 2 1 0 ai g 1 a i g 0 a i pd ax g 1 a x g 0 a xpd in s 0 ao s 2 a o s 1a o s 0a o p d o p s 1 o ps0 o pa1 o p a 0 v l pd cf g 0 1 5 14 1 3 12 1 1 10 9 8 7 6 5 4 3 2 1 0 vl s1 vl s0 v o l 2 vo l 1 v o l 0 s1 s 1 s 1 s 0s 1 m 1s 1 m 0 s 2 m 1 s 2 m 0 f ls 0 f ld 1 f ld 0 f lp d a g p d cf g 1 - 30 -
isd5116 7.4.3. isd5116 analog structure (right half) description su m 1 s um 2 2 ( s 2m 1 , s 2 m 0 ) r x su m 2 su m m i n g am p ar r a y 2 o l o w pa ss fi l t e r i n t e rn al cl o c k mu l t il e v e l s to r a g e ar ra y 1 (f l s 0 ) 1 (f l p d ) ar r a y an a i n am p xc l k (f l d 1 , f l d 0 ) publ i c at i on rel e ase dat e : oct ober, 2002 fi lte mu fi lter mux fi lt fi lto f l s 0 s o u r c e 0 s u m 1 1 a r r a y f l p d c o n d i ti o n 0 p o w e r u p 1 p o we r d o wn f l d 1 f l d 0 s a m p l e rate fi lter bandw i d th 0 0 8 khz 3.6 khz 0 1 6.4 khz 2.9 khz 1 0 5.3 khz 2.4 khz 1 1 4.0 khz 1.8 khz s 2 m 1 s 2 m 0 s o u r c e 0 0 b o t h 0 1 ana in only 1 0 f i l t o only 1 1 pow e r dow n 1 5 1 4 1 3 1 2 1 1 1 0 98 76 54 32 10 vl s 1 vl s0 vo l 2 v o l 1 vo l 0 s1 s1 s1 s0 s1 m 1 s1 m 0 s2 m 1 s 2 m 0 fls 0 f ld 1 f ld 0 f l pd ag p d cf g 1 - 31 - revi si on 2.1
isd5116 7.4.4. v olume control description vo l s um 2 vo l mu x s um 1 in p 2 an a i n a m p vo l u m e co n t r o l (v l s 1 , v l s 0 ) 3 ( v o l2, v o l 1 , v o l 0 ) 1 ( v lp d ) v l p d c o n d i ti o n 0 p o w e r u p 1 p o we r d o wn v l s 1 v l s 0 s o u r c e 0 0 ana in amp 0 1 s u m 2 1 0 s u m 1 1 1 i n p v o l 2 v o l 1 vol 0 attenuati on 0 0 0 0 d b 0 0 1 4 d b 0 1 0 8 d b 0 1 1 1 2 d b 1 0 0 1 6 d b 1 0 1 2 0 d b 1 1 0 2 4 d b 1 1 1 2 8 d b in s 0 ai g 1 ai g 0 a i pd ax g 1 ax g 0 a x p d ao s 2a o s 1 a o s 0a o p d o p s 1 o p s 0 o pa 1 o pa 0 vl pd cf g 0 1 5 1 4 1 3 1 2 1 1 1 0 98 7 6 54 32 10 vl s1 vl s0 vo l 2v o l 1 s 1 s 1 s 1s 0 s 1m 1 s 1 m 0 s 2m 1 s 2m 0 f l s 0f l d 1f l d 0 f l p d a g p d cf g 1 vo l 0 - 32 -
isd5116 7.4.5. speaker and aux out description s pe a k e r sp + sp ? au x o u t ca r k i t (1 v p - p m a x ) ana i n am p ou t p u t mu x f i lto s um 2 2 vo l (o p s 1 , o p s 0) 2 (o p a 1 , o p a 0 ) opa1 opa0 spkr drive aux out 0 0 p o we r d o wn p o we r d o wn 0 1 3.6 v p-p @ 150 ? p o we r d o wn 1 0 23.5 mw att @ 8 ? p o we r d o wn 1 1 pow e r dow n 1 v p-p max @ 5 k ? o p s 1 o p s 0 s o u r c e 0 0 v o l 0 1 a n a i n 1 0 f i l t o 1 1 s u m 2 in s 0 1 5 1 4 1 3 1 2 1 1 1 0 98 7 6 54 32 10 ai g 1 ai g 0 a i pd ax g 1 ax g 0 a x p d ao s 2a o s 1 a o s 0 a o p d o ps1 o p s 0 o pa 1 o pa 0 vl pd cf g 0 publ i c at i on rel e ase dat e : oct ober, 2002 - 33 - revi si on 2.1
isd5116 7.4.6. ana out description c h ip s e t an a o u t + an a o u t ? *v o l *f i l t o *s u m 2 3 ( a o s 2, a o s 1 , a o s 0) * f t hru 1 (a o p d ) *i n p *s u m 1 ( 1 v p - p m a x . f r o m a u x in o r a r r a y ) ( 6 9 4 m v p- p m a x . f r o m m i c r op ho ne inp u t ) a o p d c o n d i ti o n 0 p o w e r u p 1 p o we r d o wn a o s 2 a o s 1 a o s 0 s o u r c e 0 0 0 f t h r u 0 0 1 i n p 0 1 0 v o l 0 1 1 f i l t o 1 0 0 s u m 1 1 0 1 s u m 2 1 1 0 n / c 1 1 1 n / c *differentia l pa th in s 0 1 5 1 4 1 3 1 2 1 1 1 0 98 76 54 32 10 ai g 1 ai g 0 a i pd a x g 1 ax g 0 a xpd a o s2 a o s1 a o s0 a o pd o ps1 o ps0 o p a 1 o p a 0 v l pd cf g 0 7.4.7. analog inputs microphone inputs the microphone inputs transfer the voice signal to the on- chip agc preamplifier or directly to the ana out mux, depending on the selected path. the dire ct path to the ana out mux has a gain of 6 db so a 208 mv p-p signal across the different ial microphone inputs would give 416 mv p-p across the ana out pins. the agc circuit has a range of 45 db in order to deliver a nominal 694 mv p-p into the storage array from a typical electric microphone output of 2 to 20 mv p-p. the input impedance is typically 10k ? . the acap pin provides the capacitor connection for setting the parameters of the microphone agc circuit. it should have a 4.7 f capacitor connect ed to ground. it cannot be left floating. this is because the capacitor is also used in the playback m ode for the automute circuit. this circuit reduces the amount of noise present in the output duri ng quiet pauses. tying this pin to ground gives maximum gain; to vcca gives minimum gain for t he agc amplifier but will cancel the automute function. - 34 -
isd5116 mi c + mi c ? ac a p ft h r u ag c 1 ( a g p d ) 6 d b t o a u to m u te ( p l a yb a c k o n l y ) * * d i f f er en t i a l p a t h a g p d c o n d i ti o n 0 p o w e r u p ag c mic in 1 p o we r d o wn 1 5 1 4 1 3 1 2 1 1 1 0 98 7 6 54 32 10 vl s 1 v l s 0 v ol 2 v ol 1 v o l 0 s 1 s 1 s 1s 0 s 1m 1 s 1 m 0 s 2m 1 s 2m 0 f l s 0 f l d 1 f ld 0 f l p d ag p d cf g 1 ana in (analog input) the ana in pin is the analog input from the telephone chip set. it can be switched (by the i 2 c interface) to the speaker output, the array input or to various other paths. this pin is designed to accept a nominal 1.11 v p-p when at its minimu m gain (6 db) setting. there is additional gain available, if required, in 3 db steps, up to 15 db. the gain settings are controlled from the i 2 c interface. publ i c at i on rel e ase dat e : oct ober, 2002 ana in am plifier gain settings gain setting resist or rat i o (rb/ra) g a i n g a i n (db) 2 00 63.9 / 102 0.625 -4.1 01 77.9 / 88.1 0.883 -1.1 10 92.3 / 73.8 1.9 11 106 / 60 1.767 4.9 1.250 an a i n input a n a i n input a m plifier note: f c u tto f f 2xr a c coup 1 r a r b c coup = 0.1 f internal to the d ev ice cfg0 setting (1) 0 t l p i n p u t v p-p (3) a i g 1 a i g 0 gain (2) a r r a y in/out v p-p speaker out v p-p (4) 6 db 1.110 0 0 0.625 0.694 2.22 9 db 0.785 0 1 0.883 0.694 2.22 12 db 0.555 1 0 1.250 0.694 2.22 15 db 0.393 1 1 1.767 0.694 2.22 - 35 - revi si on 2.1
isd5116 1. gain from ana in to sp+/- 2. gain from ana in to array in 3. 0t lp input is the reference t r ansmission level point that is us ed for testing. t h is level is typically 3 db below clipping 4. speaker out gain set to 1.6 (high). (differential) aux in (auxiliary input) the aux in is an additional audio input to the is d5116, such as from the microphone circuit in a mobile phone ?car kit.? this input has a nominal 694 mv p-p level at its minimum gain setting (0 db). see the following table. additional gain is av ailable in 3 db steps (controlled by the i 2 c interface) up to 9 db. aux in input modes an a i n input a n a i n input a m plifier note: f c u tto f f 2xr a c coup 1 r a r b c coup = 0.1 f internal to the d ev ice gain setting resist or rat i o (rb/ra) g a i n g a i n (2) (db) 00 40.1 / 40.1 1.0 0 01 47.0 / 33.2 1.414 3 10 53.5 / 26.7 2.0 6 11 59.2 / 21 2.82 9 aux in amplifier gain settings cfg0 setting (1) 0 t l p i n p u t v p-p (3) a i g 1 a i g 0 gain (2) a r r a y in/out v p-p speaker out v p-p (4) 0 db 0.694 0 0 1.00 0.694 0.694 3 db 0.491 0 1 1.41 0.694 0.694 6 db 0.347 1 0 2.00 0.694 0.694 9 db 0.245 1 1 2.82 0.694 0.694 1. gain from aux in to ana out 2. gain from aux in to array in 3. 0t lp input is the refe rence t r ansmission level point that is used for testing. t h is level is typically 3 db below clipping 4. differential - 36 -
isd5116 7.5. digital mode 7.5.1. erasing digital data the digital erase command can only erase an entir e page at a time. this means that the d1 command only needs to include the 11-bit page address; the 5-bit for block address are left at 00000. once a page has been erased, each block may be written separately, 64 bits at a time. but, if a block has been previously written then t he entire page of 2048 bits must be erased in order to re-write (or change) a block. a sequence might be look like: - read the entire page - store it in ram - change the desired bit(s) - erase the page - write the new data from ram to the entire page 7.5.2. writing digital data the digital write function allows the user to select a portion of the array to be used as digital memory. the partition between analog and digital memory is left up to the user. a page can only be either digital or analog, but not both. the minimum addre ssable block of memory in the digital mode is one block or 64 bits, when reading or writing. the addr ess sent to the device is the 11-bit row (or page) address with the 5-bit scan (or block) address. however, one must send a digital erase before attempting to change digital data on a page. this means that even when changing only one of the 32 blocks, all 32 blocks will need to be rewritten to the page. command sequence: the chip enters digital mode by sending the enter digital mode command from power down. send the digital write @ addr command with the row address. after the address is entered, the data is sent in one-byte packets followed by an i 2 c acknowledge generated by the chip. data for each block is sent msb first. the data transfer is ended when the master generates an i 2 c stop condition. if only a partial block of data is sent before the stop c ondition, ?zero? is written in the remaining bytes; that is, they are left at the erase level. an er ased page (row) will be read as all zeros. the device can buffer up to two blocks of data. if the device is unabl e to accept more data due to the internal write process, the scl line will be held low indica ting to the master to halt data transfer. if the device encounters an overflow condition, it will res pond by generating an interrupt condition and an i 2 c not acknowledge signal after the last valid byte of dat a. once data transfer is terminated, the device needs up to two cycles (64 us) to complete its in ternal write cycle before another command is sent. if an active command is sent before the internal cycl e is finished, the part will hold scl low until the current command is finished. after writing is complete, send the exit digital mode command. publ i c at i on rel e ase dat e : oct ober, 2002 - 37 - revi si on 2.1
isd5116 7.5.3. reading digital data the digital read command utilizes the combined i 2 c command format. that is, a command is sent to the chip using the write data di rection. then the data directi on is reversed by sending a repeated start condition, and the slave address with r/w set to 1. after this, the slave device (isd5116) begins to send data to the master until the ma ster generates a nack. if the part encounters an overflow condition, the int pin is pulled low. no other communi cation with the master is possible due to the master generating ack signals. as with digital write, digital read can be done a ?blo ck? at a time. thus, only 64 bits need be read in each digital read command sequence. 7.5.4. example command sequences an explanation and graphical representation of the erase, write and read operations are found below. note: all sequences assumes that the chip is in power-down mode before the commands are sent. 7.5.4.1. erase digital data erase ===== i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xc0) - enter digital mode command waitack waitsclhigh i2cstop i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xd1) - digital erase command waitack waitsclhigh - 38 -
isd5116 sendbyte(row/256) - high address byte waitack waitsclhigh sendbyte(row%256) - low address byte waitack waitsclhigh i2cstop repeat until the number of rac pulses are one less than the number of rows to delete { wait rac low wait rac high } note: if only one row is going to be erased, send the following stop command immediately after erase command and skip the loop above i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xc0) - stop digital erase waitack waitsclhigh i2cstop wait until erase of the last row has completed { wait rac low wait rac high } i2cstart publ i c at i on rel e ase dat e : oct ober, 2002 - 39 - revi si on 2.1
isd5116 sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0x40) - exit digital mode command waitack waitsclhigh i2cs top notes 1. erase operations must be addressed on a row boundary. the 5 lsb bits of the low address byte will be ignored. 2. i 2 c bus is released while erase proceeds. other dev ices may use the bus until it is time to execute the stop command that caus es the end of the erase operation. 3. host processor must count ra c cycles to determine where the chip is in the erase process, one row per rac cycle. rac pulses low fo r 0.25 millisecond at the end of each erased row. the erase of the "next" row begi ns with the rising edge of rac. see the digital erase rac timing diagram on page 51. 4. when the erase of the last desired row begi ns, the following stop command (command byte = 80 hex) must be issued. this command must be completely given, including receiving the ack from the slave before the rac pi n goes high at the end of the row. - 40 -
isd5116 publ i c at i on rel e ase dat e : oct ober, 2002 - 41 - revi si on 2.1 s slave address w a con a p erase starts on falling edge of slav e acknow ledge p slave address s a d1 a data a data a w note 2 com m a nd by te high addr. by te low addr. by te "n" rac cy cles last erased row 80 p s a a s lave addre ss w n ote n ote com m a nd by te s slave address p a 40h w a
isd5116 suggest ed flow f o r digit a l e r ase i n isd5116 en ter d i g i tal mo d e sen d er ase com m a nd sen d st o p com m a nd c w a it for ra c ex it digi tal mo d e d evic e p o w e rs do w n a u tom a t i ca lly yes coun t ra c fo r n - 1 se n d sto p com m a nd rac to e r as e mult iple ( n ) pages (ro w s ) ye s 6/ 2 0 / 200 2 b o j r e v i s i on b w a it f o r rac yes ra c\ si gna l 1 25 us 1. 25 m s 80 ,c0 80 ,d 1 , nn ,n n 80 ,c0 80 ,4 0 80 ,c0 st o p c o m m a n d m u st b e f i n i sh ed be f o r e ra c\ ris e s 80 = pow e rup o r st op c0 = e n ter di g i ta l mod e d1 = erase di gi tal pag e @ 40 = exi t di gi ta l mo de com m a nds ra c\ ~ 125 us rac\ ~ 125 u s ra c\ ~ 250 us 250 us be fore ra no be fo r e ne x t no no - 42 -
isd5116 7.5.4.2. write digital data write ===== i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xc0) - enter digital mode command waitack waitsclhigh i2cstop i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xc9) - write digital data command waitack waitsclhigh sendbyte(row/256) - high address byte waitack waitsclhigh sendbyte(row%256) - low address byte waitack waitsclhigh repeat until all data is sent { sendbyte(data) - send data byte waitack() waitsclhigh() } publ i c at i on rel e ase dat e : oct ober, 2002 - 43 - revi si on 2.1
isd5116 i2cstop i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0x40) - exit digital mode command waitack waitsclhigh i2cstop p a con w a slave address s p a 40h w a slave address s p a data a data a data ~ ~ ~ ~ low addr. b y te hi g h addr. b y te a data a data a c9h c o mmand b y te w a slave address s - 44 -
isd5116 sug g e s t e d f l o w f o r di g i t a l w r i t e i n i s d5 1 1 6 e n te r d i g i ta l mod e s e n d w r it e co mm an d w / s t ar t a d d r ess e x it d i g i t a l mod e de vi c e po w e rs do w n au t o mat i c a l l y ye s 6/ 24/ 200 2 b o j re v i s i o n n / c 80 , c 0 80 , c 9, n n , n n 80 , 4 0 80 = p o w e r u p or s t op c 0 = e n te r d i g i ta l m o d e c 9 = w r i t e d i gi t a l p a ge@ 40 = e x i t d i gi t a l m o de co m m a nds by t e co u n t e r =2 5 6 ? w a it fo r s c l hi g h sen d da t a by t e ( sen d ne x t by t e ) no publ i c at i on rel e ase dat e : oct ober, 2002 - 45 - revi si on 2.1
isd5116 7.5.4.3. read digital data read ===== i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xc0) - enter digital mode waitack waitsclhigh i2cstop i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xe1) - read digital data command waitack waitsclhigh sendbyte(row/256) - high address byte waitack waitsclhigh() sendbyte(row%256) - low address byte waitack waitsclhigh i2cstart - send repeat start command sendbyte(0x81) - read, slave address zero repeat until all data is read { data = readbyte() - send clocks to read data byte sendack - send nack on the last byte waitsclhigh - the only flow control available - 46 -
isd5116 } i2cstop() i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0x40) - exit digital mode waitack waitsclhigh i2cstop s n p s a slave address w c o mmand b y te e1h a data a data a hi g h addr. b y te low addr. b y te s slave address a w 40h a p s slave address a w con a p r slave address a data ~ ~ ~ ~ a data a data publ i c at i on rel e ase dat e : oct ober, 2002 - 47 - revi si on 2.1
isd5116 s u g g e s t e d flo w fo r d i g i t a l r e a d i n i s d 5116 ent e r di g i t a l mo d e send read co m m a nd w / st art add r ess ex i t d i g i t a l mo d e d evi c e p o w e rs do w n au t o m a t i cal l y yes 6/ 24 / 200 2 b o j re v i s i o n n / c 80, c 0 80, e 1 , nn, nn 80, 40 80 = p o w e r u p or s t op c 0 = e n te r d i g i ta l m o d e e 1 = r ead d i g i t a l p age@ 40 = e x i t d i gi t a l m ode c o mma n d s byt e co unt er =256 ? w a it fo r s c l hi g h re a d dat a byt e ( r ead nex t byt e ) no - 48 -
isd5116 7.6. pin details 7.6.1. digital i/o pins scl (serial clock line) the serial clock line is a bi-directional clock line. it is an open-drain line requiring a pull-up resistor to vcc. it is driven by the "master" chips in a system and controls the timing of the data exchanged over the serial data line. sda (serial data line) the serial data line carries the data between devices on the i 2 c interface. data must be valid on this line when the scl is high. state changes can only take place when the scl is low. this is a bi-directional line requiring a pull-up resistor to vcc. rac (row address clock) rac is an open drain output pin that normally marks the end of a row. at the 8 khz sample frequency, the duration of this period is 256 ms. there ar e 2048 pages of memory in the isd5116 devices. rac stays high for 248 ms and stays low for the remain ing 8 ms before it reaches the end of the page. 1 r o w ra c w a ve fo r m du r i n g 8 k h z o p e r at i o n 25 6 m s e c t ra c 8 mse c t ra c l o the rac pin remains high for 484.4 sec and st ays low for 15.6 sec under the message cueing mode. see the timing parameters table on page 64 for rac timing information at other sample rates. when a record command is first initiat ed, the rac pin remains high for an extra t raclo period, to load sample and hold circuits internal to the device. the rac pin can be used for message management techniques. 1 ro w ra c w a vefo r m du ri n g m essa g e cu e i n g 500 usec t ra c 15. 6 us t ra cl o publ i c at i on rel e ase dat e : oct ober, 2002 - 49 - revi si on 2.1
isd5116 rac wav e form during digital erase 1 . 25 sec . 25 sec sample rate 4.0 khz 5.3 khz 6.4 khz 8.0 khz t rac 2 . 5 s 1 . 8 7 s 1 . 5 6 s 1 . 2 5 s t racl0 0 . 5 s 0 . 3 7 s 0. 3 1 s 0 . 2 5 s / 0 . 1 2 5 t racl1 2 . 0 s 1 . 5 0 s 1 . 2 5 s 1 . 0 0 s int (interrupt) int is an open drain output pin. the isd5116 in terrupt pin goes low and stays low when an overflow (ovf) or end of message (eom) marker is detected. each operation that ends in an eom or ovf generates an interrupt, including the message cuei ng cycles. the interrupt is cleared by a read status instruction that will give a status byte out the sda line. xclk (external clock input) the external clock input for the isd5116 product has an internal pull-down device. normally, the isd5116 is operated at one of four internal rates select ed for its internal oscillator by the sample rate select bits. if greater precision is required, the device can be clo cked through the xclk pin at 4.096 mhz as described in section 7.4.3 on page 31. because the anti-aliasing and smoothing filters tra ck the sample rate select bits, one must, for optimum performance, maintain t he external clock at 4.096 mhz and s e t the sample rate configuration bits to one of the four values to pr operly set the filters to the correct cutoff frequency as described in section 7.4.3 on page 31. the duty cycle on the input clo ck is not critical, as the clock is immediately divided by two internally. if the xclk is not used, this input should be connected to v ssd . external clock input table duration (minutes) sample rate (khz) required clock (khz) fld 1 fld 0 filter knee (khz) 8 . 7 3 8 . 0 4 0 9 6 0 0 3 . 4 1 0 . 9 6 . 4 4 0 9 6 0 1 2 . 7 1 3 . 1 5 . 3 4 0 9 6 1 0 2 . 3 1 7 . 5 4 . 0 4 0 9 6 1 1 1 . 7 - 50 -
isd5116 a0, a1 (address pins) these two pins are normally strapped for the des ired address that the isd5116 will have on the i 2 c serial interface. if there are four of these dev ices on the bus, then each must be strapped differently in order to allow the master device to address t hem individually. the possible addresses range from 80h to 87h, depending upon whether the device is being wr itten to, or read from, by the host. the isd5116 has a 7-bit slave address of which only a0 and a1 are pin programmable. the eighth bit (lsb) is the r/w bit. thus, the address will be 1000 0xy0 or 1000 0xy1. (see the table in sect ion 7.3.1 on page 12.) 7.6.2. analog i/o pins mic+, mic- (microphone input +/-) the microphone input transfers the voice signal to the on-chip agc preamplifier or directly to the ana out mux, depending on the selected path. the direct path to the ana out mux has a gain of 6 db so a 208 mv p-p signal across the differential microphone inputs would give 416 mv p-p across the ana out pins. the agc circuit has a range of 45 db in order to deliver a nominal 694 mv p-p into the storage array from a typical electret microphone output of 2 to 20 mv p-p. the input impedance is typically 10 k. publ i c at i on rel e ase dat e : oct ober, 2002 + internal to the device note: f cutoff = c coup =0.1 f r a=10k ? 6d b mic- mic+ ag c 1.5k ? 1.5k ? 220 f electret microphone w m-54b panasonic 1.5k ? 0.1 10k ? fthru mic in 1 2 rac coup ana out+, ana out- (analog output +/-) this differential output is designed to go to t he microphone input of the telephone chip set. it is de- signed to drive a minimum of 5 k between the ?+? and ??? pins to a nominal voltage level of 694 mv p-p. both pins have dc bias of approximately 1.2 vdc. the ac signal is superimposed upon this analog ground voltage. these pins can be used si ngle-ended, getting only half the voltage. do not ground the unused pin. acap (agc capacitor) - 51 - revi si on 2.1
isd5116 this pin provides the capacitor connection for se tting the parameters of the microphone agc circuit. it should have a 4.7 f capacitor connected to ground. it cannot be left floating. this is because the capacitor is also used in the playback mode for the automute circuit. this circuit reduces the amount of noise present in the output during quiet pauses. tying this pin to ground gives maximum gain; tying it to v cca gives minimum gain for the agc amplifier but cancels the automute function. sp +, sp- (speaker +/-) this is the speaker differential output circuit. it is designed to dr ive an 8 speaker connected across the speaker pins up to a maximum of 23.5 mw rm s power. this stage has two selectable gains, 1.32 and 1.6, which can be chosen through the configurat ion registers. these pins are biased to ap- proximately 1.2 vdc and, if us ed single-ended, must be capacitivel y coupled to their load. do not ground the unused pin. aux out (auxiliary output) the aux out is an additional audio output pin to be used, for example, to drive the speaker circuit in a ?car kit.? it drives a minimum load of 5 k and up to a maximum of 1 v p-p. the ac signal is superimposed on approximately 1.2 vdc bias and must be capacitively coupled to the load. s p e ake r sp + sp ? au x o u t ca r k i t (1 v p - p m a x ) an a i n am p ou t p u t mu x fi l t o su m 2 2 vo l (o p s 1 , o p s 0 ) 2 (o p a 1 , o p a 0 ) in s 0 15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 0 ai g 1 ai g 0 a i p d a x g 1 a x g 0 a x p d ao s 2 a o s 1 ao s 0 ao p d o p s1 o p s0 o p a 1 o p a 0 vl pd cf g 0 ops1 opa0 spkr drive aux out 0 0 p o we r d o wn p o we r d o wn 0 1 3.6 v p.p @150 ? p o we r d o wn 1 0 23.5 mw att @ 8 ? p o we r d o wn 1 1 pow e r dow n 1 v p.p max @ 5k ? o p s 1 o p s 0 s o u r c e 0 0 v o l 0 1 a n a i n 1 0 f i lt o 1 1 s u m 2 - 52 -
isd5116 ana in (analog input) the ana in pin is the analog input from the telephone chip set. it can be switched (by the i 2 c interface) to the speaker output, the array input or to various other paths. this pin is designed to accept a nominal 1.11 v p-p when at its minimu m gain (6 db) setting. there is additional gain available, if required, in 3 db steps, up to 15 db. the gain settings are controlled from the i 2 c interface. ana in input modes publ i c at i on rel e ase dat e : oct ober, 2002 internal to the d ev ice c coup = 0.1 f r b an a i n input a n a i n input a m plifier note: f c u tto f f 2xr a c ccup r a 1 gain setting resistor ration (rb/ra) g a i n g a i n 2 (db) 00 63.9 / 102 0.625 -4.1 01 77.9 / 88.1 0.88 -1.1 10 92.3 / 73.8 1.25 1.9 11 106 / 60 1.77 4.9 ana in am plifier gain settings cfg0 setting (1) 0 t l p i n p u t v p-p (3) a i g 1 a i g 0 gain (2) a r r a y in/out v p-p speaker out v p-p (4) 6 db 1.110 0 0 0.625 0.694 2.22 9 db 0.785 0 1 0.883 0.694 2.22 12 db 0.555 1 0 1.250 0.694 2.22 15 db 0.393 1 1 1.767 0.694 2.22 1. gain from ana in to sp+/- 2. gain from ana in to array in 3. 0t lp input is the refe rence t r ansmission level point that is used for testing. t h is level is typically 3 db below clipping 4. speaker out gain set to 1.6 (high). (differential) - 53 - revi si on 2.1
isd5116 aux in (auxiliary input) the aux in is an additional audio input to the is d5116, such as from the microphone circuit in a mobile phone ?car kit.? this input has a nominal 694 mv p-p level at its minimum gain setting (0 db). see the aux in amplifier gain settings table on page 55. additional gain is available in 3 db steps (controlled by the i 2 c interface) up to 9 db. aux in input modes an a i n input a n a i n input a m plifier note: f c u tto f f 2xr a c ccup 1 r a r b c coup = 0.1 f internal to the d ev ice gain setting resist or rat i o (rb/ra) g a i n g a i n (2) (db) 00 40.1 / 40.1 1.0 0 01 47.0 / 33.2 1.414 3 10 53.5 / 26.7 2.0 6 11 59.2 / 21 2.82 9 aux in amplifier gain settings cfg0 setting (1) 0 t l p i n p u t v p-p (3) a i g 1 a i g 0 gain (2) a r r a y in/out v p-p speaker out v p-p (4) 0 db 0.694 0 0 1.00 0.694 0.694 3 db 0.491 0 1 1.41 0.694 0.694 6 db 0.347 1 0 2.00 0.694 0.694 9 db 0.245 1 1 2.82 0.694 0.694 1. gain from aux in to ana out 2. gain from aux in to array in 3. 0t lp input is the refer ence t r ansmission level point that is used for testing. t h is level is typically 3 db below clipping 4. differential - 54 -
isd5116 7.6.3. pow e r and ground pins v cca , v ccd (voltage inputs) to minimize noise, the analog and digital circuits in the isd5116 device use separate power busses. these +3 v busses lead to separate pins. tie the v ccd pins together as close as possible and decouple both supplies as near to the package as possible. v ssa , v ssd (ground inputs) the isd5116 series utilizes separate analog and digital ground busses. the analog ground (v ssa ) pins should be tied together as close to t he package as possible and connected through a low- impedance path to power supply ground. the digital ground (v ssd ) pin should be connected through a separate low impedance path to power supply gr ound. these ground paths should be large enough to ensure that the impedance between the v ssa pins and the v ssd pin is less than 3. the backside of the die is connected to v ssd through the substrate resistance. in a chip-on-board design, the die attach area must be connected to v ssd . nc (not connect) these pins should not be connected to the board at any time. connection of these pins to any signal, ground or v cc, may result in incorrect device behav ior or cause damage to the device. 7.6.4. sample pc lay out the soic package is illustrated from the top. pc board traces and the three chip capacitors are on the bottom side of the board. o o o o o o o o o o o o o o o o o o o o o o o o o o o o v c c d xc l k a n a l og g r oun d 1 v ss a to v cc a v s s d (d igita l g r ound) no te 1: v ss d t r ac es s h ou ld be k e p t s e pa r a ted ba c k t o the v ss s u pply f eed point. . no te 2: v ccd t r aces s h o u ld be k e p t s e p a r a t e b a c k to th e v cc sup p l y f e ed point. no t e 3: t h e digit a l and a n a l og gr oun ds t i e toge t h e r at t h e po we r s u pply . t h e v cca an d v cc d s u pplies will als o n eed f i lter c apa c i tor s per g ood en gin eer ing pr ac t i c e ( t y p . 50 t o 10 0 u f ) . c1 c2 c3 n o te 1 not e 2 c 1 = c 2= c3 = 0 . 1 uf c h ip ca pa c i t o r s n o te 3 no te 3 publ i c at i on rel e ase dat e : oct ober, 2002 - 55 - revi si on 2.1
isd5116 8. timing diagrams 8.1. i 2 c timing diagram stop start f t su - s to t t su - d at r t f t hi gh t t sc l k t low sda scl - 56 -
isd5116 i 2 c interface timing standard-mode fast-mode pa ra meter symbol min. ma x. min. ma x. unit scl clock frequency f scl 0 1 0 0 0 4 0 0 k h z hold time (repeated) st art condition. after this period, the first clock pulse is generated t hd-st a 4 . 0 - 0 . 6 - s low period of the scl clock t low 4 . 7 - 1 . 3 - s high period of the scl clock t high 4 . 0 - 0 . 6 - s set-up time for a repeated st art condition t su-st a 4 . 7 - 0 . 6 - s data set-up time t su-dat 2 5 0 - 100 (1 ) - n s rise time of both sda and scl signals t r - 1000 20 + 0.1c b (2 ) 3 0 0 n s f a ll time of both sda and scl signals t f - 300 20 + 0.1c b (2 ) 3 0 0 n s set-up time for st op condition t su-st o 4 . 0 - 0 . 6 - s bus-free time betw een a st op and st art condition t buf 4 . 7 - 1 . 3 - s capacitive load for each bus line c b - 4 0 0 - 4 0 0 pf noise margin at the low level for each connected device (including hy steresis) v nl 0.1 v dd - 0 . 1 v dd - v noise margin at the high level for each connected device (including hy steresis) v nh 0.2 v dd - 0 . 2 v dd - v 1. a f a st-mode i 2 c-interface device can be used in a standard-mode i 2 c-interface system , but the requirement t su ;d at > 250 ns must then be met. this w ill automatic ally be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line; t r m a x + t su ;d at = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c -interface specification) before the scl line is released. 2. c b = total capacitance of one bus line in pf . if mix ed w i th hs mode devices, faster fall-times are allow ed. publ i c at i on rel e ase dat e : oct ober, 2002 - 57 - revi si on 2.1
isd5116 8.2. playback and stop cycle sda scl ana in ana out data clock pulses stop play at addr t stop t start stop - 58 -
isd5116 8.3. example of power up command (first 12 bits) publ i c at i on rel e ase dat e : oct ober, 2002 - 59 - revi si on 2.1
isd5116 9. absolute maximum ratings absolute maximum ratings (packaged parts) (1) condition value junction temperature 150 0 c storage temperature range -65 0 c to + 150 0 c voltage applied to any pin (v ss - 0.3v) to (v cc + 0.3v) voltage applied to any pin (input current limited to +/-20 ma) (v ss ? 1.0v) to (v cc + 1.0v) lead temperature (soldering ? 10 seconds) 300 0 c v cc - v ss -0.3v to + 5 .5v 1. stresses above those listed may cause permanent damage to the devic e. exposure to the absolute maximum ratings may affect device reliability. func tional operation is not imp lied at these conditions. absolute maximum ratings (die) (1) condition value junction temperature 150 0 c storage temperature range -65 0 c to + 150 0 c voltage applied to any pad (v ss - 0.3v) to (v cc + 0.3v) v cc - v ss -0.3v to + 5 .5v 1. stresses above those listed may c ause permanent damage to the devic e. exposure to the absolute maximum ratings may affect device reliability. func tional operation is not imp lied at these conditions. - 60 -
isd5116 operating conditions (packaged parts) condition value commercial operating temperature range (1) 0 0 c to + 7 0 0 c extended operating temperature (1) - 2 0 0 c to + 7 0 0 c industrial operating temperature (1) - 4 0 0 c to + 8 5 0 c supply voltage (v cc ) (2) + 2 .7v to + 3 .3v ground voltage (v ss ) (3) 0 v 1 . case temperature 2. v cc = v cca = v ccd 3. v ss = v ssa = v ssd operating conditions (die) condition value die operating temperature range (1) 0 0 c to + 5 0 0 c supply voltage (v cc ) (2) + 2 .7v to + 3 .3v ground voltage (v ss ) (3) 0 v 1. case temperature 2. v cc = v cca = v ccd 3. v ss = v ssa = v ssd publ i c at i on rel e ase dat e : oct ober, 2002 - 61 - revi si on 2.1
isd5116 10. electrical characteristics 10.1. general parameters sy mbol parameters min (2) ty p (1) max (2) unit s conditions v il input low voltage v cc x 0.2 v v ih input high voltage v cc x 0.8 v v ol scl, sda output low voltage 0 . 4 v i ol = 3 a v il2v input low voltage for 2v interface 0 . 4 v apply o n l y t o scl, sda v ih2v input high voltage for 2v interface 1 . 6 v apply only t o scl, sda v ol1 rac, int output low voltage 0.4 v i ol = 1 ma v oh output high voltage v cc ? 0.4 v i ol = -10 a i cc v cc current (operating) - playback - record - feedthrough 15 30 12 25 40 15 ma ma ma no load (3) no load (3) no load (3) i sb v cc current (standby) 1 10 a (3) il input leakage current +/-1 a i 1. t y pical values: t a = 25c and vcc = 3.0 v. 2. all min/max limits are guaranteed by w i nbond via electrical testing or characteriz a tion. not all specifications are 100 percent tested. 3. v cca and v ccd summed together. - 62 -
isd5116 10.2. timing parameters sy mbol parameters min (2) ty p (1) max (2) units conditions f s s a m p l i n g f r e q u e n c y 8 . 0 6.4 5.3 4.0 khz khz khz khz (5) (5) (5) (5) f cf f i l t e r k n e e 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 3.4 2.7 2.3 1.7 khz khz khz khz knee point (3)(7) knee point (3)(7) knee point (3)(7) knee point (3)(7) t rec r e c o r d d u r a t i o n 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 8.73 10.9 13.1 17.5 min min min min (6) (6) (6) (6) t play p l a y b a c k d u r a t i o n 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 8.73 10.9 13.1 17.5 min min min min (6) (6) (6) (6) t pud p o w e r - u p delay 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 1 1 1 1 msec msec msec msec t st op or pause stop or pause record or play 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 32 40 48 64 msec msec msec msec t rac rac clock period 8.0 khz (sample rate) 256 msec (9) publ i c at i on rel e ase dat e : oct ober, 2002 - 63 - revi si on 2.1
isd5116 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 320 384 512 msec msec msec (9) (9) (9) t raclo rac clock low time 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 8 10 12.1 16 msec msec msec msec t racm rac clock period in message cueing mode 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 500 625 750 1000 sec sec sec sec tracml rac clock low time in message cueing mode 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 15.6 19.5 23.4 31.2 sec sec sec sec t race rac clock period in erase mode 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 1.25 1.56 1.87 2.50 sec sec sec sec thd total harmonic distortion ana in to array, array to spkr 1 1 2 2 % % @1 khz at 0tlp, sample rate = 5.3 khz - 64 -
isd5116 10.3. analog parameters microphone input (14) sy mbol parameters min (2) ty p (1)(14) max (2) units conditions v mi c+/ - mic + / - input voltage 3 0 0 m v peak-to-peak (4 )(8 ) v mi c (0 t l p ) mic + / - input reference transmission level point (0t l p) 2 0 8 m v peak-to-peak (4 )(1 0 ) a mi c gain from mic + / - input to ana out 5 . 5 6 . 0 6 . 5 d b 1 khz at v mi c (0 t l p ) (4 ) a mi c (g t ) mic + / - gain t r a c k i n g + / - 0 . 1 d b 1 khz, + 3 to ?40 db 0t lp input r mi c microphone input resistance 10 k ? ana in (14) s ymbol parameters min (2) ty p (1)(14) max (2) units conditions v an a in ana in input voltage 1. 6 v peak-to-peak ( 6 d b gain setting) v an a in ( 0 t l p) ana in (0t l p) input voltage 1 . 1 v p e a k - t o - p e a k ( 6 d b gain setting) ( 10) a an a in ( s p) gain from ana in to sp+/- +6 to +15 db 4 steps of 3 db a an a in ( a u x ou t ) gain from ana in to aux out -4 to + 5 db 4 steps of 3 db a an a in ( g a) ana in gain accuracy - 0 . 5 + 0 . 5 d b ( 1 1 ) a an a in ( g t ) ana in gain t r acking + / -0.1 db 1000 hz, + 3 to ?45 db 0t lp input, 6 db setting r an a in ana in input resistance (6 db to + 15 db) 10 to 100 k ? publ i c at i on rel e ase dat e : oct ober, 2002 - 65 - revi si on 2.1
isd5116 aux in (14) s ymbol parameters min (2) ty p (1)(14) max (2) units conditions v au x in aux in input voltage 1. 0 v peak-to-peak ( 0 d b gain setting) v au x in ( 0 t l p) aux in (0t l p) input voltage 6 9 4 . 2 m v p e a k - t o - p e a k ( 0 d b gain setting) a aux in ( a na out ) gain from aux in to ana out 0 to + 9 db 4 steps of 3 db a au x in ( g a) aux in gain accuracy -0.5 +0.5 db (11) a aux in ( g t ) aux in gain t r acking + / -0.1 db 1000 hz, + 3 to ?45 db 0t lp input, 0 db setting r au x in aux in input resistance 10 to 100 k ? depending on aux in gain speaker outputs (14) s ymbol parameters min (2) ty p (1)(14) max (2) units conditions v sph g sp+ /- output voltage (high gain setting) 3 . 6 v p e a k - t o - p e a k , differential load = 150 ? , opa1, opa0 = 01 r splg sp+ /- output load imp. (low gain) 8 ? opa1, opa0 = 10 r sph g sp+ /- output load imp. (high gain) 7 0 1 5 0 ? opa1, opa0 = 01 c sp sp+ /- output load cap. 100 pf v spag sp+ /- output bias voltage (analog ground) 1 . 2 v d c v s p dco speaker output dc offset +/-100 mv dc with ana in to speaker, ana in ac coupled to v ssa icn an a in /( sp+ /- ) ana in to sp+/- idle channel noise - 6 5 d b speaker l o a d = 150 ? ( 12) ( 13) c r t ( sp+ /- ) / an a out sp+/- to ana out cross ta l k -65 db 1 khz 0t lp input to ana in, w i th mic+ /- and aux in ac coupled to v ss , and measured at ana out feed through mode ( 12) p s r r pow e r supply rejection ratio -55 db measured w i th a 1 khz, 100 mv p-p ii t t - 66 -
isd5116 sine w a ve input at v cc and v cc pins f r f r equency response (300- 3400 hz) + 0.5 db w i th 0t lp input to ana in, 6 db setting ( 12) guaranteed by design p out l g pow e r output (low gain setting) 2 3 . 5 mw rms differential load at 8 ? sinad sinad ana in to sp+ /- 62.5 db 0t lp ana in input minimum gain, 150 ? load ( 12) ( 13) ana out (14) s ymbol parameters min (2) ty pe (1)(14) max (2) units conditions sinad sinad, mic in to ana out 62.5 db load = 5k ? ( 12) ( 13) sinad sinad, aux in to ana out (0 to 9 db) 6 2 . 5 d b load = 5k ? ( 12) ( 13) ico nic/a n a out idle channel noise ? microphone - 6 5 d b load = 5k ? ( 12) ( 13) icn aux in/ana out idle channel noise ? aux in (0 to 9 db) - 6 5 d b load = 5k ? ( 12) ( 13) psrr (a na out ) p o w e r supply r e j e c t i o n ratio -55 db measured w i th a 1 khz, 100 mv p- p sine w a ve to v cca , v ccd pins v bias ana out + and ana out - 1.2 vdc inputs ac coupled to v ssa v offset ana out + to ana out - + / - 100 mv dc inputs ac coupled to v ssa r l minimum load impedance 5 k ? differential load f r f r equency r e s p o n s e (300- 3400 hz) + 0.5 d b 0t lp input t o mic+/- in feedthrough mode. 0t lp input to aux in in feedthrough mode ( 12) c r t ana o u t / ( s p+ / - ) ana out to sp+/- cross ta l k -65 db 1 khz 0t lp output from ana out , w i th ana in ac coupled to v ssa , and measured at publ i c at i on rel e ase dat e : oct ober, 2002 - 67 - revi si on 2.1
isd5116 sp+/- ( 12) c r t an a ou t / au x out ana out to aux out cross t a lk -65 db 1 khz 0t lp output from ana out , w i th ana in ac coupled to v ssa , and measured at aux out ( 12) aux out (14) s ymbol parameters min (2) ty p (1(14)) max (2) units conditions v au x ou t aux out ? max i mum output sw ing 1 . 0 v 5k ? load r l minimum load impedance 5 k ? c l maximum load capacitance 100 pf v bias a u x out 1 . 2 v d c s i n a d sinad ? ana in to aux out 62.5 db 0t lp ana in input, minimum gain, 5k load ( 12) ( 13) icn (a ux out ) idle channel noise ? ana in to aux out - 6 5 d b load= 5k ? ( 12) ( 13) c r t au x ou t / an a out aux out to ana out cross t a lk -65 db 1 khz 0t lp input to ana in, w i th mic + / - and aux in ac coupled to v ssa , measured at sp+ /-, load = 5k ? . referenced to nominal 0t lp @ output volume control (14) s ymbol parameters min (2) ty p (1)(14) max (2) units conditions a out output gain -28 to 0 db 8 steps of 4 db, referenced to output a b s o l u t e g a i n - 0 . 5 + 0 . 5 d b ana in 1.0 khz 0t lp, 6 db gain setting measured differentially at sp+/- - 68 -
isd5116 conditions 1. t y pical values: t a = 25c and vcc = 3.0v. 2. all min/max limits ar e guaranteed by w i nbond via electrical test ing or characteriz a tion. not all specifications are 100 percent tested. 3. low -frequency cut off depends upon the value of external capacitors (see pin descriptions). 4. differential input mode. nominal diffe rential input is 208 mv p-p. (0t l p) 5. sampling frequency can vary as much as ?6/+ 4 percent over the industr ial temperature and voltage ranges. for greater stability, an external cl ock can be utiliz ed (see pin descriptions). 6. playback and record duration can vary as much as ?6/+ 4 percent over t he industrial temperature and voltage ranges. for greater stab ility, an external clock can be utiliz ed (see pin descriptions). 7. f ilter specification applie s to the low pass filter. 8. f o r optimal signal quality, th is maximum limit is recommended. 9. w hen a record command is sent, t ra c = t ra c + t ra cl o on the first page addressed. 10. t he maximum signal level at any input is defined as 3.17 db hi gher than the reference transmission level point. (0t l p) t h is is the point w here signal clipping may begin. 11. measured at 0t lp point for each gain setting. see the ana in table and aux in table on pages 53 and 55 respectively. 12. 0t lp is the reference test le vel through inputs and outputs. see the ana in table and aux in table on pages 53 and 54 respectively. 13. referenced to 0t lp input at 1 khz , measured over 300 to 3,400 hz bandw idth. 14. f o r d i e, o n l y typ i cal valu es are ap p licab le. 10.4. characteristics of the i 2 c serial interface the i 2 c interface is for bi-directional, two-line comm unication between different ics or modules. the two lines are a serial data line (sda) and a serial cl ock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the interface bus is not busy. bit transfer one data bit is transferred during each clock pulse . the data on the sda line must remain stable during the high period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal. publ i c at i on rel e ase dat e : oct ober, 2002 - 69 - revi si on 2.1
isd5116 - 70 - start and stop conditions both data and clock lines remain high when the inte rface bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condi tion (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). sy stem configuration a device generating a message is a ?transmitter?; a dev ice receiving a message is the ?receiver?. th sda scl s p sta r t condi ti on stop condi ti on definition of sta r t and stop conditions sda scl sda scl data line stable; data v a li d changed of data a ll o w ed bit transfer on the i 2 c -bus sy stem configuration a device generating a message is a ?transmitter?; a dev ice receiving a message is the ?receiver?. the device that controls the message i sthe ?master? and t he devices that are contro lled by the master are the ?slaves?.
isd5116 publication release date: october, 2002 - 71 - revision 2.1 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the interface bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. in addition, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull down the sda line during the acknowledge clock pulse so that the sda line is stable low during the high period of the acknowledge related clock pulse (set- up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the da ta line high to enable the master to generate a stop condition. example of an i 2 c-bus confi g uration usin g two microcontrollers sda scl micro- controller lsd driver static ram or eeprom gate array isd 5116 8 data output by transmitter data output by receiver scl from master not acknowledge acknowledge dock pulse for acknowledgement s start condition acknowledge on the i 2 c-bus 1 2 9
isd5116 10.5. i 2 c protocol since the i2c protocol allows multiple devices on the bus, each device must have an address. this address is known as a ?slave address?. a slave addr ess consists of 7 bits, followed by a single bit that indicates the direction of data flow. this single bi t is 1 for a write cycle, which indicates the data is being sent from the current bus ma ster to the device being addressed. this single bit is a 0 for a read cycle, which indicates that the data is being sent from the device being addressed to the current bus master. for example, the valid slave addresse s for the isd5116 device, for both write and read cycles, are shown in section 7.3.1 on page 12 of this datasheet. before any data is transmitted on the i2c interface, the current bus master mu st address the slave it wishes to transfer data to or from. the sl ave address is always sent out as the 1 st byte following the start condition sequence. an example of a mast er transmitting an address to a isd5116 slave is shown below. in this case, the master is writing dat a to the slave and the r/w bi t is ?0?, i.e. a write cycle. all the bits transferred are from the master to the slave, except fo r the indicated acknowledge bits. the following example details the transfer explained in section 7.3.1 - 2 - 3 on pages 12-19 of this datasheet . master transmits to slav e receiv e r (write) mode s w a aaa p s l a v e a d d r es s c om m a nd by t e hig h a d dr . by t e l o w a d d r . b y t e acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w start bit stop bit a common procedure in the isd5116 is the reading of the status bytes. the read status condition in the isd5116 is triggered when the master addresse s the chip with its proper slave address, immediately followed by the r/w bit set to a ?0? and without the command byte being sent. this is an example of the master sending to the slave, imm ediately followed by the slave sending data back to the master. the ?n? not-acknowledge cycle from the ma ster ends the transfer of data from the slave. the following example details the transfer explained in section 7.3.1 on page 12 of this datasheet. - 72 -
isd5116 master reads from slav e immediately after first by te (read mode) r/w fr om ma s t e r st art bi t fr o m ma s t e r stop b i t fr om ma s t e r ack now ledge m ent from sla v e a ckn owle dgem en t from m a s t e r not-a ck nowle dged f r om m a ster ac kno w ledg em ent fro m m a ster fr o m m a s t er from s l ave fr o m s l av e fr om slav e sr a a a n p l o w a d dr by t e sla v e a d d r e s s s t a t u s w o r d hi g h a d d r . b y t e another common operation in the isd5116 is the reading of digital data from the chip?s memory array at a specific address. this requires the i 2 c interface master to first send an address to the isd5116 slave device, and then receive data from the slave in a single i 2 c operation. to accomplish this, the data direction r/w bit must be changed in the middl e of the command. the following example shows the master sending the slave addr ess, then sending a command byte and 2 bytes of address data to the isd5116, and then immediately changing the dat a direction and reading some number of bytes from the chip?s digital array. an unlimited number of bytes can be read in this operation. the ?n? not- acknowledge cycle from the master forces the end of the data transfer from the slave. the following example details the transfer explained in section 7.5.4 on page 46 of this datasheet. master reads from the slav e after setting data a ddress in slav e (write data address, read data) s w aa aa s l a v e a d d r e s s com m a nd byt e hi gh a ddr . by t e lo w a d d r . b y t e acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w from master start bit from master sr a a a n p 8 b i ts of d a ta s l a v e a ddre s s 8 bi t s of da t a 8 bi t s o f da t a r/w from master start bit from master stop bit from master acknowledgement from slave acknowledgement from master not-acknowled from master acknowledgement from master from master from slave from slave from slave publ i c at i on rel e ase dat e : oct ober, 2002 - 73 - revi si on 2.1
isd5116 11. typical application circuit < to be determ ined > please see w e b site www. wi nbond-usa.com for updates. - 74 -
isd5116 publ i c at i on rel e ase dat e : oct ober, 2002 - 75 - revi si on 2.1 12. package specification 12.1. plastic thin small outline package (tsop) ty pe e dimensions 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 2 2 3 3 4 4 15 15 16 16 17 17 18 18 19 19 2 0 20 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 a a b b g g f f c c d e e h h j j i 21 1 mi n n o m ma x m i n n o m m a x a 0.5 2 0 0 .528 0.53 5 1 3.20 13 . 4 0 1 3.60 b 0.4 6 1 0 .465 0.46 9 1 1.70 11 . 8 0 1 1.90 c 0.3 1 1 0 .315 0.31 9 7 .90 8 . 0 0 8 .10 d 0.0 0 2 0 .00 6 0.05 0.15 e 0.0 0 7 0 .009 0.01 1 0 .17 0 . 2 2 0 .27 f 0.02 17 0 . 5 5 g 0.0 3 7 0 .039 0.04 1 0 .95 1 . 0 0 1 .05 h 0 0 3 0 6 0 0 0 3 0 6 0 i 0.0 2 0 0 .022 0.02 8 0 .50 0 . 5 5 0 .70 j 0.0 0 4 0 .00 8 0.10 0.21 not e : l ead c o pl an ar i t y t o b e w i th i n 0.00 4 i n c h e s . i n c h es m i lli m e t e rs pl a s t i c t h i n sm a l l o u t l i n e pa c k a ge ( t so p ) t y pe e d i m e ns i o n s
isd5116 12.2. plastic small outline integr ated circuit (soic) dimensions 28 27 26 25 24 23 22 21 20 19 18 1 7 16 15 1 2 3 45 6 7 8 91 0 11 12 1 3 14 a d e f b g c h mi n n o m ma x m i n n o m m a x a 0. 701 0. 706 0. 711 17. 81 17. 93 18. 06 b 0. 097 0. 101 0. 104 2. 46 2. 56 2. 64 c 0. 292 0. 296 0. 299 7. 42 7. 52 7. 59 d 0. 005 0. 009 0. 0115 0. 127 0. 22 0. 29 e 0. 014 0. 016 0. 019 0. 35 0. 41 0. 48 f 0. 050 1. 27 g 0. 400 0. 406 0. 410 10. 16 10. 31 10. 41 h 0. 024 0. 032 0. 040 0. 61 0. 81 1. 02 no t e : lead c oplanar it y t o be w i t h in 0. 004 inc hes . p l a s t ic s m a ll out line int e gr a t e d c i r c uit ( s oic ) d i m e ns ions i nche s m i l l i m e t e rs - 76 -
isd5116 12.3. plastic dual inline package (pdip) dimensions plastic dual inline package (pdip) (p) dimensions inches millimeters min nom max min nom max a 1 . 4 4 5 1 . 4 5 0 1 . 4 5 5 3 6 . 7 0 3 6 . 8 3 3 6 . 9 6 b 1 0 . 1 5 0 3 . 8 1 b 2 0 . 0 6 5 0 . 0 7 0 0 . 0 7 5 1 . 6 5 1 . 7 8 1 . 9 1 c 1 0 . 6 0 0 0 . 6 2 5 1 5 . 2 4 1 5 . 8 8 c 2 0 . 5 3 0 0 . 5 4 0 0 . 5 5 0 1 3 . 4 6 1 3 . 7 2 1 3 . 9 7 d 0 . 1 9 4 . 8 3 d 1 0 . 0 1 5 0 . 3 8 e 0 . 1 2 5 0 . 1 3 5 3 . 1 8 3 . 4 3 f 0 . 0 1 5 0 . 0 1 8 0 . 0 2 2 0 . 3 8 0 . 4 6 0 . 5 6 g 0 . 0 5 5 0 . 0 6 0 0 . 0 6 5 1 . 4 0 1 . 5 2 1 . 6 5 h 0 . 1 0 0 2 . 5 4 j 0 . 0 0 8 0 . 0 1 0 0 . 0 1 2 0 . 2 0 0 . 2 5 0 . 3 0 s 0 . 0 7 0 0 . 0 7 5 0 . 0 8 0 1 . 7 8 1 . 9 1 2 . 0 3 0 0 1 5 0 1 5 publ i c at i on rel e ase dat e : oct ober, 2002 - 77 - revi si on 2.1
isd5116 12.4 die bonding phy s ical lay out isd5116 device pin/pad locations with respect to die center in micron (m) pin pin name x axis y axis v ssa v ss analog ground 1879.45 3848.65 rac row address clock 1536.20 3848.65 int i n t e r r u p t 7 8 7 . 4 0 3 8 4 8 . 6 5 xclk external clock input 475.60 3848.65 v ccd v cc digital supply voltage 288.60 3848.65 v ccd v cc digital supply voltage 73.20 3848.65 scl serial clock line -201.40 3848.65 a 1 a d d r e s s 1 - 5 6 0 . 9 0 3 8 4 8 . 6 5 sda serial data address -818.20 3848.65 a 0 a d d r e s s 0 - 1 3 6 9 . 4 0 3 8 4 8 . 6 5 v ssd v ss digital ground -1671.30 3848.65 v ssd v ss digital ground -1842.90 3848.65 v ssa ? ? ? -1948.00 -3841.60 mic+ n o n - i n v e r t i n g mi crophone input - 1 7 4 2 . 2 0 - 3 8 4 1 . 6 0 m i c - i n v e r t i n g micr ophone input - 1 5 0 9 . 7 0 - 3 8 4 1 . 6 0 ana out + non-inverting a nalog output -1248.00 -3841.60 ana out - inverting anal og output -913.80 -3841.60 a c a p a g c / a u t o m u t e c a p - 6 2 6 . 5 0 - 3 8 4 1 . 6 0 s p - s p e a k e r negat i v e - 1 3 0 . 7 0 - 3 8 4 1 . 6 0 v ssa v ss analog ground 202.90 -3841.60 sp+ s p e a k e r p o s i t i v e 6 2 6 . 5 0 - 3 8 4 1 . 6 0 v cca v cc analog supply voltage 960.10 -3841.60 ana in analog input 1257.40 -3841.60 aux in auxiliary input 1523.00 -3841.60 aux out auxiliary output 1767.20 -3841.60 - 78 -
isd5116 isd 5116 series bonding physical layout (1) (unpackaged die) isd 5116 ser i es d i e d i mensions x : 4125 um y : 8030 um d i e t h ickness (3) 292.1 um + 12.7 um pad o pening (min) 90 x 90 microns 3.5 x 3.5 mils v ssd isd 5116 v ssa v ssa mi c + a ux i n a na i n a na out + mi c ? v ssa (2) a na out ? a ca p a ux out sp? v cca (2) sp+ ra c v ssd a 0 sd a a 1 sc l v ccd v ccd in t xc l k notes 1. the backside of die is internally connected to vss. it must not be connected to any other potential or damage may occur. 2. double bond recommended. 3. this figure reflects the current die thick ness. please contact winbond as this thickness may change in the future. publ i c at i on rel e ase dat e : oct ober, 2002 - 79 - revi si on 2.1
isd5116 13. ordering information winbond part number description i5116 -_ _ product family i s d5116 pr oduct ( 8 - to 16- m i nute dur ations) special temperature field: blank = commercial packaged (0c to +70c) or commercial die (0c to +50c) d = extended (?20c to +70c) i = industrial (?40c to +85c) package ty pe: e = 28-lead 8x13.4mm plastic thin small outline package (tsop) ty pe 1 s = 28-lead 0.300-inch plastic small outline package (soic) x = die p = 28-lead 0.600-inch plastic dual inline package (pdip) when ordering isd5116 series devices, please refer to the following valid part numbers. part number i5116e i5116ed i5116ei i5116s i5116si i5116x i5116p chip scale package is available upon customer?s request. for the latest product information, access winbond?s w o rldw ide w e bsite at h t t p : / / www. wi nbond-usa.com - 80 -
isd5116 14. version history v e r s i o n d a t e p a g e d e s c r i p t i o n 2.0 08/28/02 overal datasheet. cl arifiying digital mode section 2.1 10/16/02 7 corrected soic/pdip labels and drawing he a dqua r t e r s winbond ele c t r onic s cor por a t i on a m e r ic a winbond ele c t r onic s ( s ha ngha i) lt d. no. 4, creation rd. iii 2727 north first street, san jose, 27f, 299 y an an w . rd. shanghai, science-based industrial park, ca 95134, u.s.a. 200336 china hsinchu, t a iw an t e l: 1-408-9436666 t e l: 86-21-62365999 t e l: 886-3-5770066 fax: 1-408-5441798 fax: 86-21-62356998 fax: 886-3-5665577 http:// www.wi nbond-usa.com/ http:// www.wi nbond.com .tw/ t a ipe i of f i c e winbond ele c t r onic s cor por a t ion j a p a n winbond ele c t r onic s ( h .k.) lt d. 9f, no. 480, pueiguang rd. 7f daini-ueno bldg, 3-7-18 unit 9-15, 22f, m illennium city , neihu district, shiny o kohama kohoku-ku, no. 378 kw un t ong rd., t a ipei, 114, t a iw an y o kohama, 222-0033 kow l oon, hong kong t e l: 886-2-81777168 t e l: 81-45-4781881 t e l: 852-27513100 fax: 886-2-87153579 fax: 81-45-4781800 fax: 852-27552064 pl ease note that al l data and speci f i c ati o ns ar e subj ect to chang e w i thout noti ce. al l the tr ademar ks of pr oducts and compani e s menti o ned i n thi s datasheet bel o ng to thei r r e specti v e ow ner s. publ i c at i on rel e ase dat e : oct ober, 2002 - 81 - revi si on 2.1

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