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slus503b ? march 2002 ? revised august 2002 1 www.ti.com features enables hot swap in compactpci high availability systems programmable current slew rate power supply sequencing sense resistors set peak current (imax) overcurrent circuit breaker at 2 imax precharge output healthy# signal of board power good bd_sel# signal for peripheral enable on-chip charge pump low sleep mode current undervoltage lockout (uvlo) minimal external parts count 24-pin tssop package description the TPS2345 compactpci hot swap power manager (hspm) provides highly-integrated supply control of three positive (3.3-v, 5-v, and 12-v) and one negative (?12-v) supply rails with a minimum number of external components. a linear current amplifier (lca) in each of the four device channels provides closed-loop control of load current during insertion and extraction events. this allows the designer to configure the plug-in card?s maximum inrush slew rate and magnitude according to the requirements of the compactpci hot swap specification picmg 2.1. compactpci plug-in module back-end power planes r7 1.2 k ? r6 10 k ? c5 0.33 f c4 0.1 f c3 0.1 f c2 0.1 f c1 0.1 f r2 3 m ? c6 0.1 f r3 2.5 m ? r4 0.25 ? r5 10 k ? r1 0.025 ? r8 10 ? compactpci backplane early vio 12v 5v gnd 3.3 v ?12 v 12 v 5 v 3.3 v ?12 v pci device ad[00] ad[xx:01] cs1 vin1 bd_sel# healthy# rgnd vin4 cs4 gate1 vs1 vin2 prechg cs2 gate2 vs2 cpump cpgnd vs3 gate3 vin3 iramp cs3 vs4 gate4 TPS2345 agnd ad[00] ad[xx:01] q1 q2 q3 q4 example signal line d2 d1 maz3140 r p compactpci bus udg?01128 typical application bd_sel# healthy# maz3140 picmg , compactpci , and the picmg and compactpci logos are registered trademarks of the pci industrial computer manufacturers group. copyright ? 2002, texas instruments incorporated
slus503b ? march 2002 ? revised august 2002 2 www.ti.com description (continued) fully programmed sequencing control ramps the back-end plane voltages in order, and during shutdown from a healthy state, turns off the back-end supplies in the reverse order. in addition, electronic circuit breakers provide continuous protection for the system supplies during the plug-in operation. the control and status pins can interface directly to the back-plane bd_sel# and healthy# signals. a precharge pin (prechg) provides a 1-v bias supply for the i/o signals. absolute maximum ratings over operating free-air temperature (unless otherwise noted) ? input voltage range, vin1, vin2, vin3, bd_sel#, healthy#, prechg ? 0.3 v to 15 v . . . . . . . . . . . . . . . . vs1, vs2, vs3, cs1, cs2, cs3 ? 0.3 v to v in +0.3 v of corresponding channel . . . . . cpump, gate1, gate2, gate3 ? 0.3 v to 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vin4, vs4, gate4, cs4 ? 15 v to 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iramp ? 0.3 v to v i(vin1) +0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction temperature range, t j ? 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 300 c . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltages are with respect to gnd. currents are positive into, and negative out of the specified terminal. available options t packaged devices t a tssop (pw) ? 40 c to 85 c TPS2345pw the pw package is available taped and reeled. add tr suffix to device type (e.g. TPS2345pwtr) to order quantities of 2,000 devices per reel and 90 units per tube. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gate1 vs1 vin1 cs1 iramp bd_sel# rgnd prechg cs3 vin3 vs3 gate3 gate2 vs2 vin2 cs2 cpump cpgnd agnd healthy# cs4 vin4 vs4 gate4 pw package (top view)
slus503b ? march 2002 ? revised august 2002 3 www.ti.com electrical characteristics v i(vin1) = 12 v, v i(vin2) = 5 v, v i(vin3) = 3.3 v, v i(vin4) = ? 12 v, t a = ? 40 c to 85 c (unless otherwise noted) input supply parameter test conditions min typ max unit i cc1 supply current, vin1 6 8 i cc2 supply current, vin2 1 2 i cc3 input current, vin3 0.5 1 ma i cc4 input current, vin4 ? 1.5 ? 3 ma i cc1(slp) sleep mode current, vin1 v i(bd_sel#) = 5 v 0.5 i cc2(slp) sleep mode current, vin2 v i(bd_sel#) = 5 v 1 i cc3(slp) sleep mode current, vin3 v i(bd_sel#) = 5 v 100 a i cc4(slp) sleep mode current, vin4 v i(bd_sel#) = 5 v ? 400 a charge pump parameter test conditions min typ max unit v o(max) maximum output voltage i o(cpump) = ? 25 a 17 23 v i source peak output current v o(cpump) = 15 v ? 120 a z o charge pump source impedance 1v i o (cpump 17 v) i o (cpump 16 v) 200 k ? precharge output parameter test conditions min typ max unit v o(pchg)1 output voltage v i(vin2) = 4 v, v i(vin1/3/4) = 0 v 0.9 1 1.1 v o(pchg)2 output voltage, sourcing v i(vin2) = 4 v, v i(vin1/3/4) = 0 v, i o(prechg) = ? 5 ma 0.8 1 1.2 v v o(pchg)3 output voltage, sinking v i(vin2) = 4 v, v i(vin1/3/4) = 0 v, i o(prechg) = 5 ma 0.8 1 1.2 v t start startup time v i(vin2) = 4 v, v i(vin1/3/4) = 0 v 200 s linear current amplifiers 1, 2, 3 parameter test conditions min typ max unit v max1 imax sense voltage (vin1 ? cs1) 16 20 24 v max2 imax sense voltage (vin2 ? cs2) 17 20 23 mv v max3 imax sense voltage (vin3 ? cs3) 17 20 23 mv i pk output peak current ? 25 ? 5 i sink output current sink 0.2 10 ma i fault output current sink fault shutdown 150 ma v ol low-level output voltage fault shutdown, i o(gatex) = 10 ma 0.5 v v oh high-level output voltage i o(gatex) = ? 4 a v cpump ? 1 v linear current amplifier 4 parameter test conditions min typ max unit vmax4 imax sense voltage (vin4 ? cs4) ? 75 ? 150 ? 225 mv i ol1 output leakage current fault shutdown ? 10 10 a i ol2 output leakage current sleep mode ? 10 10 a
slus503b ? march 2002 ? revised august 2002 4 www.ti.com electrical characteristics v i(vin1) = 12 v, v i(vin2) = 5 v, v i(vin3) = 3.3 v, v i(vin4) = ? 12 v, t a = ? 40 c to 85 c (unless otherwise noted) (continued) overcurrent comparators 1, 2, 3 parameter test conditions min typ max unit v oc1 overcurrent threshold voltage (vin1 ? cs1) 34 45 56 v oc2 overcurrent threshold voltage (vin2 ? cs2) 29 40 51 mv v oc3 overcurrent threshold voltage (vin3 ? cs3) 29 40 51 t r response time 1 5 s overcurrent comparator 4 parameter test conditions min typ max unit v oc4 overcurrent threshold voltage (vin4 ? cs4) relative to vmax4 ? 50 ? 225 mv t r response time 1 5 s undervoltage (uv) parameter test conditions min typ max unit v uv1 channel 1 undervoltage limit 10.37 10.80 11.23 v uv2 channel 2 undervoltage limit 4.22 4.40 4.58 v v uv3 channel 3 undervoltage limit 2.78 2.90 3.02 v v uv4 channel 4 undervoltage limit -11.23 -10.80 -10.37 overvoltage (ov) parameter test conditions min typ max unit v ov1 channel 1 overvoltage limit 12.77 13.20 13.63 v ov2 channel 2 overvoltage limit 5.38 5.60 5.82 v v ov3 channel 3 overvoltage limit 3.55 3.70 3.85 v v ov4 channel 4 overvoltage limit -13.63 -13.20 -12.77 iramp output parameter test conditions min typ max unit i chg source current, charging v o(iramp) = 0.5 v ? 46 ? 58 ? 68 a i dsg sink current, discharging v o(iramp) = 0.5 v 1.3 1.8 2.5 a undervoltage lockout (uvlo) parameter test conditions min typ max unit v uvlo ? l vin1 uvlo, input rising 2.1 2.4 2.9 v uvlo ? h vin1 uvlo, input falling v i ( vin2 ) = v i ( vin3 ) = v i ( vin4 ) = 0 v 1.90 2.25 2.70 v v hys vin1 uvlo hysteresis v i(vin2) v i(vin3) v i(vin4) 0 v 0.05 v bd_sel# input parameter test conditions min typ max unit v il low-level input voltage 0.8 v v ih high-level input voltage 2 v i ih high-level input leakage current v i(bd_sel#) = 5 v 50 a
slus503b ? march 2002 ? revised august 2002 5 www.ti.com electrical characteristics v i(vin1) = 12 v, v i(vin2) = 5 v, v i(vin3) = 3.3 v, v i(vin4) = ? 12 v, t a = ? 40 c to 85 c (unless otherwise noted) (continued) healthy# output parameter test conditions min typ max unit i oh high ? level output (leakage) current v i(bd_sel#) = 5 v, v oh = 5 v 1 a v ol low-level output voltage v i(bd_sel#) = 0 v, i sink = 0.1 ma 0.5 v i ol low-level output (sink) current v i(bd_sel#) = 0 v, v ol = 0.5 v 4 10 ma terminal functions terminal i/o description name no. i/o description agnd 18 i analog ground bd_sel# 6 i logic low enable input for back-end power cpgnd 19 i charge pump ground cpump 20 i/o charge pump resevoir capacitor connection cs1 4 i channel 1 (12-v) current sense input cs2 21 i channel 2 (5-v) current sense input cs3 9 i channel 3 (3.3-v) current sense input cs4 16 i channel 4 ( ? 12-v) current sense input gate1 1 o gate drive for channel 1 (12-v) external pass fet gate2 24 o gate drive for channel 2 (5-v) external pass fet gate3 12 o gate drive for channel 3 (3.3v) external pass fet gate4 13 o gate drive for channel 4 ( ? 12v) external pass fet healthy# 17 o open drain output asserted low for back-end power good iramp 5 o current ramp programming pin prechg 8 o bias supply of 1v for bus signal precharge rgnd 7 i reference ground vin1 3 i channel 1 supply (12-v) input voltage sense vin2 22 i channel 2 supply (5-v) input voltage sense vin3 10 i channel 3 supply (3.3-v) input voltage sense vin4 15 i channel 4 supply ( ? 12-v) input voltage sense vs1 2 i 12-v supply back-end voltage sense vs2 23 i 5-v supply back-end voltage sense vs3 11 i 3.3-v supply back-end voltage sense vs4 14 i ? 12-v supply back-end voltage sense dissipation rating table package t a 25 c derating factor t a = 85 c tssop (pw) 800 mw 10 mw/ c 200 mw
slus503b ? march 2002 ? revised august 2002 6 www.ti.com pin descriptions agnd : analog ground reference for the device. bd_sel# : logic low enable input for back-end power. in the compactpci application, this pin ties to the short ? pin bd_sel# input to the plug-in slot. when the input supplies are above the device minimums, and this pin is asserted low the TPS2345 begins the sequential ramp ? up of the back-end supplies. pulling this input high (>2 v) turns off power to the back-end planes, and puts the TPS2345 into low-power sleep mode. cpgnd : charge pump ground pin for the device. cpump : charge pump resevoir capacitor connection. an external capacitor of value 0.1 f to 1 f must be connected between this pin and cpgnd. the capacitor provides charge storage for the internal charge pump for gate drive of the four external n-channel fets. cs1, cs2, cs3 : these pins tie to the load side of the channel 1, 2, and 3 current sense resistors, respectively. they are used in conjunction with the vin1, vin2 and vin3 inputs to provide load current magnitude information to each of the positive rail lcas. cs4 : this pin ties to the more positive side of the channel 4 current sense resistor (common with the pass fet source). it is used in conjunction with the vin4 input to provide channel 4 current magnitude information to the negative rail lca. gate1, gate2, gate3, gate4 : gate drive outputs for the channel 1 through channel 4 pass fets, respectively. the gates are driven according to the supply voltage, enable, sequence programming and load current conditions of the add-in board. healthy# : open-drain output asserted low to signal a back-end power good condition. in the compactpci application, this signal is an indication of the board ? s suitablility to be connected to the compactpci bus. the output is false when back-end power is not enabled, if any of the back-end voltage is not within the factory-programmed tolerances of the undervoltage and overvoltage comparators, or as a result of an overcurrent indication on any supply controller, or a fault time-out on any supply during linear ramp-up. iramp : current ramp programming pin. a capacitor connected between this pin and ground determines the maximum slew rate of the load current during ramp-up and ramp-down of the three positive back-end voltages. this same capacitor is also used to establish the time limit for ramping each of the supply outputs. prechg : bias supply of 1 v for bus signal precharge. during plug-in insertion events, this output provides bias supply to precharge the bus signal lines according to the requirements of the compactpci hot swap specification. rgnd : reference ground input for the device. vin1 : channel 1 supply (12-v) input voltage sense. this pin is connected to the 12-v power supply input to the add-in card. the supply potential is tested against the undervoltage limits prior to ramping voltage to the back-end 12-v plane. the input supply also serves as the reference potential for the internally generated current limit (imax) reference of the channel 1 lca. this pin also serves as the vcc supply for the TPS2345. vin2 : channel 2 supply (5-v) input voltage sense. this pin is connected to the 5-v power supply input to the add-in card. the supply potential is tested against the undervoltage limits prior to ramping voltage to the back-end 5-v plane. the input supply also serves as the reference potential for the internally generated current limit (imax) reference of the channel 2 lca. this pin also serves as the supply input for the precharge bias output. vin3 : channel 3 supply (3.3-v) input voltage sense. this pin is connected to the 3.3-v power supply input to the add-in card. the supply potential is tested against the undervoltage limits prior to ramping voltage to the back-end 3.3-v plane. the input supply also serves as the reference potential for the internally generated current limit (imax) reference of the channel 3 lca.
slus503b ? march 2002 ? revised august 2002 7 www.ti.com pin descriptions (continued) vin4 : channel 4 supply ( ? 12-v) input voltage sense. this pin is connected to the ? 12-v power supply input to the add-in card. the supply potential is tested against the undervoltage limits prior to ramping voltage to the back-end ? 12-v plane. the input supply also serves as the reference potential for the internally generated current limit (imax) reference of the channel 4 lca. vs1, vs2, vs3 : voltage sense inputs for the positive back-end power busses. these pins connect to the source nodes (load side) of the external pass fets. after the programmed voltage ramp period for each supply, these inputs are monitored to verify that the load voltages remain within the specified tolerances. vs4 : voltage sense input for the negative back-end power bus. this pin connects to the drain (load side) of the channel 4 external pass fet. after the programmed voltage ramp period for the negative supply, this input is monitored to verify that the load voltage remains within the specified tolerance. functional overview when an add-in compactpci printed circuit board (pcb) is inserted into a live chassis slot, the discharged supply bulk capacitance on the board can draw huge transient currents from the system supplies. limited only by the esr of the bulk capacitors and the impedance of the interconnect, these transients can reach sufficient magnitude to cause immediate damage to connector pins, pcb etch and plug-in and supply components, or cause latent defects reducing long-term reliability. in addition, current spikes can cause glitches on the power busses, causing other boards in the system to reset. the TPS2345 is designed for use with the connector pin staging and insertion/extraction processes defined in the compactpci hot swap specification, to enable full hot-swap capability in compactpci add-in cards. n ? channel mosfets in series with each supply input provide isolation between the early power planes and the back-end power planes during insertion and extraction events. low ohmic-value sense resistors between each input and pass mosfet feed back current information to the device. the TPS2345 uses load current sensing along with the peripheral slot enable command, bd_sel#, to determine the appropriate gate drive status for each of the four pass mosfets. in this manner, the device provides for the controlled application of power to and removal from the back-end planes during hot swap. when the add-in pcb is inserted into the slot, the long 5-v, 3.3-v and gnd power pins make contact first (see typical application diagram). at this stage of the insertion process, the TPS2345 precharge circuitry becomes active, and biases the i/o pins to a nominal 1.0 v. next, the medium length pins make contact, which includes the 12-v, ? 12-v supplies, and the majority of the 5-v and 3.3-v supply pins. the TPS2345 derives vcc power from the 12-v supply; however, the pull-up on the bd_sel# input pin causes the device to maintain pull-downs on the four gate pins, keeping the pass mosfets off. the short bd_sel# pin is one of the last pins to mate; at that point a logic low on the signal starts the turn-on of power to the back-end loads. during a ramp-up sequence, the four supply inputs are validated against the pre-programmed undervoltage (uv) and overvoltage (ov) thresholds. as each positive voltage load is enabled, current to the load is ramped at a user-programmable rate, easily set by a capacitor on the current ramp control pin, iramp. the supplies are sequenced up in the following order: 12-v, 5-v, 3.3-v and ? 12-v. the ramp of supply current on each channel is limited to a maximum value, herein referred to as imax. the imax limit is individually selectable for each channel, by selecting the appropriate value of the sense resistor. if the imax current level is attained on any channel during an insertion, charging of that channel ? s input bulk capacitance completes at that current limit, as required.
slus503b ? march 2002 ? revised august 2002 8 www.ti.com functional overview (continued) as each back-end voltage is ramped, its level is validated to ensure it is within the established uv and ov tolerances at the expiration of a programmable time period, protecting against start-up into faulted loads. the same capacitor at the iramp pin which sets the current ramp rate is also used to establish this ramp-up time limit. if all four supplies successfully reach a known good state, the healthy# output signal is pulled low to allow enumeration of the add-in card. to protect the backplane power bus, the TPS2345 provides an electronic circuit breaker that trips upon detecting an overcurrent event. the detection threshold of an overcurrent event is internally set to approximately two times (2x) imax. the ? 12-v channel also includes a circuit breaker function; its trip threshold is always a minimum of 50 mv above the current-limit sense voltage. if any channel trips the circuit breaker, all supply outputs are rapidly turned off, and remain latched off. also, the healthy# output becomes high-impedance. the TPS2345 can be reset by cycling either the bd_sel# input or power to the device. the low, 20-mv (150 mv on the ? 12-v channel) nominal sense voltage limit allows the use of low-value sense resistors, or for high-current applications, the use of pc board copper trace. this helps minimize the insertion loss across the hot swap interface. further insertion loss reduction is achieved via the on-chip charge pump, which ensures maximum gate overdrive on each of the three external pass mosfets on the positive supply channels. this feature helps users obtain lower r ds(on) characteristics with their preferred n-channel mosfets. under a normal pc board shutdown event, the TPS2345 also turns off power in a controlled manner. to initiate a shutdown, bd_sel# is brought to a logic high during a healthy# state (outputs on and no faults present). the supply outputs are then sequentially ramped off in the reverse order of the ramp-up sequence. after all supply outputs are off, the TPS2345 goes into a low-current sleep mode.
slus503b ? march 2002 ? revised august 2002 9 www.ti.com detailed description the primary circuit blocks of the TPS2345 include internal supply generation, a charge pump, a state machine, programmable ramp generator, precharge circuitry, and a rom data cell. in addition, each of the four channels contains a gate control block which includes the linear control amplifier (lca), programmable current source, and the voltage sense circuitry (see figure 1). the gate drive blocks are virtually identical, except that the channel 4 block, controlling the negative voltage channel, adds some scaling and level shift circuitry to adjust the polarity of the sense signals to that of the internal circuitry. + 1v + 2.5v supply section charge pump cpok uvlo vin1 uvov1 level[15:0] iramp vin2 state machine uvov[4:1] 100 s rom data pre ? charge + + v imax3 lca/ v ? sns3 v imax4 ls + + lca/ v ? sns4 v imax2 + + lca/ v ? sns2 v imax1 + + lca/ v ? sns1 en1 en2 en3 en4 /flt oc[4:1] uvlo cpok en ord[8:0] fs vs1 oc1 uvov3 oc3 uvov2 oc2 uvov4 oc4 vin2 va va en1 en2 en3 en4 bd_sel# healthy# vin1 vin3 vin4 3 12 11 14 8 16 13 15 5 22 23 24 21 20 2 4 1 6 17 10 vs2 vs4 vs3 gate1 cs1 cs2 cs4 cs3 gate2 gate4 gate3 19 7 18 /chg rgnd agnd prechg cpgnd cpump + dac ramp generator 3 up ch_sel[4:1] 9 mux figure 1. TPS2345 block diagram the supply generation block contains voltage regulators and references to generate the various bias voltages used internally by the TPS2345. an undervoltage lockout (uvlo) function is used to ensure proper device turn-on once the vin1 input has attained the uvlo threshold of about 2.5 v. in addition, an on-chip charge pump steps up the vin1 i nput to generate the high voltage used by the lcas to drive the pass mosfet gates. burst regulation of the charge pump limits the output to about 20.5 v (peak), with about a 1-v hysteresis. during steady-state load operation, sufficient gate overdrive is ensured to fully enhance the external mosfets, while not exceeding the typical 20-v v gs rating of common n-channel mosfets, even on the low-voltage channels. the state machine block contains the logic to control the ramp-up and ramp-down sequencing, ramp generator operation, and fault management. it uses voltage and current monitor outputs, along with the device enable status and programmed order information to determine which channel is to be acted on, whether ramp-up, ramp-down or steady-state operation is required, and the present healthy or faulted states of the back-end supplies. a nom inal 100 ? s digital filter is applied to the bd_sel# input to help protect against false triggering in systems not implementing hardware connection control. the filter acts on both high-to-low and low-to-high transitions of the enable input.
slus503b ? march 2002 ? revised august 2002 10 www.ti.com detailed description (continued) the ramp generator consists of a series of multiplexers feeding a digital-to-analog converter (dac) circuit which sets the magnitude of an internal current source. when active, the current source is used to establish a constant value source or sink current at the iramp pin. this current is used to alternately charge and discharge a capacitor connected between iramp and ground, generating a series of sawtooth timing pulses. during turn-on of the back-end voltages, the capacitor is charged with a 58- a current, then subsequently discharged with a 1.8- a load. a comparator in the ramp generator circuit monitors the iramp voltage against two alternating thresholds, such that the voltage charges up to 1.5 v and back down to 0 v. during the rising edge of this waveform, the voltage at iramp is used to develop the reference threshold at the inverting input of the active channel ? s lca. the other input is connected to the channel ? s current sense (csx) input. the lca slews the gatex output to maintain the csx pin at the reference value. since the csx voltage is developed as the drop across the external sense resistor due to load current, the current to the load is therefore ramped at a linear rate set by the dv/dt on the iramp pin. therefore, inrush slew rate limiting is easily programmed by the user with the iramp capacitor, c iramp . for channel 4, internal device offsets may cause the inrush profile to deviate from the programmed curve, particularly at initial turn-on. however, the maximum sourcing limit imposed by the vmax4 threshold still applies. during a load turn-on, the current sense voltage, if required in order to fully charge the back-end plane, can track the iramp waveform up to approximately 1.35 v on the iramp pin. if the charging current achieves that level, the lca reference is switched automatically to the fixed imax reference. load charging then continues at that fixed level until complete or until timer expiration, whichever occurs first. for channels 1, 2 and 3, the imax level has been set to 20 mv at the csx pin, referenced to vinx. for channel 4, the imax level is 150 mv. the precharge circuitry is powered from the vin2 supply input, or 5-v for cpci systems. therefore, when the long pins mate during an insertion, or until they break contact during an extraction, the precharge actively biases the bus signal lines to 1.0 v. the precharge block consists of a 1-v reference generator and a unity gain amplifier. the amplifier provides source and sink capability up to 5 ma. the rom data cell sets the configuration information for the TPS2345. these parameters include the order of channel sequencing, the magnitude of the charge and discharge currents at iramp, and the nominal voltage range of each channel. this information is all pre-programmed at the factory; no programming by the user is necessary.
slus503b ? march 2002 ? revised august 2002 11 www.ti.com detailed description (continued) the basic functional blocks of the lca/voltage sense circuits is shown in greater detail in figure 2. the lca has as its inputs the reference voltage generated by the current sources, and the current sense input. during a supply turn-on, it slews the pass mosfet gate to force the load current to track the selected source. after load charging completes, and the current decays to the nominal operating level, the lca drives the gatex output to its input supply level, the charge pump output voltage. udg ? 02004 + r lca oca ov uv uv ov r dac dac 5 5 ref_vx vsel vinx csx vsx gatex ocx uvovx mux 2:1 v cpump v imax iramp 10 v inx figure 2. linear control amplifier block the supply voltage is monitored by the undervoltage (uv) and overvoltage (ov) comparators. a voltage multiplexer (mux) selects from either the input supply voltage (vinx) or the load voltage (vsx), and provides that signal to the comparator inputs. once the channel 1 supply is above the uvlo threshold, and the bd_sel# input has been pulled low, but prior to the ramp-up of the first channel, the comparators monitor the input supplies. any supply outside its uv/ov window causes all pass mosfets to be held off. if all inputs are within tolerance, a ramp-up sequence can start, at which time the comparator inputs are switched over to the load, or vsx, voltages. within the state machine, monitoring of the ored status of the uv and ov comparators of any channel is enabled at the turn-on of the next channel, or approximately at the leading edge of the next iramp pulse. finally, a fast overcurrent comparator (oca in the diagram) also monitors the csx input. this comparator threshold is set to approximately 2 times the current limit threshold, (2 imax) for the three positive supplies. in the event of a short-circuit or other fast overcurrent event, the oca trips, disabling the lca, and causing additional gate discharge paths to be turned on for a rapid shutdown of the loads. a 1- s to 2- s filter is applied to all overcurrent and voltage faults to guard against nuisance trips. if the duration of a fault condition on any one channel exceeds the filter length, the fault is latched, the open-drain device at the healthy# output is turned off, and all four channels are shut down.
slus503b ? march 2002 ? revised august 2002 12 www.ti.com typical characteristics normal turn-on sequence normal turn-off sequence figure 3 figure 4 t ? time ? 10 ms/div iramp (500 mv/div) bd_sel# (5 v/div) be_12v (5 v/div) be_5v (5 v/div) be_3.3v (5 v/div) be_n12v (5 v/div) healthy# (5 v/div) c iramp = 0.01 f c l1 = 69 f c l2 = 690 f c l3 = 690 f c l4 = 69 f c iramp = 0.39 f c l1 = 69 f c l2 = 690 f, c l3 = 690 f c l4 = 69 f r l1 = 39 ? r l2 = 2.5 ? , r l3 = 1.6 ? r l4 = 39 ? t ? time ? 5 ms/div
slus503b ? march 2002 ? revised august 2002 13 www.ti.com typical characteristics figure 5 load current linear ramp example: 12-v load be_12v (5 v/div) i ramp (1 v/div) 12v_load (200 ma/div) c iramp = 0.39 f c load1 = 169 f t ? time ? 1 ms/div . figure 6 turn-on into a short on back-end 3.3 v c iramp = 0.39 f c load1 = 69 f r load1 = 39 ? c load2 = 690 f r load2 = 7 ? be_3.3v: shorted i ramp (1 v/div) be_12v (5 v/div) be_5v (5 v/div) be_3.3v (500 mv/div) t ? time ? 50 ms/div 3.3v_load (2 a/div)
slus503b ? march 2002 ? revised august 2002 14 www.ti.com figure 7 undervoltage fault response 5-v fault c load1 = 69 f r load1 = 39 ? c load2 = 22 f r load2 = 2.5 ? gate3 (10v/div) c load3 = 690 f r load3 = 1.6 ? c load4 = 69 f r load4 = 39 ? gate1 (10v/div) t ? time ? 5 s/div gate4 (10v/div) be_5v (2 v/div) figure 8 high level output voltage vs ambient temperature, lca1 ? 40 ? 15 10 35 60 85 0 5 10 15 20 25 t a ? ambient temperature ? c v oh ? gate1 voltage ? v v i(vin1) = 12 v i o(gate1) = ? 4 a
slus503b ? march 2002 ? revised august 2002 15 www.ti.com typical characteristics ? 40 ? 15 10 35 60 85 0 5 10 15 20 25 figure 9 high level output voltage vs ambient temperature, lca2 t a ? ambient temperature ? c v oh ? gate2 voltage ? v v i(vin1) = 12 v i o(gate2) = ? 4 a ? 40 ? 15 10 35 60 85 0 5 10 15 20 25 figure 10 high level output voltage vs ambient temperature, lca3 t a ? ambient temperature ? c v oh ? gate3 voltage ? v v i(vin1) = 12 v i o(gate3) = ? 4 a ? 40 ? 15 10 35 60 85 ? 12 ? 9 ? 6 ? 3 0 figure 11 high level output voltage vs ambient temperature, lca4 t a ? ambient temperature ? c v oh ? gate4 voltage ? v i o(gate4) = ? 8 ma ? 40 ? 15 10 35 60 85 ? 62 ? 58 ? 54 ? 52 ? 48 ? 60 ? 56 ? 50 figure 12 iramp output current vs ambient temperature t a ? ambient temperature ? c i chg ? iramp output current ? a v o(iramp) = 0.5 v current source mode
slus503b ? march 2002 ? revised august 2002 16 www.ti.com typical characteristics ? 40 ? 15 10 35 60 85 1.4 1.6 1.8 2.0 2.2 2.4 figure 13 iramp input current vs ambient temperature t a ? ambient temperature ? c i dsg ? iramp input current ? a v i(iramp) = 0.5 v current sink mode figure 14 iramp mode trip threshold vs ambient temperature t a ? ambient temperature ? c v trip ? iramp trip threshold ? v ? 40 ? 15 10 35 60 85 1.44 1.46 1.48 1.52 1.54 1.56 1.50 figure 15 prechg output voltage vs ambient temperature t a ? ambient temperature ? c v o(pchg) ? output voltage ? v ? 40 ? 15 10 35 60 85 0.0 0.2 0.4 0.6 0.8 1.2 1.0 i o(prechg) = 5 ma i o(prechg) = ? 5 ma v i(vin2) = 4 v v i(vin1) = v i(vin3) = v i(vin4) = 0 v figure 16 prechg output voltage vs supply voltage 4.0 4.5 5.0 5.5 6.0 0.90 0.92 0.98 1.06 1.10 0.94 0.96 1.00 1.02 1.08 1.04 v i(vin2) ? input voltage ? v v o(pchg) ? output voltage ? v v i(vin3) = 3.3 v v i(vin1) = v i(vin4) = float t a = 25 c i out = 5 ma i out = ? 5 ma
slus503b ? march 2002 ? revised august 2002 17 www.ti.com typical characteristics figure 17 precharge output voltage vs output current, sourcing i o(pchg) ? output current ? ma v o(pchg) ? output voltage ? v ? 8 ? 7 ? 5 0.4 0.9 1.1 0.5 0.6 0.7 0.8 1.0 ? 6 ? 4 ? 2 ? 3 ? 10 v i(vin2) = 4.75 v v i(vin3) = 3.30 v v i(vin1) = v i(vin4) = float t a = 25 c figure 18 precharge output voltage vs output current, sinking i o(pchg) ? output current ? ma v o(pchg) ? output voltage ? v 0.8 1.0 1.1 1.2 1.4 0.9 1.3 2 048 6 10121416 v i(vin2) = 5.25 v v i(vin3) = 3.30 v v i(vin1) = v i(vin4) = float t a = 25 c
slus503b ? march 2002 ? revised august 2002 18 www.ti.com application information the connections to set up the TPS2345 for operation in a compactpci plug-in are shown in the typical application diagram.the TPS2345 works in conjunction with four external n-channel mosfets to provide isolation of the back-end power planes when disabled, and to provide a low-impedance power path when the load voltages are at the full-input dc potential. for proper operation, each channel of the device must be connected to the appropriate supply as listed in table 1. table 1. TPS2345 channel to cpci supply connections TPS2345 channel cpci supply 1 12 v 2 5 v 3 3.3 v 4 ? 12 v sense resistors r1 through r4 connect between the vinx and csx pins of their respective supplies, and provide load current magnitude information to the TPS2345. to turn on the negative voltage channel, the device pulls the gate of mosfet q4 towards ground potential. resistor r5 provides a gate pull down when the lca turns off, as the channel 4 lca does not drive to the negative rail. capacitors c1 through c4 provide decoupling at the plug-in power pins, and are required by the compactpci hot swap specification. for the 5-v and 3.3-v supplies, the specification recommends an average value of between 0.1 f and 0.2 f per 10 pins. this capacitance may be distributed along the connector, or provided as a single chip on each supply. since there are eight 5-v and ten 3.3-v power pins at each backplane slot, two 0.1- f ceramic capacitors meet this requirement. the 12-v supplies should also be decoupled as shown. all four capacitors should be placed close to the j1 connector, with trace length less than or equal to 0.6 inch. resistor r7 provides the 1.2-k ? pull-up on the bd_sel# pin required by the hot swap specification. the pull-up resistor is shown connected to the early 5-v plane; alternatively, it could be connected to early vio. resistor r6 provides a pull-up to early vio on the healthy# signal; a 10-k ? resistor should suffice. a capacitor with a value between 0.1 f and 1 f (c6 in the diagram) is required between the cpump pin and ground. this capacitor provides charge storage for the on-board charge pump. a 0.1- f ceramic is sufficient for most applications. ramp-up sequence a successful ramp-up of the four cpci back-end supplies consists of five pulses on the TPS2345 iramp pin. one load voltage is ramped up during each of the first four iramp pulses. the fifth pulse enables the fault logic of the last channel (channel 4) to turn on. this is shown graphically in figure 19.
slus503b ? march 2002 ? revised august 2002 19 www.ti.com application information udg ? 02006 t0: bd_sel# input brought low to initiate a turn-on sequence. t1: channel 1 (12v) gate enabled; iramp capacitor starts charging with slow turn-on clamp. slow charging of load voltage (back-end 12v) begins. t2: slow turn-on period ends; linear ramp of current to the load begins. t3: constant di/dt period ends; load voltage ramping continues at imax rate. t4: back ? end 12v reaches input dc potential. t5: channel 2 (5v) gate is enabled. slow charging of load voltage (back-end 5v) begins. fault monitoring on ch. 1 enabled. t6: slow turn-on period ends; linear ramp of current to load begins. t7: constant di/dt period ends. load voltage ramping continues at imax rate. t8: back ? end 5v reaches input dc potential. t9: channel 3 (3.3v) gate is enabled. slow charging of load voltage (back-end 3.3v) begins. fault monitoring on ch. 2 enabled. t10: slow turn ? on period ends; linear ramp of current to the load begins. t11: constant di/dt period ends. load voltage ramping continues at imax rate. t12: back ? end 3.3v reaches input dc potential. t13: channel 4 ( ? 12v) gate is enabled. slow charging of load voltage (back-end ? 12v) begins. fault monitoring on ch. 3 enabled. t14: slow turn-on period ends; linear ramp of current to load begins. t15: constant di/dt period ends; load voltage ramping continues at imax rate. t16: back-end ? 12v reaches input dc potential. t17: channel 4 uv/ov fault enable pulse. t18: healthy# output pulled low. healthy# t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 0 v 0 v 0 v 5 v 0 v 12 v ? 12 v 0 v 1.35 v 1.5 v bd_sel# 3.3 v v o(iramp) back-end 12-v back-end 5-v back-end 3.3-v back-end ? 12-v figure 19. TPS2345 ramp-up sequence
slus503b ? march 2002 ? revised august 2002 20 www.ti.com application information a turn-on sequence is initiated when the bd_sel# input is brought low (less than 0.8 v), assuming that all four input supplies (at the vinx pins) are within their uv/ov tolerance windows. a voltage fault at any input supply causes all loads to be held off. when bd_sel# is asserted, the channel 1 amplifier is enabled, and a 58- a current source begins charging the iramp capacitor to generate the first i ramp pulse. during the linear rising edge portion of the iramp waveform, current is linearly ramped to the 12-v back-end plane. once the voltage at iramp reaches 1.5 v, the source is replaced with a 1.8- a sink that discharges iramp to 0 v. during this discharge period, load charging current, if still required, is limited to imax, the current sense voltage (vmax) divided by the sense resistor value, r snsx , or imaxx = vmaxx / r snsx , where ? x ? refers to any of the four channels. at the completion of the first pulse on iramp, the TPS2345 moves to the second voltage to be ramped up, channel 2, enables its lca and begins generating the second pulse in the iramp train. at this time, fault monitoring is enabled on the channel 1 output. therefore, if channel 1 has failed to attain at least the undervoltage threshold potential, a fault is detected, any active channels turned off, and the turn-on sequence aborted. in this manner, the maximum time allowed for ramp-up of any of the channels is the duration of one (1) iramp pulse. this protects against indefinite sourcing into faulted loads. the TPS2345 latches off in response to faults, and can be reset either by toggling the bd_sel# input high and then low again, or by cycling power to the device. after the channel 2 ramp pulse, the back ? end planes for channel 3 and channel 4 are ramped up in similar fashion. channel 2 fault detection is enabled at the start of the channel 3 ramp pulse, and so on. once all four supplies are ramped up, channel 4 fault detection is enabled on the fifth iramp pulse. this last pulse is of relatively short duration, as charge and discharge currents of approximately 256 a are selected for the uv/ov4 enable pulse. if all four channels reach a known good state, the healthy# output is asserted low. each load current waveform, at load turn-on, may have up to three distinct periods, as shown in figure 20. initially after being enabled, the ramp generator output voltage is clamped to less than 100 mv. this results in a corresponding clamp on load current of about 7% of the programmed imax value (with some variance due to internal device offset). this temporary limit applies during approximately the first 500 s of output ramping time. the purpose of this slow ramp period is to ensure the lca is pulled out of saturation, and is closely tracking the cs input, prior to enabling fast charging of the load. during this time, appreciable ramping of the back-end voltage may or may not occur, depending on a number of factors including the imax value, the amount of bulk capacitance on the load, and the magnitude and polarity of inherent offsets in the current control loop.
slus503b ? march 2002 ? revised august 2002 21 www.ti.com application information udg ? 02005 t1: slow turn-on period t2: linear current ramp (di/dt) t3: constant-current load charging t chg : iramp capacitor charge time, (1.4 c iramp /58) t1 t2 t3 0 v v in 0 a i imax 0 v 0 v 1.5 v time iramp voltage gate voltage load current back ? end voltage t chg 32 x t chg figure 20. load current at startup once the slow ramp period has expired, the clamp is removed, and the iramp voltage continues to ramp up at a constant rate of: i o c iramp 58 a c iramp since the linear amplifier acts to maintain equal voltages at its inputs (see figure 2), it slews the gatex output such that the csx voltage tracks the internally generated reference at its inverting input. therefore, the linear voltage ramp at the iramp pin results in a linear current ramp to the three positive loads.
slus503b ? march 2002 ? revised august 2002 22 www.ti.com application information the lca reference ramp tracks the iramp pin voltage up to a level of v o(iramp) 1.35 v. this corresponds to the maximum sense voltage (vinx ? csx) of 20 mv (150 mv for channel 4). if charging of the load input bulk capacitance completes during the constant di/dt section of channel turn-on (the set of dashed lines in figure 20), the load current decays to the steady-state operating level. with decreasing load current, the csx input is pulled to the vinx potential, and the pass mosfet gate is driven to the lca supply rail, fully enhancing the external mosfet. however, under certain combinations of bulk capacitance, imax, and inrush di/dt relative values, the current ramp may reach the imax limit. the variable current source is switched out for the constant current source which sets the vmax reference level (see figure 2). this defines the third stage of the load current waveform. load voltage ramping completes at the imax level, as shown by the set of solid lines in figure 20. again, once the current demand rolls off, the lca drives the pass mosfet gate high to fully enhance the mosfet. ramp-down sequence a normal shutdown sequence occurs when the bd_sel# input is brought high ( greater than 2 v) with the output supplies in a healthy state (no overvoltage, undervoltage or overcurrent faults). healthy# is deasserted and the back-end voltages are sequenced off in the reverse order of turn on: ? 12-v, 3.3-v, 5-v and 12-v (channel 4, channel 3, channel 2 and then channel 1). the turn off is also controlled by five pulses at the iramp pin. the first pulse, which is of short duration, disables the voltage fault monitoring on channel 4 ( ? 12 v). starting with the second pulse, each supply is turned off in order. at the start of each pulse at iramp, voltage fault monitoring is disabled for the next successive channel to be turned off. the iramp capacitor is charged rapidly, up to the 1.5-v threshold, at which point the variable current source in the lca block is reselected to generate the current limit reference. at the same time, the charging source at iramp is replaced with a 58- a discharge load, such that the iramp capacitor is discharged at the same rate used for di/dt control during turn on. this causes the current limit to decrease linearly, so that available load current is forced off no faster than the falling edge at iramp. the lca is disabled, and additional pull-downs applied to the gatex pin, when either the output voltage has decayed to less than 0.9 v, or the iramp waveform has decayed to approximately 0.1 v. under conditions of light loading during turn off, the bulk capacitance may hold up the back-end voltage even after the mosfet switch is turned off. in this situation, the TPS2345 waits for load discharge to less than 0.9 v prior to proceeding to the next channel. channel 4 is the exception to this operation; the vs4 status is not monitored during turn off, and the device sequences to channel 3 turn-off once the second iramp pulse ends. setting the sense resistor values due to the current limiting operation of the internal lcas, the maximum allowable load current for the application is easily programmed by selecting the appropriate value sense resistors. the lca acts to limit the csx voltage (relative to vinx) to the internal reference, which during steady-state operation is vmax. therefore, a sense resistor for each channel can be calculated from equation (1). r snsx vmaxx imaxx where r snsx is the the sense resistor value for channel x, vmaxx is the imax sense voltage limit, and imaxx is the channel x maximum load current. (1)
slus503b ? march 2002 ? revised august 2002 23 www.ti.com application information when setting the current limits, it is important to consider the device minimum that may be imposed by the TPS2345. using the values given in the electrical tables, equations (2) through (4) follow from equation (1). for channel 1: r sns1 16 mv imax1 for channels 2 and 3: r snsx 17 mv imaxx where: x = 2 or 3. for channel 4: r sns4 75 mv imax4 to ensure proper operation across the range of anticipated load currents on each channel, the maximum load under normal operating conditions must also be considered. to avoid current-limit operation during steady-state loading, the imax level must be set above the expected load. for example, if the 3.3-v (channel 3) supply of the typical application diagram needs to deliver up to 6.5 a, and a 500-ma margin is desired, using equation (3) yields: r3 17 mv 7a 2.43 m this value is rounded up to 2.5 m ? in the schematic. similarly, for up to 600-ma capability on channel 1, equation (2) indicates r1 25 m ?. setting r4 = 250 m ? , provides some margin over a 250 ma load. also, these values limit the maximum load within the cpci specification limits. setting the inrush slew rate the TPS2345 is easily programmed for the desired maximum current slew rate during turn-on and turn-off events. a single capacitor at the iramp pin (c5 in the diagram) controls the di/dt for all three positive channels. once the sense resistor values have been established, the value for c iramp , in microfarads, can be determined from equation (5). for channels 1, 2, and 3: c irampx 68 67.5 r snsx di dt x where: c irampx = the capacitor value indicated to achieve the (di/dt)x limit value, r snsx = sense resistor in ohms and (di/dt) x = the maximum di/dt rate, in amps/second. (2) (3) (4) (5)
slus503b ? march 2002 ? revised august 2002 24 www.ti.com application information the compactpci hot swap specification requires the following maximum slew rates for the input supplies (see table 2). table 2. compactpci hot swap slew rate specifications supply name maximum slew rate 5 v 1.5 a/ms 3.3 v 1.5 a/ms 12 v 150 ma/ms ? 12 v 150 ma/ms since the 12-v supplies have the more stringent limit, they are useful for obtaining an initial estimate for the iramp capacitor. using the 12-v supply values, equation (5) produces the result shown in equation (6). c iramp1 68 67.5 ( 0.025 ) 150 ma ms 0.27 f a value of 0.27 f can be used, or the next available standard value of 0.33 f provides some margin for capacitor and sense-resistor tolerances. in either case, equation (5) can be rewritten as equation (7), which is used here to verify that the 5-v and 3.3-v slew rates are within specification. di dt 2,3 68 67.5 r sns2,3 c iramp where: r sns2,3 is in ohms, c iramp is in microfarads, and (di/dt) 2,3 is given in amps/second. for a c iramp of 0.33 f, the maximum di/dt for the 5-v and 3.3-v supplies is 1.02 a/ms and 1.22 a/ms, respectively, which is well within the cpci specification. protection against faulted loads the TPS2345 allows the time period of one iramp pulse for each back-end plane ? s voltage to ramp-up to its minimum level. after this delay period, the device latches off if an undervoltage fault is subsequently detected. this nominal delay time, t timer , is set by the constant-current charging and subsequent discharging of c iramp , and is therefore determined from equation (8). t timer c iramp 1.4 1 58 1 1.8 where: c iramp is in microfarads. the resultant fault timer period should be sufficient for most applications; however, it is good design practice to verify that the delay is long enough for each load. (6) (7) (8)
slus503b ? march 2002 ? revised august 2002 25 www.ti.com application information due to the potential three-phase nature of the load current ramp (refer to figure 20), the increasing load voltage may also have three distinct periods. the first phase is during the slow turn-on period at the start of each iramp cycle. depending on a number of factors, significant voltage ramping may or may not occur during this time. also, any appreciable voltage ramp is more likely on the 3.3-v and 5-v loads. for verification of the fault timeout delay, the worst case situation is no appreciable load charging (i.e., a longer overall charge time); therefore it is assumed that no voltage ramp occurs here. the next phase is the linear load current ramp period. for any device channel x, if the imax level is not reached while charging a given load capacitor of c lx , then the time to reach the input dc level, v inx , is estimated by equation (9). t ssx 2 c lx c iramp k x r snsx v inx 58 a
where: k x = 67.5 for channels 1, 2, and 3, and k x = 7.5 for channel 4. for example, assuming the 5-v back-end plane in this application has 220- f bulk capacitance, the anticipated typical ramp-up time is about 1.6 ms. during inrush slewing, the load current ramp tracks the voltage ramp on the iramp capacitor, up to a voltage of about 1.35 v on the iramp pin. therefore, the time duration of this ramp activity, t iramp , is given by equation (10). t iramp c iramp ( 1.25 v ) 58 where: c iramp is in microfarads. if, for any channel, the time for soft-start charging of the load voltage is greater than the current ramp period, (t ssx > t iramp ), back-end plane ramp-up completes at the dc imax level. in this case, the following procedure can be used to estimate load ramp-up time. first, equation (11) is used to determine the load voltage level, v lx (t), attained during the current ramp period. v lx t iramp 58 a 2 c lx c iramp k x r snsx t iramp 2 once this voltage level is known, it can be used to estimate the additional charging time required at constant current to reach the input dc potential, t ccx . this time is calculated from equation (12). t ccx c lx v inx v lx t iramp imaxx the sum of t iramp and t ccx can then be used to estimate the total load ramp-up time for channel x. (9) (10) (11) (12)
slus503b ? march 2002 ? revised august 2002 26 www.ti.com application information precharge circuit the prechg pin can be used to generate the 1-v bias voltage which precharges the compactpci bus signals during hot swap events. the pin ? s output stage has both source and sink capability, enabling it to pull lines up from 0 v or down from v(i/o) as needed. typically, each i/o line requiring precharge is isolated from the prechg source with a minimum 10-k ? resistor (r p in the typical application diagram). depending on the signaling level of a particular system (5 v or 3.3 v), other requirements for precharge resistor value and disconnection may apply. numerous manufacturers currently offer integrated bus switches that may be useful when disconnection is desired or required. a stub resistor (r8) is inserted in each i/o line as shown, which helps provide some series damping. the value of this resistor is specified as 10 ? 5%, placed within 0.6 inch of the connector. generating local_pci_rst# the local_pci_rst# signal used to initialize the plug-in ? s pci device in compactpci systems is easily generated from the TPS2345 ? s healthy# output using as few as two logic gates. a suggested solution is shown in figure 21. the circuit functions such that local_pci_rst# is asserted whenever back-end power is not healthy, regardless of the status of pci_rst#. texas instruments and several other manufacturers produce a series of single-gate devices in small footprint, 5-pin packages. table 3 lists some of the options available within three of the technologies available from ti: ahc, ahct, and lvc. the applicable device numbers are shown sorted according to signaling environment and package type. chip-scale packaging may also be available for the lvc types. udg ? 02015 early power ? 04 ? 08 pci_rst# healthy# local_pci_rst# 5 4 3 2 1 5 4 3 2 figure 21. local_pci_rst# circuit table 3. texas instruments little logic device options signaling device packaged devices signaling environment device sot ? 23 (dbv) sc ? 70 (dck) 5v ? 04 sn74ahct1g04dbvr sn74ahct1g04dckr 5v ? 08 sn74ahct1g08dbvr sn74ahct1g08dckr ? 04 sn74ahc1g04dbvr sn74ahc1g04dckr 33v ? 08 sn74ahc1g08dbvr sn74ahc1g08dckr 3.3v ? 04 sn74lvc1g04dbvr sn74lvc1g04dckr ? 08 sn74lvc1g08dbvr sn74lvc1g08dckr
slus503b ? march 2002 ? revised august 2002 27 www.ti.com application information protecting the TPS2345 from voltage transients parasitic inductance associated with the power distribution network can cause large voltage spikes on the supply rails if the current is suddenly interrupted by the TPS2345 during a fault condition. it is important to protect the TPS2345 against such spikes to avoid device damage. there are several practices that provide sufficient protection. clamp the voltage at the supply pins of the TPS2345 with zener diodes. since the absolute maximum voltage rating of the d evice is 15 v, this is most important on the 12-v and ? 12-v rails. the typical application diagram shows the connection of these devices (d1 and d2) in the circuit. the diodes should be placed close to the TPS2345, with short trace lengths back to the vinx and gnd pins. the maximum breakdown of these devices must be less than 15 v to properly protect the TPS2345. lower voltage zeners can also be placed on the 5-v and 3.3-v pins if desired, but the steady-state operating level of these pins provides more margin from damage levels. in addition, it may be necessary to protect the sense inputs on the 12-v and ? 12-v back-end planes, vs1 and vs4, depending on the pcb characteristics. use dedicated pcb planes for the four supplies and ground nodes and maximize the trace width of high-current runs to minimize inductance associated with the power distribution. this is recommended on both the backplane and plug-in modules. layout considerations to optimize the performance of the TPS2345, care should be taken to use good layout practice with the parts placement and etch routing of the hot swap circuit components. this includes any protection devices as well as the sense and pass elements. protection devices should be located close to the hot swap controller, and trace-lengths back to their respective pins kept to a minimum. if a decoupling capacitor is used on the vin1 supply, it also should be placed close to the part. mount the charge pump reservoir capacitor (c6 in the application diagram) close to the TPS2345, with minimal trace lengths back to the cpump and cpgnd pins. for proper operation, the three ground pins of the TPS2345 must be connected together near the device. the ground leads of the ramp and charge pump capacitors, protection diodes, and any decoupling capacitors should also tie into this node close to the part. this junction should be routed separately back to the j1 connector, where it can tie into the pcb gnd node, as opposed to tying into the ground plane elsewhere in the high-current return path. use wide traces when connecting the sense resistors and power fets into their respective current paths. when feeding these connections through from an internal power plane, use multiple vias to reduce the overall impedance of the current path. this helps reduce insertion loss across the hot swap interface, and improve the thermal performance of the pcb. additional copper plane used on the land patterns of these devices can significantly reduce their thermal impedance, reducing temperature rise in the module and improving overall reliability of the power devices. connections to the sense resistors for the vinx and csx device pins should be made with good kelvin connections to optimize the accuracy of the current-limit thresholds and slew-rate control. this is especially important for the 5-v and 3.3-v sense connections. because typical load levels on these supplies are so high, up to 10 a, board trace resistance between elements in the supply current paths becomes significant. the two sense traces for each supply should connect symmetrically to the sense resistor land pattern, in close proximity to the element leads, and not upstream or downstream from the device. trace routing back to the TPS2345 should be fairly well balanced. figure 22 illustrates two recommendations for the current sense layout.
slus503b ? march 2002 ? revised august 2002 28 www.ti.com application information udg ? 02014 *additional details ommited for clarity load current path load current path sense resistor TPS2345 * 22 21 TPS2345 * 22 21 (a) (b) figure 22. recommended layout for smd chip-sense resistor for 5-v rail
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