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" for more information + ! " interfacing motorolas mpc56x microcontroller to amds am29bdd160g flash memory application note publication number 25267 revision b amendment 0 issue date april 14, 2003
. publication# 25267 rev: b amendment/ 0 issue date: april 14, 2003 interfacing motorola?s mpc56x microcontroller to amd?s am29bdd160g flash memory application note introduction this document describes how to connect amd?s 16 megabit am29bdd160gb flash memory to the mpc56x series of processors from motorola without glue logic. topics include: two interface options, the synchronous mode enable sequence, and the register configuration for the flash and processor. the am29bdd160gb is a 16 megabit, 66 mhz high- performance burst flash that can be organized in either 512 kb by 32-bit or 1 mb by 16-bit memory array. if the 1 mb by 16-bit memory array is chosen, two am29bdd160g flash memory devices can be con- nected to the processor to provide up to a total of 1 mb by 32-bit of flash memory. the am29bdd160gb fea- tures include: 2.5-volt single power supply, burst mode, bottom boot, and simultaneous read/write operations. the mpc56x family of processors is designed for ad- vanced applications in the automotive market and currently has a maximum operation frequency of 56 mhz. mpc56x series of processors operates with 2.6- volt power supply across the full automotive tempera- ture range and support functions such as single read or write and burst read operations. power supply requirements the internal logic of the processor requires 2.6 volts. the flash can operate between 2.3 and 2.75 volts. a 2.6-volt power supply can be connected to v dd and routed to the following power pins on the processor, which are v ddf , qv ddl , nv dll and kapwr. the v cc and v ccq pins of the flash memory can interface di- rectly to the v dd pin of the microprocessor as long as the supply is regulated within 5% in order not to exceed the 2.75 v maximum that the flash can handle. the ground pins v ss and v ssf pins on the microprocessor can be connected directly to v ss of the flash memory. table 1. power and ground interface hardware reset the h reset # pin of the microprocessor must be con- nected to the reset# pin of the flash memory to reset the mpc56x and am29bdd160g devices during unex- pected power down situations as v dd and v cc voltages drops and to ensure that the flash is ready to read boot code following any system reset. table 2. reset interface data bus interface since the mpc56x processor typically has its data order configured as most significant bit to least signifi- cant bit and the am29bdd160g flash memory least significant bit to most significant bit, the address and data pins connections must be bit number reversed. in x32 mode for the flash memory, d0 of the microproces- sor must be connected to d31 of the flash memory, and vice versa. for x16 mode, two flash devices are used in parallel to still provide the 32 bit wide data and in- crease the memory size. the microprocessor d0 to d15 is connected to the high order flash d15 to d0 and the microprocessor d16 to d31 is connected to the low order flash d15 to d0. table 3. data bus interface where f1 and f2 each represent a 16-bit flash device (i.e. 2 flash at x16 = x32). note: observe bit order reversal between cpu and flash. cpu flash v dd , v ddf , qv ddl , nv dll , kapwr v cc , v ccq v ss , v ssf v ss cpu flash hreset# reset# mode cpu flash 32-bit d0?d31 d31?d0 (note) 16-bit d0?d15 d15?d0 flash 1 (note) d16? d31 d15? d0 flash 2 (note)
2 interfacing motorola?s mpc56x microcon troller to amd?s am29bdd160g flash memory address bus interface when the flash memory array is used in by 32-bit mode, 19 address lines are required to address the 512 kb by 32-bit memory array. address pins a0 to a18 of the flash memory are connected to a29 to a11 of the microprocessor. for by 16-bit mode, 20 address lines are required and address pins a-1 (a minus 1) to a18 are connected to a30 to a11 of the microprocessor. table 4. address bus interface note: observe bit order reversal between cpu and flash. to select 16-bit and 32-bit modes, the word# pin must be tied to v ss or v cc respectively. it is recom- mended that the a-1 pin of the flash memory be either tied to v ccq or v ss when the device is in the 32-bit mode to reduce potential noise injection to the flash. control bus interface the clk, ce#, oe#, we#, and adv# control signals from the flash memory must be connected to clk, csx#, oe#, we#, and ts# of the microprocessor. table 5. control bus interface note: csx# can be any of the mpc56x chip select signals; however, if botting from flash then cs0# must be used. bus operations and timings configuration before reset to select either one flash memory with 32-bit data bus or two flash memories with 16-bit data buses, the port size field in the microprocessor mpc56x br0 config- uration register must be set to 00 or 10 respectively. boot-up from flash the signal timings of the flash memory and the proces- sor are compatible to a burst frequency of at least 56 mhz. upon boot-up, asynchronous read is on the de- fault mode of the flash memory. the mpc56x microprocessors come out of reset in sequential mode with its default setting of 15 wait states, which meets all of the timing requirements for single access in asyn- chronous mode of the flash. synchronous burst mode to enter synchronous burst mode after initial boot code execution in asynchronous read mode, the following steps are required: 1. make sure the boot code is already programmed into the flash memory 2. boot up the system and copy (shadow) the burst mode configuration code into internal sram 3. exit mpc56x serialized mode by modifying the isct_ser field in the ictrl register to 10b 4. branch to the mode changing code copy in the sram 5. program am29bdd160gb configuration register 6. program mpc56x br0 register for burst mode 7. program mpc56x or0 register for burst mode 8. set burst enable (be) and (burst_en) bits in the mpc56x bbcmcr and siumcr registers 9. after the code has been executed, branch back to the code in flash enabling burst sequence to enable burst mode for the flash memory, the am29bdd160gb flash configuration register is written with the sequence as follows in table 6. table 6. am29bdd160gb configuration register write definition note: the mpc56x uses byte addresses whereas the amd flash uses 32-bit word addresses. pins 30:31 are not con- nected. therefore, address cpu a29 is attached to flash a0, instead of cpu a31. this results in an address shift left by 2 bits. ?wd? represents the 16-bit flash configuration regis- ter settings. please examine table 1 in the am29bdd160gb datasheet for information on device bus operations. the bit settings for the flash configuration register after boot-up are shown in table 7. mode cpu flash 32-bit a29 - a11 a0 - a18 16-bit a30 a-1 (a minus 1 pin) a29 - a11 a0 - a18 (note) cpu flash clk clk csx# (note) ce# oe# oe# we# we# ts# adv# we0# (32-bit mode) we# we0# (16-bit mode) we# (flash 1) we2# (16-bit mode) we# (flash 2) clock cycle 1 cycle 2 cycle 3 cycle 4 addr 555h 2aah 555h xx data aah 55h d0h wd
interfacing motorola?s mpc56x microcontr oller to amd?s am29bdd160g flash memory 3 table 7. am29bdd160gb flash configuration register the following parameters need to be modified in the configuration register by using configuration register write commands while the embedded algorithm (a pro- gram or erase operation) is not active. the rm bit must be set to zero to enable synchronous burst operations. bits bs and bl needs to be set accordingly for linear or interleaved burst and to determine the number of cy- cles per burst respectively. bit definitions that need to be modified are as follows: for example, assume that a controller is in continuous linear burst with a burst initial access delay (from the flash perspective) of 5 clock cycles and a subsequent burst access of 1 clock cycle. also assume that burst starts from the rising clock edge and the ind/wait# output is asserted during the delay. the configuration register settings are shown in table 8 . 1514131211109876543210 rm ds iad3 iad2 iad1 iad0 doc wc bs cc ? ? ? bl2 bl1 bl0 1001010xxx1000xx rm 0 for sync. burst reads 1 for async. reads iad[3:0] 0010b for data valid after 4th rising edge on next rising edge of clock bs 0 for interleaved burst 1 for linear burst bl[2:0] determines the number of consecutive burst cycles: 001 = 8 byte burst 010 = 16 byte burst 011 = 32 byte burst 100 = 64 byte burst 111 = continuous burst iad[3:0] 0000 = 2 clk cycle 0001 = 3 clk cycle 0010 = 4 clk cycle 0011 = 5 clk cycle 0100 = 6 clk cycle 0101 = 7 clk cycle 0110 = 8 clk cycle 0111 = 9 clk cycle
4 interfacing motorola?s mpc56x microcon troller to amd?s am29bdd160g flash memory table 8. am29bdd160gb flash configuration register the mpc56x generates 15 wait states by default for ei- ther a random access read or the initial read of a burst access. similarly, the am29bdd160g has a default burst initial access delay of 9 clock cycles. this means that both the mpc56x memory controller op- tion register (orx[24-27]) and the am20bdd160g configuration register (iad [3:0]) must be modified to insure correct operation. it is important to note here that the number of mpc56x wait states may differ from the number of clock cycles comprising the burst initial access delay. the first wait state (clock cycle) for the mpc56x is the clk cycle that puts the address on the bus and then latches it with the falling edge of both the clk and adv#. however, the first clock cycle for the burst initial access delay is the clock with either the first valid clock edge after adv# assertion or the rising edge of adv#. see figure 1 for a graphic of burst ini- tial access delay. the burst initial access delay is defined as the number of clk cycles that must elapse from the first valid clock edge after adv# assertion (or the rising edge of adv#) until the first valid clk edge when the data is valid. see table 1 for a breakdown of configuration register settings and the correspond- ing burst initial access delay. figure 1 and table 1 are valid for the majority of applications, and have the following operating conditions. ? burst initial access starts with the first clk rising edge after adv# assertion. ? configuration register 6 is set to 1 (cr[6] = 1). burst starts and data outputs on rising clk edge. with these operating conditions valid for table 1 and table 1, there is a one cycle (wait state) difference be- tween the flash and the controller, with the controller being one cycle greater. figure 1. burst initial access delay 1514131211109876543210 rm ds iad3 iad2 iad1 iad0 doc wc bs cc ? ? ? bl2 bl1 bl0 0000110011000111 valid d d d valid 1 2 3 clk adv # a18- a0 dq31-dq0 burst initial access delay 3 clk cycles burst initial access delay d0 d1 d2 d3
interfacing motorola?s mpc56x microcontr oller to amd?s am29bdd160g flash memory 5 table 9. burst initial access delay configuration register setting burst initial access delay (clk cycles) cr13 cr12 cr11 cr10 0000 2 0001 3 0010 4 0011 5 0100 6 0101 7 0110 8 0111 9 table 10. am29bdd160g and mpc56x access delays am29bdd160g mcp65x system clock speed configuration register iad[3:0] burst initial access delay total wait states orx configuration register orx[24-27] 56 mhz 0010b 4 5 0011b 66 mhz 0001b 3 4 0010b table 11. mpc56x brx configuration register bit name value comment 0?16 base address user defined flash base address 17?19 address type user defined user assign the flash to any address space 20?21 port size 00b 00 ? 32 bit port size 10 ? 16 bit port size 22 0 reserved 23 write protect user defined 0 ? for flash programming 1 ? for flash reading only 24 0 reserved 25 burst length user defined 0 ? burst access up to 4 words 1 ? burst access up to 8 words 26 webs 0 27 tbdip 0 do not toggle bdip 28 lbdip 0 no late bdip 29 seta 0 no external ta 30 burst inhibit user defined 0 ? enable burst access 1 ? disable burst access 31 valid 1 activate current bank
6 interfacing motorola?s mpc56x microcon troller to amd?s am29bdd160g flash memory the mpc56x operates in serialized mode where in- structions are executed serialized after boot-up. it is recommended for the mpc56x to exit the sequential mode immediately after boot-up since reading in syn- chronous burst mode with the default cpu configuration will degrade flash memory performance. by modifying the isct_ser field in the ictrl regis- ter to 0b1xxh (0b101, 0b110, or 0b111h) for ?an indirect change of flow?, system performance can be enhanced by allowing the cpu to suspend serialized mode. for best results, the register should be set to 0b111h, since the rcpu wil output a show cycle on branches with settings of 0b101 or 0b110h. calculating bus timings to calculate the bus timings for the cpu to flash inter- face, the following parameters need to be considered: time for address to become valid on to the address bus time for flash memory access time for cpu data setup time for system margin that includes clock skew, slew, and propagation delay time for burst access as an example, a 56 mhz cpu will be illustrated. example: 56 mhz operation initial access time (n + 1) * clk period ? data setup ? system margin where n is the burst initial access delay 4 * (17.86?6?1) ns 64.44 ns burst access time clk period ? data setup ? system margin burst access time (17.86 ? 6 ? 1) ns 10.86 ns taking into account the cycle in which the address is presented by the controller, a 5-1-1-1 system is possi- ble for 56 mhz operation. the ?5? represents the total number of cycles the mpc56x must wait before the ini- tial data can be read in a non-serialized operation. the ?1?s represent the cycles needed for each additional table 12. mpc56x orx configuration register bit name value comment 0?15 address mask user defined 0xffe0 for mask in 16 bit setup 0xffc0 for mask in 32 bit setup 16 address mask 0 bit 16 must be on always 17?19 address type mask user defined user defined 20 csnt 0 21?22 acs 00b no delay needed 23 ehtr 0 not needed 24?27 scy 011b initialize 3 wait states + 2 cycles 28?30 bscy 000b initialize 1 clock period per beat 31 trlx 0 not needed table 13. timing parameters obtained from datasheets frequency 56 mhz source cycle time 17.86 ns 1/freq. data setup 6.0 ns mpc56x system margin 1.0 ns mpc56x initial access time < 60 ns am29bdd160g burst access time < 10.0 ns am29bdd160g
interfacing motorola?s mpc56x microcontr oller to amd?s am29bdd160g flash memory 7 figure 2. 56 mhz 5-1-1-1 burst read hardware interface the following two figures depicts the flash cpu interfaces. figure 3. one x32 flash device connected to the microprocessor with the flash word# pin tied to v dd 5 clock initial access time t bacc t lbs t lah clk address adv# data oe# t data setup data data data data 17.86 ns 2 clock initial access delay clk adv# a18 - a0 dq31 - dq0 we# oe# ce# clk ts# a11 - a29 dq0 - dq31 wex# oe# csx# processor flash memory
8 interfacing motorola?s mpc56x microcon troller to amd?s am29bdd160g flash memory figure 4. two x16 flash devices connected to the microprocessor with the flash word# pin tied to v ss clk adv# a18-a - 1 dq15 - dq0 we# oe# clk ts# a11 - a30 dq0 - dq31 wex# oe# ce# csx# processor flash device #1 clk adv# a18-a - 1 dq31 - dq16 we# oe# ce# flash device #2
interfacing motorola?s mpc56x microcontr oller to amd?s am29bdd160g flash memory 9 appendix a valid part numbers are for revision 4a. all other part numbers for revision 4 and earlier are obsolete. valid combinations for pqfp packages order number am29bdd160gt54d, am29bdd160gb54d ki, ke am29bdd160gt65d, am29bdd160gb65d am29bdd160gt64c, am29bdd160gb64c am29bdd160gt65a, am29bdd160gb65a obsolete combinations for pqfp packages order number am29bdd160gt80c, am29bdd160gb80c ki, ke am29bdd160gt90a, am29bdd160gb90a valid combinations for fortified bga packages order number package marking am29bdd160gt54d, am29bdd160gb54d bd160gt54d bd160gb54d am29bdd160gt65d, am29bdd160gb65d bd160gt65d bd160gb65d am29bdd160gt64c, am29bdd160gb64c bd160gt64c bd160gb64c am29bdd160gt65a, am29bdd160gb65a bd160gt65a bd160gb65a obsolete combinations for fortified bga packages order number package marking am29bdd160gt80c, am29bdd160gb80c bd160gt80c bd160gb80c am29bdd160gt90a, am29bdd160gb90a bd160gt90a bd160gb90a
10 interfacing motorola?s mpc56x microcon troller to amd?s am29bdd160g flash memory revision summary revision a (january 17, 2002) initial release. revision b (april 14, 2003) table 3. data bus interface updated table, added note. table 4. address bus interface updated table, added note. table 5. control bus interface updated table, added note. bus operations and timings modified step 3 under synchronous burst mode. updated table 6, am29bdd160g configuration reg- ister write definition, added note. updated table 7, am29bdd160gb flash configura- tion register. added table 8, configuration register settings example. added table 9, burst initial access delay. added table 10, am29bdd160g and mpc56x access delays. calculating bus timings updated calculations for example: 56 mhz operation. appendix a new section. trademarks copyright ? 2003 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc.

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