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asahi kasei [ak9813a] dad03e-00 1999/05 - 1 - ak9813a 12ch 8bit d/a converter with eeprom general description the ak9813a includes 12 channel, 8bit d/a converters with on-chip output buffer amps and it is capable to store the input digital data of each dac by on-chip non-volatile cmos eeprom. the ak9813a is optimally designed for various circuit adjustments for consumer and industrial equipments and it is ideally suited for replacing mechanical trimmers. features ? eeprom section 12 words ? 8bit ? 4 organization for dac ? d/a converter section 12 channels resolution : 8bit dnl : -1 a +2 lsb inl : ? 1.5 lsb analog output voltage range : gnd a vcc ? operating voltage range digital section : 2.7v a 5.5v analog section : 5.0v ? 0.5v,3.3v ? 0.3v ? 24pin vsop block diagram
asahi kasei [ak9813a] dad03e-00 1999/05 - 2 - ? ? ? ? ordering guide AK9813AF -10 to +85 c 24-pinvsop ? ? ? ? y pin layout
asahi kasei [ak9813a] dad03e-00 1999/05 - 3 - ? ? ? ? y pin description(1) no. pin name i/o function 20 di i serial data input pin sel=high : 16bit data input format sel=low : 14bit data input format (sel=high:cs i/f) ak9813a reads out the data with lsb first in the 16bit shift register to do pin synchronously with falling edge of clk. when the cs pin is high level, the do pin becomes high impedance. in status mode, the do pin outputs ready/busy status. 17 do o (sel=low:ld i/f) ak9813a reads out the data with msb first in the 14bit shift register to do pin synchronously with falling edge of clk. in write mode, the do pin outputs ready/busy status. 19 clk i shift clock input pin(schmitt-trigger input) ak9813a takes in the data from di pin synchronously with rising edge of the clk pin. the data are transferred to the internal shift register. chip select input pin(schmitt-trigger input) the cs/ld is internally pulled up to vcc. (sel=high:cs i/f) after the cs pin changes from high level to low level while the clk pin is high level, the ak9813a can input the data to the internal shift register and takes in the data from the di pin synchronously with the rising edge of the clk pin. after the cs pin changes from high level to low level while the clk pin is low level, the ak9813a becomes the status mode and reads out the ready/busy status to the do pin. when the cs pin changes from low level to high level regardless of low/high level of the clk pin, the ak9813a removes from the status mode to the normal mode. the cs pin usually should be kept at high level. 18 cs/ld i (sel=low:ld i/f) when the ld pin receives high pulse, the data of the internal shift register is transferred to the internal decoder or the register for d/a. the ld pin usually should be kept at low level.
asahi kasei [ak9813a] dad03e-00 1999/05 - 4 - ? ? ? ? pin description(2) no. pin name i/o function 1 | 12 ao1 | ao12 o 8bit d/a outputs with op-amp 14 vcc - digital section power supply pin 23 gnd - digital section ground pin 13 vdd - op-amp and d/a section power supply 24 vss - op-amp and d/a section ground (sel=high:cs i/f) in auto read operation and ecl operation, the address of eeprom is selected by the ea0 and the ea1 pins. 21 22 ea0 ea1 i (sel=low:ld i/f) the address of eeprom is selected by the ea0 and the ea1 pins. 16 ecl i when the ecl pin receives high pulse, the data in eeprom is automatically loaded to each corresponding d/a, starting from ao1 to ao12 in order. then each d/a output is settled to pre-determined value. 15 sel i input data format select pin sel=high : cs i/f sel=low : ld i/f after power-up, this pin should be kept either at "high" or "low."
asahi kasei [ak9813a] dad03e-00 1999/05 - 5 - data configuration ak9813a have a shift register in order to control the chip. when the sel pin is "h"(cs i/f), the shift register becomes 16bit configuration and the data on the di pin should be loaded with lsb first. when the sel pin is "l"(ld i/f), the shift register becomes 14bit configuration and the data on the di pin is loaded with msb first. the following description shows the configuration of the shift register. the data set consist of 2-bits for the control of the internal eeprom, 2-bits for the address of the eeprom (cs i/f only), 4-bits for select of d/a converter and 8-bits for the digital input data of the 8bit d/a converter and total data set is 16bits or 14bits. 1 { shift register configuration : sel=high(cs i/f) output voltage for d/a converter d7 d6 d5 d4 d3 d2 d1 d0 output voltage for d/a a1 a0 eeprom address 00000000 = gnd=vss 0 1 address : 0 00000001 = vdd/255 ? 1 0 1 address : 1 00000010 = vdd/255 ? 2 1 0 address : 2 1 1 address : 3 11111110 = vdd/255 ? 254 11111111 = vdd d/a converter channel selection d11 d10 d9 d8 d/a channel d11 d10 d9 d8 d/a channel 0000 don't care 1000 ao8 0001 ao1 1001 ao9 0010 ao2 1010 ao10 0011 ao3 1011 ao11 0100 ao4 1100 ao12 0101 ao5 1101 can't use 0110 ao6 1110 can't use 0111 ao7 1111 don't care (note) above "don't care" state is valid only when ak9813a is in dac mode or write mode. refer to the following section "instruction set" about mode.
asahi kasei [ak9813a] dad03e-00 1999/05 - 6 - 2 { shift register configuration:sel=low(ld i/f) output voltage for d/a converter d0 d1 d2 d3 d4 d5 d6 d7 output voltage for d/a ea1 ea0 eeprom address 00000000 = gnd=vss 0 0 address : 0 10000000 = vdd/255 ? 1 0 1 address : 1 01000000 = vdd/255 ? 2 1 0 address : 2 1 1 address : 3 01111111 = vdd/255 ? 254 note) 11111111 = vdd eeprom address is selected by t he ea0 and ea1 pins. d/a converter channel selection d8 d9 d10 d11 d/a channel d8 d9 d10 d11 d/a channel 0000 don't care 1000 ao8 0001 ao1 1001 ao9 0010 ao2 1010 ao10 0011 ao3 1011 ao11 0100 ao4 1100 ao12 0101 ao5 1101 can't use 0110 ao6 1110 can't use 0111 ao7 1111 don't care (note) above "don't care" state is valid only when ak9813a is in dac mode or write mode. refer to the following section "instruction set" about mode.
asahi kasei [ak9813a] dad03e-00 1999/05 - 7 - instruction set the ak9813a can be controlled for the following mode. the following mode is common to the ld i/f and the cs if. when ld i/f is selected, "a1" and "a0" are set by the external pins (ea0 pin and ea1 pin). 1 { dac mode(external di pin -> d/a converter) [ ? :don't care] a1 a0 cl wr d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function ?? 0 0 d/a channel digital data for d/a d/a output 2 { call mode(internal eeprom -> d/a converter) [ ? :don't care] a1 a0 cl wr d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function address 1 0 d/a channel ???????? read the output of d/a converter is set by the data in the internal eeprom. 3 { all call mode(internal eeprom -> d/a converter) [ ? :don't care] a1 a0 cl wr d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function address 100000 ???????? all channel read the outputs of all d/a converters are set by the data in the internal eeprom. internal ecl function 4 { write enable mode(internal eeprom write enable) [ ? :don't care] a1 a0 cl wr d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function ?? 110000 ???????? write enable after write enable mode is executed, the programming to the internal eeprom is enabled. upon power-up and after the execution of the ecl function, the ak9813a is in the programming disable state. 5 { write disable mode(internal eeprom write disable) [ ? :don't care] a1 a0 cl wr d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function ?? 111111 ???????? write disable after write disable mode is executed, the programming to the internal eeprom is disabled. 6 { write mode(external di pin -> internal eeprom) [ ? :don't care] a1 a0 cl wr d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function address 0 1 d/a channel digital data for d/a write the digital data for d/a (d0 a d7) is written into the specified address in the internal eeprom. the state of the internal eeprom must be the programming enable state. 7 { read mode(internal eeprom -> external do pin) [ ? :don't care] a1 a0 cl wr d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function address 1 1 d/a channel ???????? eeprom data output the do pin outputs the data in the internal eeprom synchronously with the falling edge of of the input pulse of the clk pin.
asahi kasei [ak9813a] dad03e-00 1999/05 - 8 - functional description 1 { timing diagram for cs i/f (sel="h") 1.dac mode:the internal eeprom is not used. 2.write enable/disable mode:the programming state of the internal eeprom is set. 3.call mode: the output of the d/a is set by the data in the internal eeprom.
asahi kasei [ak9813a] dad03e-00 1999/05 - 9 - 4.all call mode : the outputs of the all d/as are set by the data in the internal eeprom. the d/a outputs are set from ao1 to ao12 in order. 5.write mode:the digital input data for d/a converter is written into the internal eeprom. 6.read mode:the data in the internal eeprom is read from the do pin.
asahi kasei [ak9813a] dad03e-00 1999/05 - 10 - 7.status mode: the do pin outputs the ready/busy status from the do pin. 8.ecl function : for "h" pulse to the ecl pin, the data in the selected address in the internal eeprom is automatically loaded. then each d/a converter output is settled to pre-determined value. 9. transfer mode for the cascade connection in case that ak9813a devices are connected in cascade, the ak9813a under programming cycle can transfer the data to the other ak9813a. the some ak9813a devices can be operated by the common cs signal at the same time. please note that the input data into to the ak9813a under programming cycle should be all"0" when the cs pin is changed from "l" to "h". if data except all"0" is input into the ak9813a under programming cycle, accidental data disturbance may occur.
asahi kasei [ak9813a] dad03e-00 1999/05 - 11 - 2 { timing diagram for ld i/f (sel ="l") 1.dac mode:the internal eeprom is not used. 2.write enable/disable mode:the programming state of internal eeprom is set. 3.call mode: the output of the d/a is set by the data in the internal eeprom.
asahi kasei [ak9813a] dad03e-00 1999/05 - 12 - 4.all call mode : the outputs of the all d/as are set by the data in the internal eeprom. the d/a outputs are set from ao1 to ao12 in order. 5.write mode:the digital input data for d/a converter is written into the internal eeprom. (note) * in case that ak9813a devices are connected in cascade, when a ak9813a device is under programming cycle, the ak9813a device under programming cycle can not transfer the data to the other ak9813a device and some ak9813a devices can not be operated by the common cs signal at the same time. * while programming cycle, the cs/ld pin should be "l". * when the ready/busy signal from the do pin is verified, the cs pin should be changed from "h" to "l" and kept at "l". if the cs pin is kept at "h", the ready/busy signal does not output correctly.
asahi kasei [ak9813a] dad03e-00 1999/05 - 13 - 6.read mode:the data in the internal eeprom is read from the do pin. 7.ecl function: when the ecl pin received high pulse, the data in eeprom is automatically loaded to each corresponding d/a, and starting from ao1 to ao12 in order. then each d/a output is settled to pre-determined value.
asahi kasei [ak9813a] dad03e-00 1999/05 - 14 - absolute maximum ratings parameter symbol condition spec. units power supply input voltage ambient temperature storage temperature vcc vio ta tst relative to gnd relative to gnd -0.3 ~ +6.5 -0.3 ~ vcc+0.3 -10 ~ +85 -65 ~ +150 v v c c recommended operating conditions parameter symbol conditions min typ max units power supply 1 (digital section) vcc 2.7 5.5 v vdd1 4.5 5.0 5.5 power supply 2 (dac,amp sections) vdd2 vdd 3 vcc 3.0 3.3 3.6 v analog output source current 1 ial 1 ma analog output sink current 1 iah vdd=5.0v ? 0.5v 1ma analog output source current 2 ial 500 ua analog output sink current 2 iah vdd=3.3v ? 0.3v 500 ua 0.001 uf load crcuit-a 0.8 1.0 uf analog output load capacitance aoc load circuit-b 1.0 uf load circuit-a load circuit-b
asahi kasei [ak9813a] dad03e-00 1999/05 - 15 - electrical characteristics ? ? ? ? dc characteristics (1)digital section (vcc=2.7v ~ 5.5v,vdd=5.0v ? 0.5v or 3.3v ? 0.3v(vdd 3 vcc),gnd,vss=0v,ta=-10 ~ 85 c) parameter symbol pin conditions min max units power supply (digital section) vcc 2.7 5.5 v operating current (read) (1)(2) icc vcc clk=1mhz 1.5 ma leakage current ili clk,di cs/ld ea0,ea1 ecl,sel vin=vcc -10.0 10.0 ua high level input voltage1 vih 0.5 ? vcc v low level input voltage1 vil di ea0,ea1 ecl,sel 0.2 ? vcc v high level input voltage2 vih 0.6 ? vcc v low level input voltage2 vil cs/ld clk 0.15 ? vcc v voh1 4.5v vcc 5.5v ioh=-400ua vcc-0.4 v high level output voltage voh2 2.7v vcc<4.5v ioh=-200ua 0.7 ? vcc v vol1 4.5v vcc 5.5v iol=1.0ma 0.4 v low level output voltage vol2 do 2.7v vcc<4.5v iol=1.0ma 0.4 v (1) all input pins are connected to either vcc or gnd. (2) do=open
asahi kasei [ak9813a] dad03e-00 1999/05 - 16 - (2)analog section (2-1)vdd=5.0v ? 0.5v (vcc=2.7v ~ 5.5v,vdd=5.0v ? 0.5v (vdd 3 vcc),gnd,vss=0v,ta=-10 ~ 85 c) parameter symbol pin conditions min typ max units power supply1 (analog section) vdd1 vdd 3 vcc 4.5 5.0 5.5 v power dissipation1 (analog section) idd1 vdd ao1 ~ ao12=open 10.0 ma resolution res 8 bits integral (3) non-linearity :inl le -1.5 1.5 lsb differential non-linearity :dnl d le ao1 | ao12 ao1 ~ ao12=open 0.05v ao vdd-0.1v -1.0 2.0 lsb buffer-amp minimum output voltage 1 vaol1 ial = 0ua data= 00(hex) gnd 0.05 v buffer-amp minimum output voltage 2 vaol2 ial = 500ua data= 00(hex) -0.1 0.1 v buffer-amp minimum output voltage 3 vaol3 iah = 500ua data= 00(hex) gnd 0.1 v buffer-amp minimum output voltage 4 vaol4 ial = 1ma data= 00(hex) -0.2 0.2 v buffer-amp minimum output voltage 5 vaol5 iah = 1ma data= 00(hex) gnd 0.2 v buffer-amp maximum output voltage 1 vaoh1 iah = 0ua data= ff(hex) vdd-0.1 vdd v buffer-amp maximum output voltage 2 vaoh2 ial = 500ua data= ff(hex) vdd-0.2 vdd v buffer-amp maximum output voltage 3 vaoh3 iah = 500ua data= ff(hex) vdd-0.2 vdd+0.2 v buffer-amp maximum output voltage 4 vaoh4 ial = 1ma data= ff(hex) vdd-0.3 vdd v buffer-amp maximum output voltage 5 vaoh5 ao1 | ao12 iah = 1ma data= ff(hex) vdd-0.3 vdd+0.3 v (3) integral non-linearity is the error between the actual line and the ideal line. the ideal line exhibits a perfect linear d/a converter output characteristic between the input digital data"00" and the input digital data"ff".
asahi kasei [ak9813a] dad03e-00 1999/05 - 17 - (2-2) vdd=3.3v ? 0.3v (vcc=2.7v ~ 3.6v,vdd=3.3v ? 0.3v (vdd 3 vcc),gnd,vss=0v,ta=-10 ~ 85 c) parameter symbol pin conditions min typ max units power supply 2 (analog section) vdd2 vdd 3 vcc 3.0 3.3 3.6 v power dissipation2 (analog section) idd2 vdd ao1 ~ ao12=open 7.0 ma resolution res 8 bits integral (3) non-linearity :inl le -1.5 1.5 lsb differential non-linearity :dnl d le ao1 ~ ao12=open 0.15v ao vdd-0.15v -1.0 2.0 lsb output voltage for input data "05" 0.1 0.15 v output voltage for input data "fa" ao1 | ao12 ao1 ~ ao12=open vdd=3.3v 3.15 3.25 v buffer-amp minimum output voltage 6 vaol6 ial = 0ua data= 00(hex) gnd 0.05 v buffer-amp minimum output voltage 7 vaol7 ial = 250ua data= 00(hex) -0.1 0.1 v buffer-amp minimum output voltage 8 vaol8 iah = 250ua data= 00(hex) gnd 0.1 v buffer-amp minimum output voltage 9 vaol9 ial = 500ua data= 00(hex) -0.2 0.2 v buffer-amp minimum output voltage 10 vaol10 iah = 500ua data= 00(hex) gnd 0.2 v buffer-amp maximum output voltage 6 vaoh6 iah = 0ua data= ff(hex) vdd-0.1 vdd v buffer-amp maximum output voltage 7 vaoh7 ial = 250ua data= ff(hex) vdd-0.2 vdd v buffer-amp maximum output voltage 8 vaoh8 iah = 250ua data= ff(hex) vdd-0.2 vdd+0.2 v buffer-amp maximum output voltage 9 vaoh9 ial = 500ua data= ff(hex) vdd-0.3 vdd v buffer-amp maximum output voltage 10 vaoh10 ao1 | ao12 iah = 500ua data= ff(hex) vdd-0.3 vdd+0.3 v (3) integral non-linearity is the error between the actual line and the ideal line. the ideal line exhibits a perfect linear d/a converter output characteristics between the input digital data"05" and the input digital data"fa".
asahi kasei [ak9813a] dad03e-00 1999/05 - 18 - ? ? ? ? ac characteristics (1) cs i/f, ld i/f : common timing (vcc=2.7v ~ 5.5v,vdd=5.0v ? 0.5v or 3.3v ? 0.3v (vdd 3 vcc),gnd,vss=0v,ta=-10 ~ 85 c) parameter symbol conditions min max units vcc rise time tvcr 50 ms auto address hold time tvah 3.5 ms auto read time tpor test load2 3.5 ms ecl "h" pulse width tecw1 tecw2 *1 *2 100 250 ns ns external call time tecl test load2 3.5 ms address set up time tesu1 tesu2 *1 *2 50 100 ns ns ecl address hold time teah 3.5 ms repeat call prohibition time tecc1 tecc2 *1 *2 20 100 ns ns *1:4.5v vcc 5.5v *2:2.7v vcc<4.5v
asahi kasei [ak9813a] dad03e-00 1999/05 - 19 - (2)cs i/f timing (vcc=2.7v ~ 5.5v,vdd=5.0v ? 0.5v or 3.3v ? 0.3v (vdd 3 vcc),gnd,vss=0v,ta=-10 ~ 85 c) parameter symbol conditions min max units clock "l" pulse width tckl1 tckl2 *5 *6 200 500 ns ns clock "h" pulse width tckh1 tckh2 *5 *6 200 500 ns ns clock rising time clock falling time tcr tcf 200 ns data set up time tdsu1 tdsu2 *5 *6 30 150 ns ns data hold time tdhd1 tdhd2 *5 *6 60 150 ns ns cs set up time tcsu1 tcsu2 *5 *6 100 250 ns ns cs hold time tcch 200 ns dac etc *3,*4,*5 *3,*4,*6 100 250 ns ns write *4,*5 *4,*6 10 15 ms ms call read 15 us cs "h" hold time tcsh all call 3.5 ms data output enable time tdod1 tdod2 *5 *6 200 500 ns ns data output float delay tdoz1 tdoz2 *5 *6 200 500 ns ns data output delay tdoc1 tdoc2 test load1 *5 *6 170 300 ns ns dac test load2 200 us call test load2 250 us d/a output setting time tcsd all call test load2 3.5 ms status set up time tssu 100 ns status hold time tshd1 tshd2 *5 *6 100 250 ns ns *3: please refer to "dac etc" regarding cs "h" hold time before status mode execute. *4: if ready/busy="h" is confirmed in status mode in the write mode, the cs pin can be changed to "l" shorter than the values specified on above. please refer to "dac etc" regarding cs "h" hold time in case that ak9813 to be connected in cascade is under programming cycle(ready/busy="l"). *5: 4.5v vcc 5.5v *6: 2.7v vcc<4.5v
asahi kasei [ak9813a] dad03e-00 1999/05 - 20 -
asahi kasei [ak9813a] dad03e-00 1999/05 - 21 - (3)ld i/f timing (vcc=2.7v ~ 5.5v,vdd=5.0v ? 0.5v or 3.3v ? 0.3v (vdd 3 vcc),gnd,vss=0v,ta=-10 ~ 85 c) parameter symbol conditions min max units clock "l" pulse width tckl1 tckl2 *5 *6 200 500 ns ns clock "h" pulse width tckh1 tckh2 *5 *6 200 500 ns ns clock rising time clock falling time tcr tcf 200 ns data set up time tdch1 tdch2 *5 *6 30 150 ns ns data hold time tchd1 tchd2 *5 *6 60 150 ns ns load set up time tchl 200 ns load hold time tldc1 tldc2 *5 *6 100 250 ns ns tldh1 tldh2 modes except *5 read mode *6 100 250 ns ns load "h" pulse width tldh3 read mode 5 us data output delay tdo1 tdo2 test load1 *5 test load1 *6 170 300 ns ns dac test load2 200 us call test load2 250 us d/a output setting time tlddd all call test load2 3.5 ms address set up time tasu1 tasu2 *5 *6 100 200 ns ns write address hold time twahd1 twahd2 *5 *6 20 100 ns ns programming cycle twrt *7 15 ms ready signal delay tryd test load1 0.4 us repeat write prohibition time tryh1 tryh2 test load1 *5 test load2 *6 20 100 ns ns call,read mode 15 us read hold time trhd all call mode 3.5 ms call,read mode 15 us read address hold time trahd all call mode 3.5 ms *7: if ready/busy="l" is confirmed in status mode in the write mode, the next operation can be started.
asahi kasei [ak9813a] dad03e-00 1999/05 - 22 - * please refer to the data timing regarding the input timing for the di pin
asahi kasei [ak9813a] dad03e-00 1999/05 - 23 - * please refer to the data timing regarding the input timing for the di pin * ac measurement circuit test load1 test load2 ac test point digital input/output level : 50% 20% of vcc analog output level : 90% 10% of vcc
important notice z these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. z akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. z it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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