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product specification asd0401 ultra low power 20/40/65/80 msps, 10-bit analog-to-digital converter functional block diagram adc clk control interface c k p c k n p d _ n d v s s d v d d d v d d c k a v s s a v d d ip in d ck_ext d v s s c k cm_ext s l p _ n c m _ e x t b c orng oe_n 10 figure 1 : functional block diagram vestre rosten 81, 7075 tiller, norway org. no: no 991 265 163mva phone: +47 73 10 29 00, fax: +47 73 10 29 19 www.arcticsilicon.com page 1 of 16 confidential description the asd0401 is a high performance ultra low power analog-to-digital converter (adc). the adc employs internal reference circuitry, a cmos control interface and cmos output data, and is based on a proprietary structure. digital error correction is employed to ensure no missing codes in the complete full scale range. two idle modes with fast startup times exist. the entire chip can either be put in standby mode or power down mode. the two modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. the asd0401 has a highly linear tha optimized for frequencies up to nyquist. the differential clock interface is optimized for low jitter clock sources and supports lvds, lvpecl, sine wave and cmos clock inputs. features 10-bit resolution 20/40/65/80 msps maximum sampling rate ultra-low power dissipation: 15/25/38/46 mw 61.6 db snr at 80 msps and 8 mhz f in internal reference circuitry 1.8 v core supply voltage 1.7 C 3.6 v i/o supply voltage parallel cmos output 40 pin qfn package pin compatible with asd0501 applications medical imaging portable test equipment digital oscilloscopes if communication
product specification table of contents functional block diagram ............................................... 1 features ............................................................................ 1 applications ..................................................................... 1 description ....................................................................... 1 specifications ................................................................... 3 digital and timing specifications ..................................... 8 timing diagram ............................................................... 9 absolute maximum ratings ............................................. 9 pin configuration and description ................................. 10 recommended usage ..................................................... 12 package mechanical data .............................................. 15 product information ....................................................... 16 ordering information ...................................................... 16 datasheet status .............................................................. 16 asd0401 rev v3.2 , 2010.04.23 confidential page 2 of 16
product specification specifications avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, 20/40/65/80msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted parameter condition min typ max unit dc accuracy no missing codes guaranteed offset error midscale offset 1 lsb gain error full scale range deviation from typical +/- 6 %fs dnl differential nonlinearity +/- 0.15 lsb inl integral nonlinearity +/- 0.2 lsb v cm common mode voltage output v avdd /2 v analog input input common mode analog input common mode voltage v cm -0.1 v cm +0.2 v full scale range differential input voltage range 2.0 vpp input capacitance differential input capacitance 2 pf bandwidth input bandwidth 500 mhz power supply core supply voltage supply voltage to all 1.8v domain pins. see pin configuration and description 1.7 1.8 2.0 v i/o supply voltage output driver supply voltage (ovdd). should be higher than or equal to core supply voltage (v ovdd v dvdd ) 1.7 2.5 3.6 v asd0401 rev v3.2 , 2010.04.23 confidential page 3 of 16
product specification asd0401 l20 avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, fs=20msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted. parameter condition min typ max unit performance snr signal to noise ratio f in = 2 mhz 61.7 dbfs f in = 8 mhz 60 61.6 dbfs f in @ fs/2 61.6 dbfs f in = 20 mhz 61.6 dbfs sndr signal to noise and distortion ratio f in = 2 mhz 61.7 dbfs f in = 8 mhz 60 61.6 dbfs f in @ fs/2 60.5 dbfs f in = 20 mhz 61.6 dbfs sfdr spurious free dynamic range f in = 2 mhz 80 dbc f in = 8 mhz 70 81 dbc f in @ fs/2 70 dbc f in = 20 mhz 80 dbc hd2 second order harmonic distortion f in = 2 mhz -90 dbc f in = 8 mhz -80 -90 dbc f in @ fs/2 -90 dbc f in = 20 mhz -90 dbc hd3 third order harmonic distortion f in = 2 mhz -80 dbc f in = 8 mhz -70 -81 dbc f in @ fs/2 -70 dbc f in = 20 mhz -80 dbc enob effective number of bits f in = 2 mhz 10.0 bits f in = 8 mhz 9.7 9.9 bits f in @ fs/2 9.8 bits f in = 20 mhz 9.9 bits power supply analog supply current 5.7 ma digital supply current digital core supply 1.0 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext enabled 1.7 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext disabled 1.2 ma analog power 10.3 mw digital power ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 4.8 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 15.1 mw power down 9.9 w sleep mode power dissipation, sleep mode 7.7 mw clock inputs max. conversion rate 20 msps min. conversion rate 3 msps asd0401 rev v3.2 , 2010.04.23 confidential page 4 of 16
product specification asd0401 l40 avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, fs=40msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted. parameter condition min typ max unit performance snr signal to noise ratio f in = 2 mhz 61.6 dbfs f in = 8 mhz 60.0 61.6 dbfs f in @ fs/2 61.6 dbfs f in = 30 mhz 61.5 dbfs sndr signal to noise and distortion ratio f in = 2 mhz 61.6 dbfs f in = 8 mhz 60.0 61.6 dbfs f in @ fs/2 61.2 dbfs f in = 30 mhz 61.4 dbfs sfdr spurious free dynamic range f in = 2 mhz 80 dbc f in = 8 mhz 70 81 dbc f in @ fs/2 72 dbc f in = 30 mhz 80 dbc hd2 second order harmonic distortion f in = 2 mhz -90 dbc f in = 8 mhz -80 -90 dbc f in @ fs/2 -85 dbc f in = 30 mhz -85 dbc hd3 third order harmonic distortion f in = 2 mhz -80 dbc f in = 8 mhz -70 -81 dbc f in @ fs/2 -72 dbc f in = 30 mhz -80 dbc enob effective number of bits f in = 2 mhz 9.9 bits f in = 8 mhz 9.7 9.9 bits f in @ fs/2 9.9 bits f in = 30 mhz 9.9 bits power supply analog supply current 9.3 ma digital supply current digital core supply 1.7 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext enabled 3.1 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext disabled 2.2 ma analog power 16.7 mw digital power ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 8.6 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 25.3 mw power down 9.7 w sleep mode power dissipation, sleep mode 11.3 mw clock inputs max. conversion rate 40 msps min. conversion rate 20 msps asd0401 rev v3.2 , 2010.04.23 confidential page 5 of 16
product specification asd0401 l65 avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, fs=65msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted. parameter condition min typ max unit performance snr signal to noise ratio f in = 8 mhz 60.0 61.6 dbfs f in = 20 mhz 61.6 dbfs f in @ fs/2 61.5 dbfs f in = 40 mhz 61.3 dbfs sndr signal to noise and distortion ratio f in = 8 mhz 60.0 61.6 dbfs f in = 20 mhz 61.6 dbfs f in @ fs/2 60.4 dbfs f in = 40 mhz 61.1 dbfs sfdr spurious free dynamic range f in = 8 mhz 70 77 dbc f in = 20 mhz 77 dbc f in @ fs/2 70 dbc f in = 40 mhz 75 dbc hd2 second order harmonic distortion f in = 8 mhz -80 -90 dbc f in = 20 mhz -95 dbc f in @ fs/2 -85 dbc f in = 40 mhz -90 dbc hd3 third order harmonic distortion f in = 8 mhz -70 -77 dbc f in = 20 mhz -77 dbc f in @ fs/2 -70 dbc f in = 40 mhz -75 dbc enob effective number of bits f in = 8 mhz 9.7 9.9 bits f in = 20 mhz 9.9 bits f in @ fs/2 9.7 bits f in = 40 mhz 9.9 bits power supply analog supply current 13.8 ma digital supply current digital core supply 2.6 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext enabled 4.9 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext disabled 3.4 ma analog power 24.8 mw digital power ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 13.2 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 38.0 mw power down 9.3 w sleep mode power dissipation, sleep mode 15.7 mw clock inputs max. conversion rate 65 msps min. conversion rate 40 msps asd0401 rev v3.2 , 2010.04.23 confidential page 6 of 16
product specification asd0401 l80 avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, fs=80msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted. parameter condition min typ max unit performance snr signal to noise ratio f in = 8 mhz 60.0 61.6 dbfs f in = 20 mhz 61.2 dbfs f in = 30 mhz 61.3 dbfs f in @ fs/2 61.3 dbfs sndr signal to noise and distortion ratio f in = 8 mhz 60.0 61.3 dbfs f in = 20 mhz 60.7 dbfs f in = 30 mhz 61.0 dbfs f in @ fs/2 59.0 dbfs sfdr spurious free dynamic range f in = 8 mhz 70 75 dbc f in = 20 mhz 75 dbc f in = 30 mhz 75 dbc f in @ fs/2 65 dbc hd2 second order harmonic distortion f in = 8 mhz -80 -90 dbc f in = 20 mhz -95 dbc f in = 30 mhz -90 dbc f in @ fs/2 -80 dbc hd3 third order harmonic distortion f in = 8 mhz -70 -75 dbc f in = 20 mhz -75 dbc f in = 30 mhz -75 dbc f in @ fs/2 -65 dbc enob effective number of bits f in = 8 mhz 9.7 9.9 bits f in = 20 mhz 9.8 bits f in = 30 mhz 9.8 bits f in @ fs/2 9.5 bits power supply analog supply current 16.5 ma digital supply current digital core supply 3.3 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext enabled 5.9 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext disabled 4.1 ma analog power 29.7 mw digital power ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 16.2 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 45.9 mw power down 9.1 w sleep mode power dissipation, sleep mode 18.3 mw clock inputs max. conversion rate 80 msps min. conversion rate 65 msps asd0401 rev v3.2 , 2010.04.23 confidential page 7 of 16
product specification digital and timing specifications avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, conversion rate: max specified, 50% clock duty cycle, -1dbfs input signal, 5 pf capacitive load on data outputs, unless otherwise noted parameter condition min typ max unit clock inputs duty cycle 20 80 % high compliance cmos, lvds, lvpecl, sine wave input range differential input swing 0.4 vpp input range differential input swing, sine wave clock input 1.6 vpp input common mode voltage keep voltages within ground and voltage of ovdd 0.3 v ovdd -0.3 v input capacitance differential 2 pf timing t pd start up time from power down mode to active mode 900 clock cycles t slp start up time from sleep mode to active mode 20 clock cylcles t ovr out of range recovery time 1 clock cycles t ap aperture delay 0.8 ns ? rms aperture jitter < 0.5 ps t lat pipeline delay 12 clock cycles t d output delay (see timing diagram). 5pf load on output bits 3.0 10.0 ns t dc output delay relative to ck_ext (see timing diagram) 1.0 6.0 ns logic inputs v hi high level input voltage. v ovdd 3.0v 2 v v hi high level input voltage. v ovdd = 1.7v C 3.0v 0.8 v ovdd v v li low level input voltage. v ovdd 3.0v 0 0.8 v v li low level input voltage. v ovdd = 1.7v C 3.0v 0 0.2 v ovdd v i hi high level input leakage current +/-10 a i li low level input leakage current +/-10 a c i input capacitance 3 pf logic outputs v ho high level output voltage v ovdd -0.1 v v lo low level output voltage 0.1 v c l max capacitive load. post-driver supply voltage equal to pre-driver supply voltagev ovdd = v ocvdd 5 pf c l max capacitive load. post-driver supply voltage above 2.25v (1) 10 pf (1) the outputs will be functional with higher loads. however, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum asd0401 rev v3.2 , 2010.04.23 confidential page 8 of 16
product specification timing diagram analog input clock input data output n-1 n n+1 n+2 n+3 n+4 n+5 n-13 n-12 n-11 n-10 n-9 n-8 t d t ap ck_ext t dc figure 2 : timing diagram absolute maximum ratings absolute maximum ratings are limiting values to be applied for short periods of time. exposure to absolute maximum rating conditions for an extended period of time may reduce device lifetime. table 1 : pin pin rating avdd vss -0.3v to +2.3v dvdd vss -0.3v to +2.3v avss, dvssck, dvss, ovss vss -0.3v to +0.3v ovdd vss -0.3v to +3.9v ip, in, analog inputs and outputs vss -0.3v to +2.3v digital outputs vss -0.3v to +3.9v ckp, ckn vss -0.3v to +3.9v digital inputs vss -0.3v to +3.9v operating temperature -40 to +85 o c storage temperature -60 to +150 o c soldering profile qualification j-std-020 this device can be damaged by esd. even though this product is protected with state- of-the-art esd protection circuitry, damage may occur if the device is not handled with appropriate precautions. esd damage may range from device failure to performance degradation. analog circuitry may be more susceptible to damage as very small parametric changes can result in specification incompliance. asd0401 rev v3.2 , 2010.04.23 confidential page 9 of 16
product specification pin configuration and description 4 0 3 9 3 8 3 6 3 7 3 5 3 3 3 4 3 1 3 2 30 29 27 25 26 24 22 23 21 28 1 3 5 4 6 8 7 9 10 2 1 1 1 2 1 3 1 5 1 4 1 6 1 8 1 7 2 0 1 9 s l p _ n c m _ e x t b c _ 1 c m _ e x t b c _ 0 d _ 9 d _ 8 d _ 6 o v d d d _ 7 d _ 5 o v d d d_4 d_3 d_2 ovdd ck_ext d_1 orng d_0 nc ovdd d v d d c k _ e x t _ e n p d _ n o e _ n d f r m t d v d d n c o v d d n c o v d d dvdd avdd avdd in avdd ip dvddck ckp ckn cm_ext pin 0, exposed pad for ground connection pin 1 label figure 3 : package drawing, qfn 40-pin table 2 : pin function pin # name description 0 vss ground connection for all power domains. exposed pad 1, 11, 16 dvdd digital and i/o-ring pre driver supply voltage, 1.8v 2 cm_ext common mode voltage output 3, 4, 7, avdd analog supply voltage, 1.8v 5, 6 ip, in analog input (non-inverting, inverting) 8 dvddck clock circuitry supply voltage, 1.8v 9 ckp clock input, non-inverting (format: lvds, lvpecl, cmos/ttl, sine wave) 10 ckn clock input, inverting. for cmos input on ckp, connect ckn to ground. 12 ck_ext_en ck_ext signal enabled when low (zero). tristate when high. 13 dfrmt data format selection. 0: offset binary, 1: two's complement 14 pd_n full chip power down mode when low. all digital outputs reset to zero. after chip power up always apply power down mode before using active mode to reset chip. 15 oe_n output enable. tristate when high 17, 18, 25, 26, 36, 37 ovdd i/o ring post-driver supply voltage. voltage range 1.7 to 3.6v 19 nc 20 nc asd0401 rev v3.2 , 2010.04.23 confidential page 10 of 16
product specification 21 nc 22 d_0 output data (lsb) 23 d_1 output data 24 orng out of range flag. high when input signal is out of range 27 ck_ext output clock signal for data synchronization. cmos levels 28 d_2 output data 29 d_3 output data 30 d_4 output data 31 d_5 output data 32 d_6 output data 33 d_7 output data 34 d_8 output data 35 d_9 output data (msb) 38, 39 cm_extbc_1, cm_extbc_0 bias control bits for the buffer driving pin cm_ext 00: off 01: 50ua 10: 500ua 11: 1ma 40 slp_n sleep mode when low asd0401 rev v3.2 , 2010.04.23 confidential page 11 of 16
product specification recommended usage analog input the analog inputs to the asd0401 is a switched capacitor track-and-hold amplifier optimized for differential operation. operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. the cm_ext pin provides a voltage suitable as common mode voltage reference. the internal buffer for the cm_ext voltage can be switched off, and driving capabilities can be changed by using the cm_extbc control input. figure 4 shows a simplified drawing of the input network. the signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22 ohm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. the resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. track track track track hold hold inx ipx 2.1 pf 2.1 pf figure 4 : input configuration dc-coupling figure 5 shows a recommended configuration for dc- coupling. note that the common mode input voltage must be controlled according to specified values. preferably, the cm_ext output should be used as reference to set the common mode voltage. the input amplifier could be inside a companion chip or it could be a dedicated amplifier. several suitable single ended to differential driver amplifiers exist in the market. the system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with the asd0401 input specifications. detailed configuration and usage instructions must be found in the documentation of the selected driver, and the values given in figure 5 must be varied according to the recommendations for the driver. ac-coupling a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 6 shows a recommended configuration using a transformer. make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. the bandwidth should exceed the sampling rate of the adc with at least a factor of 10. it is also important to minimize phase mismatch between the differential adc inputs for good hd2 performance. this type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. if the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the adc input. this could reduce the adc performance. to avoid this effect, the source must effectively terminate the adc kick-backs, or the traveling distance should be very short. if this problem could not be avoided, the circuit in figure 8 can be used. figure 7 shows ac-coupling using capacitors. resistors from the cm_ext output, r cm , should be used to bias the differential input signals to the correct voltage. the series capacitor, c i , form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. asd0401 rev v3.2 , 2010.04.23 confidential page 12 of 16 figure 5 : dc coupled input with buffer figure 6 : transformer coupled input ipx inx cm_ext input input amplifier 43 43 33 pf ipx inx cm_ext input 33 33 r t 47
product specification note that startup time from sleep mode and power down mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. if the input signal has a long traveling distance, and the kick-backs from the adc not are effectively terminated at the signal source, the input network of figure 8 can be used. the configuration in figure 8 is designed to attenuate the kickback from the adc and to provide an input impedance that looks as resistive as possible for frequencies below nyquist. values of the series inductor will however depend on board design and conversion rate. in some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pf) may improve adc performance further. this capacitor attenuate the adc kick-back even more, and minimize the kicks traveling towards the source. however, the impedance match seen into the transformer becomes worse. clock input and jitter considerations typically high-speed adcs use both clock edges to generate internal timing signals. in the asd0401 only the rising edge of the clock is used. hence, input clock duty cycles between 20% and 80% are acceptable. the input clock can be supplied in a variety of formats. the clock pins are ac-coupled internally. hence a wide common mode voltage range is accepted. differential clock sources as lvds, lvpecl or differential sine wave can be connected directly to the input pins. for cmos inputs, the ckn pin should be connected to ground, and the cmos clock signal should be connected to ckp. for differential sine wave clock, the input amplitude must be at least +/- 800 mvpp. the quality of the input clock is extremely important for high-speed, high-resolution adcs. the contribution to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1 , snr jitter = 20 ? log 2 ? ? f in ? t ( 1 ) where f in is the signal frequency, and t is the total rms jitter measured in seconds. the rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. this can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost importance to avoid crosstalk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. the jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter performance is obtained with lvds or lvpecl clock with fast edges. cmos and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the adc clock input. digital outputs digital output data are presented on parallel cmos form. the voltage on the ovdd pin set the levels of the cmos outputs. the output drivers are dimensioned to drive a wide range of loads for ovdd above 2.25v, but it is recommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. in applications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the adc chip. the timing is described in the timing diagram section. note that the load or equivalent delay on ck_ext always should be lower than the load on data outputs to ensure sufficient timing margins. the digital outputs can be set in tristate mode by setting the oe_n signal high. the asd0401 employs digital offset correction. this means that the output code will be 4096 with shorted inputs. however, small mismatches in parasitics at the input can cause this to alter slightly. the offset correction also results in possible loss of codes at the edges of the full scale range. with no offset correction, the adc asd0401 rev v3.2 , 2010.04.23 confidential page 13 of 16 figure 8 : alternative input network ipx inx cm_ext input 1:1 r t 68 120nh 120nh 33 33 220 22pf optional figure 7 : ac coupled input ipx inx cm_ext 22 22 22 pf c i c i r cm r cm innx inpx
product specification would clip in one end before the other, in practice resulting in code loss at the opposite end. with the output being centered digitally, the output will clip, and the out of range flags will be set, before max code is reached. when out of range flags are set, the code is forced to all ones for overrange and all zeros for underrange. data format selection the output data are presented on offset binary form when dfrmt is low (connect to ovss). setting dfrmt high (connect to ovdd) results in 2's complement output format. details are shown in table 3 . table 3 : data format description for 2vpp full scale range differential input voltage (ip - in) output data: d_9 : d_0 (dfrmt = 0, offset binary) output data: d_9 : d_0 (dfrmt = 1, 2's complement) 1.0 v 11 1111 1111 01 1111 1111 +0.24mv 10 0000 0000 00 0000 0000 -0.24mv 01 1111 1111 11 1111 1111 -1.0v 00 0000 0000 10 0000 0000 reference voltages the reference voltages are internally generated and buffered based on a bandgap voltage reference. no external decoupling is necessary, and the reference voltages are not available externally. this simplifies usage of the adc since two extremely sensitive pins, otherwise needed, are removed from the interface. operational modes the operational modes are controlled with the pd_n and slp_n pins. if pd_n is set low, all other control pins are overridden and the chip is set in power down mode. in this mode all circuitry is completely turned off and the internal clock is disabled. hence, only leakage current contributes to the power down dissipation. the startup time from this mode is longer than for sleep mode as all references need to settle to their final values before normal operation can resume. the slp_n signal can be used to set the full chip in sleep mode. in this mode internal clocking is disabled, but some low bandwidth circuitry is kept on to allow for a short startup time. however, sleep mode represents a significant reduction in supply current, and it can be used to save power even for short idle periods. the input clock should be kept running in all idle modes. however, even lower power dissipation is possible in power down mode if the input clock is stopped. in this case it is important to start the input clock prior to enabling active mode. startup initialization the asd0401 must be reset prior to normal operation. this is required every time the power supply voltage has been switched off. a reset is performed by applying power down mode. wait until a stable supply voltage has been reached, and pull the pd_n pin for the duration of at least one clock cycle. the input clock must be running continuously during this power down period and until active operation is reached. alternatively the pd pin can be kept low during power-up, and then be set high when the power supply voltage is stable. asd0401 rev v3.2 , 2010.04.23 confidential page 14 of 16
product specification package mechanical data qfn40 e 1.14 f a2 a3 1 b d d2 d 1 d d 2 a pin 1 id dia 0.20 a1 l g pin 0, exposed pad bottom view pin 1 id (top side) dia 0.50 0.45 1 40 10 11 20 21 30 31 1.14 figure 9 : qfn 40 package dimensions (millimeter unless otherwise noted) table 4 : dimensions millimeter inch symbol min typ max min typ max a 0.9 0.035 a1 0.00 0.01 0.05 0.00 0.0004 0.002 a2 0.65 0.7 0.026 0.028 a3 0.2 ref 0.008 ref b 0.2 0.25 0.32 0.008 0.010 0.013 d 6.00 bsc 0.236 bsc d1 5.75 bsc 0.226 bsc d2 3.95 4.10 4.25 0.156 0.162 0.167 l 0.3 0.4 0.5 0.012 0.016 0.020 e 0.50 bsc 0.020 bsc 1 0 12 0 12 f 0.2 0.008 g 0.24 0.42 0.6 0.0095 0.0165 0.024 asd0401 rev v3.2 , 2010.04.23 confidential page 15 of 16
product specification product information product status datasheet revision date asd0401 product specification v3.2 2010.04.23 ordering information ordering code temp. range package type package drawing msl, peak temp (1) transport media asd0401 l20-inr -40 to +85 c 40 pin qfn qfn40 level 2a tape and reel asd0401 l40-inr -40 to +85 c 40 pin qfn qfn40 level 2a tape and reel asd0401 l65-inr -40 to +85 c 40 pin qfn qfn40 level 2a tape and reel asd0401 l80-inr -40 to +85 c 40 pin qfn qfn40 level 2a tape and reel asd0401 l20-int -40 to +85 c 40 pin qfn qfn40 level 2a tray asd0401 l40-int -40 to +85 c 40 pin qfn qfn40 level 2a tray asd0401 l65-int -40 to +85 c 40 pin qfn qfn40 level 2a tray asd0401 l80-int -40 to +85 c 40 pin qfn qfn40 level 2a tray (1) msl, peak temp: the moisture sensitivity level rating classified according to the jedec industry standard and to peak solder temperature. datasheet status objective product specification: the values and functionality describe design targets only. specifications and functionality can be changed without notice preliminary product specification: the specifications are based on initial design results. specifications and functionality can be changed without notice. product specification: information is current as of publication data. products conform to specifications according to the terms of arctic silicon devices as standard warranty. production does not necessarily require all parameters to be tested. arctic silicon devices as vestre rosten 81 n-7075 tiller norway tel: +47 73 10 29 00 fax: +47 73 10 29 19 information provided in this document is believed to be accurate and reliable. however, no responsibility is assumed by arctic silicon devices as for its use. neither is any responsibility assumed for any infringement of patents or other third party rights that may result from the use of the product or information described herein. no license is implicitly or otherwise granted under any patent or patent right of arctic silicon devices as. arctic silicon devices as specifically disclaims any and all liability, including without limitation incidental or consequential damages. it is the responsibility of the user to ensure that in all respects the application in which arctic silicon devices as products are used is suited to the purpose of the end user. life support applications : products of arctic silicon devices as (asd) are not designed for use in life support appliances, devices or systems, where malfunction can result in personal injury. customers using or selling asd products for use in such applications do so at their own risk and agree to fully indemnify asd for any damages resulting from such improper use or sale. all rights reserved ?. reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. asd0401 rev v3.2 , 2010.04.23 confidential page 16 of 16 template rev. date: 2007.10.03

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