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BR1570/d, rev 0 warplink ? reference design platform white paper f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 2 table of contents abstract ....................................................................................................................... ....................3 introduction................................................................................................................... ................3 warplink 2.5 quad device ....................................................................................................3 warplink reference design platform goals .........................................................................3 warplink reference design platform overview ...................................................................4 architectural overview ..................................................................................................4 backplane...................................................................................................................... .5 line card ...................................................................................................................... ..6 switch card.................................................................................................................... 6 test card...................................................................................................................... ..6 detailed design descriptions.................................................................................................6 warplink reference backplane.............................................................................................6 backplane/chassis design considerations ...................................................................7 warplink backplane physical description ....................................................................7 backplane design rules and layer stackup..................................................................9 line, switch, and test cards ...............................................................................................10 daughter cards design considerations.......................................................................10 line card and test card layer stackups .....................................................................10 warplink signal integrity simulation program .......................................................11 warplink gigabit simulations.............................................................................................11 warplink interconnect impedance profile ..........................................................................15 warplink reference system clock simulations .................................................................16 description of passive signal integrity measurements .......................................17 time domain reflectometry ................................................................................................17 differential time domain crosstalk ....................................................................................17 eye diagrams ................................................................................................................... ....17 time domain test equipment..............................................................................................18 passive measurement results.............................................................................................18 tdr results.................................................................................................................... ......18 eye diagram measurement results ....................................................................................19 active measurement results ...............................................................................................20 test setup..................................................................................................................... .......20 eye diagrams from slot 8 to slot 1.....................................................................................21 eye diagrams from slot 7 to slot 1.....................................................................................21 summary and conclusions ...................................................................................................22 acknowledgements ............................................................................................................... ...22 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 3 abstract this paper describes the technical design process used in the development of a warplink ? reference design platform showcasing motorola?s warplink 2.5 gbps quad, a serializer-deserializer (serdes) data interface device. the reference design platform util izes a combination of good design practices to make it feasible to use an fr-4 backplane with standard components and fabrication proc esses to realize 3.125 gigabaud (gbd) xaui-compliant channels. a brief description of critical component selection is followed by a discussion of design considerations related to high-speed signal integrity performance. the technical ?right-by-design? process utilized by north east systems associates (nesa) included simula tions that were verified through measurements of the fabricated hardware. the simulation and experimental results highlight the special fe atures of the warplink 2.5 device making it possible to have 3.125 gbd wire-speed transmissions through fr-4 pwb material. introduction warplink 2.5 quad device the warplink 2.5 quad device is a serdes interface that transfers data between chips across a board, a backplane, or cables. it handles four full-duplex redundant data links. serial transceivers transmit and receive 8b/10b coded data at a nominal rate of 2.5 giga bits per second (gbps) through 3.125 gbd links. in the transmit direction, the near-end warplink device receives data on its four parallel transmit interfaces which accommodat e 8-bit uncoded or 10-bit precoded data bytes. when configured for the 8- bit mode, the device performs 8b/10b encoding on the uncoded d ata. it then serializes the coded data and sends it onto the four corres ponding primary serial differential transmitters. data can be s ent out on the four redundant transmitters or on both primary and redundant transmi tters simultaneously. coded serial data comes out of each t ransmitter at 3.125 gbd wire-speed carrying 2.5 gbps of user data through channels across a board, a backplane, or cables to far-end warpl ink devices? serial receivers. in the receive direction, serial coded data coming from far-end warplink devices? serial transmitters are received by the near- end device on one of four primary or redundant serial receivers. the near-end dev ice de-serializes the data and, if configured for the 8-bit mode, performs 8b/10b decoding. the device then sends the data out on the four corresponding parallel receive interfaces. the warplink 2.5 quad is packaged in a 324-pin pbga, with a 19 mm x 19 mm (0.75 x 0.75 in) body and a 1 mm ball-to-ball pitch. the device typically uses 1.8 watts. its core and link power supply inputs require 1.8 v. the hstl i/o power supply inputs (for the parallel and digital i/os) use either 1.5 v or 1.8 v. for further detail on the warplink 2.5 quad?s rich feature set, including selectable speed range, double data rate, 8b/10b, lin k synchronization and recovered clock mode, refer to the warplink 2.5 quad user?s manual. warplink reference design platform goals with the introduction of the warplink serdes family, consisting of the warplink quad (1.0 gbps), warplink quad double data rate (ddr) (1.0 gbps), and warplink 2.5 quad (2.5 gbps) devices, designing boards and backplanes capable of handling up to 3.125 gbd chann els could prove challenging. the warplink reference design platform was developed to assist designers in laying out the interconnec tion system as well as to provide an example of a system designed with a backplane, daughter cards, and connectors that make 3.125 g bd channels feasible. the development work served as a learning experience for motorola, with the aim of sharing the final outcome with warplink customers. a critical portion of the development effort centered on the simulation. in addition to simulations performed at 3.125 gbd, sim ulations at 5gbps were also carried out to give a better understanding of the current capabilities and limitations of the technology. the platform was designed to accommodate warplink 2.5, as it is the fastest device in the family. fr-4 was chosen for the backp lane and boards for three reasons: 1) material availability, 2) relative lower cost when compared to other fabrication materials, and 3) most pwb fabrication houses can process the material. several channels were designed to be long enough to demonstrate warplink 2.5?s xau i compliance (50cm or 19.68in). standard available components were selected, specifically the er ni hmzd connector, a high-density connector intended for high-s peed signaling. motorola?s timing solutions devices, the mc100es6111, the mc100ep222, the mpc9456, and the mc100ep8111, were examples of currently available clock network distribution devices that are intended for use in such a system. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 4 slot 8 mesh port 1 mesh port 3 mesh port 5 mesh port 7 mesh port 2 mesh port 4 mesh port 6 mesh port 8 slot 7 slot 6 slot 5 slot 4 slot 3 slot 2 slot 1 warplink reference design platform overview architectural overview mesh and fabric the warplink reference design platform consists of a 9u 19" compact pci chassis with eight double-height slots. the slots accep t three types of cards: the line card, the switch card, and the test ca rd. warplink devices on the cards are connected to one another t hrough the backplane interconnect, which supports both mesh and fabric switching schemes. for the mesh-switching scheme, each slot has eight mesh ports. the mesh channels in the backplane connect seven mesh ports per slot to a mesh port on each of the other seven slots. the one remaining unconnected port is looped back to itself. the connection is do ne such that slot- m , port- n is connected to slot- n , port- m . figure 1 and figure 2 illustrate the mesh interconnects of the backplane for slot 1 and 2, respectively. in this scheme, 2.5 gigabits of link data can go directly from any slot to any other slot. figure 1. mesh interconnects from slot 1 figure 2. mesh interconnects from slot 2 in the fabric-switching scheme, each slot has eight line ports : four primary, four redundant. slots 7 and 8 each have 32 fabric ports in addition to the line ports. the fabric channels of the backplane connect the four primary line ports of every slot to four of t he 32 fabric ports on slot 8. the four redundant line ports of every slot are connec ted to four of the 32 fabric ports on slot 7. figure 3 shows the fabric interconnects of the backplane. in this scheme, 10 gigabits of lin k data can go from any slot to any other slot through slots 7 or 8. data links going through slot 8 are primary and those through slot 7 are redundant. slot 8 mesh port 1 mesh port 3 mesh port 5 mesh port 7 mesh port 2 mesh port 4 mesh port 6 mesh port 8 slot 7 slot 6 slot 5 slot 4 slot 3 slot 2 slot 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 5 figure 3. fabric interconnects clock distribution the system has two point-to-point distributed clock networks. the pr imary network originates from slot 8 and is distributed to all slots. the redundant one is from slot 7, which is also distributed to all slots. the card in each slot selects its own on-board clock, or the clock distributed by either the primary network or the secondary netwo rk. motorola?s mc100es6111 device (on the card in slot 7 or 8) is used to drive the clock distribution network. an mc100ep222 clock receiver on each line card is used to receive the distributed clock, and the mc100ep8111 hstl clock buffer on the line card brings the clock signals to hstl level to be used by warplink. processor bus the system has a multi-drop 32-bit bus going to all slots that can be used as a processor bus. a host card in slot 7 or 8 with a processor can send and receive control and status messages to all slots. slot 8 houses the primary control card, and slot 7 the redundant control card. the multi-drop 32-bit bus is designed to terminate gunning transceiver logic plus (gtlp) drivers. backplane the key subassembly of the warplink reference design platform is the backplane. it is a 14.96 in x 15.57 in fr-4, 28-layer prin ted circuit board (pcb). eight columns of connectors form the eight slots into which the cards are inserted. the majority of the backplane traces form the 3.125 gbd channels that interconnect the warplink 2.5 devices on the daughter cards through the mesh and fabric topologies described previously. other traces form the clock distribution network and the processor bus. redundant line port 1 primary line port 3 redundant line port 4 primary line port 4 redundant line port 2 redundant line port 3 primary line port 1 primary line port 2 slot 8 slot 7 slot 6 slot 5 slot 4 slot 3 slot 2 slot 1 fabric ports 1 - 32 10 gbps per slot (primary) 10 gbps per slot (redundant) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 6 an important aspect of the backplane design was the selection of the high-speed differential connector from erni. the ermet? zd 8x10 connector is used as a differential board-to-backplane connector rated to support electrical signaling up to 5 gbps. the ermet? zd is compatible with the mechanical characteristics of the ermet? 2 mm-hm specifications as defined in iec 61076-101. line card one of the cards that reside in the warplink reference design pl atform is the line card. it can go into any of the eight slots. in the mesh topology, all eight slots can be populated with line cards. in the fabric topology, slots 1 - 6 can be populated with line card s, while slots 7 and 8 must be populated with the switch cards. each line card has two warplink 2.5 quad devices on it. each warplink 2.5 quad device has four serdes devices each capable of supporting one full-duplex data link. the parallel side o f each serdes device is not redundant. therefore, each serdes device has only one parallel port. this parallel port of the full-duplex data link supported by a serdes device consists of 8 or 10 pins for the parallel transmit interface and 8 or 10 pins for the parallel rec eive interface. the serial side, however, is redundant. therefore, each serdes device has two serial ports: a primary one and a redundant one. each of the serial ports consists of 4 pins: positive-transmit, negative-transmit, positive-receive, and negative-receive. a line card with two warplink 2.5 quad devices, therefore, can support eight full-duplex data links, to be used in either the m esh or fabric configuration. the eight serial primary ports provided by the two devices are connec ted to the eight mesh ports of the slot when the card is i nserted. the mesh ports are then connected to other mesh ports as previously discussed. in the mesh configuration, the primary serial ports are selected, and data always passes through the two warplink devices via their parallel ports and primary serial ports. the eight serial redundant ports provided by the two devices are connected to the eight fabric-topology line ports of the slot when the card is inserted. the line ports are then connected to the fabric ports on slot 7 and 8 as previously discussed. in the fabric confi guration, the redundant serial ports are selected, and data always passes through the two warplink devices via their parallel ports and redun dant serial ports. on the parallel side of the warplink devices, the hstl paralle l interfaces can be connected to asics, fpgas, or headers to be c ontrolled and monitored by pattern generators and logic analyzers. switch card the switch card is a combination of a line card and a fabric card. this card can only go into slots 7 and 8. there are 10 warpl ink devices on the switch card. two of the 10 devices are used to form the line card portion: the devices? serial primary ports are connect ed to the mesh ports and the redundant ports to the line ports. the 32 serial redundant ports of the remaining eight devices are connecte d to 32 fabric ports of the slot into which the card is inse rted. the 32 primary ports of these eight devices are unused. on the parallel side of the warplink devices, the interfaces can be connected to asics or fpgas. test card the test card is a passive card with sma connectors and 2x10 headers. it does not have any warplink or active devices on it. the card is used to characterize channels from slot to slot. for example, time domain reflectometry (tdr) measurements can be performed with this test card to show via, connector, and backplane trace impedance. the card can also be used to independently characterize transmitters and receivers operating in the system. when the card is in a slot, controlled test signals from a signal generator can be fed into the near-end test card?s transmit port of a link to characteriz e the corresponding receiver of a far-end warplink device. also, si gnals from a far-end warplink transmitter can be measured off the near-end receive port, through a pair of sma connectors on the test card. detailed design descriptions warplink reference backplane the warplink reference backplane is specifically designed for the motorola warplink 2.5 quad component. the overall design is representative of a typical backplane used in present-day communications-system chassis. figure 4 details the overall backplane as well as component selection and placement on the warplink backplane. figure 5 details the layer stackup of the backplane. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 7 backplane/chassis design considerations before we discuss the details of the motorola warplink backplane, it would be helpful to give an overview of the process and co nstraints under which a backplane and chassis are designed. the design of the backplane must consider the design elements of the system a s a whole. the major parameters that shape a chassis/backplane system must be established early on in the design, once the intended market is established. these include 1) the total power dissipated by t he system, 2) the system logical architecture, 3) the approxima te dimensions of the chassis, and 4) the subsequent regulatory requirements fo r the intended market. one of the outcomes of coupling the syst em architecture with the total power dissipation is the determinati on of the number of daughter card slots within the chassis dime nsion limitations. knowing the maximum power dissipation of the vari ous types of daughter cards and the number desired in a system he lps to establish the constraints that limit the possible system configur ations. at times, thermal constraints can directly impact the electrical architecture of a system. this is especially true if the chassis is sized so that it places limits on the total power that can be dissipated. a first pass formulation of a system takes place once a balance is reached between the requirements set by the system architect ure coupled with the intended market and the total power that can be dissipated within the chassis enclosure. the thermal analysis and subsequent physical constraints on the slot pitch are required to determine the total number of daughter cards possible in the system. thus, the ability of a chassis to cool itself can limit the number and possibly the type of components used, including logic de vices. the design of the backplane begins in parallel to the thermal ev aluation of the system, but is not set until the number of daug hter card slots and overall system configuration are established. once the number of slots is determined, the next major step is the iden tification of the type and number of signals per slot. a definition of the signaling needed in the warplink reference backplane was based on the architecture defined by the motorola design team. the general archit ecture of the warplink reference design platform is discuss ed in the introduction of this document. warplink backplane physical description the physical configuration of the motorola warplink backplane used in the reference system contains eight slots on a 1.6-inch c ard-to-card pitch. the motorola warplink reference design platform was designed to suit both switch fabric and mesh architectures. the logi cal configuration of the backplane defines slots 1 through 6 as pin- compatible line card slots, and slots 7 and 8 as pin-compatible switch/line card slots. when a switch fabric is inserted into slot 7, 8, or both, the system can function in either the fabric or mesh arch itecture. if a line card is inserted into slot 7, 8, both, or neither, the system will operate in the mesh architecture. the ability of the wa rplink to do this is due to the primary and redundant serial i/o characteristics of the device. the signal allocations for each slot type are detailed below in table 1. table 1. signal allocations signal types slot 1 - 6 (line card) slot 7 - 8 (switch/line card) signal speed differential gigabit serial links (mes h/fabric) 32 pairs 96 pairs 3.125 gbd differential clocks 2 pairs 8 pairs 156 mhz single-ended address/data/control busses 36 pins 36 pins <50 mhz the signal speed identification is critical to the design rules formulated for the layout of a gigabit backplane. for example, the addition of unnecessary vias in the gigabit lines would adversely affect their signal transmission characteristics. each via presents an im pedance discontinuity that will contribute to the distortion of the openi ng of the receiver input eye pattern. this can reduce availabl e voltage margins as well as time margins through an increase in signal jitter. therefore, all differential routes of the warplink refere nce design platform backplane had vias placed only where absolutely needed - at the device pads and at the connectors (plated-through hole s). a number of issues were assessed in arriving at a final connector selection for the motorola warplink backplane. the ermet? zd high- speed backplane connector was chosen for the gigabit nets for its high-frequency signal transmission characteristics and becaus e it is side stackable with a standard 2 mm hard metric connector. the ermet? 2 mm hard metric connector was selected for the slower speed single-ended and differential clock nets. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 8 figure 4. warplink reference backplane (front view) the backplane not only connects the eight slots of the motorola wa rplink system; it also has been designed with features that h elp exhibit its gigabit transmission capabilities. the longest gigabit traces required to connect slots 1 to 8 are about 12 to 15 inches. t he warplink backplane also contains four differential nets that are approx imately 0.5 meter long. these nets demonstrate warplink?s ability to operate over a long lossy channel. they are also used to test warplink?s compliance to xaui specifications. the backplane also contains four traces designed to inject crosstalk onto gigabit links. this serves to demonstrate warplink?s noise tolerance. these noise-gene rating nets have been placed 5 and 10 mils away from the victim gigabit nets. a recommended design rule spacing of 15 mils (minimum) was implemented for the remaining gigabit nets in order to minimize any crosstalk. the gigabit links are confined to the middle of the backplane and are connected to the daughter cards through the erni componen ts ermet? zd high-speed backplane connector. the slow-speed (single- ended) buses are positioned in the lower connector section of the backplane and are connected to the daughter cards via erni components ermet? 2 mm hard metric (hm) connectors. the clock nets r un across the upper connector section of the backplane and are connected to the daughter cards via with the erni 2 mm hm connector s as well. the backplane provides 3.3v and 5v power to the daughter cards by way of the ermet? power modules at the top of each slot . s8_j1 s8_j2 s8_j3 s8_j4 s8_j5 s7_j1 s6_j1 s5_j1 s4_j1 s3_j1 s2_j1 s1_j1 s7_j2 s7_j3 s7_j4 s6_j2 s5_j2 s4_j2 s3_j2 s2_j2 s1_j2 s7_j5 s6_j3 s5_j3 s4_j3 s3_j3 s2_j3 s1_j3 guide pin guide pin guide pin guide pin guide pin guide pin guide pin guide pin s8_j6/j7 s7_j6/j7 s6_j4/j5 s5_j4/j5 s4_j4/j5 s3_j4/j5 s2_j4/j5 s1_j4/j5 gnd gnd gnd j4 j5 j6 j3 j2 j1 +5 v +3.3 v +3.3 v dc-dc converter guide pin guide pin guide pin guide pin guide pin guide pin guide pin guide pin zd zd zd zd zd zd zd zd 2mm hm 2mm hm 2mm hm 2mm hm 2mm hm 2mm hm 2mm hm 2mm hm 2mm hm power module 2mm hm 2mm hm 2mm hm 2mm hm 2mm hm 2mm hm 2mm hm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 9 backplane design rules and layer stackup the stackup cross-section of the warplink reference backplane boar d is shown in figure 5. both broadside-coupled differential a nd single- ended routes are utilized in the layout. the characteristic impedance of the single-ended nets was designed to be 50 ohms and t he broadside-coupled differential nets 100 ohms (both 10%). all differential pairs were routed direct without vias. vias for single-ended, multi-drop buses were used only within the connector regions and at the trace ends for termination access. the warplink backpla ne was designed as a 28-layer, 0.250in thick pcb. the backplane contains six broadside-coupled routing channels (12 layers) and 14 sin gle-ended routing layers (12 of which are shared with the differentia l pairs). broadside-coupled differential routing was chosen over edg e-coupled or uncoupled differential interconnects for its ability to maintain the routing channel within the gigabit connector footprints - board thickness was not a critical parameter. this is a typical routing schem e when using high-speed differential connectors on backplanes of s ubstantial board thickness. figure 5. warplink reference backplane layer stackup dielectric metal weight thickness emi grid - 0.375" grid w/ 0.050" trace width solder mask l1 gnd grid / se signal / pad 1 oz. (plated from 0.5 oz. 1.3 d9 5 l2 gnd plane 1 oz. 1.3 d8 11 l3 5v / se signal 0.5 oz. 0.6 d7 11 l4 gnd plane 1 oz. 1.3 d3 8 l5 5v / se signal / bcs signal 0.5 oz. 0.6 d4 10 l6 5v / se signal / bcs signal 0.5 oz. 0.6 d3 8 l7 gnd plane 1 oz. 1.3 d5 8 l8 3.3v / se signal / bcs signal 0.5 oz. 0.6 d6 10 l9 3.3v / se signal / bcs signal 0.5 oz. 0.6 d5 8 l10 gnd plane 1 oz. 1.3 d3 8 l11 3.3v / se signal / bcs signal 0.5 oz. 0.6 d4 10 l12 3.3v / se signal / bcs signal 0.5 oz. 0.6 d3 8 l13 gnd plane 1 oz. 1.3 d2 5 l14 3.3v / gnd plane / 1.5v 1 oz. 1.3 d1 5 l15 3.3v / gnd plane / 1.5v 1 oz. 1.3 d2 5 l16 gnd plane 1 oz. 1.3 d3 8 l17 3.3v / se signal / bcs signal 0.5 oz. 0.6 d4 10 l18 3.3v / se signal / bcs signal 0.5 oz. 0.6 d3 8 l19 gnd plane 1 oz. 1.3 d5 8 l20 3.3v / se signal / bcs signal 0.5 oz. 0.6 d6 10 l21 3.3v / se signal / bcs signal 0.6 d5 8 l22 gnd plane 1 oz. 1.3 d3 8 l23 5v / se signal / bcs signal 0.5 oz. 0.6 d4 10 l24 5v / se signal / bcs signal 0.5 oz. 0.6 d3 8 l25 gnd plane 1 oz. 1.3 d7 11 l26 5v / se signal 0.5 oz. 0.6 d8 11 l27 gnd plane 1 oz. 1.3 d9 5 l28 gnd grid / se signal / pad 1 oz. (plated from 0.5 oz. 1.3 solder mask emi grid - 0.375" grid w/ 0.050" trace width 251.6 wtop = 6 mils wtop = 6 mils pad spwr spwr layer number / description layer stack wdiff =5mils wdiff =5mils sse sdiff =15 mils sdiff =15 mils spwr spwr s s wse wse=9mils sdiff =15 mils wdiff =5mils sdiff =15 mils wdiff =5mils wdiff =5mils wdiff =5mils wdiff =5mils wdiff =5mils wdiff =5mils wdiff =5mils wdiff =5mils wdiff =5mils sse sse sdiff =15 mils s = 25mils s = 25mils wse=9mils sse = 20mils s = 25mils s = 25mils s = 25mils = 25 mils 3.3v 3.3v 3.3v gnd 5v 3.3v sse s=25mils sdiff =15 mils pad wse sse= 20mils sse = 20mils sse = 20mils sse = 20mils sse = 20mils s =25 mils = 20 mils = 20mils = 20mils = 20 mils wse=9mils wse=9mils wse=9mils wse=9mils wse=9mils wse wse wse wse=9mils wse=9mils wse=9mils = 25 mils 1.5v 1.5v wtop = 6 mils wtop = 6 mils wse=9mils wse=9mils s = 25mils 3.3v 3.3v 3.3v 3.3v 3.3v 5v 5v 5v 5v 5v gnd wse 3.3v fr-4 r = 4.5 tan( solder mask pre-preg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 10 the warplink reference design platform has been designed for three types of daughter cards. two of the cards, the switch fabric /mesh card (switch card) and the line card contain active components in addition to the warplink serdes. the third card is the passiv e test card. the design intent of the test card is to provide access to the gigabit nets for direct sampling of the warplink signals a s well as providing access to the backplane for passive signal integrity measurements (via sma test connectors). line, switch, and test cards daughter cards design considerations an important design consideration for the daughter cards should be the pin assignment of the high-speed connector. this pin ass ignment, in a way, is affected by the number of high-speed routing layers in a card. the number of layers should be minimized so that th e card would be thin enough to fit the guiding rails of the chassis. from a signal integrity viewpoint, this should also be done so that the vias? stubs would be as short as possible, especially for the 3.125 gbd traces that are routed in the upper layers. for the chosen gigabit connector, four was the minimum number of high-speed layers we could have. once the number of layers is determined, a preliminary hand-routing exercise should be carried out to determine the pin assignment, or to determine whether the existing pin assignment is or is no t routable given these four layers. care should be exercised when assigning pins to make both the line card and the backplane routable. of ten, a couple of iterations would be required. this hand-routing exer cise should be done early in the design cycle before committing t o a pin assignment. another trivial design consideration for the daughter cards should be the placement of the warplink device. the device should b e placed as close to the connector as possible. for the line card, one warplink was placed close to the connector, and the other one fur ther away to emulate a typical layout in which many warplink devices might have been used. line card and test card layer stackups the stackups of the test and line cards are presented in this paper to document the standard design practice used in the card l ayout and fabrication. figure 6 and figure 7 detail the test card and line card stackups, respectively. the gigabit differential nets of the test card and line card were designed to be the same. the length of the traces in the test card emulated the lengths seen on the line car d. the major difference between the line and test card stackups is the addition of power planes to the line card. the test card ha s thicker dielectric material between layers 6 and 7 to account for the missing plane layers and maintain the same overall card thickness . figure 6. warplink test card layer stackup dielectric metal weight thickness solder mask (mils) l1 se si g nal / pad 1 oz. (p lated from 0.5 oz. ) 1.3 d6 5 l2 gnd p lane 0.5 oz. 0.6 d5 5 l3 se si g nal / ecd si g nal 0.5 oz. 0.6 d4 5 l4 gnd p lane 0.5 oz. 0.6 d3 5 l5 se si g nal / ecd si g nal 0.5 oz. 0.6 d2 5 l6 gnd p lane 0.5 oz. 0.6 d1 20 l7 gnd p lane 0.5 oz. 0.6 d2 5 l8 se si g nal / ecd si g nal 0.5 oz. 0.6 d3 5 l9 gnd p lane 0.5 oz. 0.6 d4 5 l10 se si g nal / ecd si g nal 0.6 d5 5 l11 gnd p lane 0.5 oz. 0.6 d6 5 l12 se si g nal / pad 1 oz. (p lated from 0.5 oz. ) 1.3 solder mask 78.6 s = 20mils gnd wse=4.5mils wdiff =4mils wdiff =4mils s = 20mils s = 20mils wdiff =4mils 5.5 mils wdiff =4mils wdiff =4mils s = 20mils s = 20mils wse=4.5mils wse=4.5mils wdiff =4mils gnd wdiff =4mils gnd wse=4.5mils gnd wse=4.5mils wdiff =4mils sdiff = sdiff = pad s=20mils layer stack wtop = 6.5 mils wtop = 6.5 mils pad wse=4.5mils s=20mils s = 20mils s = 20mils wse=4.5mils wse=4.5mils sdiff = 5.5 mils 5.5 mils tan( )= 0.021 sdiff = 5.5 mils gnd s = 20mils r = 4.5 fr-4 pad s=20mils layer number / description total thickness (pad to pad) = pre-preg solder mask core pad wtop = 6.5 mils wtop = 6.5 mils s=20mils f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 11 figure 7. warplink line card layer stackup warplink signal integrity simulation program warplink gigabit simulations as part of the motorola warplink reference design platform effo rt, nesa completed an extensive hspice signal integrity study fo r the gigabit links and differential clocks. some of the simulation model features include: coupled lossy-line models; worst-case car d via effects due to stubs; warplink driver pre-emphasis control; and data rates running at 2.5 gbd and 3.125 gbd. although the majority of t he results focus on the differential interconnects for the active warplink device, simulation cases were completed for the clock interconn ects as well. the data in this summary includes receiver input eye patterns as well as tdr impedance profiles of the various differentials in terconnects. warplink driver hm-zd connector backplane package package 5mil broadside coupled differential 4 mil edge coupled differential switch module line card hm-zd connector 4mil edge coupled differential 100 ? differential 100 ? differential 100 ? differential r term = 100 ? warplink receiver via via via via via via via via via via via via figure 8. warplink gigabit interconnect dielectric metal weight thickness solder mask (mils) l1 se signal / pad 1 oz. (plated from 0.5 oz.) 1.3 d7 5 l2 gnd plane 0.5 oz. 0.6 d6 5 l3 se signal / ecd signal 0.5 oz. 0.6 d5 5 l4 gnd plane 0.5 oz. 0.6 d4 5 l5 se signal / ecd signal 0.5 oz. 0.6 d3 5 l6 gnd plane 0.5 oz. 0.6 d2 6 l7 power plane 1 oz. 1.3 d1 5 l8 power plane 1 oz. 1.3 d2 6 l9 gnd plane 0.5 oz. 0.6 d3 5 l10 se signal / ecd signal 0.5 oz. 0.6 d4 5 l11 gnd plane 0.5 oz. 0.6 d5 5 l12 se signal / ecd signal 0.6 d6 5 l13 gnd plane 0.5 oz. 0.6 d7 5 l14 se signal / pad 1 oz. (plated from 0.5 oz.) 1.3 solder mask 78.2 pad s=20mils layer number / description layer stack wudiff = 5 mil wudiff = 5 mil sdiff = s = 20mils s = 20mils 5.5 mils wse=4.5mils wse=4.5mils wdiff =4mils wdiff =4mils gnd sdiff = s = 20mils s = 20mils 5.5 mils wse=4.5mils wse=4.5mils wdiff =4mils wdiff =4mils gnd 3.3v 3.3v gnd wse=4.5mils wse=4.5mils wdiff =4mils wdiff =4mils s = 20mils s = 20mils sdiff = 5.5 mils gnd wse=4.5mils wse=4.5mils wdiff =4mils wdiff =4mils sdiff = 5.5 mils s = 20mils s = 20mils total thickness (pad to pad) = core solder mask pre-preg gnd s=20mils wtop = 6.5mil wtop = 6.5mil s=20mils s=20mils s=20mils fr-4 r = 4.5 tan( )= 0.021 pad wtop = 6.5 mils wtop = 6.5 mils sudiff = sudiff = 6 mils 6 mils wudiff = 5 mil wudiff = 5 mil s=20mils f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 12 the motorola warplink single-threaded hspice model was inserted as the driver and receiver into the interconnect environment constructed by nesa. figure 8 details the interconnect topology for the gigabit links. motorola provided the warplink device and package hspice models. models for the ermet? zd connector were s upplied by erni components. the coupled, lossy transmission line and vi a models were created from the pcb parameters by nesa. the construction of the hspice models was followed by the i dentification of the range of data rates and transmission line lengt hs needed to prove out the gigabit capabilities of warplink. table 2 identifies the variables and ranges of the values for the simulation matrix. 0 lists the constants, which are fixed parameters within the hspice simulation matrix. table 4 identifies the simulation matrix and the resultant eye pattern parameters. note that simulations were run at 65 o c to better emulate the case temperature (versus the typical 25 o c). table 2. simulation matrix values variables range warplink device temperature 0 c, 25 c, and 100 c su pp l y volta g e (1.8 v 10%) 1.6 v, 1.8 v, and 2.0 v driver pre-emphasis (transmit equalization) off, on process ss, tt, ff interconnect backplane trace length 2, 10, and 20 inches line and switch card vias one layer transition with stub and full board transition table 3. hspice simulation matrix constants constants value device gigabit tx/rx device warplink 2 / warplink 2 package 324 pbga (wl) 19 mm x 19 mm body, 1 mm ball pitch data data rate 3.125 gbps data pattern k28.5 etch switch/mesh card trace length 6 inches line card trace length 4 inches board parameters driver location switch/mesh receiver location line backplane material fr-4 switch/uplink module material fr-4 line card material fr-4 backplane thickness 0.250 in switch/mesh card thickness 0.078 in line card thickness 0.078 in etch width (backplane) bc diff 5 / 5 / 5 mils (w/s/w) etch width (line and switch) ec diff 4 / 5.5 / 4 mils (w/s/w) switch/mesh card via count 2 - 1 @ package pad, 1 @ connector backplane via count 2 - 1 @ each connector line card via count 2 - 1 @ connector pad, 1 @ package backplane connectors gigabit nets - switch/mesh modules 8 - row hm-zd - gh row gigabit nets - line card 8 - row hm-zd - gh row f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 13 table 4. simulation matrix eye pattern parameters case temperature ( c) 0 / 65 / 100 supply voltages 10% process corner pre-emphasis on / off data rate (gbps) backplane length (in) via type eye height (mv) eye width (ps) jitter (p-p) (ps) within xaui mask 1 0 2.0 ff off 3.125 2 full 650 275 45 y 2 0 2.0 ff on 3.125 2 full 740 280 40 y 3 0 2.0 ff off 3.125 20 full 300 220 100 y 4 0 2.0 ff on 3.125 20 full 450 260 60 y 5 100 1.6 ss off 3.125 2 full 360 255 65 y 6 100 1.6 ss on 3.125 2 full 450 270 50 y 7 100 1.6 ss off 3.125 20 full 170 220 100 n 8 100 1.6 ss on 3.125 20 full 220 240 80 y 9 100 1.6 ss off 3.125 20 stub 120 190 130 n 10 100 1.6 ss on 3.125 20 stub 190 240 80 n 11 65 1.8 tt off 3.125 10 full 370 260 60 y 12 65 1.8 tt on 3.125 10 full 480 280 40 y 13 65 1.8 tt off 3.125 10 stub 280 235 85 y 14 65 1.8 tt on 3.125 10 stub 440 275 45 y the eye parameters measured at the receiver input include eye height, eye width, peak-to-peak jitter, and xaui mask. the precis e measurement point of the eye pattern is between the package and t he silicon at the receiver input. a comparison of the odd-numb ered cases (pre-emphasis off) in table 4 to the even-numbered cases (p re-emphasis on) shows a great improvement for all eye metrics when pre-emphasis is engaged. the xaui channel eye mask has been overlaid on the receiver input eye to illustrate compliance (refer to the eye pattern plots below). cases 9 and 10 and 13 and 14 contain the stub via model. in a typical backplane system, parasitic stubs are seen for vias where a signal traverse a via for less than the thickness of the backplane. for example, a differential pair routed on layers 5 and 6 will onl y pass through approximately 40 mil of the 250-mil backplane. the remaining 210 mils becomes a parasitic capacitive stub, reducing the trace i mpedance, and contributing to the degradation of the gigabit signal. figure 9 and 0 show examples of the simulated eye pattern for the warplink interconnect for cases 13 and 14. the measurement of the eye width and peak-to-peak jitter are made at the zero crossing of the pattern and the eye height is made at the center of the eye opening. since this is a zero average value pattern, there should be no dc shift of the receiver input. figure 9 and 0 are typical of the improvement seen when the warplink tr ansmit pre-emphasis feature is utilized. as shown in the simulation results of table 4, the eye height was improved by an average of 26%, the eye width improved by 10%, and the peak-to -peak jitter improved by an average of 30%. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 14 figure 9. case 13 w ith xaui mask overlay figure 10. case 14 with xaui mask overlay eye height eye width jitter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 15 warplink interconnect impedance profile time domain reflectometry (tdr) interconnect simulation shown in figure 11 and figure 12 illustrates the impact of a via stub. a differential tdr source (nesa inc. proprietary simulation model) r eplaces the warplink driver while leaving the warplink packag e in the model. the receiver model is also removed and the interconnect is left open-circuited, which offers a clear indication of the e nd of the path. table 5. warplink gigabit interconnect variations case backplane length (in) via type 1 2 full 2 2 stub 3 10 full 4 10 stub 5 20 full 6 20 stub 7 40 full 8 40 stub table 5 details the six variations of the warplink gigabit interconnect. figure 11 and figure 12 illustrate the difference of the impedance profile for a stub via and a through via, respectively. figure 11. tdr of 10-inch backplane with via stubs the tdr highlights a number of issues for the interconnect. one of the goals of a high-frequency digital interconnect is to mai ntain as constant a characteristic impedance as possible. the vias and package impedance profiles of figure 11 and figure 12 show significant excursions from the reference impedance of 100 ohms. warplink package ermet-zd connector daughter card t-line open circuit termination reference back p lane t-line daughter card t-line daughter card via back p lane via daughter card via f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 16 figure 12. tdr of 10-inch backplane with through vias a comparison of the impedance profiles show that the through via produce smaller impedance discontinuity, figure 12, than the stub via case, figure 11. the package model presents a significant discontinuity in the simulation of the warplink interconnect, for bot h via cases. the large inductive spike is likely due to the lumped-element package model used in the simulations. the discontinuity of the ermet? zd connector reflected its ab ility to transmit 5gbps signals. the peak impedance level within t he connector region was approximately 95-98 ohms. the effects of the vias on both the daughter card and backplane influence this l evel due to risetime roll-off of the tdr pulse. the lossy characteristic of the transmission line is evident as seen in the increasing i mpedance along the length of the tdr profile. warplink reference system clock simulations the clock architecture for the warplink reference design pla tform is point-to-point. the clock operates at a digital frequency of 156.25 mhz. this data rate allowed the clock to be connected to t he daughter card thought a standard 2 mm hard metric connector, the e rmet? 2 mm-hm. the interconnect path models used for the clock simulations are almost identical to that of the gigabit warplink models. the main differences were the replacement of the ermet? zd with the ermet? 2 mm-hm connectors and the inclusion of the clock driver and receivers in place of the warplink devices. table 6. simulation matrix values variables range clock buffer device temperature 0 c, 25 c, and 100 c process ss, tt, ff supply voltage (3.3 v 10%) 3.0 v, 3.3 v, and 3.6 v interconnect backplane trace length 2, 10, and 20 inches line card and switch card vias one layer transition with stub and full board transition the variables and range of the simulation matrix for the clock are shown in table 6. the results of the simulations, exemplifie d by the waveform in figure 13, show little distortion and a well-controlled clock signal. reference warplink package daughter card t-line daughter card via ermet-zd connector backplane t-line backplane via daughter card t-line daughter card via open circuit termination f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 17 figure 13. typical clock receiver input simulation description of passive signal integrity measurements time domain reflectometry tdr was used to measure the impedance profile of the warplink reference design platform?s backplane interconnects. the impedanc e of an interconnect is important to determine since impedance mismatc hes due to surrounding structures can cause reflections, which in turn cause aberrations in signal fidelity. to measure the differential impedance, two signals of a pair are driven simultaneously wi th step sources of equal amplitude and opposite polarity. the far ends of t he lines are either open circuit or match terminated and the reflections are sampled at the tdr heads. the impedance is then determined usi ng both the incident and reflected wave components as an auto matic function of tdr/dso mainframe. differential time domain crosstalk crosstalk measurements were completed using the tdr step generat or to perturb an aggressor line while monitoring a victim line via the differential input channels. crosstalk measurements are basically a form of transmission measurement, where instead of measurin g at the output ports of a given excited pair, one measures at the near - or far-end ports of a neighboring pair. any remaining open port s are terminated, ideally in their characteristic impedance. such measurements will illustrate undesired signal coupling occurring be tween neighboring lines or differential pairs. the crosstalk can be expre ssed both in terms of the voltage amplitude as well as in pe rcentage of the driver or receiver voltage. coupling the stimulus and measurement techniques of the crosst alk measurement with the signals used to generate eye patterns ca n produce some interesting effects. by using a clock aggressor signal and a standard prbs signal through the victim line, distort ion can be observed when the added signal crosstalk is present. eye diagrams eye diagrams can demonstrate the goodness of a component or connection path by passing a random bit stream through and monitoring the output over a span of time. where the hits take place in time and voltage, and the distribution of the hits, can determine whether the device under test (dut) is transmitting data that can be properly interpreted when compared to a mask or other criteria set in advance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 18 to measure an eye pattern across the warplink backplane, the hp8133a pulse generator was used in the prbs23 data pattern mode, with the differential pulse voltage characteristics set to 500 mv level at 2.5 gbps and 3.125 gbps. once the equipment was set up, the procedure consisted of introducing the bit pattern into a line or differential signal pair and monitoring the output at the far end on the hp54750a. time domain test equipment the equipment used for the passive measurements included nesa's in-house time domain reflectometer/digital storage oscilloscope (tdr/dso) and 3 ghz pulse generator with prbs capabilities. a list of the hardware used to complete the relevant tasks follows: test equipment 1. hewlett-packard (hp) 54750a dso mainframe 2. hp54754a 18 ghz differential tdr/2 channel plug-in module 3. hp54751a 20 ghz 2 channel plug in module 4. hp8133a (w/option 2) 3 ghz pulse generator fixturing 5. w. l. gore phaseflex cables with apc 3.5 mm connectors (bw: dc-26.5 ghz) 6. sma, and apc loads, adapters, probes, and miscellaneous fixturing the tdr/dso equipment required for these investigations had to be very capable in terms of bandwidth, accuracy, and software su pport. nesa's in-house hp54750a tdr/dso is capable of completing diffe rential tdr and crosstalk, and can be used as a four-channel sam pler for measurements such as bit-pattern data rate tests. the hp8133a 3 ghz pulse generator was selected for its high bandwidth and many high-end features including two sets of differen tial outputs. the hp8133a can supply standard pulses, 32-bit pattern data sequences for data rate testing, and pseudo-random bit str eams (prbs), useful for such measurements as eye diagrams. this uni t allowed for testing up to 3.125 gbps. these measurements were collected and stored electronically using hewlett-packard's benchlink lightwave tm software. passive measurement results a passive signal integrity study was performed as part of the des ign of the warplink reference design platform. this study was performed in support of the active measurement and demonstration testing. the evaluation of the backplane establishes the quality of the impedance control of the pcb construction as well as setting a baseline for the eye pattern data before any equalization is used to recov er the gigabit signal. tdr results figure 14. simulated tdr of 10-inch backplane with via stubs warplink package ermet-zd connector daughter card t-line open circuit termination reference back p lane t-line daughter card t-line daughter card via back p lane via daughter card via f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 19 figure 15. measured tdr of 4.6-inch test card and 6.9-inch backplane figure 14 and figure 15 show the simulated and measured tdr impedance profiles for the warplink gigabit interconnect. the measured tdr profile was taken using the test card designed as part of this project, to access the channels on the backplane. the far en d of the backplane interconnect was left open-circuited to ease detection. although the impedance profiles are on different time scales the features of the interconnect do match. using this type of evaluat ion we can confirm that the simulation result, shown in the se ction warplink signal integrity simulation program , uses an interconnect model that is representative of the physical interconnect. note that the actual measurement does not include the package or the second daughter card in the impedance profile. the tdr measurement was also used to confirm the quality of t he pcb fabrication. the broadside couple differential interconnect s routes were specified to be 100 ohms 10%. this is the case for the warplink reference backplane and test card. the model and the measurement also similarly model the increasing impedance al ong the length of the interconnect due to accumulated losses. eye diagram measurement results as part of the passive signal-integrity study, eye diagrams were taken for a variety of route lengths on the warplink backplane . table 7 contains a full set of data measurements for both 2.5 gbd as well as 3.125 gbd. as expected, the longer the interconnect got an d the higher the data rate got, the smaller the eye opening got. these results proved the need for equalization in gigabit signaling over long interconnects. table 7. 2.5 / 3.125 gbd data measurements net name total length (in) data rate (gbps) eye height (mv) eye width (ps) jitter (p ? p) (ps) reference signal cables only 2.5 850.0 358.0 40.7 reference signal cables only 3.125 840.0 255.5 61.1 s4_d1_d0-s4_d1_d0_[n ? p] 8.1 2.5 537.8 295.8 101.5 s4_d1_d0-s4_d1_d0_[n ? p] 8.1 3.125 480.2 183.1 133.5 s7_d10_d0-s8_d10_c0_[n ? p] 11.3 2.5 501.3 291.6 107.1 s7_d10_d0-s8_d10_c0_[n ? p] 11.3 3.125 342.3 215.0 105.0 s2_d1_c0-s3_d1_b0_[n ? p] 18 2.5 376.9 252.3 145.9 s2_d1_c0-s3_d1_b0_[n ? p] 18 3.125 163.2 170.0 150.0 s1_d2_c0-s7_d9_a0_[n ? p] 29.0 2.5 253.0 185.5 212.7 s1_d2_c0-s7_d9_a0_[n ? p] 29.0 3.125 39.8 83.0 237.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 20 figure 16(b), demonstrates the distortion seen for the different ial pair s4_d1_d0-s4_d1_d0_p|n, a moderately long interconnect, 8.1 inches in total length, when compared to a reference path measur ement, shown in figure 16(a). the direct comparison allows us t o attribute the pcb interconnect of the warplink backplane and test card as the cause of the distortion in the eye opening. (a) reference path (b) s4_d1_d0-s4_d1_d0_[p|n] figure 16. passive eye patterns active measurement results while the passive measurements quantify the quality of the passive transmission channels, the active measurements show how warp link 2.5 quad performs over the same transmission channels. active eye patterns driven by a warplink transmitter through a variety o f transmission channels of the system?s backplane were obtained. xaui compliance was confirmed by overlaying the measured eye pat terns to the eye mask defined in the xaui specification. the followi ng sections describe the test setup and the various channels chos en for the active measurements presented in the paper. test setup eye diagrams from two different transmission channels are pres ented. the transmission channel connecting slot 8 and slot 1 was chosen as an example of the longest, and thus worst case, backplane channel that was not artificially lengthened. the second transmiss ion channel chosen connects slot 7 and slot 1. this channel was artificially lengthened to present a condition that exceeds an inte rconnect length defined by the xaui standard. a line card was installed in either slot 7 or 8. a test card from which the eye diagrams were obtained was in slot 1. the trans mitter was configured for the built-in self-test (bist) mode, configured fo r pn equation 2 of the 23-bit pn generator (please refer to the warplink 2.5 quad product brief for more details of the bist mode). the full dat a path from a warplink transmitter on a line card in slots 7 or 8 to the test card in slot 1 consisted of: 1. warplink device 2. package via 3. line card fr-4 trace 4. line card connector via 5. line card - backplane ermet? zd connector 6. backplane connector via 7. backplane fr-4 trace 8. backplane connector via 9. backplane connector 10. test card - backplane ermet? zd connector 11. test card fr-4 trace 12. sma via 13. smt - sma connector 14. sma right-angle adapter 15. 36 inches of rosenberger rf-coaxial cable 16. ac-coupling sma adapter 17. tds-8000 scope. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 21 the warplink device is clocked via the clock distribution networks originating from slot 7. (please refer to the clock distribu tion section for more details). the clock trigger of the tds-8000 is also clocked with the same clock distribution network, by way of the test c ard in slot 1. (a) without equalization (b) with equalization figure 17. active eye patterns tx ? slot 8 to rx ? slot 1 eye diagrams from slot 8 to slot 1 the interconnect between slots 8 and 1 are the longest channel in the 19" rack warplink design reference system that is not art ificially lengthened. the total length of the transmission channel in fr-4 is 18.7?. this includes 1.8? of fr-4 on the line card, 12.2? o n the backplane, and 4.7? on the test card. without pre-emphasis/equalizati on, warplink exceeds the xaui mask with a 5% margin. with pre- emphasis/equalization, the warplink gigabit link satisfies the xaui mask with a 9% margin. the comparison of figure 17(a) and f igure 17(b) shows a clear benefit of pre-emphasis/equalizat ion to the signal fidelity of the eye diagram. eye diagrams from slot 7 to slot 1 the artificially lengthened interconnect between slots 7 and 1 present s a condition that is worse than that defined by the xaui standard. this is a worst case routing condition that exemplifies a rout ing implementation on a large backplane. the total length of the transmission channel in fr-4 is 26.2?. this includes 1.8? of fr-4 on the line card, 19.7? on the backplane, and 4.7? on the test card. with pre- emphasis/equalization on, warplink passes the xaui mask with a 3% margin. as expected via simulation the resultant eye does not conform to the xaui mask with pre-emphasis/equalization disabled. again, the comparison of figure 18(a) and figure 18(b) shows a clear benefit of pre-emphasis/equalization to t he signal fidelity of the eye diagram. (a) without equalization (b) with equalization figure 18. active eye patterns tx ? slot 7 to rx ?slot 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 22 summary and conclusions the motorola warplink reference design platform demonstrates the capabilities of the warplink 2.5 quad serdes device. the devic e was operated at wire speed of 3.125 gbd to provide an aggregate speed of 10gbps per device. the device?s pre-emphasis/equalizat ion feature proved indispensable for data transfer at gigabit wire s peeds over long interconnects. in particular, warplink 2.5 quad has demonstrated the ability to operate at, and beyond the xaui specification of 3.125 gbd over 50cm long channels. the warplink reference design platform is built with common design practices, components, and pcb material (fr-4). unrealistic and expensive gigabit design requirements - such as blind vias, via drill-back, bottom-layer-only routing, and low dielectric const ant pcb materials - were not required. using a fully matured simulation and design methodology, nesa implemented a full end-to-end gigabit simulation matrix of cases. the currently available serdes model for warplink 2.5 quad was verified to emulate actual measured results. using this modeling str ategy, areas of risk for the gigabit links were identified and properly addressed while still in the design phase. the motorola warplink reference design platform has shown that 3.125 gbd serdes technology is a reality, with readily available support. proven reference design platforms and confirmed warplink i/o simulation models are available from motorola. acknowledgements this white paper was prepared as a joint effort by quang xuan nguyen of the motorola warplink design team and dr. edward sayer 3rd from north east systems associates inc. (nesa, www.nesa.com). nesa was contracted by motorola to do the design, perform simulat ions and define the layout rules for the reference backplane. their expertise lies in the area of the practical design and manufactu ring techniques required for high performance systems and backplanes. additional thanks go to michael baxter, nesa and thecla chomicz, motorola for their technical expertise and assistance in perfo rming the extensive passive and active measurements presented in this paper. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
warplink reference design platform ? 23 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola reserves the right to make changes without further not ice to any products herein. motorola makes no warranty, representation, or guarantee regarding the suitabilit y of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters can and do vary in different applications and actual performance may vary over time. a ll operating parameters, including ?typicals?, must be validated for each customer applic ation by customer?s technical experts . motorola does not convey any license under its patent rights nor the ri ghts of others. motorola produc ts are not designed, intended , or authorized for use as components in systems intended for surgical implant into the bo dy, or other applications inte nded to support or sustain life, or for any other applicati on in which the failure of the motorola prod uct could create a situation where personal injury or death may occur. should buye r purchase or use motorola products fo r any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries , affiliates, and distributors harmless against all claims, costs, dam ages, and expenses, and reasonabl e attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regar ding the design or manufacture of the pa rt. motorola and the stylized m logo are registered in the us pat ent & trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002 BR1570/d, rev 0 how to reach us: usa / europe / locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-303-675-2140 1-800-441-2447 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu, minato-ku tokyo, 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 technical information center: 1-800-521-6274 home page : http://www.motorola.com/semiconductors/ f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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