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lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers application note january 2001 order number: 249136-001 as of january 15, 2001, this document replaces the level one document known as an120 .
application note information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ? reserved ? or ? undefined. ? intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
application note 3 lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers contents 1.0 general description .................................................................................................. 5 2.0 digital interface ........................................................................................................... 6 2.1 unipolar/bipolar interface...................................................................................... 6 2.1.1 bipolar interface ....................................................................................... 6 2.1.2 unipolar interface ..................................................................................... 7 2.2 timing considerations...........................................................................................8 2.3 loss of signal detection........................................................................................ 9 2.3.1 bipolar mode ............................................................................................ 9 2.3.2 unipolar mode .......................................................................................... 9 2.4 bpv detection ....................................................................................................... 9 2.4.1 bipolar mode ............................................................................................ 9 2.4.2 unipolar mode .......................................................................................... 9 2.5 ais detection ......................................................................................................10 3.0 jitter attenuator ........................................................................................................11 4.0 5v i/o tolerance .......................................................................................................12 5.0 design guidelines ....................................................................................................13 figures 1 bipolar interface .................................................................................................... 6 2 unipolar interface .................................................................................................. 8 tables 1 bipolar interface settings ...................................................................................... 7 2 unipolar interface settings ....................................................................................8

lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers application note 5 1.0 general description the lxt380/4 series of octal line interface units (lius) are the highest density t1/e1 solutions currently available on the market. the lxt380 is an octal e1 (only) liu with clock and data recovery. the lxt384 is a full featured t1/e1 liu with crystal-less jitter attenuator. in many applications, these lius will interface with multi-port framers. the transwitch txc- 03108 octal t1 framer and the txc-03109 octal e1 framer are a natural choice given their rich feature set and high density packages. this application note shows that the transwitch octal t1/e1 framers can easily interface with the lxt380/4 series of lius. the following sections provide some guidelines regarding the connection of these devices in a typical t1/e1 application. lxt380/4 lxt380/4 txc-03109 or txc-03108 txc-03109 or txc-03108 backplane backplane 8 x t1/e1 8 x t1/e1
lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers 6 application note 2.0 digital interface 2.1 unipolar/bipolar interface the lxt380/4 and the txc-03108/9 interface at the digital level through independent sets of data and clock signals for the receive and transmit paths. this interface can be either unipolar or bipolar. given the bipolar interface?s simplicity, it is recommended for most applications. 2.1.1 bipolar interface in bipolar mode, the liu and the framer communicate using three signals in each direction: positive pulse (pos), negative pulse (neg) and clock (clk). see figure 1 . at the receive side, rpos and rneg indicate the liu receiver has detected either a positive or negative pulse. rclk is the clock extracted from the incoming signal, and is used to latch the rpos/rneg data into the framer. bipolar mode is sometimes called ?dual rail mode?, or ?transparent mode? as the liu simply reports the reception of negative or positive pulses to the framer. note that the t1/e1 input signal is a three level signal with 0 v, positive or negative pulses. therefore, in bipolar mode the framer must decode the sequence of positive and negative pulses into a data stream of 0?s and 1?s. as a result, the framer?s hdb3 or ami/b8zs decoders must be enabled. at the transmit side, the liu outputs either positive or negative pulses according to the tpos/ tneg data. when tpos is high, a positive pulse is transmitted. when tneg is high, a negative pulse is transmitted. when both tpos and tneg are low, no pulse is transmitted onto the line. tclk is used to latch the tpos/tneg data into the liu. note that since the sequence of positive and negative pulses (encoding) is not determined by the liu, the hdb3 or b8zs/ami encoder must be enabled in the framer. table 1 summarizes the settings in both the lxt380/4 and the txc- 03108/9 for bipolar interface mode. figure 1. bipolar interface lxt380/4 (one channel) txc-03108/9 (one channel) tclk tpos tneg tclk tpos tneg rclk rpos rneg rclk rpos rneg tx rx
lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers application note 7 2.1.2 unipolar interface in unipolar mode, the liu and the framer exchange data using only two signals in each direction: one for data (data) and another for clock (clk). see figure 2 . unipolar mode is sometimes referred to as ? single rail ? or ? nrz ? mode. at the receive side, rdata indicates the data content in the receive signal. rclk is used to latch the rdata information into the framer. unipolar mode assumes that the data content of the liu receive signal has already been decoded into a stream of 1 ? s and 0 ? s. therefore, the hdb3 or b8zs/ami codecs should enabled in the liu. at the transmit side, the tnrz/tclk outputs from the framer connect directly to the tdata/ tclk inputs of the liu. the liu is responsible for encoding the data stream into hdb3 or b8zs/ ami line code. table 2 summarizes the settings in both the lxt380/4 and the txc-03108/9 for unipolar interface mode. table 1. bipolar interface settings lxt380/4 txc-03109/8 clke = high : rpos/rneg valid on falling edge of rclk. tpos/tneg valid on falling edge of tclk. rxcp = 0: bit 5 in register x+00h. rpos/rneg valid on falling edge of rclk. txcp = 0: bit 3 in register x+05h. tpos/tneg valid on falling edge of tclk. rail = 1: bit 7 in register x+00h. sets dual rail interface. 1 b8zs: bit 6 in register x+00h. 2 b8zs = 1 sets b8zs codec b8zs = 0 sets ami codec 1. note that transwitch refers to this interface as being ? unipolar ? . this is the reverse of intel ? s notation. 2. txc-03108 with lxt384 only.
lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers 8 application note 2.2 timing considerations the timing characteristics of the lxt380/4 and the txc-03108/9 are compatible. there is sufficient setup and hold time margin at both the receive and transmit interfaces. figure 2. unipolar interface table 2. unipolar interface settings lxt380/4 txc-03109/8 clke = high : rdata valid on falling edge of rclk. tdata valid on falling edge of tclk (default). rxcp = 0 : bit 5 in register x+00h. rnrz valid on falling edge of rclk. tneg/ubs = high : sets unipolar mode. txcp = 0 : bit 3 in register x+05h. tnrz valid on falling edge of tclk. coden pin in hardware mode 2 : coden=high for ami coden=low for b8zs coden bit in software mode 2 , bit 4 in register gcr: coden=1 for ami coden=0 for b8zs note: in unipolar mode, the lxt380 enables hdb3 codecs by default. rail = 0 : bit 7 in register x+00h. sets single rail interface. 1 3. note that transwitch refers to this interface as a ? nrz interface ? . 1. txc-03108 with lxt384 only. lxt380/4 (one channel) txc-03108/9 (one channel) tclk tnrz tclk tdata tneg/ubs rclk rnrz rscan rclk rdata rneg/bpv tx rx 10 k vcc
lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers application note 9 2.3 loss of signal detection 2.3.1 bipolar mode loss of signal (los) can be detected at either the framer or at the liu. the txc-03108/9 los detection is based on the content of the rpos/rneg outputs. the los status is reported in the corresponding line status registers. alternatively, the lxt380/4 can be used to detect los. in software mode, the los register will indicate a los condition in any of the eight channels. in hardware mode, the individual los pins will go high when a los condition is detected in the corresponding channel. 2.3.2 unipolar mode in unipolar mode, the liu is responsible for los detection. in software mode, los status is reported in the lxt380/4 los register. los status can also be communicated to the framer via the los pins. if the los condition is to be reported to the framer, then the los output pin for each channel should be connected to the corresponding rscan input pin of the txc-03108/9. in addition, the rxfs bit (address x+1ff) and the exlos and elosn bits (address x+00) should be set as follows: rxfs = 0; rscan is not used as frame sync. exlos = 1; rscan is used as external los detect. elosn = 0; rscan los detect is active high. with the above configuration, the los status will be reflected in the framer line status registers. 2.4 bpv detection 2.4.1 bipolar mode in bipolar mode, code violations are detected by the framer and reported in the corresponding performance counters. 2.4.2 unipolar mode in unipolar mode, code violations are detected by the liu and reported at the rneg/bpv output pins. if the code violations need to be monitored, the rneg/bpv pin should be connected to the corresponding rscan inputs of the txc-03108/9. see figure 2 . in addition, the rxfs bit (address x+1ff) and exlos bit (address x+00) should be set as follows: rxfs = 0; rscan is not used as frame sync. exlos = 0; rscan used as code violation detect.
lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers 10 application note with the above configuration, code violations will be detected by the framer and reported in the corresponding performance counters. note that since the rscan inputs are being used for bpv detection, los detection can only be done at the liu level. therefore, either los or bpv can be communicated to the framer, but not both. see ? loss of signal detection ? on page 9 . 2.5 ais detection an alarm indication signal (ais) can be detected by the framer. the ais alarm is reported in the corresponding status register. the lxt384 can also detect ais in software mode. this feature is not available in the lxt380.
lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers application note 11 3.0 jitter attenuator for e1 only applications the txc-3109 offers a digital jitter attenuator that will remove jitter in the receive path. for t1 only or t1/e1 applications, the lxt384 offers an advanced ctr12 compliant jitter attenuator that can be placed in either the receive or the transmit path.
lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers 12 application note 4.0 5v i/o tolerance both the txc-03108/9 and the lxt380/4 are 3.3v devices. when either of them interface with a 5v i/o device (a microprocessor for example), it is crucial to have 5v tolerant inputs. all these devices can interface directly with 5v ics. the txc-03108/9 and the lxt384 accomplish this by offering 5v tolerant inputs. the lxt380 on the other hand, includes separate output ring power pins (vccio) that should be connected to the 5v supply when interfacing with 5v devices. please refer to the lxt380 faq, section 4.6 for details.
lxt380/4 octal t1/e1 lius ? interfacing with the transwitch octal framers application note 13 5.0 design guidelines here ? s a list of general design guidelines: avoid routing digital signals near analog signals . this is especially important near the receiver inputs as the cross- talk may induce bit errors. provide ample power and ground planes . this practice will reduce emissions and assure signal integrity across the board. reduce trace lengths connecting the devices, especially the clock signals . although the t1/ e1 clock frequencies are relatively low, the rise and fall times in modern sub-micron cmos technologies can be extremely fast. the lxt380/4 have controlled slew rate output buffers that help minimize problems associated with fast transitions. however, the rise/fall time from the framers, or other digital devices, may be considerably faster. this can create signal integrity problems when long traces connect the devices. as a rule of thumb, terminate clock signals between devices when the distance exceeds 6 inches. use decoupling capacitors near the power supply pins . decoupling capacitors will help reduce switching noise in the power supply. follow the recommendations in the corresponding datasheets.

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