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1 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p040-xxm 68040 features n selection of processor speeds: 25, 33mhz n military temperature range: - 55 c to +125 c n packaging ? 179 pin ceramic pga (p4) ? 184 lead ceramic quad flatpack, cqfp (q4) n 6-stage pipeline, 68030-compatible iu n 68881/68882-compatible fpu n independent instruction and data mmus n simultaneously accessible, 4-kbyte physical instruction cache and 4-kbyte physical data cache n low-latency bus acceses for reduced cache miss penalty n multimaster/multiprocessor support via bus snooping n concurrent iu, fpu, mmu, and bus controller operation maximizes throughput n 32-bit, nonmultiplexed external address and data buses with synchronous interface july 1998 fig. 1 block diagram n user object-code compatible with all earlier 68000 microprocessors n 4-gigabyte direct addressing range description the wc32p040 is a 68000-compatible, high-performance, 32- bit microprocessor. the wc32p040 is a virtual memory microprocessor employing multiple concurrent execution units and a highly intergrated architecture that provides very high performance in a monolithic hcmos device. it has a 68030- compatible integer unit (iu) and two independent caches. the wc32p040 contains dual, independent, demand-paged memory management units (mmus) for instruction and data stream accesses and independent, 4-kbyte instruction and data caches. the wc32p040 has a 68881/68882-compatible floating-point unit (fpu).
2 white microelectronics ? phoenix, az ? (602) 437-1520 fig. 2 pin configuration for wc32p040-xxm, cqfp (q4) 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 gnd gnd a 31 a 30 v cc a 29 a 28 gnd a 27 a 26 v cc a 25 a 24 gnd a 23 a 22 v cc a 21 a 20 gnd a 19 a 18 v cc gnd a 17 a 16 gnd a 15 a 14 v cc a 13 a 12 gnd a 11 a 10 gnd v cc tt 1 tt 0 gnd upa 1 upa 0 v cc ciout ipend gnd rsto td 0 td 1 tck gnd trst tms gnd v cc mdis cdis rsti ipl 2 ipl 1 ipl 0 gnd gnd bclk v cc gnd v cc gnd pclk gnd gnd dle gnd gnd tci avec tbi v cc gnd sc 0 sc 1 bg tea ta pst 0 gnd pst 1 pst 2 v cc pst 3 tip gnd d 27 gnd d 28 d 29 v cc d 30 d 31 gnd gnd a 9 a 8 v cc a 7 a 6 gnd a 5 a 4 v cc a 3 a 2 gnd a 1 a 0 v cc gnd tm 2 tm 1 gnd tm 0 tln 1 v cc tln 0 siz 0 gnd r/w locke v cc gnd siz 1 lock gnd mi br v cc ts bb d 0 d 1 v cc gnd d 2 d 3 gnd d 4 gnd d 5 v cc d 6 d 7 gnd d 8 d 9 v cc gnd d 10 d 11 gnd d 12 d 13 v cc d 14 d 15 gnd d 16 d 17 v cc gnd d 18 d 19 gnd d 20 d 21 v cc d 22 v cc d 23 gnd d 24 d 25 gnd v cc d 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 wc32p040-xxm top view pin group gnd vcc pll 17,22,24 19,21 internal logic 5,8,10,27,28,33,55,68,95,108,121, 9,32,56,69,81,94,100,109,122,136,149, 130,135,162,174 161,175 output drivers 16,20,25,40,46,52,59,65,72,78,84,85, 43,49,62,75,88,102,115,128,143,155, 91,98,105,112,118,125,132,139,140, 168,181 146,152,158,165,171,178,184
3 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p040-xxm fig. 3 pin configuration for wc32p040-xxm, pga (p4) ipend ciout upa 1 a 10 a 12 a 13 a 14 a 15 a 17 a 18 a 20 a 21 a 22 a 24 a 27 a 29 a 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 tdo gnd v cc gnd tt1 gnd v cc gnd a 16 a 19 gnd v cc gnd a 26 gnd v cc gnd d 3 trst tdi rtso upa 0 tt 0 a 11 v cc gnd gnd v cc v cc a 23 a 25 a 28 a 30 d 0 d 1 d 4 gnd tck gnd d 2 gnd d 5 cdis tms v cc v cc v cc d 6 ipl 2 mdis gnd gnd gnd d 7 ipl 1 rsti bclk gnd d 8 d 9 ipl 0 v cc v cc v cc gnd d 10 dle gnd pclk gnd v cc d 11 tci gnd gnd v cc gnd d 12 avec tbi gnd gnd d 16 d 13 bb gnd v cc gnd siz 0 gnd v cc gnd tm 2 a 2 gnd v cc gnd d 30 gnd v cc gnd d 21 br lock locke tln 0 tln 1 tm 0 tm 1 a 0 a 1 a 3 a 4 a 5 a 7 a 8 d 31 d 28 d 26 d 24 t s r q p n m l k j h g f e d c b a v cc d 18 d 14 gnd gnd d 15 v cc v cc d 17 d 23 gnd d 19 pst 3 v cc ts mi siz 1 r/w gnd v cc gnd v cc v cc a 6 a 9 d 29 d 27 d 25 d 22 d 20 sc 0 sc 1 v cc bg tea gnd ta pst 1 pst 2 pst 0 gnd tip bottom view pin group gnd vcc pll s9,r6,r10 r8,s8 internal logic c6,c7,c9,c11,c13,k3,l3,m16,r4, c5,c8,c10,c12,c14,h3,h16,j3,j16, r11,r13,s6,s10,t4 l16,m3,r5,r12 output drivers b2,b4,b6,b8,b10,b13,b15,b17,d2, b5,b9,b14,c2,c17,g2,g17,m2,m17, d17,f2,f17,h2,h17,l2,l17,n2,n17, r2,r17,s16 q2,q17,s2,s15,s17
4 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p040-xxm addressing modes addressing syntax register direct data register direct dn address register direct an register indirect address register indirect (an) address register indirect with postincrement (an) + address register indirect with predecrement - (an) address register indirect with displacement (d 16 ,an) register indirect with index address register indirect with index (8-bit displacement) (d 8 ,an,xn) address register indirect with index (base displacement) (bd,an,xn) memory indirect memory indirect postindexed ([bd,an],xn,od) memory indirect preindexed ([bd,an,xn],od) program counter indirect with displacement (d 16 ,pc) program counter indirect with index pc indirect with index (8-bit displacement) (d 8 ,pc,xn) pc indirect with index (base displacement) (bd,pc,xn) program counter memory indirect pc memory indirect postindexed ([bd,pc],xn,od) pc memory indirect preindexed ([bd,pc,xn],od) absolute absolute short (xxx).w absolute long (xxx).l immediate # operand data format size supported in notes bit 1 bit iu C bit field 1-32 bits iu field of consecutive bits binary-coded decimal (bcd) 8 bits iu packed: 2 digits/byte; unpacked: 1 digit/byte byte integer 8 bits iu, fpu C word integer 16 bits iu, fpu C long-word integer 32 bits iu, fpu C quad-word integer 64 bits iu any two data registers 16-byte 128 bits iu memory only, aligned to 16-byte boundary single-precision real 32 bits fpu 1-bit sign, 8-bit exponent, 23-bit fraction double-precision real 64 bits fpu 1-bit sign,11-bit exponent, 52-bit fraction extended-precision real 80 bits fpu 1-bit sign,15-bit exponent, 64-bit mantissa addresssing the wc32p040 supports the basic addressing modes of the 68000 family. the register indirect addressing modes support postincrement, predecrement, offset, and indexing. the program counter indirect mode also has indexing and offset capabilities. data formats opcode operation syntax abcd bcd source + bcd destination + x ? destination abcd dy,dx abcd -(ay),-(ax) add source + destination ? destination add ,dn add dn, adda source + destination ? destination adda ,an addi immediate data + destination ? destination addi #, addq immediate data + destination ? destination addq #, addx source + destination + x ? destination addx dy,dx addx -(ay),-(ax) and source l destination ? destination and ,dn and dn, andi immediate data l destination ? destination andi #, andi to ccr source l ccr ? ccr andi #,ccr andi to sr if supervisor state andi #,sr then source l sr ? sr else trap asl,asr destination shifted by count ? destination asd dx,dy (1) asd #,dy (1) asd (1) bcc it condition true bcc then pc + dn ? pc instruction set summary data formats the wc32p040 supports the basic data formats of the 68000 family. some data formats apply only to the iu, some only to the fpu, and some to both. in addition, the instruction set supports operations on other data formats such as memory addresses.
5 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p040-xxm instruction set summary (cont.) opcode operation syntax bchg ~(bit number of destination) ? z; bchg dn, ~(bit number ot destination) ? (bit number) of destination bchg #, bclr ~(bit number ot destination) ? z; bclr dn, 0 ? bit number ot destination bclr #, bfchg ~(bit field ot destination) ? bit field of destination bfchg {offset:width} bfclr 0 ? bit field of destination bfclr {offset:width} bfexts bit field of source ? dn bfexts {offset:width}, dn bfextu bit offset of source ? dn bfextu {offset:width}, dn bfffo bit offset of source bit scan ? dn bfffo {offset:width}, dn bfins dn ? bit field of destination bfins dn, {offset:width} bfset 1s ? bit field of destination bfset {offset:width} bftst bit field of destination bftst {offset:width} bkpt run breakpoint acknowledge cycle; trap as illegal instruction bkpt # bra pc+d n ? pc bra bset ~(bit number ot destination) ? z; bset dn, 1 ? bit number of destination bset #, bsr sp - 4 ? sp; pc ? (sp); pc + dn ? pc bsr btst C(bit number of destination) ? z btst dn, btst #, cas cas destination C compare operand ? cc; cas dc,du, if z, update operand ? destination else destination ? compare operand cas2 cas2 destination 1 C compare 1 ? cc; cas2 dc1-dc2,du1-du2,(rn1)-(rn2) if z, destination 2 C compare ? cc; if z, update 1 ? destination 1; update 2 ? destination 2 else destination 1 ? compare 1; destination 2 ? compare 2 chk if dn < 0 or dn > source then trap chk ,dn chk2 if rn < lb or if rn > ub then trap chk2 ,rn cinv if supervisor state cinvl , then invalidate selected cache lines (an) cinvp , else trap (an) cinva clr 0 ? destination clr cmp destination C source ? cc cmp ,dn cmpa destination C source cmpa ,an cmpi destination C immediate data cmpi #, cmpm destination C source ? cc cmpm (ay)+,(ax)+ cmp2 compare rn < lb or rn > ub and set condition codes cmp2 ,rn cpush if supervisor state cpushl , (an) then it data cache push selected dirty data cache lines; cpushp , (an) invalidate selected cache lines cpusha else trap dbcc if condition false dbcc dn, then (dn-1 ? dn; if (dn 1 -1 then pc + dn pc) divs, divsl destination + source ? destination divs.w ,dn 32 + 16 ? 16r:16q divs.l ,dq 32 + 32 ? 32q divs.l ,dr:dq 64 + 32 ? 32r:32q divsl.l ,dr:dq 32 + 32 ? 32r:32q divu, divul destination + source ? destination divu.w ,dn 32 + 16 ? 16r:16q divu.l ,dq 32+32 ? 32q divu.l ,dr:dq 64 + 32 ? 32r:32q divul.l ,dr:dq 32 + 32 ? 32r:32q eor source ? destination ? destination eor dn, eori immediate data ? destination ? destination eori #, eori to ccr source ? ccr ? ccr eori #,ccr
6 white microelectronics ? phoenix, az ? (602) 437-1520 instruction set summary (cont.) opcode operation syntax eori to sr if supervisor state eori #,sr then source ? sr ? sr else trap exg rx ? ry exg dx,dy exg ax,ay exg dx,ay exg ay,dx ext,extb destination sign C extended ? destination ext.w dn extend byte to word ext.l l dn extend word to long word extb.l dn extend byte to long word fabs absolute value of source ? fpn fabs. ,fpn fabs.x fpm,fpn fabs.x fpn frabs. ,fpn (2) frabs.x fpm,fpn (2) frabs.x fpn (3) fadd source + fpn ? fpn fadd.,fpn fadd.x fpm,fpn fradd. ,fpn (2) fradd.x fpm,fpn (2) fbcc if condition true fbcc.size then pc + d n ? pc fcmp fpn C source fcmp. ,fpn fcmp.x fpm,fpn fdbcc it condition true fdbcc dn, then no operation else dn-1 ? dn if dn 1 -1 then pc + d n ? pc else execute next instruction fdiv fpn + source ? fpn fdiv. ,fpn fdiv.x fpm,fpn frdiv. ,fpn (2) frdiv.x fpm,fpn (2) fmove source ? destination fmove. ,fpn fmove. fpm, fmove.p fpm,{dn} fmove.p fpm,{#k} frmove. ,fpn (2) fmove source ? destination fmove.l ,fpcr fmove.l fpcr, fmovem register list ? destination fmovem.x , (3) source ? register list fmovem.x dn, fmovem.x , (3) fmovem.x ,dn fmovem register list ? destination fmovem.l , (4) source ? register list fmovem.l , (4) fmul source x fpn ? fpn fmul. ,fpn fmul.x fpm,fpn frmul ,fpn (2) frmul.x fpm,fpn (3) fneg C(source) ? fpn fneg. ,fpn fneg.x fpm,fpn fneg.x fpn frneg. ,fpn (2) frneg.x fpm,fpn (2) frneg.x fpn (2) fnop none fnop frestore if in supervisor state frestore then fpu state frame ? internal state else trap ? wc32p040-xxm
7 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p040-xxm instruction set summary (cont.) opcode operation syntax fsave if in supervisor state fsave then fpu internal state ? state frame else trap fscc if condition true fscc.size then 1s ? destination else 0s ? destination fsgldiv fpn ? source ? fpn fsgldiv. ,fpn fsgldiv.x fpm,fpn fsglmul source x fpn ? fpn fsgmul. ,fpn fsglmul.x fpm, fpn fsqrt square root of source ? fpn fsqrt. ,fpn fsqrt.x fpm,fpn fsqrt.x fpn frsqrt. ,fpn fsub.x fpm,fpn frsub. ,fpn (2) frsub.x fpm,fpn3 (2) ftrapcc if condition true ftrapcc then trap ftrapcc.w # ftrapcc.l # ftst condition codes tor operand ? fpcc ftst.dmt> ftst.x fpm illegal ssp C 2 ? ssp; vector offset ? (ssp); illegal ssp C 4 ? ssp; pc ? (ssp); ssp C 2 ? ssp; sr ? (ssp) illegal instruction vector address ? pc jmp destination address ? pc jmp jsr sp C 4 ? sp; pc ? (sp) jsr destination address ? pc lea ? an lea ,an link sp C 4 ? sp;an ? (sp) link an,d n sp ? an, sp + d ? sp lsl,lsr destination shifted by count ? destination lsd dx,dy (1) lsd #,dy (1) lsd (1) move source ? destination move , movea source ? destination movea , an move from ccr ccr ? destination move ccr, move to ccr source ? ccr move ,ccr move from sr if supervisor state move sr, then sr ? destination else trap move to sr if supervisor state move ,sr then source ? sr else trap move usp it supervisor state move usp,an then usp ? an or an ? usp move an,usp else trap move1 6 source block ? destination block move16 (ax)+, (ay)+ (5) move16 (xxx).l, (an) move16 (an), (xxx).l move16 (an)+, (xxx).l movec if supervisor state then rc ? rn or rn ? rc else trap movec rc,rn movec rn,rc movem registers ? destination movem , (3) source ? registers movem , (3) movep source ? destination movep dx,(d n ,ay) movep (d n ,ay),dx
8 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p040-xxm instruction set summary (cont.) opcode operation syntax moveq immediate data ? destination moveq #,dn moves if supervisor state moves rn, then rn ? destination [dfc) or source [sfc] ? rn moves ,rn else trap muls source x destination ? destination muls.w ,dn 16 x 16 ? 32 muls.l ,dh-dl 32 x 32 ? 64 mulu source x destination ? destination mulu.w ,dn 16 x 16 ? 32 mulu.l ,di 32 x 32 ? 32 mulu.l ,dh-di 32 x 32 ? 64 nbcd 0 C (destination10) C x ? destination nbcd neg 0 C (destination) ? destination neg negx 0 C (destination) C x ? destination negx nop none nop not ~ destination ? destination not or source v destination ? destination or ,dn or dn, ori immediate data v destination ? destination ori #, ori to ccr source v ccr ? ccr ori #,ccr ori to sr if supervisor state ori #,sr then source v sr ? sr else trap pack source (unpacked bcd) + adjustment ? destination (packed bcd) pack -(ax),-(ay),#(adjustment) pack dx,dy,#(adjustment) pea sp C 4 ? sp; ? (sp) pea pflush if supervisor state pflush (an) then invalidate instruction and data atc entries pflushn (an) for destination address pflusha else trap pflushan ptest if supervisor state ptestr (an) then logical address status ? mmusr; entry ? atc ptestw (an) else trap reset if supervisor state reset then assert rsto line else trap rol, ror destination rotated by count ? destination rod rx,dy(1) rod #,dy(1) roxl, roxr destination rotated with x by count ? destination roxd dx,dy(1) roxd #,dy(1) roxd (1) rtd (sp) ? pc; sp + 4 + d n ? sp rtd #(d n ) rte if supervisor state rte then (sp) ? sr; sp + 2 ? sp; (sp) ? pc; sp + 4 ? sp; restore state and deallocate stack according to (sp) else trap rtr (sp) ? ccr; sp + 2 ? sp; rtr (sp) ? pc; sp + 4 ? sp rts (sp) ? pc; sp + 4 ? sp rts sbcd destination10 C source 10 C x ? destination sbcd dx,dy sbcd C(ax),C(ay) scc if condition true scc then 1s ? destination else 0s ? destination stop if supervisor state stop # then immediate data ? sr; stop elsetrap
9 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p040-xxm instruction set summary (cont.) opcode operation syntax sub destination C source ? destination sub ,dn sub dn, suba destination C source ? destination suba ,an subi destination C immediate data ? destination subi #, subq destination C immediate data ? destination subq #, subx destination C source C x ? destination subx dx,dy subx (ax), (ay) swap register 31 C 16 ? register 15 C 0 swap dn tas destination tested ? condition codes; tas 1 ? bit 7 of destination trap ssp C 2 ? ssp; format + offset ? (ssp) trap # ssp C 4 ? ssp; pc ? (ssp); ssp - 2 ? ssp; sr ? (ssp); vector address ? pc trapcc if cc trapcc then trap trapcc.w # trapcc.l # trapv if v trapv then trap tst destination tested ? condition codes tst unlk an ? sp; (sp) ? an; sp + 4 ? sp unlk an unpk source (packed bcd) + adjustment ? destination (unpacked bcd) unpack C(ax ), C(ay), # (adjustment) unpack dx,dy, #(adjustment) notes: 1. where d is direction, left or right. 2. where r is rounding precision, single or double precision. 3. list refers to register. 4. list refers to control registers only. 5. move16 (ax)+, (ay)+ is functionally the same as move16 (ax), (ay)+ when ax = ay. the address register is only incremented onc e, and the line is copied over itself rather than to the next line.
10 white microelectronics ? phoenix, az ? (602) 437-1520 fig. 4 functional signal groups a31-a0 d31-d0 tt0 tt1 tm0 tm1 tm2 tln0 tln1 upa0 upa1 r/w siz0 siz1 lock locke ciout ts tip ta tea tci tbi dle sc0 sc1 mi br bg bb cdis mdis rsti rsto ipl0 ipl1 ipl2 ipend avec pst0 pst1 pst2 pst3 bclk pclk tck tms tdi tdo trst vcc gnd transfer attributes power supply bus snoop control and response bus arbitration master transfer control processor control address bus data bus slave transfer control interrupt control status and clocks test wc32p040-xxm
11 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p040-xxm signal index signal name mnemonic function address bus a31-a0 32-bit address bus used to address any of 4-gbytes. data bus d31-d0 32-bit data bus used to transfer up to 32 bits of data per bus transfer. transfer type tt1,tt0 indicates the general transfer type: normal, move16, alternate logical function code, and acknowledge. transfer modifier tm2-tm0 indicates supplemental information about the access. transfer line number tln1-tln0 indicates which cache line in a set is being pushed or loaded by the current line transfer. user-progammable attributes upa1,upa0 user-defined signals, controlled by the corresponding user attribute bits from the address translation entry. read/write r/w identifies the transfer as a read or write. transfer size siz0/siz1 indicates the data transfer size. these signals, together with a0 and a1, define the active sections of t he data bus. bus lock lock indicates a bus transfer is part of a read-modify-write operation, and the sequence of transfers should be interrupted. bus lock end locke indicates the current transfer is the last in a locked sequence of transfers. cache inhibit out ciout indicates the processor will not cache the current bus transfer. transfer start ts indicates the beginning of the bus transfer. transfer on progress tip asserted for the duration of a bus transfer. transfer acknowledge ta asserted to acknowledge a bus transfer. transfer error acknowledge tea indicates an error condition exists for a bus transfer. transfer cache inhibit tci indicates the current bus transfer should not be cached. transfer burst inhibit tbi indicates the slave cannot handle a line burst access. data latch enable dle alternate clock input used to latch input data when the processor is operating in dle mode. snoop control sc1,sc0 indicates the snooping operation required during an alternate master access. memory inhibit mi inhibits mem ory devices from responding to an alternate master access during snooping operations. bus request br asserted by the processor to request bus mastership. bus grant bg asserted by an arbiter to grant bus mastership to the processor. bus busy bb asserted by the current bus master to indicate it has assumed ownership of the bus. cache disable cdis dynamically disables the internal caches to assist emulator support. mmu disable mdis disables the translation mechanism of the mmus. reset in rsti processor reset. reset out rsto asserted during execution of a reset instruction to reset external devices. interrupt priority level ipl2-ipl0 provides an encoded interrupt level to the processor. interrupt pending ipend indicates an interrupt is pending. autovector avec used during an interrupt acknowledge transfer to request internal generation of the vector number. processor status pst3-pst0 indicates internal processor status. processor clock pclk clock input used for internal logic timing. the pclk frequency is exactly 2 x the blck frequency. test clock tck clock signal for the ieee p1149.1 test access port (tap). test mode select tms selects the principle operations of the test-support circuitry. test data input tdi serial data input for the tap. test data output tdo serial data output for the tap. test reset trst provides an asynchronous reset of the tap controller. power supply vcc power supply. ground gnd ground connection.
12 white microelectronics ? phoenix, az ? (602) 437-1520 dc electrical specifications (v cc = 5.0 v dc 5%) notes: 1. capacitance is guaranteed by design but not tested. characteristics symbol min max unit input high voltage v ih 2.0 vcc v input low voltage v il gnd 0.8 v undershoot C C 0.8 v input leakage current avec, bclk, bg, cdis, mdis, iplx, pclk, rsti, scx, tbi, i in 20 20 m a @ 0.5/2.4v tmx, tlnx, tci, tck, tea high-z (off state) leakage current an, bb, ciout, dn, lock, locke, r/w, siz x , ta, i tsi 20 20 m a @ 0.5/2.4 v tdo, tip, tmx, tlnx, ts, ttx, upax signal low input current, v il = 0.8v tms, tdi, trst i il -1.1 -0.18 ma signal high input current, v ih = 2.0v tms, tdi, trst i ih -0.94 -0.16 ma output high voltage, i oh = 5ma (small buffer mode) v oh 2.4 C v output low voltage, i ol = 5ma (small buffer mode) v ol C 0.5 v output high voltage, i oh = 55ma (large buffer mode) v oh 2.4 C v output low voltage, i ol = 55ma (large buffer mode) v ol C 0.5 v capacitance (1), v in = 0v, f = 1mhz c in -20pf wc32p040-xxm parameter symbol value unit supply voltage v cc -0.3 to +7.0 v input voltage v in -0.5 to +7.0 v maximum operating temperature t j +125 c minimum operating temperature t a -55 c storage temperature t stg -55 to +150 c maximum ratings parameter symbol value rating thermal resistance, junction to case C q jc 3.0 c/w pga package thermal characteristics power dissipation buffer mode 25 mhz 33 mhz small unterminated, i ol = i oh = 5ma 4.9w 6.2w large unterminated, i ol = i oh = 5ma 5.1w 6.6w large terminated, 50 w , 2.5v, i ol = i oh = 55ma 6.5w 8.0w
13 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p040-xxm fig.5 clock input timing diagram clock ac timing specifications (see fig. 5) characteristic specification 25 mhz 33 mhz unit min max min max frequency of operation 20 25 20 33 mhz pclk cycle time 1 20 25 15 25 ns pclk rise time 2 C 1.7 C 1.7 ns pclk fall time 3 C 1.6 C 1.6 ns pclk duty cycle measured at 1.5v 4 47.50 52.50 46.67 53.33 % pclk pulse width high measured at 1.5v 4a (1) 9.50 10.50 7 8 ns pclk pulse width low measured at 1.5v 4b (1) 9.50 10.50 7 8 ns bclk cycle time 5 40 50 30 50 ns bclk rise and fall time 6,7 C4C3ns bclk duty cycle measured at 1.5v 8 40 60 40 60 % bclk pulse width high measured at 1.5v 8a (1) 16 24 12 18 ns bclk pulse width low measured at 1.5v 8b (1) 16 24 12 18 ns pclk, bclk frequency stability 9 C 1000 C 1000 ppm pclk and bclk skew 10 C 9 C n/a ns notes: 1. specification value at maximum frequency of operation.
14 white microelectronics ? phoenix, az ? (602) 437-1520 output ac timing specifications (see fig. 6-10) 25 mhz 33 mhz large (1) small (2) large (1) small (2) unit min max min max min max min max bclk to address ciout, lock, locke, r/w, sizx, tln, tmx, 11 (3) 9 21 9 30 6.50 18 6.50 25 ns ttx, upax valid bclk to output invalid (output hold) 12 9 C 9 C 6.50 C 6.50 C ns bclk to ts valid 13 9 21 9 30 6.50 18 6.50 25 ns bclk to tip valid 14 9 21 9 30 6.50 18 6.50 25 ns bclk to data out valid 18 (4) 9 23 9 32 6.50 20 6.50 27 ns bclk to data out invalid (output hold) 19 (4) 9 C 9 C 6.50 C 6.50 C ns bclk to output low inpedance 20 (3,4) 9 C 9 C 6.50 C 6.50 C ns bclk to data-out high impedance 21 (5) 9 20 9 20 6.50 17 6.50 17 ns bclk to multiplexed address valid 26 (3) 19 31 19 40 14 26 14 33 ns bclk to multiplexed address driven 27 (3,5) 19 C 19 C 14 C 14 C ns bclk to multiplexed address high impedance 28 (3,4,5) 9 18 9 18 6.50 15 6.50 15 ns bclk to multiplexed data valid 29 (4,5) 19 C 19 C 14 20 14 20 ns bclk to multiplexed data driven 30 (4) 19 33 19 42 14 28 14 35 ns bclk to address, ciout, lock, locke, r/w, sizx, ts, tlnx, 38 (3) 9 18 9 18 6.50 15 6.50 15 ns tmx, ttx, upax high impedance blclk to bb, ta, tip high impedance 39 19 28 19 28 14 23 14 23 ns bclk to br, bb valid 40 9 21 9 30 6.50 18 6.50 25 ns bclk to mi valid 43 9 21 9 30 6.50 18 6.50 25 ns bclk to ta valid 48 9 21 9 30 6.50 18 6.50 25 ns bclk to ipend, pstx, rsto valid 50 9 21 9 30 6.50 18 6.50 25 ns wc32p040-xxm characteristic specification notes: 1. output timing is specified for a valid signal measured at the pin. large buffer timing is specified driving a 50 w transmission line with a length characterized by a 2.5ns one-way propagation delay, terminated through 50 w to 2.5v. large buffer output impedance is 4-12 w , resulting in incident wave switching for this environment. all large buffer outputs must be terminated to guarantee operation. 2. small buffer timing is specified driving an unterminated 30 w transmission line with a length characterized buy a 2.5ns one-way propagation delay. small buffer output impedance is typically 30 w ; the small buffer specifications include approximately 5ns for the signal to propagate the length of the transmission line and back. 3. timing specifications 11, 20, and 38 for address bus output timinng apply when normal bus operation is selected. specificatio ns 26, 27, and 28 should be used when the multiplexed bus mode of operation is enabled. 4. timing specifications 18 and 19 for data bus output timing apply when normal bus operation is selected. specifications 28 and 29 should be used when the multiplexed bus mode of operation is enabled. 5. timing specifications 21, 27, 28, and 29 are measured from bclk edges. by design, the 68040 cannot drive address and data sim ultaneously during multiplexed operations.
15 white microelectronics ? phoenix, az ? (602) 437-1520 intput ac timing specifications (see fig. 6-10) characteristic specification 25 mhz 33 mhz unit min max min max data-in valid to bclk (setup) 15 5C4Cns bclk to data-in valid (hold) 16 4C4Cns bclk to data-in high impedance (read followed by write) 17 C 49 C 36.5 ns ta valid to bclk (setup) 22a 10 C 10 C ns tea valid to bclk (setup) 22b 10 C 10 C ns tci valid to bclk (setup) 22c 10 C 10 C ns tbi valid to bclk (setup) 22d 11 C 10 C ns bclk to ta, tea, tci, tbi invalid (hold) 23 2C2Cns avec valid to bclk (setup) 24 5C5Cns bclk to avec invalid (hold) 25 2C2Cns dle width high 31 8C8Cns data-in valid to dle (setup) 32 2C2Cns dle to data-in invalid (hold) 33 8C8Cns bclk to dle hold 34 3C3Cns dle high to bclk 35 16 C 12 C ns data-in valid to bclk (dle mode setup) 36 5C5Cns bclk to data-in invalid (dle mode hold) 37 4C4Cns bb valid to bclk (setup) 41a 7C7Cns bg valid to bclk (setup) 41b 8C7Cns cdis, mdis valid to bclk (setup) 41c 10 C 8 C ns iplx valid to bclk (setup) 41d 4C3Cns bclk to bb, bg, cdis, iplx, mdis invalid (hold) 42 2C2Cns address valid to bclk (setup) 44a 8C7Cns sizx valid bclk (setup) 44b 12 C 8 C ns ttx valid to bclk (setup) 44c 6 C 8.5 C ns r/w valid to bclk (setup) 44d 6C5Cns scx valid to bclk (setup) 44e 10 C 11 C ns bclk to address, sizx, ttx, r/w, scx invalid (hold) 45 2C2Cns ts valid to bclk (setup) 46 5C9Cns bclk to ts invalid (hold) 47 2C2Cns bclk to bb high impedance (mc68040 assumes bus mastership) 49 C9C9ns rsti valid to bclk 51 5C4Cns bclk to rsti invalid 52 2C2Cns mode select setup to rsti negated 53 20 C 20 C ns rsti negated to mode selects invalid 54 2C2Cns wc32p040-xxm
16 white microelectronics ? phoenix, az ? (602) 437-1520 note: 1. this output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. this input timing is applicable to all parameters specified relative to the rising edge of the clock. 3. this timing is applicable to all parameters specified relative to the negation of the rsti signal. legend: a. maximum output delay specification. b. minimum output hold time. c. minimum input setup time specification. d. minimum input hold time specification. e. mode select setup time to rsti negated. e. mode select hold time to rsti negated. fig. 6 drive levels and test points for ac specificatons wc32p040-xxm
17 white microelectronics ? phoenix, az ? (602) 437-1520 fig. 7 read/write timing diagram wc32p040-xxm note: transfer attribute signals = upax, sizx, ttx, tmx, tlnx, r/w, lock, locke, ciout
18 white microelectronics ? phoenix, az ? (602) 437-1520 fig. 8 bus arbitration timing diagram wc32p040-xxm note: transfer attribute signals = upax, sizx, ttx, tmx, tlnx, r/w, ciout
19 white microelectronics ? phoenix, az ? (602) 437-1520 fig. 9 snoop hit timing diagram wc32p040-xxm fig. 10 snoop miss timing diagram
20 white microelectronics ? phoenix, az ? (602) 437-1520 fig. 11 other signal timing diagram wc32p040-xxm
21 white microelectronics ? phoenix, az ? (602) 437-1520 fig. 13 184 lead, ceramic quad flat pack, cqfp (q4) all linear dimensions are millimeters and parenthetically in inches 1 34.93 (1.375) 0.55 (0.022) 0.33 (0.013) 0.65 (0.026) 31.31 (1.232) 0.44 (0.017) sq. 4.08 (0.161) 0.80 (0.031) 0.20 (0.008) 0.05 (0.002) 34.93 (1.375) 0.55 (0.022) 4.08 (0.161) 0.80 (0.031) 0.80 (0.031) ref 0.80 (0.031) 0.15 (0.006) 0 - 4 detail a detail a 0.76 (0.030) 0.16 (0.006) 29.25 (1.152) ref 46 138 93 139 184 92 47 0 - 8 1.80 (0.071) ref 0.20 (0.008) ref 0.75 (0.030) wc32p040-xxm fig. 12 179 pin grid array, pga (p4) all linear dimensions are millimeters and parenthetically in inches 47.25 (1.860) 0.50 (0.020) sq. 2.54 (0.100) 3.18 (0.125) 0.38 (0.015) 4.07 (0.160) 0.26 (0.010) t s r q p n m l k j h g f e d c b a 1 2 3 45 6 7 8 910 11 12 13 0.46 (0.018) 0.05 (0.002) 2.54 (0.100) pin a1 indicator 14 15 16 17 18
22 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p040-xxm ordering information w c 32 p040 - x x m device grade: m = military temperature -55 c to +125 c package: p4 = 179 pin ceramic pga q4 = 184 lead ceramic quad flatpack, cqfp operating frequency in mhz 68040 32 bit wide microcontroller white microelectronics

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