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1 of 15 110501 features open-drain pio pin is controlled by matching 64-bit, laser-engraved registration number associated with each device logic level of open drain output can be determined over 1-wire ? bus for closed-loop control pio pin sink capability is greater than 4ma at 0.4v multiple ds2405s can be identified on a common 1-wire bus and be turned on or off independent of other devices on the bus unique, factory-lasered and tested 64-bit registration number (8-bit family code +48- bit serial number +8-bit crc tester) assures absolute identity because no two parts are alike built-in multidrop controller ensures compatibility with other microlan products reduces control, address, data, and power to a single data pin directly connects to a single port pin of a microprocessor and communicates at up to 16.3kbits/s 8-bit family code specifies ds2405 communications requirements to reader 8-bit cyclic redundancy check ensures error- free selection zero standby power required low cost to-92, sot-223, or 6-pin tsoc surface mount package 1-wire communication operates over a wide voltage range of 2.8v to 6.0v from -40c to +85c pin assignment tsoc package pin description tsoc pin 1 - ground pin 1 - ground pin 2 - data pin 2 - data pin 3 - pio pin 3 - pio pin 4 - ground pin 4-6 -no connect ds2405 addressable switch www.maxim-ic.com top view top view 3.7 x 4.0 x 1.5 gnd data pio n c n c n c bottom view see mech. drawings section to-92 ds2405 2 3 1 1 2 3
ds2405 2 of 15 ordering information ds2405 to-92 package ds2405z 4-pin sot-223 package ds2405p 6-pin tsoc package ds2405/t&r tape & reel version of ds2405 ds2405z/t&r tape & reel version of ds2405z ds2405p/t&r tape & reel version of ds2405p description the ds2405 addressable switch is an open drain n-channel transistor th at can be turned on or off by matching the 64-bit factory-lasere d registration number within each part. the 64-bit number consists of an 8-bit family code, a unique 48-bit serial number, and an 8-bit cyclic redundancy check. communication with the ds2405 follows the standard dallas semiconductor 1-wire protocol and can be accomplished with a single port pin of a microc ontroller. multiple ds2405 devices can reside on a common 1-wire bus creating a microlan. the network controller circuitry is embedded within the chip including a search algorithm to determine the id entity of each ds2405 on the network. the open drain output (pio pin) for each ds2405 on the microlan can be independently toggled on or off whether there is one or many devices sharing the same 1-wire bus. the logic level of the pio pin for each device on the microlan can also be individually se nsed and reported to the bus master. overview the ds2405 addressable switch provides a means for assigning an el ectronically readable identification to a particular node or location with additional control capability provided by an open drain n-channel mosfet that can be remotely switched and sensed via communication over the 1-wire bus. the ds2405 contains a factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit crc, and an 8-bit family code (05h). the 64-bit rom por tion of the ds2405 not only creates an absolutely unique electronic identification for the device itself but also is a means to locate and change or obtain the state of the switch that is associated with the 64- bit rom. the structure of the 64-bit rom is shown in figure 1. the device derives its power entirely from the 1-wire bus by storing energy on an internal capacitor during periods of time when the signal line is high and continues to operate off of this ?parasite? power source during the low times of the 1-wire line until it returns high to replenish the parasite (capacitor) supply. the ds2405 uses the standard dallas semiconductor 1-wi re protocol for data transfers, with all data being read and written least significant bit first. communication to and from the ds2405 requires a single bidirectional line that is ty pically the port pin of the microcontroller. the 1- wire bus master (microcontroller) must first issu e one of five rom functi on commands: 1) read rom, 2) match rom, 3) search rom, 4) skip rom, and 5) active-only search rom. these commands operate on the 64-bit lasered rom portion of each device and can sing ulate a specific device if many are present on the 1-wire line as well as indicate to the bus how many and what type of each device is present. the protocol required for these rom functi on commands is described in figure 4. after a rom function command is successfully executed, the open dr ain output can be toggled or its current status determined via the 1-wire bus. 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. in all instances, the ds2405 is a slave device. the bus mast er is typically a microcontroller. the discussion of this bus system is broken down into three topics: hardware configuration, transacti on sequence, and 1-wire signaling (signal type and timing). for a more detailed protocol description, re fer to chapter 4 of the book of ds19xx ibutton? standards.
ds2405 3 of 15 hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have an open drain connection or 3-state outputs. the ds2405 is an open drain part with an internal circuit equivalent to that shown in figure 2. the bus master can be the same equivalent ci rcuit. if a bidirectional pin is not available, separate output and input pins can be tied togeth er. the bus master requires a pullup resistor at the master end of the bus, with the bus ma ster circuit equivalent to the one shown in figure 3. the value of the pullup resistor should be approximately 5 k for short line lengths. a multidrop bus consists of a 1-wire bus with multiple slaves attached. the 1-wire bus has a maximum data rate of 16.3kbits/s. the idle state for the 1-wire bus is high. if, for any reason, a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset. in addition, the state of the pio pin for one or more of the ds2405s on the bus may return to its default (off) condition. ds2405 memory map figure 1 8-bit crc code 48-bit serial number 8-bit family code (05h) msb lsb msb lsb msb lsb ds2405 equivalent circuit figure 2
ds2405 4 of 15 bus master circuit figure 3 a) open drain transaction sequence the sequence for accessing the ds2405 vi a the 1-wire port is as follows: initialization rom function command read data initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that at least one ds2405 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section. b ) standard ttl to data connection of ds2405 to data connection of ds2405
ds2405 5 of 15 rom function commands once the bus master has detected a presence, it ca n issue one of five rom function commands. all rom function commands are 8 bits long. a list of these co mmands follows (refer to flowchart in figure 4). read rom [33h] this command allows the bus master to read the ds2405?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can be used only if there is a single ds2405 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produc e a wired-and result). match rom [55h] the match rom command, followed by a 64-bit rom sequence, allows the bus master to address a specific device on a multidrop bus. all devices that do not match the 64-bit rom sequence will wait for a reset pulse. the ds2405 that exactly matches the 64- bit rom sequence will toggle the state of its pio pin after the 64 th bit of the match is entered. if the open drain n-channel device was off, it will be turned on and vice versa. after the last bit of the rom sequ ence is received from the bus master and the pio pin of the selected ds2405 has toggled, additional read time slots issued by the bus master will cause the ds2405 to output the logic state of its pio pin onto th e 1-wire bus. if the pulldown is on and the pio pin is a logical 0, the ds2405 will respond with read-0 time sl ots. if the pulldown is off and the pio pin is a logical 1 (external pullup is required), the ds2405 w ill respond with read-1 time slot. each additional read time slot issued by the bus master will continue to indicate the state of the pio pin until a reset pulse is received from the bus master. search rom [f0h] when a system is initially interrogated, the bus ma ster may not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search rom command allows the bus master to use a process of elimination to identify the 64-bit rom codes of all slave devices on the bus. this process of elimination involves repeated applica tion of a simple three-step proce dure where the bus master starts by reading a bit position in the 64-bit rom, followed by reading the complement of that bit position, and finally writing to all the devices still involved in the search the desired logic value for that bit position. an example is shown below and a flowchart for the sear ch algorithm can be found in the ?book of ds19xx ibutton standards.? four devices are connected to the 1-wire bus . their binary rom contents are listed below: device 1: xxxxxx10101100 device 2: xxxxxx01010101 device 3: xxxxxx10101111 device 4: xxxxxx10001000 the x?s represent the higher remaining bits. shown are the lowest 8 bits of the rom contents. the least significant bit is to the right in this repr esentation. the search process runs as follows: 1. the master begins the initialization sequence by issu ing a reset pulse. the devices respond by issuing presence pulses. 2. the master will then issue the search rom command on the 1-wire bus.
ds2405 6 of 15 3. the master reads 1 bit from the 1-wire bus. each de vice will respond by placing the value of the first bit of its respective rom data onto the 1-wire bus. devices 1 and 4 will place a 0 onto the 1-wire bus; that is, they pull it low. devices 2 and 3 will send a 1 by allowing the line to stay high. the result is the logical and of all devices on the line; therefore the master reads a 0. the master will issue another read time slot. since th e rom search command is being executed, all devices respond to this second read by placing the complement of the firs t bit of their respective rom data onto the 1-wire bus. devices 1 and 4 will send a 1; devices 2 and 3 will send a 0. thus the 1-wire bus will be pulled low. the master again reads a 0 for the complement of the first rom data bit. this tells the master that there are devices on the bus that have a 0 in the first position and others that have a 1. if all devices had a 0 in this bit position, the reading woul d be 01; if the bit position contained a 1, the result would be 10. (note that the 11 c ondition indicates that no devices are present on the 1-wire bus.) 4. the master now decides to write a 0 on the 1-wi re bus. this deselects devices 2 and 3 for the remainder of the search pass, leaving only device s 1 and 4 participating in the search process. 5. the master performs two more reads and receives a 0 followed by a 1 bit. this indicates that all active devices have a 0 in this bit position of their rom. 6. the master then writes a 0 to keep devices 1 and 4 selected. 7. the master executes two reads and receives two 0 bits . this again indicates that both 1 and 0 exist as the third bit of the rom of the active devices. 8. the master again writes a 0. this deselects de vice 1, leaving device 4 as the only active device. 9. subsequent reads to the end of the rom will not show bit conflicts. therefore, they directly tell the master the rom contents of the active device. after having learned any new rom bit, the master has to resend this bit to keep the device selected. as soon as all rom bits of the device are known and the last bit is resent by the master, the device is re ady to output the state of the pio pin using additional read time slots. 10. the master must learn the other devices? rom data. therefore, it starts another rom search sequence by repeating steps 1 through 7. 11. at the highest bit position, where the master wrote a 0 at the first pass (step 8), it now writes a 1. this deselects device 4, leaving device 1 active. 12. as in step 9, subsequent reads to the end of the rom will not show bit conflicts. this completes the second rom search pass where the master has learned another rom?s contents. 13. the master must learn the other devices? rom data. therefore, it starts another rom search sequence by repeating steps 1 to 3. 14. at the second highest bit position where the master wr ote a 0 at the first pass (step 4), it now writes a 1. this deselects devices 1 and 4, leaving devices 2 and 3 active. 15. the master sends two read time slots and r eceives two 0 bits, indicating a bit conflict. 16. the master again decides to write a 0. this deselects device 3, leaving device 2 as the only active device. 17. as in step 9, subsequent reads to the end of the rom will not show bit conflicts. this completes the third rom search pass where the master has learned another rom?s contents.
ds2405 7 of 15 18. the master must learn the other devices? rom data . therefore it starts anot her rom search sequence by repeating steps 13 to 15. 19. at the highest bit position where the master wrote a 0 at the previous pass (step 16), it now writes a 1. this deselects device 2, leaving device 3 active. 20. as in step 17, subsequent reads to the end of the rom will not show bit conf licts. this completes the fourth rom search pass where the master has learned anothe r rom?s contents. after one complete pass, the bus ma ster knows the contents of the 64- bit rom in one device. subsequent passes will reveal the total number of devices and their individual ro m codes. in addition, after each complete pass of the search that successfully determines the 64-bit rom for a specific device on the multidrop bus, that particular device can be individually accessed as if a match rom has been issued since all other devices will have dropped out of the search process and are waiting for a reset pulse. the ds2405 that was discovered by the search process will not toggle the state of its pio pin at the end of the search, but additional read time slots issued by the bus master after the search is completed will cause the ds2405 to output the logic state of its pio pin onto th e 1-wire bus. if the pulldown is on and the pio pin is a logical 0, the ds2405 will respond with read-0 time sl ots. if the pulldown is off and the pio pin is a logical 1 (external pullup is required), the ds2405 w ill respond with read-1 time slots. each additional read time slot issued by the bus master will continue to indicate the state of the pio pin until a reset pulse is received from the bus master. the combination of match rom and search rom allows the user to change the state of the pio pin and report the current state (match rom) or simply report the current state of the pio pin without changing it (search rom). active-only search rom [ech] the active-only search rom command operates similarly to the search rom command except that only devices with their output pulldown turned on are a llowed to participate in the search. this provides an efficient means for the bus master to determine devices on a multidrop system that are active (pio pin driven low). after each pass of the active-only search that successfully determines the 64-bit rom for a specific device on the multidrop bus with its output pu lldown turned on, that particular device can be individually accessed as if a match rom had been i ssued since all other devi ces will have dropped out of the active-only search process and are waiting for a reset pulse. the ds2405 that was discovered by the active-only search process will not toggle the state of its pio pin at the end of the search, but additional read time slots issued by the bus master after the search is completed will cause the ds2405 to output the logic state of its internal control signal (see figure 2) onto the 1-wire bus. since the active-only search rom command only operates on devices with their pulldown on, the internal control signal for each of these parts is always a logical 1. w ith control=1, the selected ds2405 will respond to the bus master with read-0 time slots after an active-only search pass is successfully completed. each additional read time slot issued by the bus master will continue to appear as a read-0 until a reset pulse is received from the bus master. if the control signal is a logical 0 for any ds2405, that device will not participate in the active-only search. the combination of search rom and active-only search rom allows the user to search in the most efficient manner depending on the requirements. if the bus master interrogates a multidrop system comprised of ds2405s whose pio conditions are unknown, the active- only search can quickly determine which devices are turned on. the two commands also allow the bus master to separately determine the state of the pio pin and the internal control signal which may be useful in detecting certain conditions. if search rom returns read-0 time slots (pio=logical 0) for a given device, it may be due to that particular ds2405 driving its pio pin low, or under certain conditions the logical 0 may be caused by some other device hol ding pio low. if that same device is found using an active-only search, control must be a logical 1 a nd the pio pin is being held low by the ds2405. if
ds2405 8 of 15 that same device is not found using an active-only se arch, control must be a logical 0 and the pio pin is being held low by some other device or perhap s a fault condition such as a pio shorted to ground. a second fault condition may be detected if search rom for a given device returns read-1 time slots (pio=logical 1) but active-only search rom is successful (control=logical 1) and returns read-0 time slots for the same device, indicating the possibility that pio may be shorted to a positive voltage.
ds2405 9 of 15 rom functions flow chart figure 4
ds2405 10 of 15 rom functions flow chart figure 4 (cont.)
ds2405 11 of 15 skip rom [cch] the complete 1-wire protocol for all dallas semiconductor ibuttons contains a skip rom command. since the ds2405 contains only the 64-bit rom with no additional data fields, the skip rom is not applicable and will cause no further activity on the 1-wire bus if executed. the ds2405 does not interfere with other 1-wire parts on a multidrop bus that do respond to a skip rom (for example, a ds2405 and ds1994 on the same bus). 1-wire signaling the ds2405 requires strict protocols to ensure data integrity. the prot ocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1 and read data. all these signals except presence pulse are initiated by the bus master. the initialization sequence required to begin any co mmunication with the ds2405 is shown in figure 5. a reset pulse followed by a presence pulse indicates the ds2405 is ready to send or receive data given the correct rom command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 s). the bus master then releases the line and goes into receive mode (rx). the 1-wi re bus is pulled to a high state via the 5k pullup resistor. after detecting the rising edge on the data pin, the ds2405 waits (t pdh , 15-60 s) and then transmits the presence pulse (t pdl , 60-240 s). initialization procedure ?reset and presence pulses? figure 5 480 s t rstl < * 480 s t rsth < (includes recovery time) 15 s t pdh < 60 s 60 s t pdl < 240 s in order not to mask interrupt signalin g by other devices on the 1-wire bus, t rstl + t r should always be less than 960 s. resistor master ds2405
ds2405 12 of 15 read/write time slots the definitions of write and read time slots are illustrated in figure 6. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds2405 to the master by triggering a delay circuit in the ds2405. during write time slots, the delay circ uit determines when the ds2405 will sample the data line. for a read data time slot, if a ?0? is to be transmitted, the delay circuit determines how long the ds2405 will hold the data line low overriding the ?1? generated by the master. if the data bit is a 1, the device will leave the read data time slot unchanged. read/write timing diagram figure 6 write-1 time slot 60 s t slot < 120 s 1 s t low1 < 15 s 1 s t rec < write-0 time slot 60 s t low0 < t slot < 120 s 1 s t rec < resistor master
ds2405 13 of 15 read/write timing diagram figure 6 (cont.) read-data time slot 60 s t slot < 120 s 1 s t lowr < 15 s 0 t release < 45 s 1 s t rec < t rdv = 15 s t su < 1 s crc generation to validate the data transmitted from the ds2405, the bus master may generate a crc value from the data as it is received. this generated value is compared to the value stored in the last 8 bits of the ds2405. if the two crc values match, the transmission is error-free. the equivalent polynomial function of this crc is: crc = x 8 + x 5 + x 4 + 1 for more details, see the book of ds19xx ibutton standards. resistor master ds2405
ds2405 14 of 15 absolute maximum ratings* voltage on any pin relativ e to ground -0.5v to +7.0v operating temperature range -40c to +85c storage temperature range -55c to +125c solder temperature see j-std-020a specification this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (-40 c to +85 c; v pup = 2.8v to 6.0v) parameter symbol min typ max units notes logic 1 v ih 2.2 v cc +0.3 v 1,6,8 logic 0 v il -0.3 +0.8 v 1,10 output logic low @ 4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1,2 input load current (data pin) i l 5 a 3 input resistance (pio pin) i r 10 m 9 capacitance (t a = 25 c) parameter symbol min typ max units notes capacitance data pin c d 800 pf 7 capacitance pio pin c p 10 pf ac electrical characteristics (-40 c to +85 c; v pup =2.8v to 6.0v) parameter symbol min typ max units notes time slot t slot 60 120 s write-1 low time t low1 115 s 12 write-0 low time t low0 60 120 s read low time t lowr 115 s 12 read data valid t rdv 15 s 11 release time t release 015 45 s read data setup t su 1 s 5 recovery time t rec 1 s reset time high t rsth 480 s 4 reset time low t rstl 480 960 s 13 presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s
ds2405 15 of 15 notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage. 3. input load is to ground. 4. an additional reset or communica tion sequence cannot begin until th e reset high time has expired. 5. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 s of this falling edge and will remain valid for 14 s minimum (15 s total from falling edge on 1-wire bus). 6. v ih is a function of the external pull-up resistor and the v cc supply. 7. capacitance on the data pin could be 800pf when power is first applied. if a 5k resistor is used to pull-up the data line to v cc , 5 s after power has been applied the parasite capacitance will not affect normal communications. 8. v ih for pio pin should always be greater than or equal to v pup -0.3v. 9. input resistance is to ground. 10. under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 11. the optimal sampling point for the master is as close as possible to the end of the 15s t rdv period without exceeding t rdv. for the case of a read 1 time slot, this maximizes the amount of time for the pull-up resistor to recover the line to a high level. for a read 0 time slot, it ensures that a read will occur before the fastest 1-wire device(s) release the line. 12. the duration of the low pulse sent by the master should be a minimum of 1s with a maximum value as short as possible to allow time for the pull-up resistor to recover the line to a high level before the 1-wire device samples in the case of a write 1 low time, or before the master samples in the case of a read low time. 13. the reset low time (t rstl ) should be restricted to a maximum of 960s to allow interrupt signaling; otherwise, it could mask or conceal interrupt pulses.

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