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| minirisc ? EZ4021-FC building blocks order number c14070 technical manual april 2000
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. document db14-000108-00, first edition april 2000 this document describes revision a of the lsi logic corporation minirisc ? EZ4021-FC easymacro building blocks and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 1999, 2000 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, coreware and coreware logo design, g12 and g12 logo design, flexcore, flexstream, gigablaze, merlin, minirisc, minisim, right-first-time, and serialink are trademarks or registered trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. preface iii preface this book is the primary reference and users guide for the minirisc ? EZ4021-FC microprocessor easymacro building blocks. it contains a complete functional description for each building block. audience this document assumes that you have some familiarity with microprocessors and related support devices. the people who bene?t from this book are: engineers and managers who are evaluating the EZ4021-FC building blocks for possible use in a system engineers who are designing the processor and associated building blocks into a system organization this document contains the following chapters and appendixes: chapter 1, introduction , introduces the EZ4021-FC feature set and brie?y discusses the available building blocks. chapter 2, sdram controller , describes the EZ4021-FC sdram controller and its operation. chapter 3, quick bus , describes the EZ4021-FCs 64 bit high-performance on-chip bus, the quickbus. chapter 4, external bus controller , describes the external bus controller, which allows off-chip peripherals to communicate with the EZ4021-FC through the quickbus. iv preface related publications minirisc ? EZ4021-FC microprocessor easymacro technical manual , document no. db15-000080-01 conventions used in this manual the ?rst time a word or phrase is de?ned in this manual, it is italicized. the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x for example, 0x32cf. binary numbers are indicated by the pre?x 0b for example, 0b0011.0010.1100.1111. contents v contents chapter 1 introduction 1.1 system overview 1-1 1.2 EZ4021-FC features 1-3 1.3 building blocks overview 1-4 1.3.1 sdram controller 1-4 1.3.2 quick bus 1-5 1.3.3 external bus controller 1-5 1.4 minirisc support tools 1-5 1.5 coreware program 1-6 1.5.1 coreware building blocks 1-6 1.5.2 design environment 1-6 1.5.3 expert support 1-7 chapter 2 sdram controller 2.1 overview 2-1 2.2 features 2-2 2.3 sdram overview 2-2 2.4 sdram types and memory area 2-4 2.5 sdram controller and sdram device interface 2-4 2.6 sdram addressing 2-6 2.6.1 quick bus to sdram controller 2-6 2.6.2 sdram controller to sdram 2-7 2.7 sdram controller signals 2-8 2.7.1 signal descriptions 2-11 2.8 programming the sdram mode register 2-15 2.9 sdram commands 2-16 2.9.1 row active (actv) command 2-17 2.9.2 mode register set (mrs) command 2-18 2.9.3 no operation (nop) command 2-18 vi contents 2.9.4 precharge all banks (pall) command 2-18 2.9.5 precharge selected bank (pre) command 2-18 2.9.6 read (read) command 2-19 2.9.7 refresh (ref) command 2-19 2.9.8 write (writ) command 2-20 2.10 sdram controller registers 2-20 2.10.1 sdram controller con?guration register 2-20 2.10.2 sdram controller refresh register 2-26 2.11 sdram initializatio 2-27 2.12 mbus timing waveforms 2-27 2.12.1 single transactions 2-28 2.12.2 burst transactions 2-32 2.12.3 initialization 2-35 chapter 3 quick bus 3.1 overview and features 3-1 3.2 quick bus transactions 3-3 3.3 device attachment criteria 3-3 3.4 supported devices 3-3 3.5 signal descriptions 3-4 3.5.1 master - command signals 3-7 3.5.2 master - read return signals 3-10 3.5.3 slave - command 3-11 3.5.4 slave - read return 3-13 3.6 functional description 3-14 3.6.1 command cycle 3-14 3.6.2 read return cycle 3-18 3.6.3 slave ready logic 3-22 3.6.4 burst transactions 3-23 3.6.5 bus locking 3-24 3.6.6 bus snooping 3-25 chapter 4 external bus controller 4.1 overview 4-1 4.2 local bus overview 4-3 4.3 ebc signals 4-3 4.3.1 ebc signal descriptions 4-7 contents vii 4.4 ebc transactions 4-13 4.4.1 EZ4021-FC as lbus master 4-14 4.4.2 EZ4021-FC as lbus slave 4-15 4.5 ebc registers 4-16 4.5.1 ebc watchdog timer failing address register 4-16 4.5.2 ebc watchdog timer error register 4-17 4.6 timing waveforms 4-17 4.6.1 EZ4021-FC as lbus master 4-18 4.6.2 lbus device as lbus master 4-25 4.6.3 lbus transaction termination by watchdog timer expiration 4-27 customer feedback figures 1.1 EZ4021-FC in a typical system 1-2 2.1 sdram versus standard dram timing 2-3 2.2 sdram controller and sdram array interface 2-5 2.3 sdram controller address bit assignment (qb_addrp[31:0]) 2-7 2.4 64 mbit sdram device address bit assignment (o_saddrp[13:0] 2-8 2.5 sdram controller connection diagram 2-9 2.6 sdram mode register 2-15 2.7 sdram controller con?guration register (r/w) 2-21 2.8 sdram controller refresh register (r/w) 2-26 2.9 single read transaction (cl = 2) 2-29 2.10 single read transaction (cl = 3) 2-30 2.11 single write transaction 2-31 2.12 burst read transaction (cl = 2) 2-33 2.13 burst write transaction 2-34 2.14 initialization sequence 2-35 3.1 quick bus block diagram 3-2 3.2 quick bus signals 3-5 3.3 typical quick bus command logic 3-15 3.4 quick bus command timing 3-18 3.5 typical quick bus read return logic 3-20 viii contents 3.6 quick bus read return timing 3-22 3.7 slave ready logic 3-23 3.8 four-word burst lock example 3-24 3.9 snoop interface 3-26 3.10 snooping back-to-back writes in 1:1 mode 3-27 3.11 logic for generating backoff 3-28 4.1 external local bus controller (ebc) block diagram 4-2 4.2 ebc controller connection diagram 4-4 4.3 ebc watchdog timer failing address register 4-16 4.4 watchdog timer error register 4-17 4.5 quick bus master read/write timing waveforms (32 bit access) 4-20 4.6 quick bus master read/write timing waveforms (64 bit access) 4-22 4.7 lbus transaction terminated by retry request 4-24 4.8 lbus master read timing waveforms 4-26 4.9 lbus master write timing waveforms 4-27 4.10 lbus transaction terminated by watchdog timer expiration 4-29 tables 2.1 sdram types and available memory area 2-4 2.2 sdram controller address bit assignments (qb_addrp[31:0]) 2-7 2.3 sdram controller alphabetical signal list 2-9 2.4 sdram command summary (64 mbit mode) 2-17 2.5 con?guration register programming example 2-25 2.6 sdram refresh register programming value 2-26 2.7 state acronyms 2-28 3.1 quick bus signal summary 3-5 4.1 lbus features 4-3 4.2 external bus controller alphabetical signal list 4-5 minirisc ez4021 building blocks technical manual 1-1 chapter 1 introduction this chapter introduces the building blocks available with the lsi logic minirisc EZ4021-FC microprocessor core. the chapter contains the following sections: section 1.1, system overview, page 1-1 section 1.2, EZ4021-FC features, page 1-3 section 1.3, building blocks overview, page 1-4 section 1.4, minirisc support tools, page 1-5 section 1.5, coreware program, page 1-6 1.1 system overview the minirisc EZ4021-FC microprocessor easymacro core is a compact, high-performance, 64-bit microprocessor subsystem. the EZ4021-FC uses the lsi logic coreware ? system-on-a-chip methodology and executes the mips iii instruction set. it is ideal for high-performance, cost-sensitive embedded processor applications. for detailed information about the EZ4021-FC, see the minirisc ez4021fc microprocessor core technical manual . you can easily design the EZ4021-FC into a wide range of products. it can be combined with industry standard cores and proprietary functional building blocks to create a completely customized embedded system on a chip. lsi logic currently provides the following building blocks: sdram controller (sdramc), described in chapter 2, sdram controller. 1-2 introduction quick bus, described in chapter 3, quick bus. external bus controller (ebc), described in chapter 4, external bus controller. the building blocks are brie?y described in section 1.3, building blocks overview. system designers can use these building blocks as they are provided, or modify them for speci?c needs. figure 1.1 shows how the EZ4021-FC microprocessor core interfaces with building blocks in a typical design. figure 1.1 EZ4021-FC in a typical system quick bus ez4021/ez4021fc bus controller external sdram microprocessor core controller sdram array lbus device 1 lbus lbus device n bus interface unit 64 32 EZ4021-FC features 1-3 1.2 EZ4021-FC features this section summarizes the key features of the EZ4021-FC. high-performance risc cpu core for coreware asic C single issue, ?ve-stage pipeline C 250 native mips, 250+ dhrystone mips at 250 mhz C 250-mhz operation at wc125 (tj = 125 c, vdd = 1.71 v, worst-case process) mips iii instruction set architecture (isa) C thirty-two 64-bit general-purpose registers C 32-bit wide mips iii isa supporting 64-bit integer operations C r4000-style status register and exception processing C wait for interrupt (waiti) instruction for power saving C supports special2 multiply-accumulate extensions both big and little endian support for load and store operations integrated multiplier and divider C high-performance eight bit/cycle multiplier 32-bit unsigned or signed multiplication in ?ve cpu clock cycles 64-bit unsigned or signed multiplication in nine cpu clock cycles C compact and low performance (1 bit/cycle) divider 32-bit unsigned or signed division in 34 cpu clock cycles 64-bit unsigned or signed division in 66 cpu clock cycles integrated instruction and data caches (harvard architecture) C mmu implements 32 dual-entry page translations C 16 kbyte 2-way set-associative instruction cache least recently used (lru) algorithm for replacement line level lock for instruction cache ram 1-4 introduction C 16 kbyte 2-way set-associative data cache lru algorithm for replacement line level lock for scratchpad memory write-through or write-back update policy, programmable on a per-page basis integrated ejtag debug support features C mips products standard ejtag 1.5.3 compliant simple instruction and data breakpoints program counter (pc) trace processor single step and software debug breakpoints system coprocessor zero (cp0) count and compare registers mips cpu standard interrupt exceptions (one nmi, one timer, ?ve hardware, two software) serial scan for device testing and ejtag support for on-chip system debug 13 mm 2 core size 1.8 v core vdd lsi logic g12? cmos technology (0.18 m l-drawn, 0.15 m l-effective) 1.3 building blocks overview this section gives a brief overview of the available EZ4021-FC building blocks. 1.3.1 sdram controller the sdram controller allows an EZ4021-FC-based design to interface directly to a 64 mbit sdram array without the need for external logic. the sdram controller generates all commands for the sdram array, including row address select (ras) and column address select (cas). the sdram controller supports up to 64 mbytes of sdram. minirisc support tools 1-5 1.3.2 quick bus the quick bus is a demultiplexed 32-bit address, 64-bit data split-transaction on-chip bus. it permits the overlap of command request and data return operations. this feature allows for higher bus utilization and the ability to hide long memory latency times to off-chip devices. the quick bus also supports multiple bus masters and data burst transactions. 1.3.3 external bus controller the external bus controller (ebc) allows the EZ4021-FC to interface to off-chip devices, such as ethernet controllers, serial i/o devices, and roms. the ebc serves as a bridge between the on-chip quick bus and the off-chip local bus (lbus). the lbus is a 32-bit multiplexed address/data bus. external bus masters on the lbus can arbitrate for ownership of the local bus and thereby make read and write requests on the quick bus. the ebc supports a retry mechanism that can be used if a peripheral device cannot complete a request. the target device can assert retry, which causes the ebc to retry the transaction at a later time. 1.4 minirisc support tools the EZ4021-FC has all the tools needed to develop a system on a chip, including: the lsi logic minisim ? -20 architectural simulator verilog models a system veri?cation environment a prom monitor third-party software support a full-featured core evaluation chip (ev4020) bus functional model for quick bus 1-6 introduction 1.5 coreware program the coreware program consists of three main elements: a library comprised of a wide range of complex cores based on accepted and emerging industry standards. the library includes high-speed interconnection, digital video, digital signal processing (dsp), and other cores. a design development and simulation package. lsi logic provides a complete framework for device and system development and simulation. the lsi logic advanced asic technologies consistently produce right-first-time? silicon. support for expert applications. the lsi logic in-house experts provide design support from system architecture de?nition through chip layout and test vector generation. using the coreware program, you can combine the EZ4021-FC microprocessor core with other cores on a single chip to create products uniquely suited to speci?c applications. the program provides unparalleled design ?exibility and lets you create high-quality, leading edge products for a wide range of markets. 1.5.1 coreware building blocks the coreware building blocks include elements based on the lsi logic high-performance standard products, as well as other industry-standard products. the coreware building blocks, which include embedded minirisc mips processors, bus interface controllers, and a family of ?oating-point processors, are fully supported library elements for use in the lsi logic hardware development environment. the building blocks include gate-level simulation models with timing information, so that designers can accurately simulate device performance and trade off various implementation options. in addition to gate-level simulation models, the building blocks also include behavioral simulation models. 1.5.2 design environment asic families are supported by the lsi logic comprehensive system-on- a-chip design methodology. this design methodology uses both internally developed and industry-standard tools integrated with coreware program 1-7 flexstream ? software and libraries that lets you use third-party software to access lsi logic technology. you can select from a suite of industry standard simulators, synthesizers, timing analyzers, and test tools that are seamlessly integrated into a common environment for veri?cation and sign-off. 1.5.3 expert support the lsi logic in-house experts support the coreware program with high-level design experience in a wide variety of application areas. these experts provide design support from system architecture de?nition through chip layout and test-vector generation. they help determine how many functions can be integrated on a single chip to ?nd the most cost-effective solution. 1-8 introduction minirisc ez4021 building blocks technical manual 2-1 chapter 2 sdram controller this chapter explains the operation of the EZ4021-FCs on-chip synchronous dram controller, and contains the following sections: section 2.1, overview, page 2-1 section 2.2, features, page 2-2 section 2.3, sdram overview, page 2-2 section 2.4, sdram types and memory area, page 2-4 section 2.5, sdram controller and sdram device interface, page 2-4 section 2.6, sdram addressing, page 2-6 section 2.7, sdram controller signals, page 2-8 section 2.8, programming the sdram mode register, page 2-15 section 2.9, sdram commands, page 2-16 section 2.10, sdram controller registers, page 2-20 section 2.11, sdram initialization, page 2-27 section 2.12, mbus timing waveforms, page 2-27 2.1 overview the on-chip synchronous dram (sdram) controller interfaces directly to a 64 mbit sdram memory array, eliminating the need for discrete control logic. this approach saves board space, reduces component count and design complexity, and increases performance by eliminating the inherent delays caused by external discrete components. 2-2 sdram controller 2.2 features the EZ4021-FC sdram controller operates with industry-standard 64 mbit devices (4-, 8-, and 16-bit wide) at clock frequencies up to 125 mhz, and offers the following features: in-page hits the sdram controller supports in-page hits (also known as row parking). once a row address is latched into a bank of the sdram, subsequent column addresses in the same row are clocked out according to the programmed column latency. no precharge is required. each internal bank can store a row address. quick bus optimized the sdram controller is optimized for use with the quick bus. due to the split transaction nature of the quick bus, the requesting device may not immediately acknowledge the output data when it is latched by the sdram controller. the controller output buffer stores output data until the quick bus is ready to read. as long as the write buffer is not full, the sdram controller accepts read requests from the quick bus. if a burst read request is received while data is in the output buffer, the sdram controller queues the read request and reissues it when the output buffer empties. four doubleword (burst) transaction the sdram controller does not support burst mode; all transactions are sequential. however, a four-doubleword request acts as a burst transaction. the sdram controller performs four sequential accesses from a single address. the term burst in this document refers to the four-doubleword transaction. 2.3 sdram overview sdrams offer signi?cant performance advantages over standard fast page mode (fpm) or extended data out (edo) dram devices. in standard dram architectures, once the processor has requested data, it must wait for a certain number of clocks until data is returned. the amount of delay depends on the design of the memory system and the speed of the drams used. sdram overview 2-3 in standard dram, the row address select (ras) and column address select (cas) signals must be held active from the start of the cycle until data is retrieved, which means that the dram cannot accept new cycle information during this time. design techniques such as interleaving multiple memory banks helps address this latency problem. with this approach, subsequent accesses go to alternate banks, hiding some of the dram latency time. interleaved memory systems achieve a performance boost over their noninterleaved counterparts, but require large amounts of real estate and increase the controller complexity. the clocked nature of the sdram allows for pipelining. new cycle information is driven to the array on every clock. once the pipeline is ?lled, data can be driven out of the sdram on each subsequent clock. in addition, each 64 mbit sdram device contains four internal banks, allowing for the implementation of an interleaved memory system without the added component count and controller complexity. figure 2.1 shows a timing diagram comparing sdram and standard dram accesses. dram devices are asynchronousaccess times in figure 2.1 are relative to an sdram device with an equivalent access time. figure 2.1 sdram versus standard dram timing sdrams contain an on-chip mode register that provides a high degree of programmability. on-chip burst counters allow for the support of burst mode without the need for an external discrete counter to increment subsequent addresses of the burst. column address select (cas) addr. latch decode read/ write data out addr. latch decode read/ write data out addr. 1 addr. 2 addr. 1 addr. 3 addr. 2 addr. 1 addr. 4 addr. 3 addr. 2 addr. 1 addr. 5 addr. 4 addr. 3 addr. 2 clock 1 clock 2 clock 3 clock 4 clock 5 addr. 1 addr. 1 addr. 1 addr. 1 addr. 2 asynchronous times are approximate relative to sdram clock. 2-4 sdram controller latency, the number of clocks between the time data is requested and the time it is driven onto the bus, is also programmable. the higher the latency, the longer it takes to retrieve the ?rst data item. 2.4 sdram types and memory area the sdram controller supports 64 mbit sdram devices with 4-, 8-, and 16-bit wide data buses. the 64m bit in the sdram con?guration register must be set. refer to section 2.10.1, sdram controller con?guration register, on page 2-20 for more information on the 64m bit. table 2.1 shows available sdram types, the total number of sdram devices required to design a memory system, the total memory size requirements, and the available address ranges. 2.5 sdram controller and sdram device interface the sdram controller interfaces to the sdram array without external glue logic. figure 2.2 shows a connection diagram for a 1 mword x 16-bit type sdram. table 2.1 sdram types and available memory area sdram type devices needed total memory size address area 4 mwords x 16 bits 4 32 mbytes 0x0000.0000C0x01ff.ffff 8 mwords x 8 bits 8 64 mbytes 0x0000.0000C0x03ff.ffff 16 mwords x 4 bits 16 128 mbytes 0x0000.0000C0x07ff.ffff sdram controller and sdram device interface 2-5 figure 2.2 sdram controller and sdram array interface csn rasn casn wen a[13:0] udqm ldqm dq[15:0] cke clk x64 sdram csn rasn casn wen a[13:0] udqm ldqm dq[15:0] cke clk x64 sdram csn rasn casn wen a[13:0] udqm ldqm dq[15:0] cke clk x64 sdram csn rasn casn wen a[13:0] udqm ldqm dq[15:0] cke clk x64 sdram [7] [6] [5] [4] [3] [2] [1] [0] [63:48] [47:32] [31:16] [15:0] o_sdqmp[7:0] b_sdop[63:0] o_saddrp[13:0] o_srasn o_scasn o_swen EZ4021-FC high o_scsn mclk_outp (from clock sdram controller generation logic) 2-6 sdram controller you must strap the the clock enable (cke) input high on all sdram devices, because the sdram controller does not have a separate cke signal. strapping the input high permanently enables the sdram devices. the EZ4021-FC provides the clock for the sdram array. although the EZ4021-FC internally adjusts the phase, the skew in the sdram array must be carefully monitored. placing the devices as close together as possible alleviates some of the skew. multiple clocks, each derived from the master memory clock, can be used if the array is large. 2.6 sdram addressing the EZ4021-FC sdram controller passes address information between the quick bus and the sdram array. the sdram controller receives a 32-bit address from the quick bus and communicates with the sdram array using the sdram 14-bit address bus. 64 mbit sdram devices contain four internal banks. row address bits o_saddrp[13:12] select the bank. one row address, speci?ed by row address bits [11:0], is kept in each bank. all four banks may be activated independently. the controller manages four pages (banks), which are selected by row address bits [13:12]. the sdram controller also holds four sets of address bits [22:11]. 2.6.1 quick bus to sdram controller the quick bus communicates with the sdram controller using a 32-bit bus, qb_addrp[31:0]. the valid bits are encoded in the qb_addrp[26:3] signal. figure 2.3 shows the address bit assignment for the sdram controller. sdram addressing 2-7 figure 2.3 sdram controller address bit assignment (qb_addrp[31:0]) table 2.2 lists the bit assignments of the address bus shown in figure 2.3. 2.6.2 sdram controller to sdram the sdram controller communicates with the sdram devices using a 14-bit bus, o_saddrp[13:0]. row addresses are driven separately from column addresses. figure 2.4 shows the row and column address bit assignments for 4-, 8-, and 16-bit wide 64 mbit sdram devices. in figure 2.4, an x indicates a dont care. 31 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved c9 c8 b1 b0 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c7 c6 c5 c4 c3 c2 c1 c0 byte select table 2.2 sdram controller address bit assignments (qb_addrp[31:0]) address bits description 31:27 these bits must be zero. the sdram controller does not respond to the transaction if any of these bits are nonzero. 26:25 these bits are assigned to column address bits [9:8]. when 8-bit wide sdrams are used, bit 25 is ignored. when 16-bit wide devices are used, both bits are ignored. 24:23 this signal selects one of four internal banks. note that these banks reside internal to each sdram device. a value of 0b00 on these bits selects internal bank 0, 0b01 selects bank 1, 0b10 selects bank 2, and 0b11 selects bank 3. these bits are used as bits 13:12 for both the row and column address. 22:11 sdram row address [11:0]. 10:3 sdram column address [7:0] 2:0 these three bits are ignored during all operation. 2-8 sdram controller figure 2.4 64 mbit sdram device address bit assignment (o_saddrp[13:0] 2.7 sdram controller signals this section describes the sdram controller signals, which are listed in table 2.3. figure 2.5 shows the connections between the quick bus controller, the sdram controller, and the sdram array. refer to figure 2.2 on page 5 for more details on the sdram controller to sdram array connections. row addressing for all 64 mbit sdram devices column addressing for 4-bit wide 64 mbit sdram devices column addressing for 8-bit wide 64 mbit sdram devices column addressing for 16-bit wide 64 mbit sdram devices 13 12 11 10 9 8 7 6 5 4 3 2 1 0 b1 b0 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 131211109876543210 b1 b0 x 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 131211109876543210 b1b0 x 0 x c8c7c6c5c4c3c2c1c0 131211109876543210 b1 b0 x 0 x x c7 c6 c5 c4 c3 c2 c1 c0 sdram controller signals 2-9 figure 2.5 sdram controller connection diagram table 2.3 sdram controller alphabetical signal list signal name input/output source destination description b_sdop[63:0] bidirectional sdram array sdram cont. sdram cont. sdram array read data from sdram write data to sdram o_saddrp[13:0] output sdram cont. sdram array address o_scasn output sdram cont. sdram array column address select (cas) command o_scsn output sdram cont. sdram array chip select o_sdqmp[7:0] output sdram cont. sdram array byte mask o_srasn output sdram cont. sdram array row address select (ras) command global quick sdram qb_sel_sdc_dp qb_burstreqp qb_readp qb_addrp[26:3] qb_bytep[7:0] qb_datap[63:0] sdc_d_cmdrdyp sdc_rdrdyp resetp sclkp o_srasn o_scasn o_swen o_saddrp[13:0] o_sdqmp[7:0] sdc_sdoen sdc_rddatap[63:0] bus b_sdop[63:0] qb_rdack_sdcp qb_writep qb_cmdmidp[3:0] o_scsn sdc_rdlockp qb_sel_sdc_rp sdram controller device sdc_r_cmdrdyp 2-10 sdram controller o_swen output sdram cont. sdram array write enable qb_addrp[26:3] input quick bus sdram cont. address qb_burstreqp input quick bus sdram cont. four-doubleword (burst) request qb_bytep[7:0] input quick bus sdram cont. byte enable qb_cmdidp[3:0] input quick bus sdram cont. command id qb_wrdatap[63:0] input quick bus sdram cont. write data qb_rdack_sdcp input quick bus sdram cont. read data acknowledge qb_readp input quick bus sdram cont. read request qb_slsel_sdc_dp input quick bus sdram cont. memory access request qb_slsel_sdc_rp input quick bus sdram cont. register access request qb_writep input quick bus sdram cont. write request resetp input C sdram cont. system reset sclkp input global sdram cont. system clock sdc_d_cmdrdyp output sdram cont. quick bus sdram controller data command ready sdc_r_cmdrdyp output sdram cont. quick bus sdram controller register command ready sdc_rddatap[63:0] output sdram cont. quick bus memory read data sdc_rdlockp output sdram cont. quick bus read return lock sdc_rdrdyp output sdram cont. quick bus register read ready sdc_sdoen output sdram cont. sdram data out enable table 2.3 sdram controller alphabetical signal list (cont.) signal name input/output source destination description sdram controller signals 2-11 2.7.1 signal descriptions b_sdop[63:0] memory data in/out bidirectional this 64-bit bus carries data between the sdram controller and the sdram array. the bus operates as an input to the sdram controller during read accesses, and as an output to the sdram array during writes. the sdc_sdoen signal controls the direction of this bus. o_saddrp[13:0] row/column address output this 14-bit bus outputs the address for a given transaction. during a row address select (ras) cycle, the sdram controller drives row address information on this bus. during a column address select (cas) cycle, this bus drives the column address. refer to section 2.6, sdram addressing, on page 2-6 for more information. o_scasn column address select (cas) command output the sdram controller asserts this signal when driving a column address to the sdram array. the controller also uses o_scasn, along with o_swen and o_srasn, as a control signal for signaling commands such as mode register set, active, and precharge to sdram devices. refer to section 2.9, sdram commands, on page 2-16, for more information. o_scsn chip select output the sdram controller asserts this signal to enable the sdram device. o_sdqmp[7:0] byte enable output this 8-bit bus operates as a byte mask for b_sdop[63:0] on write transactions. the following table shows the correspondence between the byte enable signals and the valid data bits. byte enable valid data bits byte enable valid data bits o_sdqmp[7] [63:56] o_sdqmp[3] [31:24] o_sdqmp[6] [55:48] o_sdqmp[2] [23:16] o_sdqmp[5] [47:40] o_sdqmp[1] [15:8] o_sdqmp[4] [39:32] o_sdqmp[0] [7:0] 2-12 sdram controller o_srasn row address select (ras) command output the sdram controller asserts this signal when driving a row address to the sdram array. the controller also uses o_srasn, along with o_swen and o_scasn, as a control signal for signaling commands such as mode register set, active, and precharge to sdram devices. refer to section 2.9, sdram commands, on page 2-16, for more information. o_swen write enable output the sdram controller uses this signal in two ways. the controller asserts this signal to indicate the current transaction is a write transaction. the controller also uses o_swen, along with o_srasn and o_scasn, as a control signal for signaling commands such as mode register set, active, and precharge to sdram devices. refer to section 2.9, sdram commands, on page 2-16, for more information. qb_addrp[26:3] address input this 24-bit bus carries the read or write address from the quick bus to the sdram controller. the sdram controller, in turn, signals address information to the sdram device using the o_saddrp[13:0] signal. refer to section 2.6, sdram addressing, page 2-6, for more information. qb_burstreqp burst request input the quick bus asserts this signal to indicate a burst (four-doubleword) transaction. qb_bytep[7:0] byte enableinput the quick bus uses this 8-bit bus to indicate which bytes are valid on qb_datap[63:0]. the sdram controller passes this data to the sdram device using o_sdqmp[7:0]. the following table shows the correspondence between the byte enable signals and the valid data bits. sdram controller signals 2-13 qb_cmdidp[3:0] command id input this 4-bit bus carries the command id for each request from the quick bus. on read returns, the sdram controller returns the command id on the sdc_rdmid_rp[3:0] signal. qb_datap[63:0] write data in input this 64-bit bus contains write data from the quick bus. qb_rdack_sdcp read data acknowledge input the quick bus asserts this signal to acknowledge receiving input data from the sdram controller. qb_readp read request input the quick bus asserts this signal to indicate a read request. qb_slsel_sdc_dp memory access request input the quick bus asserts this signal to request a read or write transaction from the sdram controller. qb_slsel_sdc_rp register access request input the quick bus asserts this signal to select an internal register in an sdram device for read or write access. qb_writep write request input the quick bus asserts this signal to indicate a write request to the sdram controller. resetp system reset input master system reset input. the sdram controller is idle after reset. byte enable valid data bits byte enable valid data bits qb_bytep[7] [63:56] qb_bytep[3] [31:24] qb_bytep[6] [55:48] qb_bytep[2] [23:16] qb_bytep[5] [47:40] qb_bytep[1] [15:8] qb_bytep[4] [39:32] qb_bytep[0] [7:0] 2-14 sdram controller sclkp system clock input master system clock input. all transactions occur on the rising edge of the clock. sdc_d_cmdrdyp sdram controller data command ready output the sdram controller asserts this signal when capable of handling data requests. the sdram controller deasserts command ready when the command buffer is full. typically, command ready is asserted unless a burst request is pending. sdc_r_cmdrdyp output sdram controller register command ready the sdram controller asserts this signal when capable of handling requests to internal registers. the sdram controller deasserts command ready when the command buffer is full. typically, command ready is asserted unless a burst request is pending. sdc_rddatap[63:0] memory read data output this 64-bit bus contains read data from the sdram array. sdc_rdlockp read return lock output this signal must be tied low. the sdram controller never locks the quick bus. sdc_rdrdyp memory data ready output the sdram controller asserts this signal to indicate that valid data is on the quick bus. sdc_sdoen data out enable output this signal determines the direction of the b_sdop[63:0] bus. the sdram controller asserts sdc_sdoen to indicate that the b_sdop[63:0] bus is operating as an output (that is, writing to the sdram array). when deasserted, the b_sdop[63:0] bus operates as an input (that is, reading from the sdram array). programming the sdram mode register 2-15 2.8 programming the sdram mode register sdram have several programmable parameters, as discussed in section 2.3. these parameters are set in the mode register of each sdram device. the mode register set (mrs) command causes the sdram controller to send programming information to the sdram. the same content is written to all sdram devices. the information written depends upon the programming of the sdram controller con?guration register. refer to section 2.10.1, sdram controller con?guration register, page 2-20, for more information. the sdram mode register for 64 mbit devices contains a 14-bit wide mode register. figure 2.6 shows the sdram mode register. figure 2.6 sdram mode register r reserved 13 this bit must be set to zero for 64 mbit devices. r reserved [12:10] these bits must be set to zero. wt write-through bit 9 when cleared, this bit selects write-through mode. the sdram controller only supports write-through mode. r reserved [8:7] these bits must be set to zero. lmode column address latency (cas latency) [6:4] these bits set the amount of cas latency on reads. cas latency is the number of sdram clock cycles between the column address being driven to the sdram and the sdram returning data. 13 12 10 9 8 7 6 4 3 2 0 r r wt r lmode bt bl 2-16 sdram controller 64 mbit sdram devices only support column latencies of 2 or 3 cycles. a latency of one cycle is not supported. bt burst type 3 this bit must be cleared during initialization. the EZ4021-FC sdram controller does not support burst mode. in lieu of burst mode, the EZ4021-FC sdram controller supports a four-doubleword transaction that performs four sequential accesses to the same row. bl burst length [2:0] this ?eld must be set to 0b000, as the EZ4021-FC sdram controller only supports single-word accesses. in lieu of burst mode, the controller supports a four- doubleword transaction that performs four sequential accesses to the same row. 2.9 sdram commands sdram devices support a number of commands. the quick bus sends these commands to the sdram controller on the qb_addrp[26:3] bus. the sdram controller passes commands to the sdram array using the o_srasn, o_scasn, o_swen, and o_saddrp[13:0] signals. table 2.4 shows a truth table of the supported sdram commands. the address bits in table 2.4 refer to the qb_addrp[26:3] bus. the controller maps these bits to the o_saddrp[13:0] bus. lmode[2:0] cas latency 000 reserved 001 unsupported for 64 mbit devices 010 2 cycles 011 3 cycles 1xx 1 reserved 1. x = dont care sdram commands 2-17 2.9.1 row active (actv) command the actv command executes prior to any read or write operation. the actv command latches and decodes the row address and activates the appropriate row within the sdram device. once the row has been latched, a read or writ command latches the appropriate column address to access the sdram. table 2.4 sdram command summary (64 mbit mode) 1 sdram command (mnemonic) sdram controller signals o_saddrp[13:0] bit encoding 2 o_srasn o_scasn o_swen [13] [12] [11] [10] [9:0] row active (actv) low high high a[24] a[23] a[22] a[21] a[20:11] mode register set (mrs) low low low a[24] a[23] a[22] a[21] a[20:11] no operation (nop) high high high x xxxx precharge all (pall) low high low x x x high x precharge bank 0 (pre) low high low low low x low x precharge bank 1 (pre) low high low low high x low x precharge bank 2 (pre) low high low high low x low x precharge bank 3 (pre) low high low high high x low x read (read) high low high a[24] a[23] x low a[24,23, 10:3] refresh (ref) low low high x xxxx write (writ) high low low a[24] a[23] x low a[24,23, 10:3] 1. x = dont care. 2. address bits a refer to the qb_addrp[26:3] signal. 2-18 sdram controller when the actv command completes, read or write operations can occur and a column address is driven. 2.9.2 mode register set (mrs) command the mrs command executes on power-up, or whenever the sdram controller modi?es the operating parameters of the sdram device. the mrs command initializes the mode register, which contains the operating parameters for each sdram device in the memory array. the mode register is programmed during initialization. refer to section 2.8, programming the sdram mode register, on page 2-15, for more information. 2.9.3 no operation (nop) command the nop command has no effect on the internal operation of the sdram state machines and any cycles in progress are allowed to continue. some sdram vendors require a nop operation during intialization. to manually issue the nop command, set the nop bit in the sdram controller con?guration register. 2.9.4 precharge all banks (pall) command the pall command initiates a precharge operation to all banks of the sdram. precharging a bank clears the previous row address and prepares the bank for subsequent operations. you must issue the precharge all command before issuing a refresh command. in a 64 mbit sdram, address bit o_saddrp[10] determines whether all banks are precharged, or only a particular bank. this bit must be set to precharge all banks. the sdram ignores address bits o_saddrp[13:12] during this command. other cycles cannot execute while the pall command is in progress. at the completion of the pall command, the controller enters the idle state. 2.9.5 precharge selected bank (pre) command the pre command precharges a single bank of the sdram device. precharging a bank clears the previous row address and prepares the sdram commands 2-19 bank for subsequent operations. the sdram controller does not precharge the bank if subsequent operations are to the same row. in a 64 mbit sdram, address bits o_saddrp[13:12] select between the four banks. address bit o_saddrp[10] must be deasserted to use the pre command. the state of the control signals for a pre command is identical to the pall command with the exception of address bit o_saddrp[10]. if o_saddrp[10] is low, a pre command executes; if o_saddrp[10] is high, a pall command executes. 2.9.6 read (read) command the read command signals a read operation to the sdram. during execution of a read command, a column address is latched into the appropriate sdram device. the row address for the read operation is latched by the actv command. when a read command executes, data is available either two or three cycles later, according to the value programmed in the cas latency ?eld of the sdram mode register. at the completion of the read command, the sdram output buffers are placed into the high-impedance state. 2.9.7 refresh (ref) command the ref command refreshes the voltage in the sdram device to prevent data loss (the ref command is equivalent to a cas-before-ras refresh in a standard dram). you must precharge all banks prior to the ref command. o_saddrp[13:12] o_saddrp[10] selected bank 0b00 0b0 bank 0 0b01 0b0 bank 1 0b10 0b0 bank 2 0b11 0b0 bank 3 0bxx 0b1 all banks 2-20 sdram controller the sdram controller must be idle to execute the ref command; all cycles in progress complete prior to command execution. the refresh command halts operations in progress (except for burst reads). burst reads ?nish prior to ref command execution. an on-chip refresh counter provides refresh address and bank select bits; no external address counter is required. each bank is automatically precharged after a ref operationthe pre or pall commands are not required following a refresh operation. the ref command cannot be interrupted. the sdram controller returns to the idle state after completing the refresh operation. 2.9.8 write (writ) command the writ command signals a write operation to the sdram. during execution of a writ command, a column address is latched into the appropriate sdram device. the row address for the write operation is latched by the actv command. 2.10 sdram controller registers there are two sdram controller registers located at the following virtual addresses. sdram controller con?guration register (0xbeff.ffd0) sdram controller refresh register (0xbeff.ffd4) these registers are de?ned in the following subsections. 2.10.1 sdram controller con?guration register the sdram controller con?guration register contains the general operating parameters for the sdram controller. this register is located at physical address 0x1eff.ffd0. sdram controller registers 2-21 figure 2.7 sdram controller con?guration register (r/w) 64m 64 mbit sdram 31 this bit selects the address format for the memory array. this bit must be set to use 64 mbit sdrams. this bit is cleared on reset. pc manual precharge 30 when set, this bit causes the sdram controller to issue a manual precharge command. the bit is cleared on reset and automatically cleared after the precharge command is issued. during sdram initialization, the pc, mrs, and ref bits must be set during the initial write to the con?guration register. setting these bits causes the following sequence of operations: precharge, mode register set, refresh. mrs mode register set 29 when set, this bit causes the sdram controller to issue a mode register set command. the mode register set command programs the individual sdram devices. the mrs bit is cleared automatically when the command is issued. during sdram initialization, the pc, mrs, and ref bits must be set during the initial write to the con?guration register. setting these bits causes the following sequence of operations: precharge, mode register set, refresh. ref manual refresh request 28 when set, this bit causes the sdram controller to issue a manual refresh request for all banks of the sdram device. the bit is cleared at reset and automatically after the refresh operation is executed. during sdram initialization, the pc, mrs, and ref bits must be set during the initial write to the con?guration register. setting these bits causes the following sequence of operations: precharge, mode register set, refresh. r reserved [27:25] these bits are read as zero. 31 30 29 28 27 25 24 23 22 21 20 19 18 16 15 12 11 8 7 3 2 1 0 6 4m pc mrs ref r nop r cl r rcd rc ras reserved rp dpl 2-22 sdram controller nop manual nop command 24 when set, this bit causes the sdram controller to generate a nop (no operation) command to the sdram array. this bit is cleared on reset and automatically cleared after the nop command is executed. r reserved [23:22] these bits are read as zero. cl cas latency [21:20] this ?eld de?nes the latency, in mclk_outp cycles, between the time when the read command is issued by the sdram controller and when data is driven onto the bus by the sdram. cas latency applies to all read trans- actions. the value in this ?eld is programmed into the lmode ?eld of each individual sdram device. the column latency parameter applies to all read transactions (single and burst). 64 mbit sdram devices only support column latencies of two or three cycles. a latency of one cycle is not supported. the encoding for this ?eld is shown below. r reserved 19 this bit is read as zero. rcd active ras to read/write command period [18:16] this ?eld de?nes the number of clock cycles between the row active (actv) command and a read or writ command. this parameter is also known as t rcd . cl[2:0] cas latency 0b000 reserved 0b001 unsupported for 64 mbit devices 0b010 2 cycles 0b011 3 cycles 0b1xx 1 reserved 1. x = dont care sdram controller registers 2-23 the encoding for this ?eld is shown below. rc refresh-to-refresh/active command period [15:12] this ?eld de?nes the minimum number of clock cycles between a refresh command (ref) and the next refresh or row active (actv) command. select a value between 2 and 15 cycles. this parameter is also known as t rc . the encoding for this ?eld is shown below. rcd[2:0] actv to read/writ latency t rcd (mclk_outp cycles) 0b000 unde?ned 0b001 1 cycle 0b010 2 cycles 0b011 3 cycles 0b100 4 cycles 0b101 5 cycles 0b110 6 cycles 0b111 7 cycles rc [15:12] ref to ref/actv command period t rc (mclk_outp cycles) 0b0000 unde?ned 0b0001 unde?ned 0b0010 2 cycles 0b0011 3 cycles 0b0100 4 cycles 0b0101 5 cycles 0b0110 6 cycles 0b0111 7 cycles 0b1000 8 cycles 0b1001 9 cycles 2-24 sdram controller ras active to precharge command period [11:8] this ?eld de?nes the minimum number of clock cycles between a row active (actv) command and a precharge (pre or pall) command. select a value between three and seven clock cycles. this parameter is also known as t ras . the encoding for this ?eld is shown below. r reserved [7:3] these bits are read as zero. rp precharge/mrs to active command period [2:1] this ?eld de?nes the minimum number of clock cycles from a precharge (pre/pall) command to the next row active (actv) command and the minimum number of cycles from a mode register set (mrs) command to the next actv command. this parameter is also known as t rp . 0b1010 10 cycles 0b1011 11 cycles 0b1100 12 cycles 0b1101 13 cycles 0b1110 14 cycles 0b1111 15 cycles rc [15:12] ref to ref/actv command period t rc (mclk_outp cycles) (cont.) ras[2:0] actv to pre/pall command period t ras (mclk_outp cycles) 0b000C0b010 unde?ned 0b011 3 cycles 0b100 4 cycles 0b101 5 cycles 0b110 6 cycles 0b111 7 cycles sdram controller registers 2-25 select a value between two and ?ve clock cycles. the programmed value sets both parameters. the encoding for this ?eld is shown below. dpl data in to precharge command period 0 this bit de?nes the minimum number of clock cycles from a write (writ) command (data in) to a precharge (pre/pall) command. setting this bit indicates a delay of two clock cycles. clearing this bit indicates a delay of one clock cycle. this parameter is also known as t dpl . 2.10.1.1 con?guration register example the values programmed into the sdram controller con?guration register depend upon the frequency and type of sdram devices used. refer to the sdram vendors documentation for proper refrseh values. table 2.5 shows example values for nec 64 mbit sdram upd4564441 and upd4564841-80, -10, -12 parts including the minimum clock cycles (in ns) for each parameter. rp[1:0] pre/pall to actv and mrs to actv command period t rp (mclk_outp cycles) 0b00 2 cycles 0b01 3 cycles 0b10 4 cycles 0b11 5 cycles table 2.5 con?guration register programming example sdram clock type/frequency minimum clock cycles -80 version -10 version -12 version cl rcd rc ras rp dpl 125 mhz 100 mhz 83 mhz 3 3 10 6 3 1 83mhz 66mhz 55mhz 227421 80mhz C C 227421 2-26 sdram controller 2.10.2 sdram controller refresh register all sdram devices lose charge over time. to prevent data loss, the voltage in the sdram array must be refreshed periodically. the sdram controller refresh register stores the refresh interval parameter (the time between refresh operations), which depends upon the sdram frequency. this register is located at physical address 0x1eff.ffd4. figure 2.8 shows the refresh register. figure 2.8 sdram controller refresh register (r/w) reserved reserved [31:12] this ?eld is read as zero. refresh refresh interval time [11:0] this ?eld de?nes the sdram refresh cycle interval time. table 2.6 shows recommended refresh intervals based on sdram clock cycle time. 31 12 11 0 reserved refresh table 2.6 sdram refresh register programming value sdram clock frequency sdram clock cycle time recommended cas latency recommended refresh cycle decimal hex 125 mhz 8 ns 3 1942 0x796 100 mhz 10 ns 3 1551 0x61a 80 mhz 12.5 ns 3 1238 0x4d6 66 mhz 15 ns 2 1031 0x407 sdram initialization 2-27 2.11 sdram initialization the sdram controller initializes the memory array at system power-up. during initialization, the controller: assures that v dd is stable precharges all sdram banks performs a minimum of eight refresh operations drives the mode register set command refer to section 2.12, mbus timing waveforms, page 2-27, for the waveforms associated with sdram initialization. sdram requires a minimum of 200 m s between the time when v cc is stable and the pall command is executed. the time t rp is the amount of time required for precharge of a bank. this time must be a minimum of three cycles. a minimum of eight consecutive refresh commands are issued by the sdram controller. the time t rc is the row address select cycle time and must be a minimum of eight clocks. the time t mrd is the delay between the mrs command and the initial bank activation (actv) command and must be a minimum of three clocks. 2.12 mbus timing waveforms the sdram controller transfers data to and from memory based on the parameters programmed into the on-chip sdram controller con?guration register. this section shows signal waveforms associated with the following sdram transactions: single read single write burst read burst write initialization 2-28 sdram controller this section shows signal names for bidirectional signals (such as b_sdop[63:0]) explicitly as input or output signals. for example, b_sdop[63:0] is shown as i_sdop[63:0] when it operates as an input signal and o_sdop[63:0] when it operates as an output signal. the waveforms also show the internal state of the sdram controller for clarity, using the state signal. the state signal is not externally visible to the user. the acronyms used to indicate state are given in table 2.7. 2.12.1 single transactions this section shows example timing waveforms for EZ4021-FC sdram controller single read and write transactions. on a read transaction, the casn latency parameter in the sdram mode register determines the number of clocks between the sdram device latching the column address and the sdram controller driving data out. the column latency parameter applies to all read transactions (single and burst). figure 2.9 shows the waveforms for a single read transaction with a column latency value of two cycles. table 2.7 state acronyms state description cas column address cbr refresh idle idle state (inactive) mrw mode register set (write) pca precharge ra row address rcdx x-cycle wait state (active to read/write command) mbus timing waveforms 2-29 figure 2.9 single read transaction (cl = 2) figure 2.10 shows the timing waveforms for a single read with a cas latency of three cycles. 2800 3000 3200 3400 3600 3800 4000 4200 sclkp 006000 1 idle ra rcd3 cas 0060 0x00 t rcd = 2 qb_slsel_sdc_dp qb_readp qb_boffp qb_burstreqp sdc_d_cmdrdyp qb_addrp[26:3] qb_cmdmidp[3:0] state o_scsn o_scasn o_srasn o_swen o_saddrp[13:0] sdc_rdmidp{[3:0] c1 column address driven o_sdop[63:0] sdc_rddatap[63:0] sdc_rdrdyp qb_rdack_sdc_dp *effff *effff 1 t cl = 2 (input) 2-30 sdram controller figure 2.10 single read transaction (cl = 3) 2800 3000 3200 3400 3600 3800 4000 4200 sclkp *6000 1 idle ra rcd3 cas 0060 0x00 t rcd = 3 qb_slsel_sdc_dp qb_readp qb_boffp qb_burstreqp sdc_d_cmdrdyp qb_addrp[26:3] qb_cmdmidp[3:0] state o_scsn o_scasn o_srasn o_swen o_saddrp[13:0] sdc_rdmidp{[3:0] c1 i_sdip[63:0] sdc_rddatap[63:0] sdc_rdrdyp qb_rdack_sdcp *effff *effff t cl = 3 actual read ras 1 mbus timing waveforms 2-31 figure 2.11 shows a single write transaction. the sdram controller asserts o_swen to signal a write transaction. the sdram controller drives write data and the column address simultaneously. figure 2.11 single write transaction 2800 3000 3200 3400 3600 3800 4000 4200 c1 sclkp *6000 *bcde0 3 idle ra rcd3 cas 0060 0x00 ras actual write t rcd = 3 qb_slsel_sdc_dp qb_readp qb_writep qb_boffp qb_burstreqp sdc_d_cmdrdyp qb_addrp[26:3] qb_wrdatap[63:0] qb_cmdmidp[3:0] state o_scsn o_scasn o_srasn o_swen o_saddrp[13:0] o_sdop[63:0] data must be valid in this cycle 2-32 sdram controller 2.12.2 burst transactions this section shows example timing waveforms for EZ4021-FC sdram controller burst read and write transactions. asserting qb_burstreqp signals a burst transaction. on a read transaction, the casn latency parameter in the sdram mode register determines the number of clocks between the sdram device latching the column address and the sdram controller driving data out. figure 2.12 shows the timing waveforms for a burst read transaction with cas latency set to two cycles. mbus timing waveforms 2-33 figure 2.12 burst read transaction (cl = 2) 3000 3200 3400 3600 3800 4000 4200 4400 c2 idle ra rcd3 cas *6000 1 0060 0x00 0x01 0x02 0x03 *00000*11111*22222 *33333 *00000 *11111 *22222*33333 t cl = 2 actual read t rcd = 2 sclkp qb_slsel_sdc_dp qb_readp qb_boffp sdc_d_cmdrdyp qb_addrp[26:3] qb_burstreqp qb_cmdmidp[3:0] state o_scsn o_scasn o_srasn o_swen o_saddrp[13:0] i_sdip[63:0] sdc_rdrdyp sdc_rddatap[63:0] sdc_rdmidp[3:0] qb_rdack_sdcp 1 2-34 sdram controller figure 2.13 shows a burst write transaction. the sdram controller asserts qb_writep to signal a write transaction. figure 2.13 burst write transaction 2800 3000 3200 3400 3600 3800 4000 4200 c1 c2 0000000000000000 *11111*22222 *33333 0060 0x00 0x01 0x02 0x03 xxxx idle ra rcd3 cas 3 *00000 *11111*22222*33333 *6000 *6001 *6002 *6003 sclkp qb_slsel_sdc_dp qb_readp qb_writep qb_boffp qb_burstreqp sdc_d_cmdrdyp qb_addrp[26:3] qb_wrdatap[63:0] qb_cmdmidp[3:0] state[3:0] o_scsn o_scasn o_srasn o_swen o_saddrp[13:0] o_sdop[63:0] write t rcd = 3 mbus timing waveforms 2-35 2.12.3 initialization the sdram array must be initialized on power-up. figure 2.14 shows the waveforms associated with initialization. the timing parameters for a particular sdram vendor may differ from figure 2.14. figure 2.14 initialization sequence 1000 1200 1400 1600 1800 2000 2200 sclkp 2400 2600 2800 c1 c2 qb_slsel_sdc_rp qb_readp qb_writep qb_boffp sdc_r_cmdrdyp qb_wrdatap[63:0] state o_scsn o_scasn o_srasn o_swen o_saddrp[13:0] idle pca idle mrw idle cbr idle cbr idle *xxx *000 *653 *653 t rc = 8 t mrd = 3 t rp = 3 2-36 sdram controller minirisc ez4021 building blocks technical manual 3-1 chapter 3 quick bus this chapter explains the operation of the EZ4021-FCs on-chip bus, the quick bus, and contains the following sections: section 3.1, overview and features, page 3-1 section 3.2, quick bus transactions, page 3-3 section 3.3, device attachment criteria, page 3-3 section 3.4, supported devices, page 3-3 section 3.5, signal descriptions, page 3-4 section 3.6, functional description, page 3-14 3.1 overview and features the quick bus is a 64-bit, high-performance, on-chip bus that allows rapid data transfer between high-bandwidth, high-latency modules that include synchronous drams, pipelined srams, and pipelined flash eproms. it is also suitable for use with low-bandwidth, high-latency devices, such as boot proms. the quick bus uses a split-transaction protocol, which makes requests from a master and the response from a slave completely independent. all transactions require one command cycle to send a command from a master to a slave. read transactions require an additional read return cycle. after a bus master issues a data request, the bus remains unlocked while the master waits for the read return. the quick bus includes the following features: uses split-transaction protocol handles high-latency devices 3-2 quick bus allows application-dependent arbitration supports these bus operations: C burst mode - a standard burst is reading or writing four 64-bit words C non-pipelined transactions - only one read or write transaction outstanding at any given time C pipelined transactions - multiple read or write transactions outstanding at any given time supports multiple bus masters: C multiple cpus i-cache (each cpu) d-cache (each cpu) C off-chip dma C on-chip dma figure 3.1 shows a block diagram of the quick bus and attached devices. figure 3.1 quick bus block diagram quick bus slave 1 slave n master 1 master m master 2 slave 2 quick bus transactions 3-3 3.2 quick bus transactions the quick bus uses a general protocol that works for any application. a quick bus master initiates a read or write transaction with a single command cycle. for write transactions, the single command cycle is all that is required. for read transactions, an additional cycle is required to return the requested data from the slave to the requesting master. 3.3 device attachment criteria deciding what devices to attach to the quick bus is a decision the system designer makes based on the performance and latency of the individual device. the criteria listed here are guidelines with examples. for a more complete list see the next section. high-latency devices. normally, all off-chip devices are high latency. C controllers for off-chip memory devices, such as: dram, sdram, and eproms C controllers for external buses, such as: pci, isa, pc/at, and pcmcia high bandwidth devices (such as fibre channel) masters, such as the following devices that are tightly coupled to memory: C cpus C dma - for example, when serving as a data pump handling i/o ?y-by transfers to memory 3.4 supported devices below is a list of devices that should work well on the quick bus. selection of these devices is based on the criteria described in section 3.3, device attachment criteria, page 3-3. bus masters display controller 3-4 quick bus dma controllers ethernet-110 gigablaze ? serialink ? core gigablaze transceiver ieee 1394 link memory controllers for: C sdrams C srams C flash eproms C proms merlin ? dl fibre channel controller pc/ata interface pc card (pcmcia) pci-66 flexcore ? controller rdram controllers scsi transceiver video dac 2x smartcard 3.5 signal descriptions this section describes the quick bus signals. the signals are divided among the following functional groups: master command master read return slave command slave read return signal names in this document are in upper case, whereas in the rtl source code the same signals appear in lower case. the notation signal descriptions 3-5 figure 3.2 shows the quick bus signals grouped according to function. table 3.1 summarizes the quick bus signals. figure 3.2 quick bus signals table 3.1 quick bus signal summary signal name input/ output source destination description 3-6 quick bus signal descriptions 3-7 3.5.1 master-command signals this interface provides a path between bus masters and the quick bus. bus masters use this interface to send read and write commands to the quick bus. a quick bus master initiates a read or write transaction with a single command cycle. for write transactions, the single command cycle is all that is required. for read transactions, an additional cycle is required to return the requested data from the slave to the requesting master. each bus command triggers one of three handshake responses: bad address command ready command not ready a bad address response means the master must abort the command, because no slave device exists at the address speci?ed. a command ready response indicates that the addressed slave can accept the com- mand. a command not ready means the addressed slave is busy, and that the master must retry the command later. read returns can get out of sequence when a master initiates reads with more than one slave at a time. you can avoid this risk by prohibiting a master from having outstanding read requests with multiple slaves. since slaves typically handle read requests on a ?rst-in-?rst-out basis, a single slave can handle multiple read requests without risk of getting the return transactions out of sequence. qb_slsel_ 3-8 quick bus to manage multiple outstanding requests, a device can interface with the quick bus as more than one master device. for example, the EZ4021-FC cpu uses three types of requests: instructions, data, and ejtag debug. for each request type, the EZ4021-FC can function as a separate quick bus master. although most of the bus signals are shared among the bus masters, there are several signals that must be replicated for each master. the signals include: signal descriptions 3-9 3-10 quick bus qb_burstackp burst acknowledge (optional) qb->m the quick bus drives this signal to indicate that the selected slave is capable of supporting burst operations. typically, the address decode logic generates the burst acknowledge signal by oring together the select signals of all the burst capable slave devices. qb_cmdrdyp command ready qb->m the quick bus forwards this signal to the bus master to indicate whether a slave device can accept a read or write command. qb_cmdrdyp high indicates a slave can accept a read or write command. when the signal is low, the slave is busy. qb_grant_ signal descriptions 3-11 normally should be ready to receive data, so this signal is seldom deasserted. qb_rderrp read data error qb->m the quick bus asserts this signal to tell a bus master that the data on the bus is invalid due to an error. typically, this signal is used to report a nonexistent address or other read error on a bus that is attached to the quick bus by a bus bridge. qb_rdrdy_ 3-12 quick bus qb_bytep[7:0] byte enables qb->s these are the read or write data byte enables the quick bus forwards to a slave device from a bus master. qb_cmdmidp[3:0] command master id qb->s encoded identi?cation of the master that is sending a read or write request command. qb_readp read request qb->s the quick bus sends this signal to a slave to indicate that a bus master is making a data read request. qb_slsel_ signal descriptions 3-13 3-14 quick bus use this signal unless the bus was previously granted through normal arbitration. typically, read return bus locking is not used. it can be used if a slave needs to prevent rearbitration in the middle of a burst transaction. refer to section 3.6.5, bus locking, on page 3-24. functional description 3-15 figure 3.3 typical quick bus command logic encoder data cmd mux ready addr, mux mux arbitration logic address decoder qb_cmdmidp[3:0] qb_wrdatap[63:0] qb_slsel_ 3-16 quick bus 3.6.1.1 arbitrating for the command bus during command arbitration, the quick bus arbitrates one or more requests from bus master devices. a master that wins the arbitration receives a bus grant signal from the quick bus arbitration logic. if a bus master asserts the optional command lock signal ( functional description 3-17 3.6.1.4 selecting command ready from slave the slave select signals (generated by the quick bus address decoder) also control the slave command ready mux. the mux selects the command ready ( 3-18 quick bus figure 3.4 quick bus command timing 3.6.2 read return cycle after a slave device obtains the requested data and is ready to send it to the master device, the slave initiates a read return cycle. to do this, the slave sends a read ready signal to the quick bus along with the 64 data bits, the master id, and the read error signal ( functional description 3-19 there are three steps in a read return cycle: 1. arbitrating for the read return bus 2. selecting read data 3. acknowledging a slave read figure 3.5 shows typical quick bus read return logic, and figure 3.6 provides a diagram of the read return timing. 3-20 quick bus figure 3.5 typical quick bus read return logic read lock optional master read mux data mux mux read logic decoder functional description 3-21 3.6.2.1 arbitrating for the read return bus to determine which slaves read return data to select, the quick bus arbitrates the 3-22 quick bus figure 3.6 quick bus read return timing 3.6.3 slave ready logic the slave ready logic (see figure 3.7) allows a bus master to monitor a busy slave until the slave becomes ready. monitoring the slave allows the master to avoid wasting time arbitrating repeatedly for access to the bus. one command cycle is required before the master can begin monitoring the slave. after a master wins a bus grant, the quick bus decodes the slave address and sends the command to the selected slave. if the slave is busy, as indicated by functional description 3-23 when a master receives the slave busy response, it can handle it in a variety of ways. one method is to set a busy ?ip-?op and then monitor the qb_slrdy_ 3-24 quick bus 3.6.5 bus locking a lock signal overrides the arbitration logic and forces a bus grant (see figure 3.8) over any other device currently requesting the bus. for that reason, the lock signal should not be used unless the bus was previously granted through normal arbitration. after bus access is granted through normal arbitration, a bus device can assert its lock signal for consecutive bus cycles. a bus master can use the functional description 3-25 3.6.6 bus snooping the quick bus snoop interface provides signals that the master can use to monitor write commands sent to slave devices. if a write to a slave device occurs and the address matches data held in a masters internal cache, the master can invalidate the cache data for that address. typically, a master ignores the following: the masters own write commands (indicated when its own bus grant signal is asserted), any write when back-off is asserted (qb_boffp high) any write whose associated command ready signal is not asserted (qb_cmdrdyp low) the snoop interface signals are a subset of the command signals sent to masters and slaves during a command bus cycle. the signals shown in the list below are used for snooping in addition to their normal function. note that the qb_addr and qb_write signals go to the master for snooping only. qb_addrp[31:0] address qb->m qb_boffp back off qb->m qb_cmdrdyp command ready qb->m qb_grant_ 3-26 quick bus figure 3.9 snoop interface 3.6.6.1 snooping in 1:1 mode when the system clock (sclkp) is running at the same speed as the processor clock (pclkp), the second of two consecutive writes may not snoop properly. to properly snoop the second write, the quick bus generates a back off signal to allow the write to be backed off to a third cycle. this is only necessary if the following conditions are met: sclkp_divp[1:0] = 0b01 the EZ4021-FC must run in 1:1 mode (pclkp = sclkp). snoop_enablep must be asserted data cache invalidate quick bus snooping must be enabled. last write must be from a non-EZ4021-FC master and be valid. the signals on the last cycle were: C qb_writep = high C qb_cmdrdyp = high C qb_badaddrp = low C qb_boffp = low the current request must be a write from a non-EZ4021-FC master to a different address than the previous request. figure 3.10 shows the waveforms for the 1:1 snooping condition. cache ta g qb_writep qb_grant_ functional description 3-27 figure 3.10 snooping back-to-back writes in 1:1 mode as shown in figure 3.10, there are two consecutive writes, neither of which is initiated by the EZ4021-FC. the addresses of the two writes are assumed to be different. to guarantee that the second write (cycle 2) is snooped correctly, the write of cycle 2 must be repeated in a subsequent cycle (for example, cycle 3). in burst writes, the EZ4021-FC must only snoop the ?rst write cycle to verify a cache line hit. it is not required to snoop the subsequent three write cycles. if the above conditions are met, the quick bus generates a back off signal for the quick bus masters and slaves. figure 3.11 shows the logic for generating the backoff signal. last address cur. address cycle 1 cycle 2 pclkp qb_addrp[31:0] qb_writep cycle 3 valid invalid valid qb_boffp last address and current address are distinct 3-28 quick bus figure 3.11 logic for generating backoff the lwa_good register stores the information that the previous cycle was a valid write cycle. the last_address register stores the upper address bits of the previous quick bus write cycle. the registers are active at the rising edge of the clock. comparator not equal lwa_good lwa_good last_ address qb_addrp[31:5] qb_badaddrp qb_cmdrdyp qb_boffp sclkp_div == 0b01 snoop_enablep qb_boffp qb_writep minirisc ez4021 building blocks technical manual 4-1 chapter 4 external bus controller this chapter explains the use of the EZ4021-FC external bus controller (ebc). the ebc interfaces the EZ4021-FC to an off-chip local bus (lbus) that contains system peripherals. this chapter includes the following sections: section 4.1, overview, page 4-1 section 4.2, local bus overview, page 4-3 section 4.3, ebc signals, page 4-3 section 4.4, ebc transactions, page 4-13 section 4.5, ebc registers, page 4-16 section 4.6, timing waveforms, page 4-17 4.1 overview the EZ4021-FC external bus controller (ebc) interfaces the EZ4021-FC on-chip quick bus to an off-chip local bus (lbus). the ebc functions as either a master or slave on both the quick bus and the lbus. the maximum ebc clock frequency is 125 mhz. the ebc requires an external i/o controller on the lbus. the external i/o controller decodes addresses from the ebc and asserts the appropriate chip select. figure 4.1 shows a block diagram of the ebc in a typical EZ4021-FC design. 4-2 external bus controller figure 4.1 external local bus controller (ebc) block diagram the ebc offers the following features: clock synchronization the ebc synchronizes requests between the quick bus, which operates at up to 125 mhz, and the lbus, which operates at a maximum frequency of 50 mhz (assuming lclk is a multiple of sclk). 64-bit to 32-bit conversion the quick bus supports a 64-bit data path between the EZ4021-FC cpu and the ebc, but the lbus supports only a 32-bit data path between the ebc and external lbus devices. the ebc handles the task of converting between the two buses. split transaction optimization the EZ4021-FCs quick bus supports split transactions (requests are decoupled from returns) to prevent low-latency devices from tying up the quick bus. the ebc registers data, address, byte enables, and read or write signals for requests to the lbus to allow the quick bus to continue serving other devices in the system. watchdog timer if the EZ4021-FC attempts to access an invalid address on the local bus, no device responds, causing the bus to hang. the ebc uses a programmable watchdog timer to recover from this condition. if the timer expires before the target device on the lbus responds, the ebc generates a bus error (on read) or saves the address and generates an interrupt to the EZ4021-FC (upon write). i/o device 1 i/o device 2 ez4021 customer asic ebc b i u 125 mhz 125 mhz 125 mhz 125 mhz quick i/o device n 50 mhz 50 mhz local i/o bus (lbus) cpu bus local bus overview 4-3 local bus retry the ebc registers the address, data, byte enables, and read or write signals of all requests. if an lbus device cannot respond to an ebc request (for instance, the device may be waiting for data from other components in the system), it can request that the ebc reassert the request. the ebc requires the lbus device to wait 128 quick bus cycles before asserting retry. this prevents the device from locking the lbus. this feature is only available when the EZ4021-FC is master on the lbus. 4.2 local bus overview the local bus (lbus) uses a 32-bit demultiplexed address bus and a 32-bit data bus. it shares many features with vlbus (or 486 bus) used by intel 80486 microprocessors. table 4.1 summarizes the lbus features. 4.3 ebc signals this section describes the external bus controller signals, which are listed in table 4.2. figure 4.2 shows the connections between the quick bus controller, the ebc, and the lbus. table 4.1 lbus features feature lbus i/o space no interrupt acknowledge cycle no support for single transaction yes support for burst transaction no hold/hlda bus arbitration yes bus retry input yes 4-4 external bus controller figure 4.2 ebc controller connection diagram global qb_slsel_xb_dp qb_writep qb_readp qb_addrp[26:3] qb_bytep[7:0] qb_cmdmidp[3:0] qb_rddatap[63:0] qb_wrdatap[63:0] xb_d_cmdrdyp xb_rdrdyp resetp sclkp b_xb_lben[7:0] o_xb_lhldap b_xb_lrdyn o_xb_laen xb_wrdatap[63:0] qb_rdack_xbp qb_rdrdy_xbp qb_grant_xbp xb_breqp xb_readp xb_writep xb_rdmidp[3:0] xb_bytep[7:0] xb_addrp[31:0] xb_rddatap[63:0] o_xb_lden b_xb_ladsn b_xb_laddrp[31:2] i_xb_lrtyn i_xb_lholdp lclkp cpu xb_intp b_xb_ldatap[31:0] xb_rderrp qb_slsel_xb_rp bigendianp xb_rdackp xb_r_cmdrdyp controller quick bus external bus controller (ebc) o_xb_lren external b_xb_lwritep i/o lbus controller and xb_lockp ebc signals 4-5 table 4.2 summarizes the ebc signals. all signals are driven on the rising edge of the clock. table 4.2 external bus controller alphabetical signal list signal name i/o/b 1 source destination transaction description b_xb_laddrp[31:2] b lbus ebc ebc lbus lbus r/w quick bus r/w address to quick bus address to lbus b_xb_ladsn b lbus ebc ebc lbus lbus r/w quick bus r/w address strobe address strobe b_xb_lben[3:0] b lbus ebc ebc lbus lbus w quick bus w byte enable byte enable b_xb_ldatap[31:0] b lbus ebc ebc lbus lbus r/w quick bus r/w data data b_xb_lrdyn b lbus ebc ebc lbus lbus r/w quick bus r/w request ready request ready b_xb_lwritep b lbus ebc ebc lbus lbus r/w quick bus r/w write enable (high = write, low = read) bigendianp i global ebc C endianness select i_xb_lholdp i lbus ebc lbus r/w lbus bus hold i_xb_lrtyn i lbus ebc lbus r/w request retry lclkp i EZ4021-FC ebc C lbus clock o_xb_laen o ebc lbus quick bus r/w address enable o_xb_lden o ebc lbus quick bus w lbus r data enable o_xb_lhldap o ebc lbus lbus r/w hold acknowledge o_xb_lren o ebc lbus lbus r/w ready enable qb_addrp[26:3] i quick bus ebc quick bus r/w address qb_bytep[7:0] i quick bus ebc quick bus r/w byte enable qb_cmdmidp[3:0] i quick bus ebc quick bus r command id (sheet 1 of 3) 4-6 external bus controller qb_grant_xbp i quick bus ebc lbus r/w quick bus grant qb_rdack_xbp i quick bus ebc quick bus r read ready acknowledge qb_rddatap[63:0] i quick bus ebc lbus r read data qb_rdrdy_xbp i quick bus ebc lbus r read data ready qb_readp i quick bus ebc quick bus r/w read transaction qb_slsel_xb_dp i quick bus ebc quick bus r/w lbus data select qb_slsel_xb_rp i quick bus ebc quick bus r/w ebc module register select qb_wrdatap[63:0] i quick bus ebc quick bus w write data qb_writep i quick bus ebc quick bus r/w write transaction resetp i global ebc C system reset sclkp i EZ4021-FC all C quick bus clock xb_addrp[31:0] o ebc quick bus lbus r/w address xb_breqp o ebc quick bus lbus r/w quick bus ownership request xb_bytep[7:0] o ebc quick bus lbus r/w byte enable xb_d_cmdrdyp o ebc quick bus quick bus r/w data command ready xb_intp o ebc EZ4021-FC cpu quick bus w watch dog timeout (write error interrupt) xb_r_cmdrdyp o ebc quick bus quick bus r/w register command ready xb_rdackp o ebc quick bus lbus r read acknowledge xb_rddatap[63:0] o ebc quick bus quick bus r read data xb_rderrp o ebc quick bus quick bus r watch dog timeout (read error) table 4.2 external bus controller alphabetical signal list (cont.) signal name i/o/b 1 source destination transaction description (sheet 2 of 3) ebc signals 4-7 4.3.1 ebc signal descriptions this section lists detailed descriptions of all external bus controller signals. direction of bidirectional signals is with respect to the ebc. b_xb_laddrp[31:2] address bidirectional this 30-bit bus carries addresses between the lbus and the ebc. as an input, it carries an address from the lbus to the quick bus. as an output, it carries an address from the quick bus to the lbus. the o_xb_laen signal controls the direction of b_xb_laddrp[31:2]. b_xb_ladsn address strobe bidirectional all lbus transactions are initiated with this signal. the lbus asserts this signal for one cycle to initiate a transaction to the quick bus. the ebc asserts this signal for one cycle to initiate a transaction on the lbus. the o_xb_laen signal controls the direction of b_xb_ladsn. b_xb_lben[3:0] byte enable bidirectional this 4-bit bus operates as a byte mask for lbus transactions. the lbus asserts this signal during transactions to the quick bus. the ebc asserts this signal during read and write transactions to the lbus. the xb_lockp 2 o ebc quick bus lbus r/w lock quick bus xb_rdmidp[3:0] o ebc quick bus quick bus r read master id xb_rdrdyp o ebc quick bus quick bus r read ready xb_readp o ebc quick bus lbus r quick bus read request xb_wrdatap[63:0] o ebc quick bus lbus w write data xb_writep o ebc quick bus lbus w write request 1. i = input, o = output, b = bidirectional 2. this signal is tied low. the ebc cannot lock the quick bus. table 4.2 external bus controller alphabetical signal list (cont.) signal name i/o/b 1 source destination transaction description (sheet 3 of 3) 4-8 external bus controller o_xb_laen signal controls the direction of b_xb_lben. the following table shows the encoding for this bus: b_xb_ldatap[31:2] read/write data bidirectional this 30-bit bus contains read or write data from the lbus. the o_xb_lden signal controls the direction of b_xb_ldatap[31:2]. b_xb_lrdyn request ready bidirectional an lbus device asserts this signal to indicate it has completed a transaction. the ebc asserts this signal to indicate it has completed a transaction. on read transactions, read data is driven simultaneously with this signal. on write transactions, assertion of b_xb_ldryn indicates that write data has been taken. the o_xb_lren signal controls the direction of b_xb_lrdyn. b_xb_lwritep write enable bidirectional when an lbus device is bus master on the lbus, an lbus device asserts this signal to indicate a write request to the quick bus. when deasserted, this signal indicates a read request to the quick bus. when the EZ4021-FC is the lbus master, assertion of b_xb_lwritep indicates an lbus write request. when deasserted, this signal indicates a read request to the lbus. the o_xb_laen signal controls the direction of b_xb_lwritep. bigendianp endianness select input assertion of this signal indicates big endian addressing. deassertion of this signal indicates little endian addressing. byte enable valid data bits b_xb_lben[3] [24:31] b_xb_lben[2] [16:23] b_xb_lben[1] [8:15] b_xb_lben[0] [0:7] ebc signals 4-9 i_xb_lholdp lbus hold input an lbus device asserts this signal to hold the lbus. the ebc grants this request with the o_xb_lhldap signal. i_lrtyn retry request input an lbus device asserts this signal to request a retry. the ebc waits until the retry counter decrements and then reissues the request. refer to section 4.4.1.1, transaction retry, page 4-15 for more information on the retry counter. lclkp lbus clock input this is the lbus clock input from the EZ4021-FC clock generator to the ebc module. the maximum lbus clock frequency is 50 mhz. all transactions happen on the rising clock edge. o_xb_laen address enable output this signal controls the direction of the following signals: b_xb_laddrp[31:2], b_xb_ladsn, b_xb_lben, and b_lwritep signals. when o_xb_laen is asserted, these signals operate as outputs. when o_xb_laen is deasserted, they operate as inputs. o_xb_ldatap[31:0] data output this 32-bit bus contains write data for the current transaction. the ebc drives this data to the lbus. o_xb_lden data enable output this signal controls the direction of the b_xb_ldatap[31:2] bus. when o_xb_lden is asserted, the b_xb_ldatap[31:2] bus operates as an output. when o_xb_lden is deasserted, the b_xb_ldatap[31:2] bus operates as an input. o_xb_lren lbus ready enable output this signal controls the directionality of the b_xb_lrdyn signal. when o_xb_lren is asserted, b_xb_lrdyn operates as an output. when o_xb_lren is deasserted, b_xb_lrdyn operates as an input. 4-10 external bus controller qb_addrp[26:3] address input this 24-bit bus carries address information from the quick bus to the ebc. qb_bytep[7:0] byte enable input this 8-bit bus operates as a byte mask on data from the quick bus to the ebc. the following table shows the cor- respondence between the byte enable signals and the valid data bits: qb_cmdidp[3:0] command id input this 4-bit bus carries the command id for each request from the quick bus. on read returns, the ebc returns the command id on the xb_rdmidp[3:0] bus. qb_grant_xbp quick bus grant input the quick bus asserts this signal to grant access to the ebc. the ebc requests quick bus access using the xb_breqp signal. qb_rdack_xbp read ready acknowledge input the quick bus asserts this signal to indicate it has accepted the data the ebc placed on the quick bus. qb_rddatap[63:0] read data input this 64-bit bus carries read data from the quick bus to the ebc. qb_rdrdy_xbp read data ready input the quick bus asserts this signal to indicate that valid read data is on the quick bus. byte enable valid data bits byte enable valid data bits qb_bytep[7] [63:56] qb_bytep[3] [31:24] qb_bytep[6] [55:48] qb_bytep[2] [23:16] qb_bytep[5] [47:40] qb_bytep[1] [15:8] qb_bytep[4] [39:32] qb_bytep[0] [7:0] ebc signals 4-11 qb_readp read transaction input the quick bus asserts this signal to indicate that the current request is a read transaction. qb_slsel_xb_dp lbus data select input the quick bus asserts this signal to request access to the lbus device at the address currently on the qb_addrp[26:3] bus. qb_slsel_xb_rp ebc register select input the quick bus asserts this signal to access the internal ebc registers. the address of the desired register must be signaled on the qb_addrp[26:3] bus. refer to section 4.5, ebc registers, page 4-16, for information on the ebc registers. qb_wrdatap[63:0] write data input this 64-bit bus carries write data from the quick bus to the ebc. qb_writep write transaction input the quick bus asserts this signal to indicate that the current request is a write transaction. resetp system reset input master system reset input. the ebc is idle after reset. sclkp system clock input master system clock input. all transactions occur on the rising edge of the clock. xb_addrp[26:3] address output this 24-bit bus carries address information from the ebc to the quick bus. xb_breqp quick bus ownership request output the ebc asserts this signal to request ownership of the quick bus. the quick bus responds by asserting qb_grant_xbp. 4-12 external bus controller xb_bytep[7:0] byte enable input this 8-bit bus operates as a byte mask on data from the ebc to the quick bus. the following table shows the correspondence between the byte enable signals and the valid data bits: xb_d_cmdrdyp data command ready output the ebc asserts this signal to indicate it can accept data access (read/write) requests. xb_intp write error (watchdog timer timeout) output the ebc asserts this signal to indicate a write error due to the expiration of the watchdog timer. on expiration of the watchdog timer, the ebc saves the failing address in the watchdog timer failing address register and sets the err bit in the watchdog timer error register. refer to section 4.5, ebc registers, page 4-16, for more information. xb_rdackp read acknowledge output the ebc asserts this signal to acknowledge it has taken the read data currently on the lbus. xb_rddatap[63:0] read data output this 64-bit bus carries read data from the ebc to the quick bus. xb_rderrp read error (watchdog timer timeout) output the ebc asserts this signal to indicate a read error due to the expiration of the watchdog timer. refer to section 4.5, ebc registers, page 4-16, for more information. byte enable valid data bits byte enable valid data bits xb_bytep[7] [63:56] xb_bytep[3] [31:24] xb_bytep[6] [55:48] xb_bytep[2] [23:16] xb_bytep[5] [47:40] xb_bytep[1] [15:8] xb_bytep[4] [39:32] xb_bytep[0] [7:0] ebc transactions 4-13 xb_lockp quick bus lock request output this signal is tied low. the ebc cannot request a quick bus lock. xb_rdmidp[3:0] read master id output this 4-bit bus returns the command id for each request from the quick bus. this command id matches the one sent by the quick bus on the qb_cmdidp[3:0] bus. xb_rdrdyp read ready output the ebc asserts this signal to indicate valid read data is on the quick bus. xb_readp quick bus read request output the ebc asserts this signal to indicate the current transaction is a read request. xb_r_cmdrdyp register command ready output the ebc asserts this signal to indicate it can accept register access requests. xb_wrdatap[63:0] write data output this 64-bit bus carries write data to the quick bus when an lbus device is lbus master. xb_writep write request output the ebc asserts this signal to indicate the current transaction is a write request when an lbus device is lbus master. 4.4 ebc transactions this section explains the interactions between the ebc and the lbus. the ebc interfaces the quick bus to the lbus. as such, each ebc transaction is made up of two parts: a transaction between the requesting bus and the ebc, and a transaction between the ebc and the target bus. for clarity, these transactions are divided into two types: transactions where the EZ4021-FC is the lbus master transactions where the EZ4021-FC is the lbus slave 4-14 external bus controller both transaction types support read and write operations. in addition, the ebc handles conversion between 32- and 64-bit formats when moving data between the quick bus and the lbus. refer to section 4.6, timing waveforms, page 4-17, to see how 32- and 64-bit requests are handled. 4.4.1 EZ4021-FC as lbus master the EZ4021-FC is the default lbus master device, and assumes ownership unless the i_xb_lholdp signal is asserted. as lbus master, the EZ4021-FC drives address and data information to the ebc on the quick bus. when the EZ4021-FC is the lbus master (that is, when the quick bus is the requesting bus), the ebc registers the information associated with the request. this allows the quick bus to respond to other devices and prevents stalling while waiting for a high-latency device on the lbus to respond. the ebc deasserts xb_r_cmdrdyp once it has accepted the request. the ebc initiates an lbus transaction by asserting the lbus address strobe signal. along with the address strobe, the ebc also drives the address, byte enable, and write enable signals. during a read transaction, the ebc drives address and control information and waits for the peripheral device to return data. during a write transaction, the ebc drives the write data at the same time as address and control information. an lbus transaction is completed when the lbus slave drives the i_xb_lrdyn signal for one cycle. during a read transaction, the lbus slave drives data and i_xb_lrdyn simultaneously to indicate that valid data is on the bus. during a write transaction the lbus slave device asserts i_xb_lrdyn to indicate that it has accepted the data on the bus. when the ebc samples i_xb_lrdyn active, it deasserts the address information associated with the request. this causes the external i/o controller to deassert the chip select signal to the lbus slave device. ebc transactions 4-15 if the lbus slave cannot complete the transaction, it can assert the i_xb_lrtyn signal, causing the ebc to abort the transaction and retry it at a later time. refer to section 4.4.1.1, transaction retry, page 4-15, for more information. on read transactions, the ebc then asserts xb_rdrdyp on the quick bus and drives the return data on xb_rddatap[63:0]. 4.4.1.1 transaction retry in cases where the transaction must be terminated prior to completion of the data transfer, the lbus slave can assert i_xb_lrtyn (retry request) instead of i_xb_lrdyn. assertion of i_xb_lrtyn causes the master device to abort the transaction and retry it at a later time. this feature is used to avoid a dead lock condition. a transaction retry can only be performed when the EZ4021-FC is the lbus master. to issue the same request at a later time, the ebc saves the address, data, byte enable, and the read/write requestthe EZ4021-FC does not reissue the request itself. the ebc contains a hard-wired timeout counter with a value of 0x7f (128 quick bus clock cycles). the counter begins decrementing once i_xb_lrtyn is asserted. when the counter reaches its terminal count of zero, the ebc regenerates the request. if the i_xb_lholdp signal is asserted when the counter reaches zero (an lbus device is master on the lbus), the pending request is serviced before the transaction is generated again. note: i_xb_lrdyn has higher priority than i_xb_lrtyn if both are asserted at the same time. 4.4.2 EZ4021-FC as lbus slave certain types of devices can function as lbus masters. an lbus device must gain ownership of the lbus before initiating a transfer. the lbus device asserts the lbus hold signal (i_xb_lholdp) to request lbus ownership. this signal is never 3-stated; it is always in either the asserted or deasserted state. after asserting the hold signal, the lbus device waits for the ebc to grant lbus ownership. the ebc allows any outstanding transactions to complete before surrendering lbus ownership. the ebc asserts o_xb_lhldap to acknowledge giving lbus ownership to the lbus device. while o_xb_lhldap is asserted, the EZ4021-FC cannot initiate an lbus 4-16 external bus controller transaction. the ebc asserts o_xb_lhldap continuously until the lbus device deasserts the i_xb_lholdp signal. once granted the bus, the lbus device drives the address strobe signal for one cycle, indicating to the ebc that a transaction is in progress. along with the address strobe, the lbus device also drives the address, byte enable, and write enable signals. during a read operation, the lbus device waits for the ebc to return data. the ebc asserts the o_xb_lrdyn signal at the same time it drives data onto the bus. during a write operation, the lbus device drives data at the same time as the address. the ebc asserts o_xb_lrdyn to indicate that it has accepted the incoming data from the lbus master. 4.5 ebc registers there are two ebc control registers for con?guring and controlling the lbus. the registers are located at the following virtual addresses: ebc watchdog timer failing address register (0xbeff.ffd8) ebc watchdog timer error register (0xbeff.ffdc) 4.5.1 ebc watchdog timer failing address register this register records the failing address of an lbus device that does not respond prior to expiration of the watchdog timer. figure 4.3 ebc watchdog timer failing address register erraddr watchdog timer error address [31:2] this ?eld contains the address of the lbus target device that caused the watchdog timer to expire. when the lbus target device does not respond to the transaction by asserting either i_xb_lrdyn or i_xb_lrtyn before the 31 210 erraddr r timing waveforms 4-17 watchdog timer reaches zero, the ebc records the failing address and stores it in this ?eld. this register is read only by the EZ4021-FC. r reserved [1:0] this ?eld must be set to zero. 4.5.2 ebc watchdog timer error register this register contains the timeout value for the watchdog timer, and the error bit for watchdog timer expiration on writes. figure 4.4 watchdog timer error register r reserved [31:16] this ?eld must be set to zero. timeout timeout value [15:7] this 8-bit ?eld speci?es the upper half of the watchdog timeout value. the minimum timeout value is 0x100. the maximum timeout value is 0xff00. setting this ?eld to 0x0 disables the watchdog timer. 0 preset field [6:0] this ?eld contains the lower half of the 16-bit timeout value. this ?eld is preset to 0x0. err watchdog timer error 0 this bit is set whenever the watchdog timer expires on a quick bus to lbus write transaction. the ebc writes the failing address to the ebc watchdog timer failing address register. it is cleared by the EZ4021-FC. 4.6 timing waveforms this section shows waveforms for ebc transactions. the examples show read and write operations when the EZ4021-FC is both a master and a slave device on the lbus, and waveforms for transaction termination by retry and watchdog timer expiration. 31 16 15 7 6 1 0 reserved timeout 0 err 4-18 external bus controller signal names for bidirectional signals such as b_xb_ladsn are shown explicitly as input or output signals. for example, b_xb_ladsn is shown as i_xb_ladsn when it operates as an input signal and o_xb_ladsn when it operates as an output signal. signals associated speci?cally with read or write transactions are annotated. 4.6.1 EZ4021-FC as lbus master this section shows waveforms for read and write transactions when the EZ4021-FC is master on the lbus. transaction termination by retry request is also shown. to allow communication between the 32-bit lbus and the 64-bit quick bus, the ebc handles bit-length conversion. this action is transparent to the user and no special handling is required. the ebc uses the byte enable signals to determine if a request is a 32- or 64-bit request. for 64-bit requests, the ebc issues two 32-bit requests to the lbus and concatenates the results prior to signaling request ready on the quick bus. 4.6.1.1 32-bit requests for a 32-bit read request, the ebc: takes the read request from the quick bus, registers the associated information (address, data, byte enables, and read signal), and deasserts command ready (xb_d_cmdrdyp) on the quick bus. issues a 32-bit request to the lbus. waits for the 32-bit read return from the lbus (data accompanied by the b_xb_lrdyn signal). asserts xb_rdrdyp and puts the read data on the quick bus. returns to the idle state and reasserts xb_d_cmdrdyp on the quick bus. timing waveforms 4-19 for a 32-bit write request, the ebc: takes the 32-bits of write data from the quick bus, registers the associated information (address, data, byte enables, and write signal) and deasserts command ready (xb_d_cmdrdyp) on the quick bus. asserts the lbus address strobe (b_xb_ladsn) and drives the 32-bit address and data to the lbus slave device. waits for a write acknowledge (b_xb_lrdyn) signal from the lbus. returns to the idle state and reasserts xb_d_cmdrdyp on the quick bus. figure 4.5 shows the waveforms associated with lbus read and write transactions when the EZ4021-FC makes a 32-bit request. 4-20 external bus controller figure 4.5 quick bus master read/write timing waveforms (32 bit access) sclkp qb_addrp[26:3] qb_slsel_xb_dp qb_readp qb_writep xb_d_cmdrdyp read write xb_rdrdyp rd read write write qb_rdack_xbp qb_bytep[7:0] f0 1f d0 d2 a2 qb_wrdatap[63:0] read (write) (read) (read) a0 xb_rddatap[63:0] write read a0 a3 01 d0 d3 rd lclkp o_xb_ladsn o_xb_lae o_xb_laddrp[31:2] o_xb_lwritep i_xb_lrdyn i_xb_ldatap[31:0] o_xb_lden o_xb_ldatap[31:0] o_xb_lben[3:0] (write) (write) (read) timing waveforms 4-21 4.6.1.2 64-bit request for a 64-bit read request, the ebc: takes the read request from the quick bus, registers the associated information (address, data, byte enables, and read signal), and deasserts command ready (xb_d_cmdrdyp) on the quick bus. issues a 32-bit request to the lbus. waits for the 32-bit read return from the lbus (data accompanied by the b_xb_lrdyn signal). registers the ?rst 32-bits of read return data from the lbus. issues a second 32-bit request to the lbus. waits for the second 32-bit read return from the lbus (data accompanied by the b_xb_lrdyn signal). concatenates the second 32-bit read return with the ?rst. asserts xb_rdrdyp and puts the 64-bits of read data on the quick bus. returns to the idle state and reasserts xb_d_cmdrdyp on the quick bus. for a 64-bit write request, the ebc: takes the 64-bits of write data from the quick bus, registers the associated information (address, data, byte enables, and write signal), and deasserts command ready (xb_d_cmdrdyp) on the quick bus. asserts the lbus address strobe (b_xb_ladsn) and drives the ?rst 32-bit address and data to the lbus slave device. waits for a write acknowledge (b_xb_lrdyn) signal from the lbus. asserts the lbus address strobe (b_xb_ladsn) and drives the second 32-bit address and data to the lbus slave device. waits for a write acknowledge (b_xb_lrdyn) signal from the lbus. returns to the idle state and reasserts xb_d_cmdrdyp on the quick bus. figure 4.6 shows the waveforms associated with lbus read and write transactions when the EZ4021-FC makes a 64-bit request. 4-22 external bus controller figure 4.6 quick bus master read/write timing waveforms (64 bit access) rd 10 d0 sclkp qb_addrp[26:3] qb_slsel_xb_dp qb_readp qb_writep xb_d_cmdrdyp xb_rdrdyp (read) lclkp o_xb_ladsn o_xb_laen o_xb_laddrp[31:2] o_xb_lwritep i_xb_lrdyn i_xb_ldatap[31:0] o_xb_lden read write read qb_rdack_xbp (read) qb_bytep[7:0] o_xb_ldatap[31:0] qb_wrdatap[63:0] a0 a1 o_xb_lben[3:0] (write) xb_rddatap[63:0] (write) (read) (write) (read) a0 rd0 rd1 write write 1 d0 d1 0 read write read timing waveforms 4-23 4.6.1.3 lbus transaction terminated by retry in cases where the transaction must be terminated prior to completion of the data transfer, the lbus slave can assert i_xb_lrtyn instead of b_xb_lrdyn, causing the master device to abort the transaction and retry it at a later time. retries are only available when the EZ4021-FC is the lbus master. this feature avoids a dead lock condition. the ebc generates the internal transaction termination at least one lclkp cycle after the lbus device asserts i_xb_lrtyn. if the i_xb_lholdp signal is asserted, the pending request is serviced before the transaction is generated again. the ebc contains a hard-wired timeout counter with a value of 0x7f (128 quick bus clock cycles). the counter starts counting down when i_xb_lrtyn is asserted. when the counter reaches its terminal count of zero, the ebc regenerates the request. figure 4.7 shows the waveforms associated with a retry request. 4-24 external bus controller figure 4.7 lbus transaction terminated by retry request fo d0 read a0 a0 write 0 read write sclkp qb_addrp[26:3] qb_slsel_xb_dp qb_readp qb_writep xb_d_cmdrdyp lclkp o_xb_ladsn o_xb_laen o_xb_laddrp[31:2] o_xb_lwritep i_xb_lrtyn o_xb_lden qb_bytep[7:0] o_xb_ldatap[31:0] qb_wrdatap[63:0] o_xb_lben[3:0] (write) retry timer xb_rdrdyp (read) i_xb_lrdyn (write) (internal to ebc) (write) 7e 7d 1 0 7f 7f d0 read write timing waveforms 4-25 4.6.2 lbus device as lbus master this section gives waveforms for read/write transactions when an lbus device is master on the lbus. all lbus requests to the quick bus are 32-bits by de?nition. figure 4.8 shows the waveforms associated with quick bus read transactions when an lbus device is master on the lbus. figure 4.9 shows the waveforms associated with quick bus write transactions when an lbus device is master on the lbus. 4-26 external bus controller figure 4.8 lbus master read timing waveforms sclkp lclkp i_xb_lholdp i_xb_lwritep o_xb_lden xb_breqp xb_readp qb_rdrdy_xbp qb_grant_xbp i_xb_ladsn o_xb_lrdyn o_xb_lren i_xb_laddrp[31:2] o_xb_lhldap qb_rddatap[63:0] o_xb_ldatap[31:0] i_xb_lben[3:0] xb_bytep[7:0] xb_laddrp[31:0] a0 f0 rd0 read (read) a0 0 rd0 timing waveforms 4-27 figure 4.9 lbus master write timing waveforms 4.6.3 lbus transaction termination by watchdog timer expiration the ebc provides a watchdog timer to eliminate the possibility of a bus hang condition if a slave device fails to respond. the 32-bit timer begins counting down from its programmed value whenever there is an lbus sclkp lclkp i_xb_lholdp i_xb_lwritep i_xb_ldatap[31:0] o_xb_lden xb_breqp qb_grant_xbp xb_writep i_xb_ladsn o_xb_lrdyn o_xb_lren i_xb_laddrp[31:2] o_xb_lhldap i_xb_lben[3:0] xb_bytep[7:0] xb_laddrp[31:0] xb_wrdatap[63:0] (write) a0 (write) d0 d0 f0 4-28 external bus controller request from the quick bus. on a write transaction, if the counter counts down to zero before a slave device asserts either i_xb_lrdyn or i_xb_lrtyn, the ebc generates an interrupt to the EZ4021-FC and saves the failing address. on a read transaction, a local bus read error is generated. if the device responds by asserting either i_xb_lrdyn or i_xb_lrtyn, the counter is reset. figure 4.10 shows a timing diagram of an lbus transaction terminated by expiration of the watchdog timer. timing waveforms 4-29 figure 4.10 lbus transaction terminated by watchdog timer expiration 00 read a0 a0 0 read write sclkp qb_addrp[26:3] qb_slsel_xb_rp qb_readp qb_writep xb_d_cmdrdyp lclkp o_xb_ladsn o_xb_laen o_xb_laddrp[31:2] o_xb_lwritep i_xb_lrtyn i_xb_lrdyn o_xb_lden qb_bytep[7:0] o_xb_ldatap[31:0] qb_wrdatap[63:0] o_xb_lben[3:0] watchdog timer xb_rdrdyp (read) xb_intp (write error) error_addr[31:3] qb_rdack_xbp(read) xb_rddatap[63:0] (write) (read) (internal) (internal) (write) (write) qb_slsel_xb_dp xb_r_cmdrdyp xb_rderrp (read error) reg reg d0 10000 write 100a0 a0 01 ff fe 02 00 00 write read 4-30 external bus controller customer feedback we would appreciate your feedback on this document. please copy the following page, add your comments, and fax it to us at the number shown. if appropriate, please also fax copies of any marked-up pages from this document. impor tant: please include your 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973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119 u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tulsa a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beaverton b. m. tel: 503.524.1075 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 philadelphia a. e. tel: 800.526.4812 b. m. tel: 877.351.2355 w. e. tel: 800.871.9953 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas arlington b. m. tel: 817.417.5993 austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 haymarket b. m. tel: 703.754.3399 spring?eld b. m. tel: 703.644.9045 washington kirkland i. e. tel: 425.820.8100 maple valley b. m. tel: 206.223.0080 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953 sales of?ces and design resource centers lsi logic corporation corporate headquarters 1551 mccarthy blvd milpitas ca 95035 tel: 408.433.8000 fax: 408.433.8989 north america california irvine 18301 von karman ave suite 900 irvine, ca 92612 tel: 949.809.4600 fax: 949.809.4444 pleasanton design center 5050 hopyard road, 3rd floor suite 300 pleasanton, ca 94588 tel: 925.730.8800 fax: 925.730.8700 san diego 7585 ronson road suite 100 san diego, ca 92111 tel: 858.467.6981 fax: 858.496.0548 silicon valley 1551 mccarthy blvd sales of?ce m/s c-500 milpitas, ca 95035 tel: 408.433.8000 fax: 408.954.3353 design center m/s c-410 tel: 408.433.8000 fax: 408.433.7695 wireless design center 11452 el camino real suite 210 san diego, ca 92130 tel: 858.350.5560 fax: 858.350.0171 colorado boulder 4940 pearl east circle suite 201 boulder, co 80301 tel: 303.447.3800 fax: 303.541.0641 colorado springs 4420 arrowswest drive colorado springs, co 80907 tel: 719.533.7000 fax: 719.533.7020 fort collins 2001 dan?eld court fort collins, co 80525 tel: 970.223.5100 fax: 970.206.5549 florida boca raton 2255 glades road suite 324a boca raton, fl 33431 tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta 2475 north winds parkway suite 200 alpharetta, ga 30004 tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace two mid american plaza suite 800 oakbrook terrace, il 60181 tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green 1262 chestnut street bowling green, ky 42101 tel: 270.793.0010 fax: 270.793.0040 maryland bethesda 6903 rockledge drive suite 230 bethesda, md 20817 tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham 200 west street waltham, ma 02451 tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology 77 south bedford street burlington, ma 01803 tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis 8300 norman center drive suite 730 minneapolis, mn 55437 tel: 612.921.8300 fax: 612.921.8399 new jersey red bank 125 half mile road suite 200 red bank, nj 07701 tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology 215 longstone drive cherry hill, nj 08003 tel: 856.489.5530 fax: 856.489.5531 new york fairport 550 willowbrook of?ce park fairport, ny 14450 tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh phase ii 4601 six forks road suite 528 raleigh, nc 27609 tel: 919.785.4520 fax: 919.783.8909 oregon beaverton 15455 nw greenbrier parkway suite 235 beaverton, or 97006 tel: 503.645.0589 fax: 503.645.6612 texas austin 9020 capital of tx highway north building 1 suite 150 austin, tx 78759 tel: 512.388.7294 fax: 512.388.4171 plano 500 north central expressway suite 440 plano, tx 75074 tel: 972.244.5000 fax: 972.244.5001 houston 20405 state highway 249 suite 450 houston, tx 77070 tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa 260 hearst way suite 400 kanata, on k2l 3h1 tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa 53 bis avenue de l'europe b.p. 139 78148 velizy-villacoublay cedex, paris tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh orleansstrasse 4 81669 munich tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart mittlerer pfad 4 d-70499 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milan lsi logic s.p.a. centro direzionale colleoni palazzo orione ingresso 1 20041 agrate brianza, milano tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. rivage-shinagawa bldg. 14f 4-1-8 kounan minato-ku, tokyo 108-0075 tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka crystal tower 14f 1-2-27 shiromi chuo-ku, osaka 540-6014 tel: 81.6.947.5281 fax: 81.6.947.5287 sales of?ces and design resource centers (continued) korea seoul lsi logic corporation of korea ltd 10th fl., haesung 1 bldg. 942, daechi-dong, kangnam-ku, seoul, 135-283 tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd world trade center eindhoven building rijder bogert 26 5612 lz eindhoven tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd 7 temasek boulevard #28-02 suntec tower one singapore 038987 tel: 65.334.9061 fax: 65.334.4749 sweden stockholm lsi logic ab finlandsgatan 14 164 74 kista tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan taipei lsi logic asia, inc. taiwan branch 10/f 156 min sheng e. road section 3 taipei, taiwan r.o.c. tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd greenwood house london road bracknell, berkshire rg12 2ub tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers international distributors australia new south wales reptechnic pty ltd 3/36 bydown street neutral bay, nsw 2089 tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa lozenberg 4 1932 zaventem tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. beijing representative of?ce room 708 canway building 66 nan li shi lu xicheng district beijing 100045, china tel: 86.10.6804.2534 to 38 fax: 86.10.6804.2521 france rungis cedex azzurri technology france 22 rue saarinen sillic 274 94578 rungis cedex tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik hans-pinsel str. 4 d-85540 haar tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh stahlgruberring 12 81829 munich tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag graf-zepplin-str 14 d-33181 wuennenberg-haaren tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd unit 608 tower 1 cheung sha wan plaza 833 cheung sha wan road kowloon, hong kong tel: 852.2428.0008 fax: 852.2401.2105 serial system (hk) ltd 2301 nanyang plaza 57 hung to road, kwun tong kowloon, hong kong tel: 852.2995.7538 fax: 852.2950.0386 india bangalore spike technologies india private ltd 951, vijayalakshmi complex, 2nd floor, 24th main, j p nagar ii phase, bangalore, india 560078 tel: 91.80.664.5530 fax: 91.80.664.9748 israel tel aviv eastronics ltd 11 rozanis street p.o. box 39300 tel aviv 61392 tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo daito electron sogo kojimachi no.3 bldg 1-6 kojimachi chiyoda-ku, tokyo 102-8730 tel: 81.3.3264.0326 fax: 81.3.3261.3984 global electronics corporation nichibei time24 bldg. 35 tansu-cho shinjuku-ku, tokyo 162-0833 tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 marubeni solutions 1-26-20 higashi shibuya-ku, tokyo 150-0001 tel: 81.3.5778.8662 fax: 81.3.5778.8669 shinki electronics myuru daikanyama 3f 3-7-3 ebisu minami shibuya-ku, tokyo 150-0022 tel: 81.3.3760.3110 fax: 81.3.3760.3101 yokohama-city innotech 2-15-10 shin yokohama kohoku-ku yokohama-city, 222-8580 tel: 81.45.474.9037 fax: 81.45.474.9065 macnica corporation hakusan high-tech park 1-22-2 hadusan, midori-ku, yokohama-city, 226-8505 tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. beatrix de rijkweg 8 5657 eg eindhoven tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag mattenstrasse 6a ch 2555 brugg tel: 41.32.3743232 fax: 41.32.3743233 taiwan taipei avnet-mercuries corporation, ltd 14f, no. 145, sec. 2, chien kuo n. road taipei, taiwan, r.o.c. tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd 7th fl., 52, sec. 3 nan-kang road taipei, taiwan, r.o.c. tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd 4fl., no. 34, chu luen street taipei, taiwan, r.o.c. tel: 886.2.2721.9533 fax: 886.2.2773.3756 wintech microeletronics co., ltd 7f., no. 34, sec. 3, pateh road taipei, taiwan, r.o.c. tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd 16 grove park business estate waltham road white waltham maidenhead, berkshire sl6 3lw tel: 44.1628.826826 fax: 44.1628.829730 milton keynes ingram micro (uk) ltd garamonde drive wymbush milton keynes buckinghamshire mk8 8df tel: 44.1908.260422 swindon ebv elektronik 12 interface business park bincknoll lane wootton bassett, swindon, wiltshire sn4 8sy tel: 44.1793.849933 fax: 44.1793.859555 sales of?ces with design resource centers |
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