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| data sheet c-3e network processor silicon revision a1 c3enpa1-ds/d rev 03 preliminary
data sheet c-3e network processor silicon revision a1 c3enpa1-ds/d rev 03 preli m inary copyright ? 2002 motorola, inc. all rights reserved. no part of this documentation may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from motorola. motorola reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of motorola to provide notification of such revision or change. motorola provides this documentation without warranty, term, or condition of any kind, either implied or expressed, including, but not limited to, the implied warranties, terms or conditions of merchantability, satisfactory quality, and fitness for a particular purpose. motorola may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. c-5e, c-3e, c-5, q-5, q-3, c-port, and c-ware are all trademarks of c-port, a motorola company. motorola and the stylized motorola logo are registered in the us patent & trademark office. all other product or service names are the property of their respective owners. motorola general business information c3enpa1-ds/d rev 03 c3enpa1-ds/d rev 03 contents about this guide guide overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data sheet classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 using pdf documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 guide conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 related product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 c hapter 1 functional description features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 massive processing power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 high functional integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 channel processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 executive processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 system interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 fabric processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 buffer management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table lookup unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 queue management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 c hapter 2 signal descriptions signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 pin descriptions grouped by function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 lvttl and lvpecl specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 cp interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ds1/t1 framer interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10/100 ethernet (rmii) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 gigabit ethernet (gmii) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 contents c3enpa1-ds/d rev 03 motorola general business information gigabit ethernet and fibre channel tbi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 sonet oc-3 transceiver interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 sonet oc-12 transceiver interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 executive processor system interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 serial interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 prom interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 general system interface signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 fabric processor interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 bmu sdram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 tlu sram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 qmu sram (internal mode) interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 qmu to q-5/q-3 (external mode) interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 power supply signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 signals grouped by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 jtag support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 jtag data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 boundary scan restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 boundary scan cell types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 idcode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 jtag instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 boundary scan description language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 c hapter 3 electrical specifications absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 power and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 thermal management information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 internal package conduction resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 heat sink selection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ac timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 clock timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 cp timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 contents 7 motorola general business information c3enpa1-ds/d rev 03 ds1/ds3 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10/100 ethernet timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 gigabit gmii ethernet, tbi and mii interface timing specifications . . . . . . . . . . . . . . . . . . 83 oc-3 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 oc-12 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 executive processor timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 pci timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 mdio serial interface timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 low speed serial interface timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 prom interface timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 fabric processor timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 bmu timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 tlu timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 qmu sram (internal mode) timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 qmu to q-5/q-3 (external mode) timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 c hapter 4 mechanical specifications package views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 package measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 marking codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8 contents c3enpa1-ds/d rev 03 motorola general business information motorola general business information c3enpa1-ds/d rev 03 c3enpa1-ds/d rev 03 list of figures 1 c-3e network processor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2 pin locations (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3 pin locations (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 gmii/tbi transmit and receive pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 prom interface diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6 prom interface timing outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7 observe-only cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8 cell design that can be used for both input and output pins . . . . . . . . . . . . . . . . . . . . . . . 68 9 bringup clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10 package cross section view with serveral heat sink options . . . . . . . . . . . . . . . . . . . . . . . 76 11 package with heat sink mounted to the printed circuit board . . . . . . . . . . . . . . . . . . . . . . . 77 12 test loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13 system clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 14 ds1/ds3 ethernet timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 15 10/100 ethernet timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 16 gigabit ethernet and tbi interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 17 oc-3 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18 oc-12 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 19 pci timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 20 mdio serial interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 21 low speed serial interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 22 prom interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 23 fabric processor timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 24 bmu timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 25 tlu timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 26 qmu sram (internal mode) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 27 qmu to q-5/q-3 (external mode) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 28 c-3e network processor bga package side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 29 c-3e network processor bga package (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 30 c-3e network processor bga (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10 list of figures c3enpa1-ds/d rev 03 motorola general business information motorola general business information c3enpa1-ds/d rev 03 c3enpa1-ds/d rev 03 list of tables 1 data sheet classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 navigating within a pdf document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 c-3e network processor data sheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 c-port silicon documentation set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 tlu sram configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 clock and reference signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 cp physical interface signals and pins (grouped by clusters) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 ds1/t1 framer interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 10/100 ethernet signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 transmit and receive pin combinations for gigabit ethernet and fibre channel . . . . . . . . . . . 36 11 gigabit ethernet (gmii/mii) signals one cluster example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 gigabit ethernet and fibre channel tbi signals example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13 oc-3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 14 oc-12 signals example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 15 pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 16 serial interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 17 prom interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 18 general system interface signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 19 fabric interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 20 utopia1*, 2, 3 atm mode, c-3e network processor to fabric interface pin mapping . . . . . . 50 21 utopia1*, 2, 3 phy mode, c-3e network processor to fabric interface pin mapping . . . . . . . 50 22 bmu sdram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 23 tlu sram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 24 qmu sram (internal mode) interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 25 qmu to q-5/q-3 (external mode) interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 26 power supply signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 27 miscellaneous test signals for jtag, scan, and internal test routines . . . . . . . . . . . . . . . . 57 28 signals listed by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 29 jtag internal register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 30 jtag identification code and its sub-components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12 list of tables c3enpa1-ds/d rev 03 motorola general business information 31 instruction register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 32 c-3e network processor absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 33 c-3e network processor recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .72 34 c-3e network processor dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 35 c-3e network processor capacitance data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 36 c-3e network processor power and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 37 system clock timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 38 ds1/ds3 ethernet timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 39 10/100 ethernet timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 40 gigabit gmii/mii ethernet interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 41 gigabit tbi interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 42 oc-3 timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 43 oc-12 timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 44 pci timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 45 mdio serial interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 46 low speed serial interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 47 prom interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 48 fabric processor timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 49 bmu timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 50 signal groups in bmu timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 51 tlu timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 52 signal groups in tlu timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 53 qmu sram (internal mode) timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 54 signal groups in qmu sram (internal mode) timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . .99 55 qmu to q-5/q-3 (external mode) timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 56 signal groups in qmu to q-5/q-3 (external mode) timimg diagrams . . . . . . . . . . . . . . . . . . . 101 57 package measurements (reference figure 28 , figure 29 and figure 30 for symbols) . . . . 106 58 c-3e network processor marking codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 motorola general business information c3enpa1-ds/d rev 03 c3enpa1-ds/d rev 03 about this guide guide overview the c-3e network processor data sheet describes the hardware layout specifications including pinouts, memory configuration guidelines, timing diagrams, power and power sequencing guidelines, thermal design guidelines, and mechanical specifications. this document contains information on a pre-production product. specifications and information herein are subject to change without notice. this guide assumes a good understanding of the c-3e tm network processor (np) architecture. see the c-5e/c3e network processor architecture guide (part number c5ec3earch-rm/d) for more detail about how the hardware works. this guide also assumes good working knowledge of the c-ware software toolset. this guide covers the following topics: ? functional description signal descriptions electrical specifications mechanical specifications 14 about this guide c3enpa1-ds/d rev 03 motorola general business information data sheet classifications table 1 describes the data sheet classifications of advance, preliminary, and production. using pdf documents electronic documents are provided as pdf files. open and view them using the adobe? acrobat? reader application, version 3.0 or later. if necessary, download the acrobat reader from the adobe systems, inc. web site: http://www.adobe.com/prodindex/acrobat/readstep.html pdf files offer several ways for moving among the document?s pages, as follows: to move quickly from section to section within the document, use the acrobat bookmarks that appear on the left side of the acrobat reader window. the bookmarks provide an expandable outline view of the document ? s contents. to display the document ? s acrobat bookmarks, press the ? display both bookmarks and page ? button on the acrobat reader tool bar. to move to the referenced page of an entry in the document ? s contents or index, click on the entry itself, each of which is hyperlinked. to follow a cross-reference to a heading, figure, or table, click the blue text. table 1 data sheet classifications classification description advance information used to advise customers of the proposed addition to the product line. this document will typically contain some useful information including interfacing with the user ? s system and some specifications. the goal of this document is to allow customers to begin designs but with expectation of changes. specification details may be changed later without notice. preliminary information describes pre-production or first production devices and is usually indicative of production stage performance. minor changes should be expected as characteristic spreads become better controlled. specification details may be changed slightly without notice, but the customer can design their product based on this data sheet. production data defines the long-term specified production limits based on fully characterized data. it includes a disclaimer to allow improvements in specifications and modifications that do not affect form, fit or function in original applications; if absolute maximum ratings are changed, they should improve rather than downgrade. using pdf documents 15 motorola general business information c3enpa1-ds/d rev 03 to move to the beginning or end of the document, to move page by page within the document, or to navigate among the pages you displayed by clicking on hyperlinks, use the acrobat reader navigation buttons shown in this figure: table 2 summarizes how to navigate within an electronic document. table 2 navigating within a pdf document to navigate this way click this move from section to section within the document. a bookmark on the left side of the acrobat reader window move to an entry in the table of contents. the entry itself move to an entry in the index. the page number move to an entry in the list of figures or list of tables. the figure or table number follow a cross-reference (highlighted in blue text). the cross-reference text move page by page. the appropriate acrobat reader navigation buttons move to the beginning or end of the document. the appropriate acrobat reader navigation buttons move backward or forward among a series of hyperlinks you have selected. the appropriate acrobat reader navigation buttons beginning of document end of next page previous previous or next hyperlink 16 about this guide c3enpa1-ds/d rev 03 motorola general business information guide conventions the following visual elements are used throughout this guide, where applicable: this icon and text designates information of special note. warning: this icon and text indicate a potentially dangerous procedure. instructions contained in the warnings must be followed. warning: this icon and text indicate a procedure where the reader must take precautions regarding laser light. this icon and text indicate the possibility of electrostatic discharge (esd) in a procedure that requires the reader to take the proper esd precautions. revision history table 3 provides details about changes made for each revision of this guide. table 3 c-3e network processor data sheet revision history revision date cst revision cds revision changes november 8, 2002 2.2 2.0 ? added information about optional capacitors, nominal values for recommended operating conditions, and updated package measurement values. pin number typographical correction in table 28 , pin af12 corrected to fin4 (instead of fin14), and pin ae5 corrected to pad23 (instead of pad27). typographic corrections throughout. related product documentation 17 motorola general business information c3enpa1-ds/d rev 03 related product documentation table 4 lists the user and reference documentation for motorola ? s c-port silicon documentation set. table 4 c-port silicon documentation set document subject document name purpose document id processor information c-5 network processor architecture guide describes the full architecture of the c-5 network processor. c5nparch-rm/d c-5 network processor data sheet describes hardware design specifications for the c-5 network processor. c5npdata-ds/d c-5e/c-3e network processor architecture guide describes the full architecture of the c-5e and c-3e network processors. c5ec3earch-rm/d c-5e network processor data sheet describes hardware design specifications for the c-5e network processor. c5enpa1-ds/d c-3e network processor data sheet describes hardware design specifications for the c-3e network processor. c3enpa1-ds/d c-5 network processor to c-5e network processor comparison delta document describes key architectural features of the c-5e, and highlights main differences between c-5 and c-5e. c5c5edelta-rm/d m-5 channel adapter architecture guide describes the full architecture of the m-5 channel adapter. m5caarch-rm/d m-5 channel adapter data sheet describes hardware design specifications for the m-5 channel adapter. m5ca0-ds/d q-5/q-3 traffic management coprocessor architecture guide describes the full architecture of the q-5 and q-3 traffic management coprocessor. q5q3arch-rm/d q-5 traffic management coprocessor data sheet describes hardware design specifications for the q-5 traffic management coprocessor. q5tmca0-ds/d 18 about this guide c3enpa1-ds/d rev 03 motorola general business information motorola general business information c3enpa1-ds/d rev 03 c3enpa1-ds/d rev 03 chapter 1 functional description features key features of the c-3e tm network processor (np) are its massive processing capabilities and its high level of functional integration on one chip. massive processing power operating frequencies: up to 180mhz 3gbps of bandwidth (for non-blocking throughput) more than 3,000mips of computing power (for adding services throughout the protocol stack) up to 9 million packets per second transmitted at wire speed 17 programmable risc cores (for cell/packet forwarding) 32 programmable serial data processors (for processing bit streams) up to 133 million table lookups per second three internal buses for 46gbs of aggregate bandwidth high functional integration 728 pin ball grid array (bga) package 16 channel processors (8 cp ? s with full functionality configurable for full i/o or recirculation, and 8 cp ? s with limited functionality configurable only for bit and byte level recirculation) including: ? embedded oc-3c, oc-12, oc-12c sonet framers ? programmable mac interface ? risc cores ? programmable pin phy interfaces embedded coprocessors for table lookup (classification), buffer management (payload control), and queue management (qos implementation) 20 chapter 1: functional description c3enpa1-ds/d rev 03 motorola general business information dedicated fabric processor and port embedded risc executive processor integrated 32bit 33/66mhz pci bus interface block diagram the c-3e tm np, has an architecture specifically designed for networking applications. the following sections describe each component of the c-3e np. the main components of the c-3e np are: channel processors executive processor fabric processor buffer management unit table lookup unit queue management unit the c-3e np conforms with both sonet and sdh. therefore, oc-3(sts-3/stm-1), and oc-12 (sts-12/stm-4). figure 1 shows a block diagram of the c-3e np, including its potential external interfaces. for more information about the architecture of the c-3e np, see the c-5e/c-3e network processor architecture guide (part number c5ec3earch-rm/d) . block diagram 21 motorola general business information c3enpa1-ds/d rev 03 figure 1 c-3e network processor block diagram phy phy phy phy buses (64gbps bandwidth) cluster cluster cp-1 cp-0 cp-2 cp-3 cp-12 cp-13 cp-14 cp-15 external host cpu (optional) oc-3 phy interface examples: oc-12 gigabit ethernet - aggregated 10/100 ethernet external prom (optional) control logic (optional) fabric processor boundary buffer mgmt unit channel processors sdram c-3e np sram sram table lookup unit fabric processor executive processor queue mgmt unit pci serial prom q-5 or q-3 (optional) 16 channel processors: 8 (cp0 to cp7) full functionality 8 (cp8 to cp15) internal-only 22 chapter 1: functional description c3enpa1-ds/d rev 03 motorola general business information channel processors the c-3e np contains eight programmable external channel processors (cps) that receive, process, and transmit network data, plus an additional eight internal cps that process data. typically one cp is assigned to each port for medium bandwidth applications (fast ethernet to oc-3). multiple cps can be assigned to a port in a configuration called channel aggregation in high bandwidth applications (greater than oc-3). multiple logical ports can be assigned to a single cp, with the addition of an external multiplexor, for low bandwidth applications, such as ds1 to ds3. the c-3e np ? s architecture supports a variety of industry-standard serial and parallel protocols and individual port data rates including: 10/100mb ethernet (rmii) 1gb ethernet (gmii and tbi) oc-3c oc-12 100mbit fibrechannel ds1/ds3, supported through the use of external framers/multiplexors the c-3e np?s programmability can also support a variety of special interfaces, such as various xdsl encapsulations and proprietary protocols. key components of each cp are a risc core (cprc) that orchestrates cell/packet processing and a set of microprogrammable, special-purpose processors, called serial data processors (sdps), that provide features such as ethernet mac and sonet/sdh framing, multichannel hdlc, and atm cell delineation. this means you usually only need to include phys to complete the system. executive processor 23 motorola general business information c3enpa1-ds/d rev 03 executive processor the executive processor (xp) serves as a centralized computing resource for the c-3e np and manages the system interfaces. the xp performs conventional supervisory tasks in the c-3e np, including: reset and initialization of the c-3e np program loading and control of cps centralized exception handling management of a host interface through the pci management of system interfaces (pci, serial bus, prom) system interfaces the system interfaces to the xp are: pci ? provides an industry standard 32bit 33/66mhz pci channel used for chip-level shared resources. the pci has both initiator and target capabilities. the pci interface is typically connected to a host processor. serial bus interface ? provides a general purpose bi-directional, two-wire serial bus and i/o port that allows the c-3e np to control external logic with either of two standard protocols: ? the mdio (high-speed) protocol : uses a 16bit data format with 10bits of addressing and supports transfers up to 25mhz. ? the low-speed protocol : uses an 8bit data format followed by an acknowledge bit and supports transfers up to 400kbps. software is used to select which protocol to use, by setting the appropriate bits in the serial bus configuration register. when a serial bus transfer is active, an external pin is driven by the c-3e np to indicate which protocol is being used (spld=0 indicates mdio protocol; spld=1 indicates low-speed protocol). both sida and sicl are bi-directional lines that are connected, via an external pull-up resistor, to a positive supply voltage. when the bus is free, both lines are high because of the pull-up resistor. the output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-and function required for its arbitration mechanism. 24 chapter 1: functional description c3enpa1-ds/d rev 03 motorola general business information prom interface ? allows the xp to boot from nonvolatile, flash memory. the prom interface is a low-speed, serial i/o port that runs at 1 / 2 to 1 / 16 the core clock rate. the maximum prom size addressable is 4mbytes, and must use a ? by 16 ? part. external board logic is required to perform serial-to-parallel conversion for prom address outputs and parallel-to-serial conversion for prom data inputs. fabric processor the fabric processor (fp) acts as a high-speed network interface port with advanced functionality. it allows the c-3e np to interface to an application-specific switching solution internal to your design. the fp port supports the bidirectional transfer of segments from the c-3e np to a hardware interface that provides connectivity to other network processors or other similar line processing hardware. there are numerous parameters that can be configured within the fp to allow the interface to be adapted to different fabric protocols. the fp can be configured to conform to three (3) different fabric interfaces that include: utopia-1, -2, -3. the fp can be configured to run at any frequency up to 125mhz, with the receive and transmit data buses up to 16 bits wide. this allows a wide range of supported bandwidths to and from the switching fabric, all the way up to 2000 mbps full duplex bandwidth. buffer management unit the buffer management unit (bmu) interfaces the c-3e np to external pipeline architecture, single data rate synchronous dram. the external memory is partitioned and used as buffers for receiving and transmitting data between cps, the fp, and the xp. it is also used as second level storage in the xp memory hierarchy. the interface to an array of sdram chips is 139bits wide, composed of 128 data bits, two internal control bits, and nine secded (single error correction-double error detection) ecc (error correction code) bits. the interface is compliant with the pc100 standard and operates at up to 125mhz with 3.3v lvttl-compatible inputs and outputs. the refresh period, trcd, tcas, trp, tmrd, and trc are configurable via boot time configuration (see the c-5e/c-3e network processor architecture guide (part number c5ec3earch-rm/d) for more details). the c-3e np non-configurable interface transfers four beats of data for each read and write using a sequential burst type. in addition, the c-3e np uses an auto-refresh mode for the ram ? s. table lookup unit 25 motorola general business information c3enpa1-ds/d rev 03 some of these parameters are programmed into the sdrams ? mode register and can be applied only once per power cycle. the ecc functionality can be enabled or disabled via configuration register writes. if needed, the interface can narrowed to 128bits by disabling ecc and providing board pull-ups for the two control bits and nine ecc bits. this is useful if dimms are used in the board design. if individual sdram parts are used, x16 and x32 are supported. the bmu supports sdram devices that use 12 address lines. internal address calculation paths limit the maximum memory size to 128mbytes. only one physical bank of sdram is supported. table lookup unit the table lookup unit (tlu) performs table lookups in external sram. it can also be used for statistics accumulation and retrieval and as general data storage. the tlu simultaneously supports multiple application-defined tables and multiple search strategies, such as those needed for routing, circuit switching, and qos lookup tasks. the c-3e np uses external 64bit wide zbt pipelined bursting static ram (sram) modules (at frequencies up to 125mhz) for storage of its tables. these modules allow implementation of tables with 2 25 x 64bit entries using 8mbit sram technology. the maximum amount of memory supported by the tlu is 128mbytes in four banks, when sram technology supports 4m x 18pins parts. table 5 tlu sram configurations sram technology min table size (one bank) maximum table size (four banks) 1mbit (32k x 32pins) 256kbytes 1mbytes 2mbit (64k x 32pins) 512kbytes 2mbytes 4mbit (256k x 18pins) 2mbytes 8mbytes 8mbit (512k x 18pins) 4mbytes 16mbytes 16mbit (1m x 18pins) 8mbytes 32mbytes 32mbit (2m x 18pins) 16mbytes 64mbytes 64mbit (4m x 18pins) 32mbytes 128mbytes 26 chapter 1: functional description c3enpa1-ds/d rev 03 motorola general business information queue management unit the queue management unit (qmu) autonomously manages a number of application-defined descriptor queues. it handles inter-cp and inter-c-3e np descriptor flows by providing switching and buffering. it also performs descriptor replication for multicast applications. a number of up to 128 queues can be assigned to each cprc for qos-based services. the qmu provides a queuing engine internal to the chip and uses external sram to store the descriptors. scheduling is done by the cps. the qmu supports up to 512 queues and 16, 384 descriptor buffers. a descriptor buffer holds an application-defined ? descriptor ? , which is a structure that defines the payload buffer handle and other attributes of the forwarded cell or packet. the qmu ? s external sram interface uses zbt synchronous srams organized in a single bank of up to 128k, 32bit words. this interface runs at up to 150mhz frequency. the c-3e provides two modes for managing queues. they consist of: internal mode (using the internal qmu only) external mode (using the internal qmu and the external q-5 traffic management coprocessor, or using the internal qmu and the external q-3 traffic management coprocessor) . see the c-5e/c-3e network processor architecture guide (part number c5ec3earch-rm/d), as well as, the q-5/q-3 traffic management coprocessor architecture guide (part number q5q3arch-rm/d) for more details. motorola general business information c3enpa1-ds/d rev 03 c3enpa1-ds/d rev 03 chapter 2 signal descriptions signal summary there are nine (9) functional groupings of signals in the c-3e network processor: clock ? 7 pins channel processors (cp0 - cp7) ? 8x7 = 56 pins executive processor (xp) ? 57 pins ? pci interface ? 50 pins ? prom interface ? 4 pins ? serial bus interface ? 2 pins ? general system interface ? 1 pin fabric processor (fp) ? 42 pins buffer management unit (bmu) ? 160 pins table lookup unit (tlu) ? 99 pins queue management unit (qmu) ? 59 pins power ? 234 pins test ? 14 pins two (2) of the sections (cps and fp) are configurable, depending on the type of device being implemented. 28 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information pinout diagram the c-3e np contains 728 pins. these pin numbers are referenced throughout the remaining chapter. figure 2 shows the pin locations from the top view. in contrast, figure 3 shows the pin locations from the bottom view. figure 2 pin locations (top view) a qd8 qd13 qd16 qd21 qd24 qd29 qbclki qnqrdy qa2 qa8 qa13 jso2 jso4 jclkbyp jtrstx jtms ma7 ma2 mdqm mdqml mwex mrasx mcasx mcsx mdclk mdecc0 b qd4 vddt qd12 qd15 qd20 gnd qd28 qbclko qdph vddt qa7 gnd jso1 jso3 jhighz gnd jtck vdd33 ma1 mdecc1 mdecc2 gnd mdecc3 mdecc4 mdecc5 vdd33 mdecc6 c qd3 qd7 qd11 vddt qd19 qd23 qd27 qdqpar qdpl qa1 qa6 qa12 jso0 jtdo jso5 jtdi ma11 ma6 ma0 mdecc7 mdecc8 md129 md128 vdd33 md127 md126 md125 d qd2 gnd qd10 qd14 qd18 vddt qd26 qd31 gnd qa0 qa5 qa11 qa16 vdd33 jse cpref ma10 ma5 gnd md124 md123 vdd33 md122 md121 md120 gnd md119 e qd1 qd6 qd9 gnd qd17 qd22 qd25 qd30 qaclki qwex qa4 qa10 qa15 cclk3 cclk2 cclk1 ma9 ma4 mba1 md118 md117 md116 md115 gnd md114 md113 md112 f qd0 qd5 td0 td1 td2 td3 td4 td5 qaclko qardy qa3 qa9 qa14 sclk sclkx cclk0 ma8 ma3 mba0 md111 md110 md109 md108 md107 md106 md105 md104 g td6 vddt td7 td8 td9 gnd td10 td11 vddt gnd vddt gnd vdd33 gnd vdd33 gnd vdd33 gnd vdd33 md103 md102 gnd md101 md100 md99 vdd33 md98 h td12 td13 td14 vddt td15 td16 td17 td18 gnd vdd gnd vdd gnd vdd33 gnd vdd gnd vdd33 gnd md97 md96 md95 md94 vdd33 md93 md92 md91 j td19 td20 td21 gnd td22 td23 td24 td25 vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md90 md89 md88 md87 gnd md86 md85 md84 k td26 gnd td27 td28 td29 vddt td30 td31 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md83 md82 vdd33 md81 md80 md79 gnd md78 l td32 td33 td34 td35 td36 td37 td38 td39 vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md77 md76 md75 md74 md73 md72 md71 md70 m td40 td41 td42 vddt td43 td44 td45 td46 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md69 md68 md67 md66 vdd33 md65 md64 md63 n td47 td48 td49 td50 td51 td52 td53 td54 vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md62 md61 md60 md59 md58 md57 md56 md55 p td55 vddt td56 td57 td58 gnd td59 td60 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md54 md53 gnd md52 md51 md50 vdd33 md49 r td61 td62 td63 tclki twe0x twe1x twe2x twe3x vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md48 md47 md46 md45 md44 md43 md42 md41 t tpar0 tpar1 tpar2 gnd tpar3 tce0x tce1x tce2x gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md40 md39 md38 md37 gnd md36 md35 md34 u tce3x ta0 ta1 ta2 ta3 ta4 ta5 ta6 vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md33 md32 md31 md30 md29 md28 md27 md26 v ta7 gnd ta8 ta9 ta10 vddt ta11 ta12 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md25 md24 vdd33 md23 md22 md21 gnd md20 w ta13 ta14 ta15 vddt ta16 ta17 ta18 ta19 vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md19 md18 md17 md16 vdd33 md15 md14 md13 y ta20 ta21 xpuhot gnd spdo spdi spld spck gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md12 md11 md10 md9 gnd md8 md7 md6 aa sicl vddt pad30 sida pidsel gnd pframex pgntx vdd33 gnd vdd33 gnd vdd33 gnd vdd33 gnd vdd33 gnd vdd33 md5 md4 gnd md3 md2 md1 vdd33 md0 ab ptrdyx pcbex0 pad31 pad26 pad20 pad16 pad10 pad4 pad0 frxctl6 fin14 fin8 fin2 ftxctl1 fout13 fout7 cp7_6 cp7_2 cp6_4 cp5_6 cp5_0 cp4_1 cp3_4 cp2_5 cp2_1 cp1_2 cp0_5 ac pinta pirdyx pperrx gnd pad21 pad17 pad11 pad5 pad1 frxctl2 fin13 fin7 fin1 ftxctl0 fout12 fout6 cp7_5 cp7_1 cp6_3 cp5_5 cp4_6 cp4_0 cp3_3 gnd cp2_0 cp1_1 cp0_4 ad preqx gnd pserrx pad27 pad22 vdd33 pad12 pad6 gnd frxctl1 fin12 fin6 fin0 vdd33 fout11 fout5 cp7_4 cp7_0 gnd cp5_4 cp4_5 vdd33 cp3_2 cp2_4 cp1_6 gnd cp0_3 ae prstx pstopx pcbex3 vdd33 pad23 pad18 pad13 pad7 pad2 frxctl0 fin11 fin5 ftxclk fout15 fout10 fout4 cp7_3 cp6_6 cp6_2 cp5_3 cp4_4 cp3_6 cp3_1 vdd33 cp1_5 cp1_0 cp0_2 af pclk vdd33 pcbex2 pad28 pad24 gnd pad14 pad8 pad3 vdd33 fin10 fin4 ftxctl6 gnd fout9 fout3 fout1 vdd33 cp6_1 cp5_2 cp4_3 gnd cp3_0 cp2_3 cp1_4 vdd33 cp0_1 ag ppar pdevselx pcbex1 pad29 pad25 pad19 pad15 pad9 frxclk fin15 fin9 fin3 ftxctl2 fout14 fout8 fout2 fout0 cp6_5 cp6_0 cp5_1 cp4_2 cp3_5 cp2_6 cp2_2 cp1_3 cp0_6 cp0_0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 a b c d e f g h j k l m n p r t u v w y a a ab ac ad ae af a g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 pinout diagram 29 motorola general business information c3enpa1-ds/d rev 03 figure 3 pin locations (bottom view) a qd8 qd13 qd16 qd21 qd24 qd29 qbclki qnqrdy qa2 qa8 qa13 jso2 jso4 jclkbypjtrstx jtms ma7 ma2 mdqm mdqml mwex mrasx mcasx mcsx mdclk mdecc0 b qd4 vddt qd12 qd15 qd20 gnd qd28 qbclko qdph vddt qa7 gnd jso1 jso3 jhighz gnd jtck vdd33 ma1 mdecc1 mdecc2 gnd mdecc3 mdecc4 mdecc5 vdd33 mdecc6 c qd3 qd7 qd11 vddt qd19 qd23 qd27 qdqpar qdpl qa1 qa6 qa12 jso0 jtdo jso5 jtdi ma11 ma6 ma0 mdecc7 mdecc8 md129 md128 vdd33 md127 md126 md125 d qd2 gnd qd10 qd14 qd18 vddt qd26 qd31 gnd qa0 qa5 qa11 qa16 vdd33 jse cpref ma10 ma5 gnd md124 md123 vdd33 md122 md121 md120 gnd md119 e qd1 qd6 qd9 gnd qd17 qd22 qd25 qd30 qaclki qwex qa4 qa10 qa15 cclk3 cclk2 cclk1 ma9 ma4 mba1 md118 md117 md116 md115 gnd md114 md113 md112 f qd0 qd5 td0 td1 td2 td3 td4 td5 qaclko qardy qa3 qa9 qa14 sclk sclkx cclk0 ma8 ma3 mba0 md111 md110 md109 md108 md107 md106 md105 md104 g td6 vddt td7 td8 td9 gnd td10 td11 vddt gnd vddt gnd vdd33 gnd vdd33 gnd vdd33 gnd vdd33 md103 md102 gnd md101 md100 md99 vdd33 md98 h td12 td13 td14 vddt td15 td16 td17 td18 gnd vdd gnd vdd gnd vdd33 gnd vdd gnd vdd33 gnd md97 md96 md95 md94 vdd33 md93 md92 md91 j td19 td20 td21 gnd td22 td23 td24 td25 vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md90 md89 md88 md87 gnd md86 md85 md84 k td26 gnd td27 td28 td29 vddt td30 td31 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md83 md82 vdd33 md81 md80 md79 gnd md78 l td32 td33 td34 td35 td36 td37 td38 td39 vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md77 md76 md75 md74 md73 md72 md71 md70 m td40 td41 td42 vddt td43 td44 td45 td46 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md69 md68 md67 md66 vdd33 md65 md64 md63 n td47 td48 td49 td50 td51 td52 td53 td54 vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md62 md61 md60 md59 md58 md57 md56 md55 p td55 vddt td56 td57 td58 gnd td59 td60 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md54 md53 gnd md52 md51 md50 vdd33 md49 r td61 td62 td63 tclki twe0x twe1x twe2x twe3x vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md48 md47 md46 md45 md44 md43 md42 md41 t tpar0 tpar1 tpar2 gnd tpar3 tce0x tce1x tce2x gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md40 md39 md38 md37 gnd md36 md35 md34 u tce3x ta0 ta1 ta2 ta3 ta4 ta5 ta6 vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md33 md32 md31 md30 md29 md28 md27 md26 v ta7 gnd ta8 ta9 ta10 vddt ta11 ta12 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md25 md24 vdd33 md23 md22 md21 gnd md20 w ta13 ta14 ta15 vddt ta16 ta17 ta18 ta19 vddt gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd33 md19 md18 md17 md16 vdd33 md15 md14 md13 y ta20 ta21 xpuhot gnd spdo spdi spld spck gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd md12 md11 md10 md9 gnd md8 md7 md6 aa sicl vddt pad30 sida pidsel gnd pframex pgntx vdd33 gnd vdd33 gnd vdd33 gnd vdd33 gnd vdd33 gnd vdd33 md5 md4 gnd md3 md2 md1 vdd33 md0 ab ptrdyx pcbex0 pad31 pad26 pad20 pad16 pad10 pad4 pad0 frxctl6 fin14 fin8 fin2 ftxctl1 fout13 fout7 cp7_6 cp7_2 cp6_4 cp5_6 cp5_0 cp4_1 cp3_4 cp2_5 cp2_ 1 cp1_2 cp0_5 ac pinta pirdyx pperrx gnd pad21 pad17 pad11 pad5 pad1 frxctl2 fin13 fin7 fin1 ftxctl0 fout12 fout6 cp7_5 cp7_1 cp6_3 cp5_5 cp4_6 cp4_0 cp3_3 gnd cp2_0 cp1 _1 cp0_4 ad preqx gnd pserrx pad27 pad22 vdd33 pad12 pad6 gnd frxctl1 fin12 fin6 fin0 vdd33 fout11 fout5 cp7_4 cp7_0 gnd cp5_4 cp4_5 vdd33 cp3_2 cp2_4 cp1_6 gnd cp0_ 3 ae prstx pstopx pcbex3 vdd33 pad23 pad18 pad13 pad7 pad2 frxctl0 fin11 fin5 ftxclk fout15 fout10 fout4 cp7_3 cp6_6 cp6_2 cp5_3 cp4_4 cp3_6 cp3_1 vdd33 cp1 _5 cp1_0 cp0_2 af pclk vdd33 pcbex2 pad28 pad24 gnd pad14 pad8 pad3 vdd33 fin10 fin4 ftxctl6 gnd fout9 fout3 fout1 vdd33 cp6_1 cp5_2 cp4_3 gnd cp3_0 cp2_3 cp1_4 vdd33 cp0_ 1 a g ppar pdevselx pcbex1 pad29 pad25 pad19 pad15 pad9 frxclk fin15 fin9 fin3 ftxctl2 fout14 fout8 fout2 fout0 cp6_5 cp6_0 cp5_1 cp4_2 cp3_5 cp2_6 cp2_2 cp1 _3 cp0_6 cp0_0 a b c d e f g h j k l m n p r t u v w y a a ab ac ad ae af a g 12 34567891011121314151617181920212223242526 27 12 3456789101112131415161718192021222324252627 30 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information pin descriptions grouped by function the c-3e np pins are categorized in groups, reflecting interfaces to the chip: clock signals cp interface signals executive processor system interface signals fabric processor interface signals bmu sdram interface signals tlu sram interface signals qmu sram (internal mode) interface signals qmu to q-5/q-3 (external mode) interface signals power supply signals test signals pins conform to joint electronic devices engineering council (jedec) standards. lvttl and lvpecl specifications c-3e np pins are the following types: low voltage ttl-compatible (lvttl). the c-3e np ? s lvttl pins conform to the jedec jesd8-b specification. low voltage positive emitter coupled logic (lvpecl). all of the signals in the following tables in this chapter denote whether the individual signal is an input (i), output (o), both input and output (i/o), or power (p). in addition, a pu, pd, and nc are used. the pu indicates that an internal resistor will pullup the pad if left unconnected. pd indicates an internal pulldown resistor. nc means the pad is to be left unconnected. pin descriptions grouped by function 31 motorola general business information c3enpa1-ds/d rev 03 clock signals table 6 describes the c-3e np clock signals. cp interface signals the c-3e np ? s 8 external cps support various network physical interfaces, providing a serial interface to the phy layer. interfaces are configured via bits in the c-3e np register set. many interfaces are possible by programming the configuration registers. cps can be used individually or in a cluster (four cps) to implement the various interfaces. table 7 provides a quick reference of all the cp pins organized by clusters. there are seven physical i/o pins associated with each cp. all pins are capable of receiving data, with some configurable to be input clocks, output clocks, or data drivers. in addition, pairs of pins can be configured as differential pairs for lvpecl compatibility. in the case of rmii, oc-3, ds1, and ds3, the drivers and receivers at the pin are locally configured to match the relevant phy or framer chip. oc-12 uses the aggregation of four cps (one cluster), while gmii and ten bit interface (tbi) can use either eight cps (four for receive and four for transmit) or four cps that share the transmit and receive functions for non-wire speed applications. during cp aggregation, all 28 pins associated with a cluster are routed to all of the serial data processors (sdps) in that cluster. this allows round-robin usage of portions of the sdps, with each getting access to the necessary i/o pins. table 6 clock and reference signals signal name pin # total type i/o signal description sclk* sclkx* * sclk and sclkx must not be ac-coupled. f14 f15 1 1 lvpecl lvpecl i i core clock rate (differential) cclk0 f16 1 lvt tl i pd programmable cp clock input cclk1 e16 1 lvt tl i pd programmable cp clock input cclk2 e15 1 lvt tl i pd programmable cp clock input cclk3 e14 1 lvt tl i pd programmable cp clock input cpref ? ? if any of the cps are configured for lvpecl operation (oc3) using the pin mode registers, then cpref must be wired to an external reference, as specified in table 34 on page 73. if none of the cps are configured for lvpecl operation, then the cpref pin can be left unconnected. d16 1 lvpecl i pd reference total 7 32 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information the signals for the following cp physical interfaces are included in this section: ds1/t1 framer interface configuration 10/100 ethernet (rmii) configuration gigabit ethernet (gmii) configuration gigabit ethernet and fibre channel tbi configuration sonet oc-3 transceiver interface configuration sonet oc-12 transceiver interface configuration pin descriptions grouped by function 33 motorola general business information c3enpa1-ds/d rev 03 table 7 cp physical interface signals and pins (grouped by clusters) cp cluster 1 cp cluster 2 signal pin # signal pin # cp0_0 ag27 cp4_0 ac22 cp0_1 af27 cp4_1 ab22 cp0_2 ae27 cp4_2 ag21 cp0_3 ad27 cp4_3 af21 cp0_4 ac27 cp4_4 ae21 cp0_5 ab27 cp4_5 ad21 cp0_6 ag26 cp4_6 ac21 cp1_0 ae26 cp5_0 ab21 cp1_1 ac26 cp5_1 ag20 cp1_2 ab26 cp5_2 af20 cp1_3 ag25 cp5_3 ae20 cp1_4 af25 cp5_4 ad20 cp1_5 ae25 cp5_5 ac20 cp1_6 ad25 cp5_6 ab20 cp2_0 ac25 cp6_0 ag19 cp2_1 ab25 cp6_1 af19 cp2_2 ag24 cp6_2 ae19 cp2_3 af24 cp6_3 ac19 cp2_4 ad24 cp6_4 ab19 cp2_5 ab24 cp6_5 ag18 cp2_6 ag23 cp6_6 ae18 cp3_0 af23 cp7_0 ad18 cp3_1 ae23 cp7_1 ac18 cp3_2 ad23 cp7_2 ab18 cp3_3 ac23 cp7_3 ae17 cp3_4 ab23 cp7_4 ad17 34 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information ds1/t1 framer interface configuration table 8 describes the serial framer interface signals. for each cp (0-7), you can implement one serial framer interface. cp3_5 ag22 cp7_5 ac17 cp3_6 ae22 cp7_6 ab17 table 7 cp physical interface signals and pins (grouped by clusters) (continued) cp cluster 1 cp cluster 2 signal pin # signal pin # table 8 ds1/t1 framer interface signals signal name* pin #? total type i/o label signal description cp n _0 table 7 1 lvt tl o pd tclk transmit clock (1.544mhz) cp n _1 table 7 1 lvt tl i pu rclk receive clock (1.544mhz) cp n _2 table 7 1 lvt tl o pd tdata transmit data cp n _3 table 7 1 lvt tl o pu tframe transmit frame synchronization cp n _4 table 7 1 lvt tl i pd rdata receive data cp n _5 table 7 1 lvt tl i pu rframe receive frame synchronization cp n _6 table 7 1 nc nc pu nc nc total pins 7 * n can be from 0 to 7. see table 7 . ? reference table 7 for pin numbers for the actual cluster(s) you are configuring. pin descriptions grouped by function 35 motorola general business information c3enpa1-ds/d rev 03 10/100 ethernet (rmii) configuration table 9 describes the 10/100base-t ethernet reduced media independent interface (rmii) signals. for each cp (0-15), you can implement one 10/100 ethernet interface. table 9 10/100 ethernet signals signal name* pin # total type i/o label signal description cp n _0 table 7 1 lvt tl o pd ref_clk transmit and receive clock (50mhz) cp n _1 table 7 1 lvt tl i pu crs_dv carrier sense (crs)/ receive data valid (rx_dv). crs indicates that traffic is on the link, and is asserted if the signal is a 1 or an alternating 1010... rx_dv indicates that a receive frame is in progress and the data present on the rxd pins is valid. it is asserted if this signal is a 1 for more than one cycle. cp n _2 table 7 1 lvt tl o pd txd(0) transmit data 0 (first on wire) cp n _3 table 7 1 lvt tl o pu txd(1) transmit data 1 (second on wire) cp n _4 table 7 1 lvt tl i pd rxd(0) receive data 0 (first on wire) cp n _5 table 7 1 lvt tl i pu rxd(1) receive data 1 (second on wire) cp n _6 table 7 1 lvt tl o pu tx_en transmit enable. when asserted, the data on txd is encoded and transmitted on the twisted pair cable. total pins 7 * n can be from 0 to 7. see table 7 . 36 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information gigabit ethernet (gmii) configuration gigabit ethernet media independent interface (gmii) is configured in one of two ways: use one cp cluster when density is more important than wire-speed performance because you can then implement up to four gigabit ethernet ports per c-3e np. use two cp clusters for wire-speed performance and additional processing power. you can implement up to two gigabit ethernet ports per c-3e np. table 10 lists the possible cp cluster combinations you can use and figure 4 shows receive and transmit pin configurations by cluster. table 11 lists the signals and pinouts for gigabit ethernet (gmii). figure 4 gmii/tbi transmit and receive pin configurations table 10 transmit and receive pin combinations for gigabit ethernet and fibre channel cluster single cluster mode (tbi or gmii) two cluster mode (gmii)* * the two cluster mode column lists typical configurations. any cluster can be set up to either receive or transmit. so you could configure a dual cluster mode where cluster 0 receives and cluster 3 transmits. 0 port 1 tx and rx port 1 tx 1 port 2 tx and rx port 1 rx cluster 0 cluster 1 cluster 2 cluster 3 port 1 port 2 } } tx tx rx rx single cluster mode pin configuration port 1 } tx tx rx rx two cluster mode pin configuration nc nc nc = not connected cluster 0 cluster 1 cluster 2 cluster 3 note: cluster 2 & 3 are internal loopback only. note: cluster 2 & 3 are internal loopback only. pin descriptions grouped by function 37 motorola general business information c3enpa1-ds/d rev 03 table 11 gigabit ethernet (gmii/mii) signals one cluster example signal name* pin # ? total type i/o label signal description cp n _0 table 7 1 lvt tl o pd t_clk gmii transmit clock (125mhz). this clock is used to synchronize the transmit data. cp n _1 table 7 1 lvt tl i pu tclki mii transmit clock. transmit data aligned to this clock input from phy in mii mode. 25 mhz in 100baset, 2.5 in mhz in 10baset cp n _2 table 7 1 lvt tl o pd txd(0) transmit data (byte-wide data, least significant bit) cp n _3 table 7 1 lvt tl o pu txd(1) transmit data cp n _4 table 7 1 lvt tl o pd txd(2) transmit data cp n _5 table 7 1 lvt tl o pu txd(3) transmit data cp n _6 table 7 1 lvt tl o pu tx_en transmit enable. when asserted, the data on txd is encoded and transmitted on the twisted pair cable. cp n+1 _0 table 7 1 nc nc pd nc nc cp n+1 _1 table 7 1 lvt tl i pu col collision. asserted when both rx_dv and tx_en are valid during half duplex operation. cp n+1 _2 table 7 1 lvt tl o pd txd(4) transmit data cp n+1 _3 table 7 1 lvt tl o pu txd(5) transmit data cp n+1 _4 table 7 1 lvt tl o pd txd(6) transmit data cp n+1 _5 table 7 1 lvt tl o pu txd(7) transmit data (byte-wide receive data, most significant bit) cp n+1 _6 table 7 1 lvt tl o pu tx_er transmit error. asserting tx_er when tx_en is a 1 causes transmission of the designated ? bad code ? in lieu of the normal encoded data on the twisted pair data. cp n+2 _0 table 7 1 nc nc pd nc nc cp n+2 _1 table 7 1 lvt tl i pu rclk receive clock (125mhz) cp n+2 _2 table 7 1 lvt tl i pd rxd(0) receive data (byte-wide receive data, least significant bit) cp n+2 _3 table 7 1 lvt tl i pu rxd(1) receive data cp n+2 _4 table 7 1 lvt tl i pd rxd(2) receive data cp n+2 _5 table 7 1 lvt tl i pu rxd(3) receive data cp n+2 _6 table 7 1 lvt tl i pu rx_dv receive data valid. indicates that there is a receive frame in progress and that the data present on the rxd signals is valid. cp n+3 _0 table 7 1 nc nc pd nc nc cp n+3 _1 table 7 1 lvt tl i pu crs carrier sense. indicates traffic is on the link. crs is asserted when a non-idle condition is detected on the receive data stream. crs is deasserted when an end of frame or idle condition is detected. 38 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information gigabit ethernet and fibre channel tbi configuration 1000base-t gigabit ethernet and fibre channel tbi is implemented in much the same way as gigabit ethernet (gmii). table 10 shows the possible cp pin combinations you can use and figure 4 shows receive and transmit pin configurations by cluster. table 12 shows the signals and pinouts for a single cluster for gigabit ethernet and fibre channel tbi. the unused pins for the two cluster configurations should be wired down using a resistor. cp n+3 _2 table 7 1 lvt tl i pd rxd(4) receive data cp n+3 _3 table 7 1 lvt tl i pu rxd(5) receive data cp n+3 _4 table 7 1 lvt tl i pd rxd(6) receive data cp n+3 _5 table 7 1 lvt tl i pu rxd(7) receive data (most significant bit) cp n+3 _6 table 7 1 lvt tl i pu rx_er receive error detected. indicates that there has been an error received in the receive frame. total pins 28 * n can be 0, or 4. ? reference table 7 for pin numbers for the actual cluster(s) you are configuring. table 11 gigabit ethernet (gmii/mii) signals one cluster example (continued) signal name* pin # ? total type i/o label signal description table 12 gigabit ethernet and fibre channel tbi signals example signal name* pin # ? total type i/o label signal description cp n _0 table 7 1 lvt tl o pd tclk transmit clock (125mhz). this clock is used to synchronize the transmit data. cp n _1 table 7 1 nc nc pu nc nc cp n _2 table 7 1 lvt tl o pd txd(9) transmit data (ten bits wide, last on wire) cp n _3 table 7 1 lvt tl o pu txd(8) transmit data cp n _4 table 7 1 lvt tl o pd txd(7) transmit data cp n _5 table 7 1 lvt tl o pu txd(6) transmit data cp n _6 table 7 1 lvt tl o pu txd(1) transmit data cp n+1 _0 table 7 1 nc nc pd nc nc cp n+1 _1 table 7 1 nc nc pu nc nc cp n+1 _2 table 7 1 lvt tl o pd txd(5) transmit data pin descriptions grouped by function 39 motorola general business information c3enpa1-ds/d rev 03 cp n+1 _3 table 7 1 lvt tl o pu txd(4) transmit data cp n+1 _4 table 7 1 lvt tl o pd txd(3) transmit data cp n+1 _5 table 7 1 lvt tl o pu txd(2) transmit data cp n+1 _6 table 7 1 lvt tl o pu txd(0) transmit data (ten bits wide, first on wire) cp n+2 _0 table 7 1 nc nc pd nc nc cp n+2 _1 table 7 1 lvt tl i pu rclk receive clock (62.5 mhz) cp n+2 _2 table 7 1 lvt tl i pd rxd(9) receive data (ten bits wide, last on wire) cp n+2 _3 table 7 1 lvt tl i pu rxd(8) receive data cp n+2 _4 table 7 1 lvt tl i pd rxd(7) receive data cp n+2 _5 table 7 1 lvt tl i pu rxd(6) receive data cp n+2 _6 table 7 1 lvt tl i pu rxd(1) receive data cp n+3 _0 table 7 1 nc nc pd nc nc cp n+3 _1 table 7 1 lvt tl i pu rclkn receive clock inverted cp n+3 _2 table 7 1 lvt tl i pd rxd(5) receive data cp n+3 _3 table 7 1 lvt tl i pu rxd(4) receive data cp n+3 _4 table 7 1 lvt tl i pd rxd(3) receive data cp n+3 _5 table 7 1 lvt tl i pu rxd(2) receive data cp n+3 _6 table 7 1 lvt tl i pu rxd(0) receive data (ten bits wide, first on wire) total pins 28 * n can be 0, or 4. ? reference table 7 for pin numbers for the actual cluster(s) you are configuring. table 12 gigabit ethernet and fibre channel tbi signals example (continued) signal name* pin # ? total type i/o label signal description 40 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information sonet oc-3 transceiver interface configuration table 13 describes the sonet optical carrier (oc) 3 transceiver interface signals. for each cp (0-15), you can implement a single oc-3 interface. table 13 oc-3 signals signal name* pin # ? total type i/o label signal description cp n _0 table 7 1 lvpecl i pd rclk_h receive clock noninverted side of pair (155.52mhz) cp n _1 table 7 1 lvpecl i pu rclk_l receive clock inverted side of pair (155.52mhz) cp n _2 table 7 1 lvpecl o pd txd_h transmit data noninverted side of pair cp n _3 table 7 1 lvpecl i pu txd_l transmit data inverted side of pair cp n _4 table 7 1 lvpecl i pd rxd_h receive data noninverted side of pair cp n _5 table 7 1 lvpecl i pu rxd_l receive data inverted side of pair cp n _6 table 7 1 lvpecl i pu signal_det a light level above a certain threshold is present at the optical receiver - single ended lvpecl. total pins 7 * n can be from 0 to 7. ? reference table 7 for pin numbers for the actual cluster(s) you are configuring. pin descriptions grouped by function 41 motorola general business information c3enpa1-ds/d rev 03 sonet oc-12 transceiver interface configuration sonet optical carrier (oc) 12 is implemented by using one cluster of cps. at any time, a cp within a cluster spends half its time performing receive functions, and the other half performing transmit functions. table 14 shows a cp cluster configured for one oc-12 interface. table 14 oc-12 signals example signal name* pin # ? total type i/o label signal description cp n _0 table 7 1 lvt tl o pd tclk deskewed transmit clock (77.76mhz). this clock is used to synchronize the transmit data. cp n _1 table 7 1 lvt tl i pu tclki transceiver transmit clock. this clock sets the frequency of the transmit data and is typically sourced by the phy chip. cp n _2 table 7 1 lvt tl o pd txd(0) transmit data (byte-wide data, least significant bit) cp n _3 table 7 1 lvt tl o pu txd(1) transmit data cp n _4 table 7 1 lvt tl o pd txd(2) transmit data cp n _5 table 7 1 lvt tl o pu txd(3) transmit data cp n _6 table 7 1 lvt tl o pu 00f out of frame cp n+1 _0 table 7 1 nc nc pd nc nc cp n+1 _1 table 7 1 nc nc pu nc nc cp n+1 _2 table 7 1 lvt tl o pd txd(4) transmit data cp n+1 _3 table 7 1 lvt tl o pu txd(5) transmit data cp n+1 _4 table 7 1 lvt tl o pd txd(6) transmit data cp n+1 _5 table 7 1 lvt tl o pu txd(7) transmit data (byte-wide data, most significant bit) cp n+1 _6 table 7 1 nc nc pu nc nc cp n+2 _0 table 7 1 nc nc pd nc nc cp n+2 _1 table 7 1 lvt tl i pu rclk receive clock (77.76mhz) cp n+2 _2 table 7 1 lvt tl i pd rxd(0) receive data (byte-wide receive data, least significant bit) cp n+2 _3 table 7 1 lvt tl i pu rxd(1) receive data cp n+2 _4 table 7 1 lvt tl i pd rxd(2) receive data cp n+2 _5 table 7 1 lvt tl i pu rxd(3) receive data cp n+2 _6 table 7 1 lvt tl i pu fp frame synchronization pulse. this is valid during the third a2 of the receive sonet frame. cp n+3 _0 table 7 1 nc nc pd nc nc 42 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information cp n+3 _1 table 7 1 nc nc pu nc nc cp n+3 _2 table 7 1 lvt tl i pd rxd(4) receive data cp n+3 _3 table 7 1 lvt tl i pu rxd(5) receive data cp n+3 _4 table 7 1 lvt tl i pd rxd(6) receive data cp n+3 _5 table 7 1 lvt tl i pu rxd(7) receive data (most significant bit) cp n+3 _6 table 7 1 nc nc pu nc nc total pins 28 * n can be 0, or 4. ? reference table 7 for pin numbers for a different cluster. table 14 oc-12 signals example (continued) signal name* pin # ? total type i/o label signal description pin descriptions grouped by function 43 motorola general business information c3enpa1-ds/d rev 03 executive processor system interface signals the xp ? s system interface manages the supervisory controls for the network interfaces, as well as the set of pins that provide interfaces to other components in the system that are not memories or network interfaces. it is also the primary interface used for initializing the c-3e np after reset. the xp signals include pci signals, serial interface signals, and prom interface signals. pci signals the pci can be configured to support a 32bit pci capable of operating at either 33mhz or 66mhz. the pci is fully compliant with pci specification revision 2.1. table 15 describes the pci signals. table 15 pci signals signal name pin # total type i/o signal description pad0 - pad31 ab9, ac9, ae9, af9, ab8, ac8, ad8, ae8, af8, ag8, ab7, ac7, ad7, ae7, af7, ag7, ab6, ac6, ae6, ag6, ab5, ac5, ad5, ae5, af5, ag5, ab4, ad4, af4, ag4, aa3, ab3, 32 pci i/o multiplexed address/data bus. these signals are multiplexed address and data bits. the c-3e np receives addresses as target and drives addresses as master. it drives the data and receives read data as master. pcbex0 - pcbex3 ab2, ag3, af3, ae3 4 pci i/o command byte enables. these signals are multiplexed command and byte enabled signals. the c-3e np receives byte enables as target and drives byte enables as master. ppar ag1 1 pci i/o parity. this signal carries even parity for ad and cbe# pins. it has the same receive and drive characteristics as the address and data bus, except that it is one pci cycle later. pframex aa7 1 pci i/o cycle frame ptrdyx ab1 1 pci i/o target ready for data transfer pirdyx ac2 1 pci i/o initiator ready for data transfer pstopx ae2 1 pci i/o target transaction stop request pdevselx ag2 1 pci i/o target device selected pperrx ac3 1 pci i/o bus parity error pserrx ad3 1 pci i/o system error pclk af1 1 i pd i bus clock prstx ae1 1 pci i bus reset preqx ad1 1 pci o initiator bus request (arbitration) 44 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information serial interface signals the serial interface is a bidirectional two-wire serial bus. it can use one of the following formats: an 8bit data format followed by an acknowledge bit, which supports transfers at up to 400kbps (low speed). a 16bit ieee 802.3 mdio data format with 10bits of addressing, which supports transfers up to 25mhz (high speed). the signals and pins are identical for both the high and low speed protocols. which of the two data rates used is selected by the state of the prom interface ? s spld signal that is asserted while the prom interface is idle. when spld is asserted hi the low speed serial bus protocol is selected and when spld is asserted low the mdio protocol is selected. the bus only supports a single master hierarchy that can operate as either a receiver or a transmitter. both sida and sicl are bidirectional lines that are connected, through a pull-up resistor, to a positive supply voltage. when the bus is free, both lines are high. the output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-and function required for its arbitration mechanism. pgntx aa8 1 i pd i initiator bus grant (arbitration) pidsel aa5 1 pci i initialization device select pinta ac1 1 pci o interrupt total pins 50 table 15 pci signals (continued) signal name pin # total type i/o signal description table 16 serial interface signals signal name pin # total type i/o signal description sicl aa1 1 lvt tl i pd /o serial clock line sida aa4 1 lvt tl i pd /o serial data line total pins 2 pin descriptions grouped by function 45 motorola general business information c3enpa1-ds/d rev 03 prom interface signals the prom interface is a low speed i/o port that allows the c-3e np to communicate through external logic to prom. the prom clock is 1 / 2 to 1 / 16 the core clock rate.the maximum prom size addressable is 4mbytes, and must use a ? by 16 ? part. the prom signals are listed in table 17 . figure 5 shows the connections between the prom interface and external board logic. the application is required to provide an external shift register with parallel-in and parallel-out capabilities, and a parallel load register. both devices should be positive-edge-triggered and perform a parallel load whenever spld is asserted. when spld is deasserted the shift register shifts. table 17 prom interface signals signal name pin # total type i/o signal description spdo y5 1 lvt tl o serial data out spdi y6 1 lvt tl i pd serial data in spld y7 1 lvt tl o when load is asserted on a positive clock edge, the external logic performs a parallel load. on each positive clock edge when load is de-asserted, the shift registers shift. when the prom interface is idle: if spld is asserted hi it indicates low speed serial protocol, if asserted low it indicates mdio serial protocol. spck y8 1 lvt tl o clock total pins 4 46 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information figure 5 prom interface diagram the prom interface operates in the following manner (note that two accesses are piplined together to execute one 32-bit fetch). the steps are shown in figure 6 . 1 the prom_addr is loaded into the network processor internal shift register. 2 the prom_addr is shifted into the external shift register for 22 spclk cycles. 3 spld is asserted for one spclk cycle, loading the prom_addr into the external presentation register. 4 spld is deasserted for 22 spclk cycles. the prom presents the first 16bit prom_data. at the same time, the next prom_addr is shifted into the external shift register. 5 spld is asserted for one spclk cycle, loading the prom_addr into the external presentation register and the first prom_data into the external shift register. 6 spld is deasserted for 22 spclk cycles, shifting the first prom_data into the network processor internal shift register. 7 spld is asserted for one spclk cycle, loading the first prom_data into the network processor prom_return_data register and the second prom_data into the external shift register. external logic prom_addr<21:1> 15 15 16 prom _h_word c-3e network processor prom clock gen. 31 21 21 6 1 0 prom _return_data prom sequencer 21 0 0 ce spclk spld spdo spdi internal shift register prom_addr<21:1> ce prom _lo_word 21 6 0 21 0 21 1 prom prom_data 16 external shift register pin descriptions grouped by function 47 motorola general business information c3enpa1-ds/d rev 03 8 spld is deasserted for 22 spclk cycles, shifting the second prom_data into the network processor internal shift register. 9 spld is asserted for one spclk cycle, loading the second prom_data into the network processor prom_return_data register. figure 6 prom interface timing outline spclk spld 12 456789 11 10 12 13 14 15 16 17 18 19 20 21 22 23 1234567891011 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 19 21 22 23 1 2 3 4 5 6 7 x a 20 a 19 a 18 spdto a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ce the prom_addr is loaded into the c-5's internal shift register. the prom_addr is shifted into the external shift register. (spclk rising edge used for shifting) the prom_addr is loaded into the external presentation register. the prom_data is presenting. the prom_data is loaded into the external shift register. the prom_data is shifted into the c-5's internal shift register. the prom_data is loaded into the c-5's internal prom_return_data register. spdti x d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xxxxxx xp prom interface outline xp prom interface detail spld spdto spdti ?` ?` a1 a2 ?` ?` a3 a4 a5 d1 d2 d3 d1 d2 a1 a2 a3 a4 1 2 3 4 5 6 7 8 9 48 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information general system interface signal table 18 provides the signal for the executive processor reset power status and i/o clock. the c-3e np can be powered up with the xp either running or with the xp in reset mode similar to the cps. when the xp remains in reset mode, an external host can be used to control the initialization of the c-3e np. table 18 general system interface signal signal name pin # total type i/o signal description xpuhot y3 1 lvt tl i pd sample at power on reset determines if the xp risc core is held in reset. low equals reset and high equals active. during normal operation, this is an external interrupt. total pins 1 pin descriptions grouped by function 49 motorola general business information c3enpa1-ds/d rev 03 fabric processor interface signals the fp has logical signal interfaces: a receive data interface and a transmit data interface, each with its own control, data, and clock signals. the interface has the following characteristic: the interface clocks frxclk and ftxclk can have a different frequency from the core c-3e np clock frequency. the fp supports a fabric interface frequency from 10mhz to 125mhz. frxclk and ftxclk can be independent of each other; typically they have the same frequency, but are allowed to be skewed relative to each other. each data bus can be configured for widths of 8 (data bits 7:0 are used), or 16 (bits 15:0). in 8bit mode, data bits 15:8 are unused. the following tables list the fabric interface pin mappings: utopia1, utopia2, utopia3 atm mode mappings are listed in table 20 utopia1, utopia2, utopia3 phy mode mappings are listed in table 21 table 19 fabric interface signals signal name pin # total type i/o signal description fin0 - fin15 ad13, ac13, ab13, ag12, af12, ae12, ad12, ac12, ab12, ag11, af11, ae11, ad11, ac11, ab11, ag10 16 lvt tl i pd fabric data bus in fout0 - fout15 ag17, af17, ag16, af16, ae16, ad16, ac16, ab16, ag15, af15, ae15, ad15, ac15, ab15, ag14, ae14 16 lvt tl o fabric data bus out frxclk ag9 1 lvt tl i pd receive clock ftxclk ae13 1 lvt tl i pd transmit clock frxctl0 - frxctl2 & frxctl6 ae10, ad10, ac10, ab10 4 lvt tl i pd , o receive control signals ftxctl0 - frxctl2 & ftxctl6 ac14, ab14, ag13, af13 4 lvt tl i pd , o transmit control signals total pins 42 50 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information when configuring two c-3e network processors back-to-back using the fabric port, set up the transmit side of each c-3e network processor in utopia atm mode and the receive side of each c-3e network processor in utopia phy mode. table 20 utopia1*, 2*, 3 atm mode, c-3e network processor to fabric interface pin mapping receive signals transmit signals c-3e network processor i/o utopia note c-3e network processor i/o utopia note frxctl0 output rxenb* pullup or no connection ftxctl0 output txenb* pullup or no connection frxctl1 input rxclav ftxctl1 input txclav frxctl2 input rxsoc ftxctl2 output txsoc frxctl6 input rxprty ftxctl6 output txprty * cell size must be 4byte aligned. both rxenb and txenb are active low. table 21 utopia1*, 2*, 3 phy mode, c-3e network processor to fabric interface pin mapping receive signals transmit signals c-3e network processor i/o utopia note c-3e network processor i/o utopia note frxctl0 input txenb* pullup ftxctl0 input rxenb* pullup frxctl1 output txclav no connection ftxctl1 output rxclav no connection frxctl2 input txsoc ftxctl2 output rxsoc frxctl6 input txprty ftxctl6 output rxprty * cell size must be 4byte aligned. both txenb and rxenb are active low. pin descriptions grouped by function 51 motorola general business information c3enpa1-ds/d rev 03 bmu sdram interface signals the bmu and sdram interface signals are described in table 22 . the bmu is designed to support sdram devices with 12 address lines. all 139 data lines and all 12 address lines must be connected to the sdram in order for the bmu to be able to read and write external sdram properly. table 22 bmu sdram interface signals signal name pin # total type i/o signal description md0 - md129 aa27, aa25, aa24, aa23, aa21, aa20, y27, y26, y25, y23, y22, y21, y20, w27, w26, w25, w23, w22, w21, w20, v27, v25, v24, v23, v21, v20, u27, u26, u25, u24, u23, u22, u21, u20, t27, t26, t25, t23, t22, t21, t20, r27, r26, r25, r24, r23, r22, r21, r20, p27, p25, p24, p23, p21, p20, n27, n26, n25, n24, n23, n22, n21, n20, m27, m26, m25, m23, m22, m21, m20, l27, l26, l25, l24, l23, l22, l21, l20, k27, k25, k24, k23, k21, k20, j27, j26, j25, j23, j22, j21, j20, h27, h26, h25, h23, h22, h21, h20, g27, g25, g24, g23, g21, g20, f27, f26, f25, f24, f23, f22, f21, f20, e27, e26, e25, e23, e22, e21, e20, d27, d25, d24, d23, d21, d20, c27, c26, c25, c23, c22 130 lvt tl i pd /o data lines in mdecc0 - mdecc8 a27, b20, b21, b23, b24, b25, b27, c20, c21 9 lvt tl i pd /o stored as data, ecc bits ma0 - ma11 c19, b19, a19, f18, e18, d18, c18, a18, f17, e17, d17, c17 12 lvt tl o pd address outputs: a0-a11 are sampled during the active command and read/write to select one location out of the memory array in the respective bank. the address inputs also provide the op-code during a load mode register command mba0 - mba1 f19, e19 2 lvt tl o pd bank address outputs: ba0 and ba1 define which bank the active, read, write or precharge command is being applied mcasx a24 1 lvt tl o pd command outputs: mrasx, mcasx, mwex and mcsx define the command being entered. note: mcsx is considered part of the command code. 52 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information mrasx a23 1 lvt tl o pd command outputs: mrasx, mcasx, mwex and mcsx define the command being entered. mcsx is considered part of the command code. mwex a22 1 lvt tl o pd command outputs: mrasx, mcasx, mwex and mcsx define the command being entered. mcsx is considered part of the command code. mcsx a25 1 lvt tl o pd chip select: mcsx enables (registered low) and disables (registered high) the command decoder. all commands are masked when mcsx is registered high. mcsx provides the external bank selection on systems with multiple banks. mcsx is considered part of the command code. mdqm mdqml a20 a21 1 1 lvt tl lvt tl o pd o pd input/output mask: mdqm is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked when mdqm is sampled high during a write cycle. the output buffers are placed in a high z state (two-clock latency) when mdqm is sampled high during the read cycle. note: mdqml is an identical copy of mdqm used to drive the loading on sdram configurations with 2 dqm pins. mdclk a26 1 lvt tl i pd clock: mdclk is driven by the system clock. all sdram input signals are sampled on the positive edge of the mdclk. mdclk also increments the internal burst counter and controls the output registers. total pins 160 table 22 bmu sdram interface signals (continued) signal name pin # total type i/o signal description pin descriptions grouped by function 53 motorola general business information c3enpa1-ds/d rev 03 tlu sram interface signals the tlu sram interface supports up to 128mbytes of sram at frequencies to 125mhz using lvttl signaling levels (in single bank-mode only) and sram technologies up to 64mbits. the tlu sram interface signals are described in table 23 . table 23 tlu sram interface signals signal name pin # total type i/o signal description td0 - td63 f3, f4, f5, f6, f7, f8, g1, g3, g4, g5, g7, g8, h1, h2, h3, h5, h6, h7, h8, j1, j2, j3, j5, j6, j7, j8, k1, k3, k4, k5, k7, k8, l1, l2, l3, l4, l5, l6, l7, l8, m1, m2, m3, m5, m6, m7, m8, n1, n2, n3, n4, n5, n6, n7, n8, p1, p3, p4, p5, p7, p8, r1, r2, r3 64 lvt tl i pd /o tlu memory data ta0 - ta21 u2, u3, u4, u5, u6, u7, u8, v1, v3, v4, v5, v7, v8, w1, w2, w3, w5, w6, w7, w8, y1, y2 22 lvt tl o pd tlu memory address tpar0 - tpar3 t1, t2, t3, t5 4 lvt tl i pd /o word data parity (i.e. tpar0 across td15:0) tce0x - tce3x t6, t7, t8, u1 4 lvt tl o pd tlu memory chip enable twe0x - twe3x r5, r6, r7, r8 4 lvt tl o pd tlu memory write enable tclki r4 1 lvt tl i pd tlu clock input total pins 99 54 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information qmu sram (internal mode) interface signals the qmu signals are described in table 24 . table 24 qmu sram (internal mode) interface signals signal name pin # total type i/o signal description qa0 - qa16 d10, c10, a10, f11, e11, d11, c11, b11, a11, f12, e12, d12, c12, a12, f13, e13, d13 17 lvt tl o address [16:0] qd0 - qd31 f1, e1, d1, c1, b1, f2, e2, c2, a2, e3, d3, c3, b3, a3, d4, b4, a4, e5, d5, c5, b5, a5, e6, c6, a6, e7, d7, c7, b7, a7, e8, d8 32 lvt tl i pd /o data qdqpar c8 1 lvt tl i pd nc qardy f10 1 lvt tl i pd nc qnqrdy a9 1 lvt tl i pd nc qwex e10 1 lvt tl o write enable qbclko b8 1 lvt tl o nc qbclki a8 1 lvt tl i pd nc qaclko f9 1 lvt tl o nc qaclki e9 1 lvt tl i pd input clock qdpl c9 1 lvt tl i pd /o data parity low qdph b9 1 lvt tl i pd /o data parity high total pins 59 pin descriptions grouped by function 55 motorola general business information c3enpa1-ds/d rev 03 qmu to q-5/q-3 (external mode) interface signals the qmu to q-5/q-3 signals are described in table 25 . table 25 qmu to q-5/q-3 (external mode) interface signals signal name pin # total type i/o signal description qa0 - qa15 d10, c10, a10, f11, e11, d11, c11, b11, a11, f12, e12, d12, c12, a12, f13, e13 16 lvt tl o enqueue data [8:23] qa16 d13 1 lvt tl o enqueue parity qd0 - qd23 f1, e1, d1, c1, b1, f2, e2, c2, a2, e3, d3, c3, b3, a3, d4, b4, a4, e5, d5, c5, b5, a5, e6, c6 24 lvt tl i pd dequeue data [0:23] qd24 - qd31 a6, e7, d7, c7, b7, a7, e8, d8 8 lvt tl i pd enqueue data [0:7] qdqpar c8 1 lvt tl i pd dequeue parity qardy f10 1 lvt tl i pd dequeue ack ready qnqrdy a9 1 lvt tl o enqueue ready qwex e10 1 lvt tl o dequeue ready qbclko b8 1 lvt tl o output clockb qbclki a8 1 lvt tl i pd input clockb qaclko f9 1 lvt tl o output clocka qaclki e9 1 lvt tl i pd input clocka qdpl c9 1 lvt tl o dequeue ack [0] qdph b9 1 lvt tl o dequeue ack [1] total pins 59 56 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information power supply signals power supply, and ground signals are described in table 26 . table 26 power supply signals signal name pin # total type signal description vdd h10, h12, h16, j11, j13, j15, j17, k10, k12, k14, k16, k18, l11, l13, l15, l17, m10, m12, m14, m16, m18, n11, n13, n15, n17, p10, p12, p14, p16, p18, r11, r13, r15, r17, t10, t12, t14, t16, t18, u11, u13, u15, u17, v10, v12, v14, v16, v18, w11, w13, w15, w17, y10, y12, y14, y16, y18 57 p core supply voltage (1.1v input) vdd33 b18, b26, c24, d14, d22, g13, g15, g17, g19, g26, h14, h18, h24, j19, k22, l19, m24, n19, p26, r19, u19, v22, w19, w24, aa9, aa11, aa13, aa15, aa17, aa19, aa26, ad6, ad14, ad22, ae4, ae24, af2, af10, af18, af26 40 p i/o supply voltage (3.3v input) gnd b6, b12, b16, b22, d2, d9, d19, d26, e4, e24, g6, g10, g12, g14, g16, g18, g22, h9, h11, h13, h15, h17, h19, j4, j10, j12, j14, j16, j18, j24, k2, k9, k11, k13, k15, k17, k19, k26, l10, l12, l14, l16, l18, m9, m11, m13, m15, m17, m19, n10, n12, n14, n16, n18, p6, p9, p11, p13, p15, p17, p19, p22, r10, r12, r14, r16, r18, t4, t9, t11, t13, t15, t17, t19, t24, u10, u12, u14, u16, u18, v2, v9, v11, v13, v15, v17, v19, v26, w10, w12, w14, w16, w18, y4, y9, y11, y13, y15, y17, y19, y24, aa6, aa10, aa12, aa14, aa16, aa18, aa22, ac4, ac24, ad2, ad9, ad19, ad26, af6, af14, af22 117 p ground vddt b2, b10, c4, d6, g2, g9, g11, h4, j9, k6, l9, m4, n9, p2, r9, u9, v6, w4, w9, aa2 20 p tlu and qmu i/o supply (3.3v) total pins 234 pin descriptions grouped by function 57 motorola general business information c3enpa1-ds/d rev 03 test signals test signals are described in table 27 . during jtag, sclk and sclkx must remain as differential inputs. table 27 miscellaneous test signals for jtag, scan, and internal test routines signal name pin # total type i/o signal description jtck b17 1 lvt tl i pd test clock jtms a17 1 lvt tl i pd test mode select. high selects modes as defined in the ieee 1149.1 jtag specification. jtrstx a16 1 lvt tl i pd test reset (low active) jtdi c16 1 lvt tl i pd test data in jtdo c14 1 lvt tl o test data out jhighz b15 1 lvt tl i pd turns off all output drivers when high jclkbyp a15 1 lvt tl i pd 1x or 2x clock mode select. low selects 1x, high selects 2x. jse d15 1 lvt tl i pd scan enable. high enables scan test. js00-js05 c13, b13, a13, b14, a14, c15 6 lvt tl o scan out pins total pins 14 58 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information signals grouped by pin number the c-3e np signals are listed by pin number in table 28 . table 28 signals listed by pin number pin function pin function pin function pin function a 1-27 a1 not present a9 qnqrdy a17 jtms a25 mcsx a2 qd8 a10 qa2 a18 ma7 a26 mdclk a3 qd13 a11 qa8 a19 ma2 a27 mdecc0 a4 qd16 a12 qa13 a20 mdqm a5 qd21 a13 js02 a21 mdqml a6 qd24 a14 js04 a22 mwex a7 qd29 a15 jclkbyp a23 mrasx a8 qbclki a16 jtrstx a24 mcasx b 1-27 b1 qd4 b9 qdph b17 jtck b25 mdecc5 b2 vddt b10 vddt b18 vdd33 b26 vdd33 b3 qd12 b11 qa7 b19 ma1 b27 mdecc6 b4 qd15 b12 gnd b20 mdecc1 b5 qd20 b13 js01 b21 mdecc2 b6 gnd b14 js03 b22 gnd b7 qd28 b15 jhighz b23 mdecc3 b8 qbclko b16 gnd b24 mdecc4 c 1-27 c1 qd3 c9 qdpl c17 ma11 c25 md127 c2 qd7 c10 qa1 c18 ma6 c26 md126 c3 qd11 c11 qa6 c19 ma0 c27 md125 c4 vddt c12 qa12 c20 mdecc7 c5 qd19 c13 js00 c21 mdecc8 c6 qd23 c14 jtdo c22 md129 signals grouped by pin number 59 motorola general business information c3enpa1-ds/d rev 03 c7 qd27 c15 js05 c23 md128 c8 qdqpar c16 jtdi c24 vdd33 d 1-27 d1 qd2 d9 gnd d17 ma10 d25 md120 d2 gnd d10 qa0 d18 ma5 d26 gnd d3 qd10 d11 qa5 d19 gnd d27 md119 d4 qd14 d12 qa11 d20 md124 d5 qd18 d13 qa16 d21 md123 d6 vddt d14 vdd33 d22 vdd33 d7 qd26 d15 jse d23 md122 d8 qd31 d16 cpref d24 md121 e 1-27 e1 qd1 e9 qaclki e17 ma9 e25 md114 e2 qd6 e10 qwex e18 ma4 e26 md113 e3 qd9 e11 qa4 e19 mba1 e27 md112 e4 gnd e12 qa10 e20 md118 e5 qd17 e13 qa15 e21 md117 e6 qd22 e14 cclk3 e22 md116 e7 qd25 e15 cclk2 e23 md115 e8 qd30 e16 cclk1 e24 gnd f 1-27 f1 qd0 f9 qaclko f17 ma8 f25 md106 f2 qd5 f10 qardy f18 ma3 f26 md105 f3 td0 f11 qa3 f19 mba0 f27 md104 f4 td1 f12 qa9 f20 md111 f5 td2 f13 qa14 f21 md110 f6 td3 f14 sclk f22 md109 table 28 signals listed by pin number (continued) pin function pin function pin function pin function 60 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information f7 td4 f15 sclkx f23 md108 f8 td5 f16 cclk0 f24 md107 g 1-27 g1 td6 g9 vddt g17 vdd33 g25 md99 g2 vddt g10 gnd g18 gnd g26 vdd33 g3 td7 g11 vddt g19 vdd33 g27 md98 g4 td8 g12 gnd g20 md103 g5 td9 g13 vdd33 g21 md102 g6 gnd g14 gnd g22 gnd g7 td10 g15 vdd33 g23 md101 g8 td11 g16 gnd g24 md100 h 1-27 h1 td12 h9 gnd h17 gnd h25 md93 h2 td13 h10 vdd h18 vdd33 h26 md92 h3 td14 h11 gnd h19 gnd h27 md91 h4 vddt h12 vdd h20 md97 h5 td15 h13 gnd h21 md96 h6 td16 h14 vdd33 h22 md95 h7 td17 h15 gnd h23 md94 h8 td18 h16 vdd h24 vdd33 j 1-27 j1 td19 j9 vddt j17 vdd j25 md86 j2 td20 j10 gnd j18 gnd j26 md85 j3 td21 j11 vdd j19 vdd33 j27 md84 j4 gnd j12 gnd j20 md90 j5 td22 j13 vdd j21 md89 j6 td23 j14 gnd j22 md88 table 28 signals listed by pin number (continued) pin function pin function pin function pin function signals grouped by pin number 61 motorola general business information c3enpa1-ds/d rev 03 j7 td24 j15 vdd j23 md87 j8 td25 j16 gnd j24 gnd k 1-27 k1 td26 k9 gnd k17 gnd k25 md79 k2 gnd k10 vdd k18 vdd k26 gnd k3 td27 k11 gnd k19 gnd k27 md78 k4 td28 k12 vdd k20 md83 k5 td29 k13 gnd k21 md82 k6 vddt k14 vdd k22 vdd33 k7 td30 k15 gnd k23 md81 k8 td31 k16 vdd k24 md80 l 1-27 l1 td32 l9 vddt l17 vdd l25 md72 l2 td33 l10 gnd l18 gnd l26 md71 l3 td34 l11 vdd l19 vdd33 l27 md70 l4 td35 l12 gnd l20 md77 l5 td36 l13 vdd l21 md76 l6 td37 l14 gnd l22 md75 l7 td38 l15 vdd l23 md74 l8 td39 l16 gnd l24 md73 m 1-27 m1 td40 m9 gnd m17 gnd m25 md65 m2 td41 m10 vdd m18 vdd m26 md64 m3 td42 m11 gnd m19 gnd m27 md63 m4 vddt m12 vdd m20 md69 m5 td43 m13 gnd m21 md68 m6 td44 m14 vdd m22 md67 m7 td45 m15 gnd m23 md66 table 28 signals listed by pin number (continued) pin function pin function pin function pin function 62 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information m8 td46 m16 vdd m24 vdd33 n 1-27 n1 td47 n9 vddt n17 vdd n25 md57 n2 td48 n10 gnd n18 gnd n26 md56 n3 td49 n11 vdd n19 vdd33 n27 md55 n4 td50 n12 gnd n20 md62 n5 td51 n13 vdd n21 md61 n6 td52 n14 gnd n22 md60 n7 td53 n15 vdd n23 md59 n8 td54 n16 gnd n24 md58 p 1-27 p1 td55 p9 gnd p17 gnd p25 md50 p2 vddt p10 vdd p18 vdd p26 vdd33 p3 td56 p11 gnd p19 gnd p27 md49 p4 td57 p12 vdd p20 md54 p5 td58 p13 gnd p21 md53 p6 gnd p14 vdd p22 gnd p7 td59 p15 gnd p23 md52 p8 td60 p16 vdd p24 md51 r 1-27 r1 td61 r9 vddt r17 vdd r25 md43 r2 td62 r10 gnd r18 gnd r26 md42 r3 td63 r11 vdd r19 vdd33 r27 md41 r4 tclki r12 gnd r20 md48 r5 twe0x r13 vdd r21 md47 r6 twe1x r14 gnd r22 md46 r7 twe2x r15 vdd r23 md45 table 28 signals listed by pin number (continued) pin function pin function pin function pin function signals grouped by pin number 63 motorola general business information c3enpa1-ds/d rev 03 r8 twe3x r16 gnd r24 md44 t 1-27 t1 tpar0 t9 gnd t17 gnd t25 md36 t2 tpar1 t10 vdd t18 vdd t26 md35 t3 tpar2 t11 gnd t19 gnd t27 md34 t4 gnd t12 vdd t20 md40 t5 tpar3 t13 gnd t21 md39 t6 tce0x t14 vdd t22 md38 t7 tce1x t15 gnd t23 md37 t8 tce2x t16 vdd t24 gnd u 1-27 u1 tce3x u9 vddt u17 vdd u25 md28 u2 ta0 u10 gnd u18 gnd u26 md27 u3 ta1 u11 vdd u19 vdd33 u27 md26 u4 ta2 u12 gnd u20 md33 u5 ta3 u13 vdd u21 md32 u6 ta4 u14 gnd u22 md31 u7 ta5 u15 vdd u23 md30 u8 ta6 u16 gnd u24 md29 v 1-27 v1 ta7 v9 gnd v17 gnd v25 md21 v2 gnd v10 vdd v18 vdd v26 gnd v3 ta8 v11 gnd v19 gnd v27 md20 v4 ta9 v12 vdd v20 md25 v5 ta10 v13 gnd v21 md24 v6 vddt v14 vdd v22 vdd33 v7 ta11 v15 gnd v23 md23 v8 ta12 v16 vdd v24 md22 table 28 signals listed by pin number (continued) pin function pin function pin function pin function 64 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information w 1-27 w1 ta13 w9 vddt w17 vdd w25 md15 w2 ta14 w10 gnd w18 gnd w26 md14 w3 ta15 w11 vdd w19 vdd33 w27 md13 w4 vddt w12 gnd w20 md19 w5 ta16 w13 vdd w21 md18 w6 ta17 w14 gnd w22 md17 w7 ta18 w15 vdd w23 md16 w8 ta19 w16 gnd w24 vdd33 y 1-27 y1 ta20 y9 gnd y17 gnd y25 md8 y2 ta21 y10 vdd y18 vdd y26 md7 y3 xpuhot y11 gnd y19 gnd y27 md6 y4 gnd y12 vdd y20 md12 y5 spdo y13 gnd y21 md11 y6 spdi y14 vdd y22 md10 y7 spld y15 gnd y23 md9 y8 spck y16 vdd y24 gnd aa 1-27 aa1 sicl aa9 vdd33 aa17 vdd33 aa25 md1 aa2 vddt aa10 gnd aa18 gnd aa26 vdd33 aa3 pad30 aa11 vdd33 aa19 vdd33 aa27 md0 aa4 sida aa12 gnd aa20 md5 aa5 pidsel aa13 vdd33 aa21 md4 aa6 gnd aa14 gnd aa22 gnd aa7 pframex aa15 vdd33 aa23 md3 aa8 pgntx aa16 gnd aa24 md2 table 28 signals listed by pin number (continued) pin function pin function pin function pin function signals grouped by pin number 65 motorola general business information c3enpa1-ds/d rev 03 ab 1-27 ab1 ptrdyx ab9 pad0 ab17 cp7_6 ab25 cp2_1 ab2 pcbex0 ab10 frxctl6 ab18 cp7_2 ab26 cp1_2 ab3 pad31 ab11 fin14 ab19 cp6_4 ab27 cp0_5 ab4 pad26 ab12 fin8 ab20 cp5_6 ab5 pad20 ab13 fin2 ab21 cp5_0 ab6 pad16 ab14 ftxctl1 ab22 cp4_1 ab7 pad10 ab15 fout13 ab23 cp3_4 ab8 pad4 ab16 fout7 ab24 cp2_5 ac 1-27 ac1 pinta ac9 pad1 ac17 cp7_5 ac25 cp2_0 ac2 pirdyx ac10 frxctl2 ac18 cp7_1 ac26 cp1_1 ac3 pperrx ac11 fin13 ac19 cp6_3 ac27 cp0_4 ac4 gnd ac12 fin7 ac20 cp5_5 ac5 pad21 ac13 fin1 ac21 cp4_6 ac6 pad17 ac14 ftxctl0 ac22 cp4_0 ac7 pad11 ac15 fout12 ac23 cp3_3 ac8 pad5 ac16 fout6 ac24 gnd ad 1-27 ad1 preqx ad9 gnd ad17 cp7_4 ad25 cp1_6 ad2 gnd ad10 frxctl1 ad18 cp7_0 ad26 gnd ad3 pserrx ad11 fin12 ad19 gnd ad27 cp0_3 ad4 pad27 ad12 fin6 ad20 cp5_4 ad5 pad22 ad13 fin0 ad21 cp4_5 ad6 vdd33 ad14 vdd33 ad22 vdd33 ad7 pad12 ad15 fout11 ad23 cp3_2 ad8 pad6 ad16 fout5 ad24 cp2_4 table 28 signals listed by pin number (continued) pin function pin function pin function pin function 66 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information ae 1-27 ae1 prstx ae9 pad2 ae17 cp7_3 ae25 cp1_5 ae2 pstopx ae10 frxctl0 ae18 cp6_6 ae26 cp1_0 ae3 pcbex3 ae11 fin11 ae19 cp6_2 ae27 cp0_2 ae4 vdd33 ae12 fin5 ae20 cp5_3 ae5 pad23 ae13 ftxclk ae21 cp4_4 ae6 pad18 ae14 fout15 ae22 cp3_6 ae7 pad13 ae15 fout10 ae23 cp3_1 ae8 pad7 ae16 fout4 ae24 vdd33 af 1-27 af1 pclk af9 pad3 af17 fout1 af25 cp1_4 af2 vdd33 af10 vdd33 af18 vdd33 af26 vdd33 af3 pcbex2 af11 fin10 af19 cp6_1 af27 cp0_1 af4 pad28 af12 fin4 af20 cp5_2 af5 pad24 af13 ftxctl6 af21 cp4_3 af6 gnd af14 gnd af22 gnd af7 pad14 af15 fout9 af23 cp3_0 af8 pad8 af16 fout3 af24 cp2_3 ag 1-27 ag1 ppar ag9 frxclk ag17 fout0 ag25 cp1_3 ag2 pdevselx ag10 fin15 ag18 cp6_5 ag26 cp0_6 ag3 pcbex1 ag11 fin9 ag19 cp6_0 ag27 cp0_0 ag4 pad29 ag12 fin3 ag20 cp5_1 ag5 pad25 ag13 ftxctl2 ag21 cp4_2 ag6 pad19 ag14 fout14 ag22 cp3_5 ag7 pad15 ag15 fout8 ag23 cp2_6 ag8 pad9 ag16 fout2 ag24 cp2_2 table 28 signals listed by pin number (continued) pin function pin function pin function pin function jtag support 67 motorola general business information c3enpa1-ds/d rev 03 jtag support the c-3e np contains jtag test logic compliant with the ieee 1149.1 specification. all required public instructions are implemented, as well as some optional instructions. this section contains information regarding the pinout, instructions, identification codes, and boundary scan cell types. pinout the c-3e np uses the standard jtag pins including the optional test reset pin. table 27 describes the pins and their functions. jtag data registers the c-3e np contains the standard internal registers as specified in ieee 1149.1. these registers are described in table 29 . boundary scan restriction sclk/sclkx inputs must not toggle when exercising the boundary scan function for jtag. boundary scan cell types the c-3e np boundary scan register contains only two cell types. all input cells are observe only cells of type bc_4. all enable and output cells are standard cells of type bc_1. in ieee 1149.1-1990 specification, the bc_4 cell is shown in figure 7 and the bc_1 cell is shown in figure 8 . table 29 jtag internal register descriptions register name register length description bypass 1 standard jtag bypass register boundary 1549 boundary scan register device identification 32 standard jtag idcode register 68 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information figure 7 observe-only cell figure 8 cell design that can be used for both input and output pins g1 0 1 1d c1 from system pin to next cell to system logic shift dr from last cell clock dr g1 0 1 1d c1 to/from system pin to next cell from/to system shift dr from last cell clock dr 1d c1 g1 0 1 update dr node jtag support 69 motorola general business information c3enpa1-ds/d rev 03 idcode register the c-3e np implements a standard 32bit jtag identification register. table 30 lists the value of the code for full identification and its sub-components. the concatenated 32bit value is hexidecimal 0002132d. jtag instruction register the c-3e np contains a 4bit instruction register. table 31 lists the instructions that are supported. table 30 jtag identification code and its sub-components field name width bit positions binary value version 4 31-28 0000 part number 16 27-12 0000_0000_0010_0001 manufacturer identity 11 11-1 001_1001_0110 lsb 1 0 1 table 31 instruction register instructions instruction mnemonic selected register instruction opcode extest boundary scan 0000 idcode identification register 0001 sample/preload boundary scan 0010 highz bypass register 0011 clamp bypass register 0100 bypass bypass register 0101 reserved* bypass register 0110 reserved* bypass register 0111 bypass bypass register 1000 bypass bypass register 1001 bypass bypass register 1010 bypass bypass register 1011 bypass bypass register 1100 bypass bypass register 1101 70 chapter 2: signal descriptions c3enpa1-ds/d rev 03 motorola general business information boundary scan description language in order to simplify board test, motorola corporation has provided a boundary scan description language (bsdl) file (c3e.bsdl) in the motorola web site that describes the complete set of instructions, boundary scan order, and identification code value in an industry standard format. http://www.motorola.com/networkprocessors bypass bypass register 1110 bypass bypass register 1111 * there are two reserved instructions intended for motorola corporation ? s internal use. these should not be programmed by users. table 31 instruction register instructions (continued) instruction mnemonic selected register instruction opcode motorola general business information c3enpa1-ds/d rev 03 c3enpa1-ds/d rev 03 chapter 3 electrical specifications absolute maximum ratings table 32 lists the absolute maximum ratings for the c-3e network processor. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and do not imply that operation under any conditions other than those listed under ? recommended operating conditions ? ( table 33 ) is possible. exposure to conditions beyond table 32 can: reduce device reliability result in premature device failure, even with no immediate sign of failure prolonged exposure to conditions at or near the absolute maximum ratings could also result in reduced useful life and reliability of the c-3e np. table 32 c-3e network processor absolute maximum ratings parameter min max unit v dd33/vddt supply voltage (3.3v input)* * voltages are relative to ground -0.5 +5 v v dd supply voltage (1.1v input)* -0.5 +2.2 v voltage on any pin -0.5 v dd33 + 0.5 v static discharge voltage 2000/500 v storage temperature -40 +125 c absolute maximum junction temperature -40 +125 c 72 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information recommended operating conditions the recommended operating conditions describe an environment the c-3e np network processor is expected to encounter during normal operation. table 33 delineates the recommended operating parameters for the c-3e np. table 33 c-3e network processor recommended operating conditions parameter min nominal max unit v dd33 supply voltage 3.135 3.3 3.465 v v ddt supply voltage 3.135 3.3 3.465 v v dd supply voltage 1.04 1.2 1.16 v i dd33 - v dd33 supply current 0.6 a i dd - v dd supply current 5.0 a t j junction temperature -40 125 c dc characteristics 73 motorola general business information c3enpa1-ds/d rev 03 dc characteristics the dc electrical characteristics define the input operating conditions for proper operation and the output responses to applied dc signals and switch characteristics over specified voltage and temperature ranges. the dc electrical characteristics are specified within the recommended operating conditions including operating temperature and power supply range as stated in this data sheet. table 34 outlines the c-3e np dc characteristics. each control input pin has a capacitance associated with it. the capacitance at the control input is due to the package and the input circuitry connected to the pin. capacitance is based on these conditions: t a = 25 c ; v dd33 = 3.3v; f = 1mhz. table 35 provides capacitance data. table 34 c-3e network processor dc characteristics parameter* * all voltages are relative to ground unless otherwise indicated. min max unit notes lvt tl input high voltage 2.0 v dd33 +.3 v lvttl input low voltage -0.3 0.8 v lvt tl output high voltage 2.4 v @i oh = -2ma lvttl output low voltage 0.4 v @i ol = +2ma lvttl input current -100 +100 a v in = 0v or v dd33 lvpecl input high voltage v dd33 -1.165 v dd33 +.3v v lvpecl input low voltage -0.3 v dd33 -1.475 v lvpecl output high voltage v dd33 -1.025 v dd33 -0.60 v load = 50ohm to v dd33 - 2v lvpecl output low voltage v dd33 -2.20 v dd33 -1.620 v load = 50ohm to v dd33 - 2v lvpecl input current -100 +100 a cpref v dd33 -1.38 v dd33 -1.26 v single-ended lvpecl reference table 35 c-3e network processor capacitance data parameter typical unit all pins 5 pf 74 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information power sequencing it is intended that the vdd33/vddt and vdd rails are sequenced to their final value together for most applications. vdd33 and vddt must be above vdd at all times. vdd must be brought to its final value within 100ms of sequencing on vdd33 and vddt. it is also required that sclk, sclkx, tclki, pclk, mdclk, ftxclk, and frxclk be running or begin running during power sequencing to propagate reset inside the c-3e np. figure 9 indicates the relationship between the clocks and prstx. there is no requirement that the asserting and deasserting edges of prstx be synchronous to the clocks. reset must be asserted within 100 s of power initiation. typically, reset is held low during power initiation. figure 9 bringup clock timing diagram tclki, pclk, sclk, sclkx, mdclk, ftxclk, frxclk prstx 3 1ms 3 100 s ( ( ) ) 100 s vdd, vdd33, vddt power and thermal characteristics 75 motorola general business information c3enpa1-ds/d rev 03 power and thermal characteristics table 36 provides the derived power and thermal characteristics for the production version of the c-3e np. table 36 note: power dissipation values assume the following conditions: bmu memory operating at 125mhz tlu memory operating at 125mhz qmu operating at 150mhz vdd = 1.1v, vdd33/vddt = 3.3v, tj at approximately 50 c for typical values. vdd and vdd33/vddt are 5% higher for maximum values ?minimum? pd based on idle condition (clocks running and no programs executing) ? typical ? pd based on test application that implements fast ethernet forwarding actively running on all cps ? maximum ? pd based on maximum consumption for any high-bandwidth communications application executing on all cps, fp, and xp thermal management information this section provides thermal management information for the ceramic ball grid array (cbga) package for air-cooled applications. proper thermal control design is primarily dependent on the system-level design ? the heat sink, airflow, and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods ? spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (refer to figure 10 ); however, due to the potential table 36 c-3e network processor power and thermal characteristics parameter min typ max units test conditions power dissipation, p d 2.5 5.5 7.5 w 180mhz core clock see note below maximum junction temperature, t j 125 o c see note below thermal resistance, junction to case, jc <0.1 o c/w see note below thermal resistance, junction to printed circuit board, jb 5.5 o c/w see note below 76 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information large mass of the heat sink, attachment through the printed circuit board is suggested. if a spring clip is used, the spring force should not exceed 5.5 pounds. figure 10 package cross section view with serveral heat sink options internal package conduction resistance for the exposed-die packaging technology the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case (or top-of-die for exposed silicon) thermal resistance the die junction-to-ball thermal resistance figure 11 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. cbga package heat sink heat sink clip thermal interface material printed circuit board power and thermal characteristics 77 motorola general business information c3enpa1-ds/d rev 03 figure 11 package with heat sink mounted to the printed circuit board heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by convection. because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. thus, the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms. heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t a + t r + ( jc + int + sa ) x p d where: t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet external resistance internal resistance external resistance radiation heat sink printed circuit board (pcb) radiation convection thermal interface material die/package die junction package/leads convection 78 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation, the die-junction temperatures (t j ) should be maintained less than the value specified in table 36 . the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the thermal interface material ( int ) is typically about 1.5 c/w. for example, assuming a t a of 30 c, a t r of 5 c, a cbga package jc = 0.1, and a maximum power consumption (p d ) of 7.5 w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.1 c/w + 1.5 c/w + sa ) x 7.5 w for this example, a sa value of 10.4 c/w or less is required to maintain the die junction temperature below the maximum value of table 36 . though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. the final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the final operating die-junction temperature ? airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs. ac timing specifications 79 motorola general business information c3enpa1-ds/d rev 03 ac timing specifications ac timing specifications consist of input requirements and output responses. the input requirements include setup and hold times, pulse widths, and high and low times. the output responses include delays from clock to signal. the ac timing specifications are defined separately for each interface to the c-3e np. see figure 12 . output timing specifications for lvttl pins are given with a 20pf load on the output. other loads can be simulated with the ibis model available from motorola. the lvpecl driver is specified into a 50 ? load terminated to a (vdd33 - 2v) reference. figure 12 test loading conditions + 2v lvttl lvpecl dut dut 20pf 50 ? vdd33 80 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information clock timing specifications the system clock timing is shown in figure 13 and described in table 37 . figure 13 system clock timing diagram t sc t sh sclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 sclkx cclkn t ccn t sl t cch t ccl table 37 system clock timing description symbol parameter min typ max unit comment tsc system cycle time 3.76 ns 180mhz core clock tsh sys clk high pulse 45 55 duty cycle* * pulse duty cycle measured at crossing voltage of sclk/sclkx tsl sys clk low pulse 45 55 duty cycle* tcc0 cclk0 cycle time 6.43 ns ? ? the frequencies specified for cclk0 - cclk3 allow full flexibility for the c-3e np. it is also possible to use one or more cclk n inputs for other frequencies; contact your motorola representative for more information. tcc1 cclk1 cycle time 6.43 ns ? tcc2 cclk2 cycle time 6.43 ns ? tcc3 cclk3 cycle time 6.43 ns ? tcch cclkm high time 40% 60% % cycle pulse is high tccl cclkm low time 40% 60% % cycle pulse is low ac timing specifications 81 motorola general business information c3enpa1-ds/d rev 03 cp timing specifications this section describes the timing for the following cp interfaces: ds1/ds3 10/100 ethernet gigabit ethernet oc-3 oc-12 ds1/ds3 timing specifications the ds1/ds3 interface timing is shown in figure 14 and described in table 38 . figure 14 ds1/ds3 ethernet timing diagram cpn_0 (tclk) cycle 1 cycle 2 cycle 2 cycle 3 cycle 3 cycle 4 cycle 4 cycle 5 cycle 5 cpn_2/3 (tx) cpn_1 (rclk) cpn_4/5 (rx) t cdt t cdo t cdr t cds t cdh table 38 ds1/ds3 ethernet timing description symbol parameter min typ max unit tcdt ds1/ds3 transmit cycle time 647/22.4 ns tcdo ds1/ds3 output time 3.0/3.0 400/15.0 ns tcdr ds1/ds3 receive cycle time 647/22.4 ns 82 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information 10/100 ethernet timing specifications the 10/100 ethernet interface timing is shown in figure 15 and described in table 39 . figure 15 10/100 ethernet timing diagram tcds ds1/ds3 setup time 2.0 ns tcdh ds1/ds3 hold time 0 ns table 38 ds1/ds3 ethernet timing description (continued) symbol parameter min typ max unit cpn_0 (tclk) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn_2/3/6 (tx) cpn_1/4/5 (rx) t cet t ceo t ces t ceh table 39 10/100 ethernet timing description symbol parameter min typ max unit tcet transmit cycle time* * std/fast ethernet 20 ns tceo output time 3.0 15.0 ns tces setup time 2.0 ns tceh hold time 0 ns ac timing specifications 83 motorola general business information c3enpa1-ds/d rev 03 gigabit gmii ethernet, tbi and mii interface timing specifications the gigabit gmii ethernet interface timing is shown in figure 16 and described in table 40 . the tbi interface timing is shown in figure 16 and described in table 41 . figure 16 gigabit ethernet and tbi interface timing diagram mii cpn_1 (tclki) cycle 1 cycle 2 cycle 3 mii cpn_2-6 (tx) t cmt t cmo mii tx cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn+2_1 (rclk) t cgr t cgs t cgh gmii/mii rx cpn+2_2-6 (rx) cpn+3_1-6 (rx) cpn_0 (tclk) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 t cgt t cgo gmii / tbi tx cpn_2-6 (tx) cpn+1_2-6 (tx) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 t ctr t ctd t cts t cth tbi rx cpn+2_1 (rclk) cpn+3_1 (rclkn) cpn+2_2-6 (rx) cpn+3_2-6 (rx) 84 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information table 40 gigabit gmii/mii ethernet interface timing description symbol gigabit parameter min typ max unit comment tcgt transmit cycle time, gmii 8.0 ns tcgo output time, gmii 3.0 6.0 ns tcgr receive cycle time 8.0 ns tcgs setup time 2.0 ns tcgh hold time 0.0 ns tcmt transmit cycle time, mii 40/400 ns 100baset/10baset tcmo output time, mii 2 12 ns table 41 gigabit tbi interface timing description symbol tbi parameter min typ max tol unit tctt transmit cycle time 8.0 ns tcto output time 3.0 6.0* * for fibre channel applications this value is 7.0ns for a transmit cycle time of 9.4ns. ns tctr receive cycle time 16.0 ns tctd rclk/rclkn deviation 1.0 ns tcts setup time 2.0 ns tcth hold time 0.0 ns ac timing specifications 85 motorola general business information c3enpa1-ds/d rev 03 oc-3 timing specifications the oc-3 interface timing is shown in figure 17 and described in table 42 . figure 17 oc-3 timing diagram cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn_2 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn_3 cpn_0 cpn_1 cpn_4 cpn_5 t c3t t c3r t c3d t c3i t c3s t c3h t c3s t c3h table 42 oc-3 timing description symbol parameter min typ max unit tc3t oc-3 transmit cycle time 6.43 ns tc3i oc-3 pulse width 2.0 ns tc3r oc-3 receive cycle time* * 155.52mhz 6.0 ns tc3d oc-3 clock duty cycle 40 60 % tc3s oc-3 setup time 2.0 ns tc3h oc-3 hold time 0.0 ns 86 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information oc-12 timing specifications the oc-12 interface timing is shown in figure 18 and described in table 43 . figure 18 oc-12 timing diagram cpn_1 (tclki) cycle 1 cycle 1 cycle 2 cycle 3 cycle 3 cycle 4 cycle 5 cpn_0 (tclk) cpn+1_2-5 (tx) cpn_1 (rclk) cpn+2_2-6 (rx) cpn+3_2-5 (rx) t c12i t c12t t c12r t c12o t c12s t c12h cycle 2 t c12d table 43 oc-12 timing description symbol parameter min typ max unit tc12i oc-12 transmit cycle time* * input from phy 12.86 ns tc12d oc-3 clock duty cycle 40 60 % tc12t oc-12 transmit cycle time ? ? output from c-3e np 12.86 ns tc12o oc-12 output time ? ? aligned to tclk 3.0 10.0 ns tc12r oc-12 receive cycle time 12.0 12.86 ns tc12s oc-12 setup time 2.0 ns tc12h oc-12 hold time 0.0 ns ac timing specifications 87 motorola general business information c3enpa1-ds/d rev 03 executive processor timing specifications the xp timing specifications include: pci timing specifications mdio serial interface timing specifications low speed serial interface timing specifications prom interface timing specifications pci timing specifications the pci timing is shown in figure 19 and described in table 44 . figure 19 pci timing diagram pclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 pad/p_ctl (output) pad/p_ctl (input) pgntx (input) pidsel (input) t pc t pao t pav t paz t pas t pah t pgs t pgh t pis t pih 88 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information table 44 pci timing description symbol parameter min typ max unit tpc pci cycle time* * 66mhz pci 15.0 ns tpas pad/p_c tl ? setup ? p_ctl includes all pci control parameters including: ppar, pframex, ptrdyx, pirdyx, pstopx, pdevselx, pperrx, pserrx 3.0 ns tpah pad/p_ctl hold 0.0 ns tpao pad/p_c tl output 2.0 6.0 ns tpaz pad/p_c tl clk to tri ? ? not fully tested, values based on design/characterization. 2.0 6.0 ns tpav pad/p_ctl clk to driven ? 2.0 6.0 ns tpgs pgntx setup 5.1 ns tpgh pgntx hold 0.0 ns tpis pidsel setup 3.0 ns tpih pidsel hold 0.0 ns prstx** ** asynchronous ns pinta** ns ac timing specifications 89 motorola general business information c3enpa1-ds/d rev 03 mdio serial interface timing specifications the mdio serial interface timing is shown in figure 20 and described in table 45 . figure 20 mdio serial interface timing diagram cycle 2 cycle 3 cycle 4 t sic t sids sicl sida (output) sida (input) t sods t sodh table 45 mdio serial interface timing description symbol parameter min typ max unit tsic sicl cycle time 40 ns tsids sida input setup 10 ns tsidh sida input hold 0.0 ns tsods sida output setup 10 ns tsodh sida output hold 10 ns 90 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information low speed serial interface timing specifications the low speed serial interface timing is shown in figure 21 and described in table 46 . figure 21 low speed serial interface timing diagram cycle 2 cycle 3 t slc t slss t slhd t slsd t slhs sicl sida t slst t slb table 46 low speed serial interface timing description symbol parameter min max unit tslc sicl cycle time 2500 ns tslss set-up time for repeated start condition 600 ns tslhs hold time start condition 600 ns tslsd data set-up time 250 ns tslhd data hold time 0.0 ns tslst set-up time for stop condition 600 ns tslb bus free time between a stop and start condition 1250 ns cmax capacitive load for each line of the bus 400 pf ac timing specifications 91 motorola general business information c3enpa1-ds/d rev 03 prom interface timing specifications the prom interface timing is shown in figure 22 and described in table 47 . figure 22 prom interface timing diagram spck cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 spdi spld spdo t spc t splo t spis t spih t spdo table 47 prom interface timing description symbol parameter min typ max unit tspc spck cycle time 40.0 ns tspis spdi setup 10.0 ns tspih spdi hold 0.0 ns tsplo spld output tsc tsc + 3.0 ns tspdo spdo output tsc tsc + 3.0 ns 92 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information fabric processor timing specifications the fp timing specifications are shown in figure 23 and described in table 48 . figure 23 fabric processor timing diagram frxclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 frxctl (output) frxctl (input) finn t frc t frco t frcv t frcz t frcs t frch t frds t frdh t ftcs t ftch ftxclk ftxctl (output) ftxctl (input) foutn t ftc t ftco t ftcv t ftcz t ftdo ac timing specifications 93 motorola general business information c3enpa1-ds/d rev 03 table 48 fabric processor timing description symbol parameter min typ max unit comment tfrc frx cycle time 8.0 ns tfrcs frxctl setup 4.0 1.5 ns utopia2 mode all other modes tfrch frxctl hold 0.0 ns tfrco frxctl output 1.0 4.0 ns tfrcz frxctl clk to tri* * not fully tested, values based on design/characterization. 1.0 4.0 ns tfrcv frxctl clk to driven* 1.0 4.0 ns tfrds fin setup 4.0 1.5 ns utopia2 mode all other modes tfrdh fin hold 0.0 ns tftc ftx cycle time 8.0 ns tftcs ftxctl setup 4.0 1.5 ns utopia2 mode all other modes tftch ftxctl hold 0.0 ns tftco ftxctl output 1.0 4.0 ns tftcz ftxctl clk to tri* 1.0 4.0 ns tftcv ftxctl tri to driven* 1.0 4.0 ns tftdo fout output 1.0 4.0 ns 94 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information bmu timing specifications the bmu timing specifications are shown in figure 24 and described in table 49 . the bmu synchronous dram interface is pc100-compliant and designed to work with industry standard sdram components with 12 or fewer address lines. the information below is intended to provide the output, setup, and hold data required to design this interface without duplicating the transaction waveform diagrams in sdram data sheets. figure 24 bmu timing diagram mdclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 m_ctl man mdn (output) mdn (input) t mc t mdo t mco t mao t mdv t mds t mdz t mdh table 49 bmu timing description symbol parameter min typ max unit tmc bmu cycle time 8.0 ns tmco bmu ctrl output 0.8 3.9 ns tmao bmu addr output 0.8 3.9 ns tmds bmu data setup 0.5 ns tmdh bmu data hold 1.1 ns tmdo bmu data output 0.8 4.5 ns tmdz bmu data clk to tri* * not fully tested, values based on design/characterization. 0.8 4.5 ns tmdv bmu data clk to driven* 0.8 4.5 ns ac timing specifications 95 motorola general business information c3enpa1-ds/d rev 03 table 50 signal groups in bmu timing diagrams signal group included signals control (m_ctl) mba0, mba1, mcasx, mrasx, mwex, mcsx, mdqm, mdqml address (man) ma0 - ma11 data (mdn) md0 - md129, mdecc0 - mdecc8 96 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information tlu timing specifications the tlu timing specifications are shown in figure 25 and described in table 51 . figure 25 tlu timing diagram tclki cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 t_ctl tan tdn (output) tdn (input) t tc t tdo t tco t tao t tdv t tds t tdz t tdh table 51 tlu timing description symbol parameter min typ max unit ttc tlu cycle time 8.0 ns ttco tlu ctrl output 0.8 3.9 ns ttao tlu addr output 0.8 3.9 ns ttds tlu data setup 1.0 ns ttdh tlu data hold 1.2 ns ttdo tlu data output 0.8 4.2 ns ttdz tlu data clk to tri* * not fully tested, values based on design/characterization. 0.8 4.2 ns ttdv tlu data clk to driven* 0.8 4.2 ns ac timing specifications 97 motorola general business information c3enpa1-ds/d rev 03 table 52 signal groups in tlu timing diagrams signal group included signals control (t_ctl) tce0x - tce3x, twe0x - twe3x address (tan) ta0 - ta21 data (tdn) td0 - td63, tpar0-3 98 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information qmu sram (internal mode) timing specifications the qmu sram (internal mode) timing specifications are shown in figure 26 and described in table 53 . figure 26 qmu sram (internal mode) timing diagram qaclki cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 q_ctl qan qdn (output) qdn (input) t qc t qdo t qco t qao t qdv t qds t qdz t qdh table 53 qmu sram (internal mode) timing description symbol parameter min typ max unit comment tqc qmu cycle time 6.7 ns tqco qmu ctrl output 0.8 4.4 ns loading is 50 ? transmission line. tqao qmu addr output 0.8 4.4 ns loading is 50 ? transmission line. tqds qmu data setup 0.8 ns tqdh qmu data hold 0.8 ns tqdo qmu data output 0.9 4.4 ns loading is 50 ? transmission line. ac timing specifications 99 motorola general business information c3enpa1-ds/d rev 03 tqdz qmu data clk to tri* 0.9 4.4 ns tqdv qmu data clk to driven* 0.9 4.4 ns * not fully tested, values based on design/characterization. table 54 signal groups in qmu sram (internal mode) timing diagrams signal group included signals control (q_ctl) qwex address (qan) qa0-qa16 data (qdn) qd0-qd31, qdpl, qdph table 53 qmu sram (internal mode) timing description (continued) symbol parameter min typ max unit comment 100 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information qmu to q-5/q-3 (external mode) timing specifications the qmu to q-5/q-3 (external mode) timing specifications are shown in figure 27 and describded in table 55 . figure 27 qmu to q-5/q-3 (external mode) timing diagram qaclki cycle 1 cycle 2 t qes qbclki dqdata t qeh t qeh qaclko qbclko nqdata t qeomin t qeomax t qes t qep t qec t qep t qec t qep t qec t qep t qec t qeomin t qeomax ac timing specifications 101 motorola general business information c3enpa1-ds/d rev 03 table 55 qmu to q-5/q-3 (external mode) timing description symbol parameter min typ max unit comment tqec qmu external cycle time 10.0 ns qaclko/qbclko derived from qaclki/qbclki tqep qmu clka-clkb delta between rising edges 4.8 ns tqes qmu input data setup 0.6 ns tqeh qmu input data hold 0.8 ns tqeo qmu data output -.85 1.3 ns determines valid time for data from each clock rising edge table 56 signal groups in qmu to q-5/q-3 (external mode) timimg diagrams signal group included signals input clocks (qnclki) qaclki, qbclki output clocks (qnclko) qaclko, qbclko input data (dqdata) qd0-23, qardy, qdpl, qdph, qnqrdy, qdqpar output data (nqdata) qa0-16, qwex, qd24-31 102 chapter 3: electrical specifications c3enpa1-ds/d rev 03 motorola general business information motorola general business information c3enpa1-ds/d rev 03 c3enpa1-ds/d rev 03 chapter 4 mechanical specifications package views the c-3e network processor is an 728 pin (27 pins x 27 pins) ball grid array (bga) package as shown in the following illustrations. table 57 defines the package measurements. figure 28 c-3e network processor bga package side view hitce: green ceramic is thermally matched to fr4 circuit board. a seating plane a 1 a 2 a 3 a 4 104 chapter 4: mechanical specifications c3enpa1-ds/d rev 03 motorola general business information figure 29 c-3e network processor bga package (bottom view) e b e d e d 1 e 1 a g af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 package views 105 motorola general business information c3enpa1-ds/d rev 03 figure 30 c-3e network processor bga (top view) 18ars10518d001 optional capacitor pads optional capacito r pads probe pad die 1.65 1.70 0.7 106 chapter 4: mechanical specifications c3enpa1-ds/d rev 03 motorola general business information package measurements table 57 defines the c-3e np package measurements, providing nominal, minimum, and maximum sizes where appropriate. at motorola ? s discretion up to fourteen (14) capacitors may or may not be attached on the top of the package. marking codes table 58 explains the marking on the c-3e np. table 57 package measurements (reference figure 28 , figure 29 and figure 30 for symbols) symbol definition nom. (mm) min. (mm) max. (mm) a overall 3.11 2.83 3.39 a 1 ball height 0.70 0.6 0.8 a 2 c4 and die 0.86 a 3 body thickness 1.55 1.41 1.69 a 4 capacitor pad 0.6 d body size 29.00 28.80 29.20 d 1 ball footprint (x) 26.00 e body size 29.00 28.80 29.20 e 1 ball footprint (y) 26.00 e ball pitch 1.00 b ball diameter 0.70 table 58 c-3e network processor marking codes marking (explanation of codes) top logo/part#/date code bottom n/a pin 1 marking chamfered corner reflow 107 motorola general business information c3enpa1-ds/d rev 03 reflow typical reflow profile for the c-3e switch module comprises: 1 follow the guidelines recommended by your solder paste supplier. flux requirements must be met for best solderability. 2 the temperature profile should be carefully characterized to ensure uniform temperature across the board and package. solder ball voiding may be affected by ramp rates and dwell times below and above liquids. 3 a nitrogen atmosphere is not required, but will make the process more robust. it can make a difference for marginally solderable pc board pads. 4 full convection forced air furnaces work best, but ir, convection/ir, or vapor phase can be used. 108 chapter 4: mechanical specifications c3enpa1-ds/d rev 03 motorola general business information motorola general business information c3enpa1-ds/d rev 03 c3enpa1-ds/d rev 03 index symbols 10/100 ethernet (rmii) configuration 35 10/100 ethernet signals 35 10/100 ethernet timing description 82 10/100 ethernet timing diagram 82 10/100 ethernet timing specifications 82 a absolute maximum ratings 71 ac timing specifications 79 b block diagram, c-3e network processor 20 bmu sdram interface signals 51 bmu signal groups 95 bmu timing description 94 bmu timing diagram 94 bmu timing specifications 94 boundary scan cell types 67 boundary scan description language 70 bringup clock timing diagram 74 buffer management unit 24 c c-3e network processor absolute maximum ratings 71 c-3e network processor bga package, bottom view 104 c-3e network processor bga package, side view 103 c-3e network processor capacitance data 73 c-3e network processor dc characteristics 73 c3e network processor power and thermal characteristics 75 c-3e np channel processors 22 channel processor interface signals 31 channel processors 22 channel processors physical interface signals and pins grouped by clusters 33 clock and reference signals 31 clock signals 31 clock timing specifications 80 configuration 10/100 ethernet (rmii) 35 ds1/t1 framer interface 34 fibrechannel tbi 38 gigabit ethernet 38 gigabit ethernet (gmii) 36 sonet oc-12 transceiver interface 41 sonet oc-3 transceiver interface 40 configurations gmii/tbi transmit and receive pin 36 cp timing specifications 81 d data registers jtag 67 dc characteristics 73 description functional 19 description language boundary scan 70 descriptions signal 27 diagram 10/100 ethernet timing 82 bmu timing 94 bringup clock timing 74 ds1/ds3 ethernet timing 81 fabric processor timing 92 gigabit ethernet (tbi) timing 83 110 index c3enpa1-ds/d rev 03 motorola general business information low speed serial interface timing 90 mdio serial interface timing 89 oc-3 timing 85 pci timing 87 pinout 28 prom interface 46 prom interface timing 91 qmu timing 98 signal groups in bmu timing 95 signal groups in qmu timing 99 signal groups in tlu timing 97 system clock timing 80 tlu timing 96 diagram, block c-3e network processor 20 ds1/ds3 ethernet timing description 81 ds1/ds3 ethernet timing diagram 81 ds1/ds3 timing specifications 81 ds1/t1 framer interface configuration 34 ds1/t1 framer interface signals 34 e electrical specifications 71 absolute maximum ratings 71 executive processor 23 pci 23 prom interface 24 serial bus interface 23 system interface signals 43 system interfaces 23 executive processor timing specifications 87 f fabric interface pin mapping utopia2/utopia3 atm mode 50 utopia2/utopia3 phy mode 50 fabric processor 24 fabric processor interface signals 49 fabric processor timing description 93 fabric processor timing diagram 92 fabric processor timing specifications 92 functional description 19 g general system interface signal 48 gigabit ethernet (gmii) configuration 36 gigabit ethernet (gmii) signals one cluster example 37 gigabit ethernet (tbi) timing description 84 , 84 gigabit ethernet (tbi) timing diagram 83 gigabit ethernet and fibrechannel tbi configuration 38 gigabit ethernet and fibrechannel tbi signals example 38 gigabit gmii ethernet, tbi and mii interface timing specification 83 gmii/tbi transmit and receive pin configurations 36 i idcode register 69 instruction register instructions 69 j jtag data registers 67 jtag identification code and its sub-components 69 jtag instruction register 69 jtag internal register descriptions 67 jtag support pinouts 67 l low speed serial interface timing description 90 low speed serial interface timing diagram 90 low speed serial interface timing specifications 90 lvpecl specifications 30 lvttl specifications 30 m mdio serial interface timing description 89 mdio serial interface timing diagram 89 mdio serial interface timing specifications 89 measurements c-3e network processor 106 mechanical specifications 103 index 111 motorola general business information c3enpa1-ds/d rev 03 miscellaneous test signals for jtag, scan, and internal test routines 57 o oc-12 signals 41 oc-12 timing description 86 oc-12 timing specifications 86 oc-3 signals 40 oc-3 timing description 85 oc-3 timing diagram 85 oc-3 timing specifications 85 operating conditions, recommended 72 p package measurements 106 pci signals 43 pci timing description 88 pci timing diagram 87 pci timing specifications 87 pin descriptions grouped by function 30 pin locations 28 pin number signals groups 58 pinout diagram 28 power sequencing 74 , 75 power supply signals 56 processor, executive 23 processor, fabric 24 prom interface diagram 46 prom interface signals 45 prom interface timing description 91 prom interface timing diagram 91 prom interface timing outline 47 prom interface timing specifications 91 q qmu signal groups 99 qmu sram (internal mode) timing diagram 98 qmu sram interface signals 54 , 55 qmu timing description 98 qmu timing specifications 98 qmu to q-5/q-3 (external mode) timing diagram 100 queue management unit 26 r recommended operating conditions 72 register idcode 69 jtag instruction 69 s serial interface signals 44 serial port signals 44 signal general system interface 48 signal descriptions 27 signal summary 27 signals 10/100 ethernet 35 bmu sdram interface 51 channel processor interface 31 clock 31 clock and reference 31 ds1/t1 framer interface 34 fabric processor interface 49 grouped by pin number 58 oc-12 41 oc-3 40 pci 43 power supply 56 prom interface 45 qmu sram interface 54 , 55 serial interface 44 serial port 44 test 57 tlu sram interface 53 sonet oc-12 transceiver interface configuration 41 sonet oc-3 transceiver interface configuration 40 specifications 10/100 ethernet timing 82 ac timing 79 bmu timing 94 clock timing 80 cp timing 81 ds1/ds3 timing 81 112 index c3enpa1-ds/d rev 03 motorola general business information electrical 71 executive processor timing 87 fabric processor timing 92 gigabit gmii ethernet, tbi and mii interface timing specification 83 low speed serial interface timing 90 mdio serial interface timing 89 mechanical 103 oc-12 timing 86 oc-3 timing 85 pci timing 87 prom interface timing 91 qmu timing 98 tlu timing 96 xp timing 87 system clock timing description 80 system clock timing diagram 80 system interfaces executive processor 23 t table lookup unit 25 test signals 57 test signals, miscellaneous, for jtag, scan, and internal test routines 57 timing outline prom interface 47 tlu signal groups 97 tlu sram interface signals 53 tlu timing description 96 tlu timing diagram 96 tlu timing specifications 96 transceiver interface configuration sonet oc-12 41 sonet oc-3 40 transmit and receive pin combinations for gigabit ethernet and fibrechannel 36 u utopia2/utopia3 atm mode, c-3e network processor to fabric interface pin mapping 50 utopia2/utopia3 phy mode, c-3e network processor to fabric interface pin mapping 50 x xp timing specifications 87 motorola, inc . c-port family of network processors 120 water street, no. andover, ma 01845 voice: (978) 773-2300 fax: (978) 773-2301 |
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