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1/25 L6235 september 2003 n operating supply voltage from 8 to 52v n 5.6a output peak current (2.8a dc) n r ds(on) 0.3 w typ. value @ t j = 25 c n operating frequency up to 100khz n non dissipative overcurrent detection and protection n diagnostic output n constant t off pwm current controller n slow decay synchr. rectification n 60 & 120 hall effect decoding logic n brake function n tacho output for speed loop n cross conduction protection n thermal shutdown n undervoltage lockout n integrated fast freeweeling diodes description the L6235 is a dmos fully integrated three-phase motor driver with overcurrent protection. realized in multipower-bcd technology, the device combines isolated dmos power transistors with cmos and bipolar circuits on the same chip. the device includes all the circuitry needed to drive a three-phase bldc motor including: a three-phase dmos bridge, a constant off time pwm current con- troller and the decoding logic for single ended hall sensors that generates the required sequence for the power stage. available in powerdip24 (20+2+2), powerso36 and so24 (20+2+2) packages, the L6235 features a non- dissipative overcurrent protection on the high side power mosfets and thermal shutdown. block diagram charge pump voltage regulator hall-effect sensors decoding logic thermal protection tacho monostable ocd1 ocd ocd ocd2 10v 5v vcp vs a gate logic vboot v boot out 1 out 2 sense a vs b out 3 sense b diag en fwd/rev brake h 3 h 1 rcpulse d99in1095b tacho rcoff h 2 ocd3 one shot monostable masking time v boot ocd1 10v v boot ocd2 10v v boot ocd3 10v sense comparator + - pwm vref ordering numbers: L6235n L6235pd L6235d powerdip24 (20+2+2) powerso36 so24 (20+2+2) dmos driver for three-phase brushless dc motor
L6235 2/25 absolute maximum ratings recommended operating condition symbol parameter test conditions value unit v s supply voltage v sa = v sb = v s 60 v v od differential voltage between: vs a , out 1 , out 2 , sense a and vs b , out 3 , sense b v sa = v sb = v s = 60v; v sensea = v senseb = gnd 60 v v boot bootstrap peak voltage v sa = v sb = v s v s + 10 v v in , v en logic inputs voltage range -0.3 to 7 v v ref voltage range at pin vref -0.3 to 7 v v rcoff voltage range at pin rcoff -0.3 to 7 v v rcpulse voltage range at pin rcpulse -0.3 to 7 v v sense voltage range at pins sense a and sense b -1 to 4 v i s(peak) pulsed supply current (for each vs a and vs b pin) v sa = v sb = v s ; t pulse < 1ms 7.1 a i s dc supply current (for each vs a and vs b pin) v sa = v sb = v s 2.8 a t stg , t op storage and operating temperature range -40 to 150 c symbol parameter test conditions min max unit v s supply voltage v sa = v sb = v s 12 52 v v od differential voltage between: vs a , out 1 , out 2 , sense a and vs b , out 3 , sense b v sa = v sb = v s ; v sensea = v senseb 52 v v ref voltage range at pin vref -0.1 5 v v sense voltage range at pins sense a and sense b (pulsed t w < t rr ) (dc) -6 -1 6 1 v v i out dc output current v sa = v sb = v s 2.8 a t j operating junction temperature -25 125 c f sw switching frequency 100 khz
3/25 L6235 thermal data pin connections (top view) (5) the slug is internally connected to pins 1, 18, 19 and 36 (gnd pins). symbol description pdip24 so24 powerso36 unit r th(j-pins) maximum thermal resistance junction-pins 18 14 c/w r th(j-case) maximum thermal resistance junction-case 1 c/w r th(j-amb)1 maximumthermal resistance junction-ambient (1) (1) mounted on a multi-layer fr4 pcb with a dissipating copper surface on the bottom side of 6 cm 2 (with a thickness of 35 m). 43 51 - c/w r th(j-amb)1 maximum thermal resistance junction-ambient (2) (2) mounted on a multi-layer fr4 pcb with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m). --35 c/w r th(j-amb)1 maximumthermal resistance junction-ambient (3) (3) mounted on a multi-layer fr4 pcb with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m), 16 via holes and a ground layer. --15 c/w r th(j-amb)2 maximum thermal resistance junction-ambient (4) (4) mounted on a multi-layer fr4 pcb without any heat-sinking surface on the board. 58 77 62 c/w gnd gnd tacho rcpulse sense b en fwd/rev 1 3 2 4 5 6 7 8 9 vref vboot brake out 3 vs b gnd gnd 19 18 17 16 15 13 14 d01in1194a 10 11 12 24 23 22 21 20 h 1 diag sense a rcoff out 1 vs a out 2 vcp h 2 h 3 gnd n.c. n.c. vs a rcoff out 1 n.c. n.c. n.c. n.c. n.c. tacho rcpulse n.c. vs b n.c. n.c. gnd 1 3 2 4 13 14 15 16 17 34 33 24 23 22 20 21 19 35 18 36 gnd gnd d01in1195a h 1 sense a diag sense b en fwd/rev 10 11 12 27 26 25 h 3 vref 9 28 out 2 h 2 vcp brake out 3 vboot 5 7 8 32 30 29 n.c. n.c. 6 31 powerso36 (5) powerdip24/so24
L6235 4/25 pin description package name type function so24/ powerdip24 powerso36 pin # pin # 110h 1 sensor input single ended hall effect sensor input 1. 2 11 diag open drain output overcurrent detection and thermal protection pin. an internal open drain transistor pulls to gnd when an overcurrent on one of the high side mosfets is detected or during thermal protection. 3 12 sense a power supply half bridge 1 and half bridge 2 source pin. this pin must be connected together with pin sense b to power ground through a sensing power resistor. 4 13 rcoff rc pin rc network pin. a parallel rc network connected between this pin and ground sets the current controller off-time. 5 15 out 1 power output output 1 6, 7, 18, 19 1, 18, 19, 36 gnd gnd ground terminals. on powerdip24 and so24 packages, these pins are also used for heat dissipation toward the pcb. on powerso36 package the slug is connected on these pins. 8 22 tacho open drain output frequency-to-voltage open drain output. every pulse from pin h 1 is shaped as a fixed and adjustable length pulse. 9 24 rcpulse rc pin rc network pin. a parallel rc network connected between this pin and ground sets the duration of the monostable pulse used for the frequency-to-voltage converter. 10 25 sense b power supply half bridge 3 source pin. this pin must be connected together with pin sense a to power ground through a sensing power resistor. at this pin also the inverting input of the sense comparator is connected. 11 26 fwd/rev logic input selects the direction of the rotation. high logic level sets forward operation, whereas low logic level sets reverse operation. if not used, it has to be connected to gnd or +5v.. 12 27 en logic input chip enable. low logic level switches off all power mosfets. if not used, it has to be connected to +5v. 13 28 vref logic input current controller reference voltage. do not leave this pin open or connect to gnd. 14 29 brake logic input brake input pin. low logic level switches on all high side power mosfets, implementing the brake function. if not used, it has to be connected to +5v. 15 30 vboot supply voltage bootstrap voltage needed for driving the upper power mosfets. 16 32 out 3 power output output 3. 17 33 vs b power supply half bridge 3 power supply voltage. it must be connected to the supply voltage together with pin vs a .
5/25 L6235 package name type function so24/ powerdip24 powerso36 pin # pin # 20 4 vs a power supply half bridge 1 and half bridge 2 power supply voltage. it must be connected to the supply voltage together with pin vs b . 21 5 out 2 power output output 2. 22 7 vcp output charge pump oscillator output. 23 8 h 2 sensor input single ended hall effect sensor input 2. 24 9 h 3 sensor input single ended hall effect sensor input 3. electrical characteristics (v s = 48v , t amb = 25 c , unless otherwise specified) symbol parameter test conditions min typ max unit v sth(on) turn on threshold 6.6 7 7.4 v v sth(off) turn off threshold 5.6 6 6.4 v i s quiescent supply current all bridges off; tj = -25 to 125c (6) 510ma t j(off) thermal shutdown temperature 165 c output dmos transistors r ds(on) high-side switch on resistance t j = 25 c 0.34 0.4 w t j =125 c (6) 0.53 0.59 w low-side switch on resistance t j = 25 c 0.28 0.34 w t j =125 c (6) 0.47 0.53 w i dss leakage current en = low; out = v cc 2ma en = low; out = gnd -0.15 ma source drain diodes v sd forward on voltage i sd = 2.8a, en = low 1.15 1.3 v t rr reverse recovery time i f = 2.8a 300 ns t fr forward recovery time 200 ns logic input (h1, h2, h3, en, fwd/rev, brake) v il low level logic input voltage -0.3 0.8 v v ih high level logic input voltage 2 7 v i il low level logic input current gnd logic input voltage -10 m a i ih high level logic input current 7v logic input voltage 10 m a v th(on) turn-on input threshold 1.8 2.0 v v th(off) turn-off input threshold 0.8 1.3 v v thhys input thresholds hysteresys 0.25 0.5 v pin description (continued)
L6235 6/25 (6) tested at 25c in a restricted range and guaranteed by characterization. (7) see fig. 1. (8) measured applying a voltage of 1v to pin sense and a voltage drop from 2v to 0v to pin vref. (9) see fig. 2. symbol parameter test conditions min typ max unit switching characteristics t d(on)en enable to out turn-on delay time (7) i load = 2.8 a, resistive load 110 250 400 ns t d(off)en enable to out turn-off delay time (7 ) i load = 2.8 a, resistive load 300 550 800 ns t d(on)in other logic inputs to output turn- on delay time i load = 2.8 a, resistive load 2 s t d(off)in other logic inputs to out turn-off delay time i load = 2.8 a, resistive load 2 s t rise output rise time (7) i load = 2.8 a, resistive load 40 250 ns t fa ll output fall time (7) i load = 2.8 a, resistive load 40 250 ns t dt dead time 0.5 1 s f cp charge pump frequency tj = -25 to 125c (6) 0.6 1 mhz pwm comparator and monostable i rcoff source current at pin rc off v rcoff = 2.5 v 3.5 5.5 ma v offset offset voltage on sense comparator v ref = 0.5 v 5 mv t prop turn off propagation delay (8) v ref = 0.5 v 500 ns t blank internal blanking time on sense comparator 1s t on(min) minimum on time 1.5 2 s t off pwm recirculationtime r off = 20k w ; c off = 1nf 13 m s r off = 100k w ; c off = 1nf 61 m s i bias input bias current at pin vref 10 a tacho monostable i rcpulse source current at pin rcpulse v rcpulse = 2.5v 3.5 5.5 ma t pulse monostable of time r pul = 20k w ; c pul = 1nf 12 m s r pul = 100k w ; c pul = 1nf 60 m s r tacho open drain on resistance 40 60 w over current detection & protection i sover supply overcurrent protection threshold t j = -25 to 125c (6) 4.0 5.6 7.1 a r opdr open drain on resistance i diag = 4ma 40 60 w i oh ocd high level leakage current v diag = 5v 1 a t ocd(on) ocd turn-on delay time (9) i diag = 4ma; c diag < 100pf 200 ns t ocd(off) ocd turn-off delay time (9) i diag = 4ma; c diag < 100pf 100 ns electrical characteristics (continued) (v s = 48v , t amb = 25 c , unless otherwise specified)
7/25 L6235 figure 1. switching characteristic definition figure 2. overcurrent detection timing definition v th(on) v th(off) 90% 10% en i out t t t fall t d(off)en t rise t d(on)en d01in1316 i sover 90% 10% i out v diag t ocd(off) t ocd(on) d02in1387 on off bridge
L6235 8/25 circuit description power stages and charge pump the L6235 integrates a three-phase bridge, which consists of 6 power mosfets connected as shown on the block diagram. each power mos has an r ds(on) = 0.3 w (typical value @25c) with intrinsic fast freewheeling diode. switching patterns are gen- erated by the pwm current controller and the hall effect sensor decoding logic (see relative para- graphs). cross conduction protection is implemented by using a dead time (t dt = 1s typical value) set by internal timing circuit between the turn off and turn on of two power mosfets in one leg of a bridge. pins vs a and vs b must be connected together to the supply voltage (v s ). using n-channel power mos for the upper transis- tors in the bridge requires a gate drive voltage above the power supply voltage. the bootstrapped supply (v boot ) is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in figure 3. the oscillator output (pin vcp) is a square wave at 600khz (typically) with 10v amplitude. recommended values/part numbers for the charge pump circuit are shown in table1. table 1. charge pump external component values. figure 3. charge pump circuit logic inputs pins fwd/rev, brake, en, h 1 , h 2 and h 3 are ttl/ cmos and c compatible logic inputs. the internal structure is shown in figure 4. typical value for turn- on and turn-off thresholds are respectively v th(on) = 1.8v and v th(off) = 1.3v. pin en (enable) may be used to implement overcurrent and thermal protection by connecting it to the open col- lector diag output if the protection and an external dis- able function are both desired, the appropriate connection must be implemented. when the external signal is from an open collector output, the circuit in fig- ure 5 can be used . for external circuits that are push pull outputs the circuit in figure 6 could be used. the re- sistor r en should be chosen in the range from 2.2k w to 180k w . recommended values for r en and c en are re- spectively 100k w and 5.6nf. more information for se- lecting the values can be found in the overcurrent protection section. figure 4. logic input internal structure figure 5. pin en open collector driving figure 6. pin en push-pull driving c boot 220nf c p 10nf r p 100 w d 1 1n4148 d 2 1n4148 d2 c boot d1 r p c p v s vs a vcp vboot vs b d01in1328 5v d01in1329 esd protection 5v 5v open collector output r en c en en diag d02in137 8 esd protection 5v push-pull output r en c en en d02in1379 diag esd protection
9/25 L6235 pwm current control the L6235 includes a constant off time pwm current controller. the current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the three lower power mos transistors and ground, as shown in figure 7. as the current in the motor increases the voltage across the sense resistor increases proportionally. when the voltage drop across the sense resistor be- comes greater than the voltage at the reference input pin vref the sense comparator triggers the monostable switching the bridge off. the power mos remain off for the time set by the monostable and the motor current recirculates around the upper half of the bridge in slow decay mode as described in the next section. when the monostable times out, the bridge will again turn on. since the internal dead time, used to prevent cross conduc- tion in the bridge, delays the turn on of the power mos, the effective off time t off is the sum of the monostable time plus the dead time. figure 8 shows the typical operating waveforms of the output current, the voltage drop across the sensing re- sistor, the pin rc voltage and the status of the bridge. more details regarding the synchronous rectification and the output stage configuration are included in the next section. immediately after the power mos turn on, a high peak current flows through the sense resistor due to the re- verse recovery of the freewheeling diodes. the L6235 provides a 1s blanking time t blank that inhibits the comparator output so that the current spike cannot prematurely retrigger the monostable. figure 7. pwm current controller simplified schematic drivers + dead time s q r drivers + dead time drivers + dead time out 3 out 2 sense b sense a r sense d02in1380 rcoff r off c off vref out 1 + + - - 1 m s 5ma blanker sense comparator monostable set 2.5v 5v from the low-side gate drivers blanking time monostable vs b vs vs a to gate logic (0) (1)
L6235 10/25 figure 8. output current regulation waveforms figure 9 shows the magnitude of the off time t off versus c off and r off values. it can be approximately cal- culated from the equations: t rcfall = 0.6 r off c off t off = t rcfall + t dt = 0.6 r off c off + t dt where r off and c off are the external component values and t dt is the internally generated dead time with: 20k w r off 100k w 0.47nf c off 100nf t dt = 1s (typical value) therefore: t off(min) = 6.6s t off(max) = 6ms these values allow a sufficient range of t off to implement the drive circuit for most motors. the capacitor value chosen for c off also affects the rise time t rcrise of the voltage at the pin rcoff. the rise time t rcrise will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. therefore, the on time t on , which depends by motors and supply parameters, has to be bigger than t rcrise for allowing a good current regulation by the pwm stage. furthermore, the on time t on can not be smaller than the minimum on time t on(min) . t rcrise = 600 c off off bc dd a t on t off bc on 2.5v 0 slow decay slow decay 1 m s t blank t rcrise t rcrise synchronous rectification 1 m s t blank 5v v rc v sense v ref i out v ref r sense d02in1351 t off 1 m s t dt 1 m s t dt t rcfall t rcfall t on t on min () > 1.5 m s (typ. value) = t on t rcrise t dt C > ? ? ?
11/25 L6235 figure 10 shows the lower limit for the on time t on for having a good pwm current regulation capacity. it has to be said that t on is always bigger than t on(min) because the device imposes this condition, but it can be smaller than t rcrise - t dt . in this last case the device continues to work but the off time t off is not more constant. so, small c off value gives more flexibility for the applications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for c off , the more influential will be the noises on the circuit performance. figure 9. t off versus c off and r off . figure 10. area where t on can vary maintaining the pwm regulation. 0.1 1 10 100 1 10 100 1 . 10 3 1 . 10 4 coff [nf] toff [ m s] r off = 100k w r off = 47k w r off = 20k w 0.1 1 10 100 1 10 100 coff [nf] ton(min) [ m s] 1.5 m s (typ. value)
L6235 12/25 slow decay mode figure 11 shows the operation of the bridge in the slow decay mode during the off time. at any time only two legs of the three-phase bridge are active, therefore only the two active legs of the bridge are shown in the figure and the third leg will be off. at the start of the off time, the lower power mos is switched off and the current recirculates around the upper half of the bridge. since the voltage across the coil is low, the current decays slow- ly. after the dead time the upper power mos is operated in the synchronous rectification mode reducing the impendence of the freewheeling diode and the related conducting losses. when the monostable times out, up- per mos that was operating the synchronous mode turns off and the lower power mos is turned on again after some delay set by the dead time to prevent cross conduction. figure 11. slow decay mode output stage configurations decoding logic the decoding logic section is a combinatory logic that provides the appropriate driving of the three-phase bridge outputs according to the signals coming from the three hall sensors that detect rotor position in a 3- phase bldc motor. this novel combinatory logic discriminates between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 electrical degrees. this decoding method allows the implementation of a uni- versal ic without dedicating pins to select the sensor configuration. there are eight possible input combinations for three sensor inputs. six combinations are valid for rotor posi- tions with 120 electrical degrees sensor phasing (see figure 12, positions 1, 2, 3a, 4, 5 and 6a) and six combi- nations are valid for rotor positions with 60 electrical degrees phasing (see figure 14, positions 1, 2, 3b, 4, 5 and 6b). four of them are in common (1, 2, 4 and 5) whereas there are two combinations used only in 120 elec- trical degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical degrees sensor phas- ing (3b and 6b). the decoder can drive motors with different sensor configuration simply by following the table 2. for any input configuration (h 1 , h 2 and h 3 ) there is one output configuration (out 1 , out 2 and out 3 ). the output configura- tion 3a is the same than 3b and analogously output configuration 6a is the same than 6b. the sequence of the hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the hall codes for 240 phasing is the reverse of 120. so, by decoding the 60 and the 120 codes it is possible to drive the motor with all the four conventions by changing the direction set. a) on time b) 1 m s dead time c) synchronous rectification d) 1 m s dead time d01in1336
13/25 L6235 table 2. 60 and 120 electrical degree decoding logic in forward direction. figure 12. 120 hall sensor sequence. figure 13. 60 hall sensor sequence. hall 120 1 2 3a - 4 5 6a - hall 60 1 2 - 3b 4 5 - 6b h 1 hh l h l lhl h 2 lh h h h lll h 3 ll l hhhhl out 1 vs high z gnd gnd gnd high z vs vs out 2 high z vs vs vs high z gnd gnd gnd out 3 gnd gnd high z high z vs vs high z high z phasing 1->3 2->3 2->1 2->1 3->1 3->2 1->2 1->2 h 1 h 2 h 2 h 2 h 2 h 2 h 3 h 3 h 3 h 3 h 3 h 1 h 1 h 1 h 1 h 3 h 2 h 1 1 2 3a 4 5 6a = h = l h 1 h 1 h 2 h 2 h 2 h 2 h 2 h 3 h 3 h 3 h 3 h 3 h 1 h 1 h 1 h 1 h 3 h 2 1 2 3b 4 5 6b = h = l
L6235 14/25 tacho a tachometer function consists of a monostable, with constant off time (t pulse ), whose input is one hall effect signal (h 1 ). it allows developing an easy speed control loop by using an external op amp, as shown in figure 14. for component values refer to application information section. the monostable output drives an open drain output pin (tacho). at each rising edge of the hall effect sensors h 1 , the monostable is triggered and the mosfet connected to pin tacho is turned off for a constant time t pulse (see figure 15). the off time t pulse can be set using the external rc network (r pul , c pul ) connected to the pin rcpulse. figure 16 gives the relation between t pulse and c pul , r pul . we have approximately: t pulse = 0.6 r pul c pul where c pul should be chosen in the range 1nf 100nf and r pul in the range 20k w 100k w . by connecting the tachometer pin to an external pull-up resistor, the output signal average value v m is propor- tional to the frequency of the hall effect signal and, therefore, to the motor speed. this realizes a simple fre- quency-to-voltage converter. an op amp, configured as an integrator, filters the signal and compares it with a reference voltage v ref , which sets the speed of the motor. figure 14. tacho operation waveforms. v m t pulse t ----------------- - v dd = t t pulse h 1 v tacho h 2 h 3 v m v dd
15/25 L6235 figure 15. tachometer speed control loop. figure 16. t pulse versus c pul and r pul . c ref2 r pul c pul r dd r 3 r 2 r 1 c 1 c ref1 vref tacho h 1 tacho monostable rcpulse v dd v ref r 4 1 10 100 10 100 1 . 10 3 1 . 10 4 cpul [nf] tpulse [ m s] r pul = 100k w r pul = 47k w r pul = 20k w
L6235 16/25 non-dissipative overcurrent detection and protection the L6235 integrates an overcurrent detection circuit (ocd) for full protection. this circuit provides output-to- output and output-to-ground short circuit protection as well. with this internal over current detection, the exter- nal current sense resistor normally used and its associated power dissipation are eliminated. figure 17 shows a simplified schematic for the overcurrent detection circuit. to implement the over current detection, a sensing element that delivers a small but precise fraction of the out- put current is implemented with each high side power mos. since this current is a small fraction of the output current there is very little additional power dissipation. this current is compared with an internal reference cur- rent i ref . when the output current reaches the detection threshold (typically i sover = 5.6a) the ocd compar- ator signals a fault condition. when a fault condition is detected, an internal open drain mos with a pull down capability of 4ma connected to pin diag is turned on. the pin diag can be used to signal the fault condition to a m c or to shut down the three-phase bridge simply by connecting it to pin en and adding an external r-c (see r en , c en ). figure 17. overcurrent protection simplified schematic figure 18 shows the overcurrent detetection operation. the disable time t disable before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. it is affected whether by c en and r en values and its magnitude is reported in figure 19. the delay time t delay before turn- ing off the bridge when an overcurrent has been detected depends only by c en value. its magnitude is reported in figure 20. c en is also used for providing immunity to pin en against fast transient noises. therefore the value of c en should be chosen as big as possible according to the maximum tolerable delay time and the r en value should be chosen according to the desired disable time. the resistor r en should be chosen in the range from 2.2k w to 180k w . recommended values for r en and c en are respectively 100k w and 5.6nf that allow obtaining 200 m s disable time. + over temperature i ref i ref i 1 +i 2 / n i 1 / n high side dmos power sense 1 cell power sense 1 cell power sense 1 cell power dmos n cells power dmos n cells power dmos n cells high side dmos high side dmos out 1 out 2 vs a out 3 vs b i 1 i 2 i 3 i 2 / n i 3 / n ocd comparator to gate logic internal open-drain r ds(on) 40 w typ. c en r en diag en v dd m c or logic d02in1381
17/25 L6235 figure 18. overcurrent protection waveforms figure 19. t disable versus c en and r en . figure 20. t delay versus c en . i sover i out v th(on) v th(off) v en(low) v dd t ocd(on) t d(on)en t en(fall) t en(rise) t disable t delay t ocd(off) t d(off)en v en =v diag bridge on off ocd on off d02in1383 1 10 100 1 10 100 1 . 10 3 c en [nf ] t disable [s] r en = 220 k w r en = 100 k w r en = 47 k w r en = 33 k w r en = 10 k w 1 10 100 1 10 100 1 . 10 3 c en [nf ] t disable [s] r en = 220 k w r en = 100 k w r en = 47 k w r en = 33 k w r en = 10 k w 1 10 100 0.1 1 10 cen [nf] tdelay [ m s]
L6235 18/25 application information a typical application using L6235 is shown in figure 21. typical component values for the application are shown in table 3. a high quality ceramic capacitor (c 2 ) in the range of 100nf to 200nf should be placed between the power pins vs a and vs b and ground near the L6235 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. the capacitor (c en ) connected from the en input to ground sets the shut down time when an over current is detected (see overcurrent protection). the two current sensing inputs (sense a and sense b ) should be connected to the sensing resistor r sense with a trace length as short as possible in the layout. the sense resistor should be non-inductive resistor to minimize the di/ dt transients across the resistor. to increase noise immunity, unused logic pins are best connected to 5v (high logic level) or gnd (low logic level) (see pin description). it is recommended to keep power ground and signal ground separated on pcb. table 3. component values for typical application. figure 21. typical application c 1 100f r 1 5k6 w c 2 100nf r 2 1k8 w c 3 220nf r 3 4k7 w c boot 220nf r 4 1m w c off 1nf r dd 1k w c pul 10nf r en 100k w c ref1 33nf r p 100 w c ref2 100nf r sense 0.3 w c en 5.6nf r off 33k w c p 10nf r pul 47k w d 1 1n4148 r h1 , r h2 , r h3 10k w d 2 1n4148 vref + - brake 14 5 18 19 21 16 out 1 h 1 h 2 h 3 gnd rcoff out 3 out 2 vs a power ground signal ground +5v + - v s 8-52v dc 13 vs b vcp vboot c p c boot r p d 2 d 1 c 1 c 2 sense a r sense 20 brake 6 7 diag en c en r en enable 2 fwd/rev fwd/rev 11 tacho 8 12 1 23 24 4 17 3 15 22 sense b three-phase motor c off r off r h1 r h2 r h3 10 c ref1 r 2 r 3 r 1 r dd r 4 c 3 c ref2 rcpulse 9 c pul r pul d02in1357 m v ref 5v hall sensor
19/25 L6235 output current capability and ic power dissipation in figure 22 is shown the approximate relation between the output current and the ic power dissipation using pwm current control. for a given output current the power dissipated by the ic can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe op- erating junction temperature (125c maximum). figure 22. ic power dissipation versus output power. thermal management in most applications the power dissipation in the ic is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. selecting the appropriate package and heatsinking con- figuration for the application is required to maintain the ic within the allowed operating temperature range for the application. figures 23, 24 and 25 show the junction-to-ambient thermal resistance values for the powerso36, powerdip24 and so24 packages. for instance, using a powerso package with copper slug soldered on a 1.5mm copper thickness fr4 board with 6cm 2 dissipating footprint (copper thickness of 35 m m), the r th(j-amb) is about 35c/w. figure 26 shows mounting methods for this package. using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15c/w. figure 23. powerso36 junction-ambient thermal resistance versus on-board copper area. no pwm f sw = 30 khz (slow decay) test conditions: supply voltage = 24 v 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 p i out [a] d [w] i out i 1 i 3 i 2 i out i out 13 18 23 28 33 38 43 12345678910111213 without ground layer with ground layer with ground layer+16 via holes sq. cm oc / w on-board copper area
L6235 20/25 figure 24. powerdip24 junction-ambient thermal resistance versus on-board copper area. figure 25. so24 junction-ambient thermal resistance versus on-board copper area. figure 26. mounting the powerso package. 39 40 41 42 43 44 45 46 47 48 49 1 2 3 4 5 6 7 8 9 101112 copper area is on bottom side copper area is on top side sq. cm oc / w on-board copper area 48 50 52 54 56 58 60 62 64 66 68 123456789101112 copper area is on top side sq. cm oc / w on-board copper area slug soldered to pcb with dissipating area slug soldered to pcb with dissipating area plus ground layer slug soldered to pcb with dissipating area plus ground layer contacted through via holes
21/25 L6235 figure 27. typical quiescent current vs. supply voltage figure 28. normalized typical quiescent current vs. switching frequency figure 29. typical low-side r ds(on) vs. supply voltage figure 30. typical high-side r ds(on) vs. supply voltage figure 31. normalized r ds(on) vs.junction temperature (typical value) figure 32. typical drain-source diode forward on characteristic 4.6 4.8 5.0 5.2 5.4 5.6 0 102030405060 iq [ma] v s [v] f sw = 1khz t j = 25c t j = 85c t j = 125c 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0 20406080100 iq / (iq @ 1 khz) f sw [khz] 0.276 0.280 0.284 0.288 0.292 0.296 0.300 0 5 10 15 20 25 30 r ds(on) [ w ] v s [v] t j = 25c 0.336 0.340 0.344 0.348 0.352 0.356 0.360 0.364 0.368 0.372 0.376 0.380 0 5 10 15 20 25 30 r ds(on) [ w ] v s [v] t j = 25c 0.8 1.0 1.2 1.4 1.6 1.8 0 20406080100120140 r ds(on) / (r ds(on) @ 25 c) tj [c] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 700 800 900 1000 1100 1200 1300 i sd [a] v sd [mv] t j = 25c
L6235 22/25 dim. mm inch min. typ. max. min. typ. max. a 3.60 0.141 a1 0.10 0.30 0.004 0.012 a2 3.30 0.130 a3 0 0.10 0 0.004 b 0.22 0.38 0.008 0.015 c 0.23 0.32 0.009 0.012 d (1) 15.80 16.00 0.622 0.630 d1 9.40 9.80 0.370 0.385 e 13.90 14.50 0.547 0.570 e 0.65 0.0256 e3 11.05 0.435 e1 (1) 10.90 11.10 0.429 0.437 e2 2.90 0.114 e3 5.80 6.20 0.228 0.244 e4 2.90 3.20 0.114 0.126 g 0 0.10 0 0.004 h 15.50 15.90 0.610 0.626 h 1.10 0.043 l 0.80 1.10 0.031 0.043 n10 (max.) s8 (max.) (1): "d" and "e1" do not include mold flash or protrusions - mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - critical dimensions are "a3", "e" and "g". powerso36 e a2 a e a1 pso36mec detail a d 118 19 36 e1 e2 h x 45? detail a lead slug a3 s gage plane 0.35 l detail b detail b (coplanarity) gc - c - seating plane e3 c n n ? m 0.12 ab b b a h e3 d1 bottom view outline and mechanical data
23/25 L6235 dim. mm inch min. typ. max. min. typ. max. a 4.320 0.170 a1 0.380 0.015 a2 3.300 0.130 b 0.410 0.460 0.510 0.016 0.018 0.020 b1 1.400 1.520 1.650 0.055 0.060 0.065 c 0.200 0.250 0.300 0.008 0.010 0.012 d 31.62 31.75 31.88 1.245 1.250 1.255 e 7.620 8.260 0.300 0.325 e 2.54 0.100 e1 6.350 6.600 6.860 0.250 0.260 0.270 e1 7.620 0.300 l 3.180 3.430 0.125 0.135 m 0? min, 15? max. powerdip 24 a1 b e b1 d 13 12 24 1 l a e1 a2 c e1 sdip24l m outline and mechanical data
L6235 24/25 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.200 c 0.23 0.32 0.009 0.013 d (1) 15.20 15.60 0.598 0.614 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.0 10.65 0.394 0.419 h 0.25 0;75 0.010 0.030 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 (1) d dimension does not include mold flash, protusions or gate burrs. mold flash, protusions or gate burrs shall not exceed 0.15mm per side. so24 0070769 c weight: 0.60gr
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