4/97 block diagram primary side voltage feed- forward control of isolated power supplies accurate dc control of secondary side short circuit current using primary side average current mode control accurate programmable maximum duty cycle clamp maximum volt-second product clamp to prevent core saturation practical operation up to 1mhz high current (2a pk) totem pole output driver wide bandwidth (8mhz) current error amplifier undervoltage lockout monitors vcc, vin and vref output active low during uvlo low startup current (500 m a) the uc3548 family of pwm control ics uses voltage feed- forward control to regulate the output voltage of isolated power supplies. the uc3548 resides on the primary side and has the necessary features to accurately control sec- ondary side short circuit current with average current mode control techniques. the uc3548 can be used to control a wide variety of converter topologies. in addition to the basic functions required for pulse width modulation, the uc3548 implements a patented technique of sensing secondary current from the primary side in an isolated buck derived converter. a current waveform syn- thesizer monitors switch current and simulates the inductor current downslope so that the complete current waveform can be constructed on the primary side without actual sec- ondary side measurement. this information on the primary side is used by an average current mode control circuit to accurately limit maximum output current. the uc3548 circuitry includes a precision reference, a wide bandwidth error amplifier for average current control, an oscillator to generate the system clock, latching pwm comparator and logic circuits, and a high current output driver. the current error amplifier easily interfaces with an optoisolator from a secondary side voltage sensing circuit. a full featured undervoltage lockout (uvlo) circuit is con- tained in the uc3548. uvlo monitors the supply voltage to the controller (vcc), the reference voltage (vref), and the input line voltage (vin). all three must be good before soft start commences. if either vcc or vin is low, the sup- ply current required by the chip is only 500 m a and the output is actively held low. two on board protection features set controlled limits to prevent transformer core saturation. input voltage is moni- tored and pulse width is constrained to limit the maximum volt-second product applied to the transformer. a unique patented technique limits maximum duty cycle within 3% of a user programmed value. these two features allow for more optimal use of trans- formers and switches, resulting in reduced system size and cost. both patents embodied in the uc3548 belong to lambda electronics incorporated and are licensed for use in appli- cations employing these devices. uc1548 uc2548 uc3548 primary side pwm controller features description udg-95037 pin numbers refer to 16-pin dil and soic packages only.
electrical characteristics unless otherwise stated, all specifications are over the junction temperature range of - 55 c to +125 c for the uc1548, - 40 c to +85 c for the uc2548, and 0 c to +70 c for the uc3548. test conditions are: vcc = 12v, ct = 400pf, ci = 100pf, ioff = 100 m a, cdc = 100nf, cvs = 100pf, and ivs = 400 m a, t a = t j . uc1548 uc2548 uc3548 supply voltage (pin 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22v output current, source or sink (pin 14) dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5a pulse (0.5 m s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2a power ground to ground (pin 1 to pin 13) . . . . . . . . . . . 0.2v analog input voltages (pins 3, 4, 7, 8, 12, 16) . . . . . . . . . . . . . . . . . . . . . -0.3 to 7v analog input currents, source or sink (pins 3, 4, 7, 8, 11, 12, 16) . . . . . . . . . . . . . . . . . . . . . . 1ma analog output currents, source or sink (pins 5 & 10) . . . 5ma power dissipation at t a = 60 c . . . . . . . . . . . . . . . . . . . . . . . . 1w storage temperature range . . . . . . . . . . . . . . . - 65 c to +150 c lead temperature (soldering 10 seconds) . . . . . . . . . . +300 c connection diagrams parameter test conditions min typ max units real time current waveform synthesizer ion amplifier offset voltage 0.95 1 1.05 v slew rate (note 1) 20 25 v/ m s lib -2 -20 m a ioff current mirror input voltage 0.95 1 1.05 v current gain 0.911.1a/a current error amplifier a vol 60 100 db vio 12v vcc 20v, 0v vcm 5v 10 mv lib -0.5 -3 m a voh i o = - 200 m a 3.1 3.3 3.5 v vol i o = 200 m a0.30.6v source current v o = 1v 1.4 1.6 2.0 ma gbw product f = 200khz 5 8 mhz slew rate (note 1) 810 v/ m s oscillator frequency t a = 25 c 240 250 260 khz 235 265 khz notes: all voltages are with respect to ground (dil and soic pin 1). currents are positive into the specified terminal. pin numbers refer to the 16 pin dil and soic packages. consult packaging section of databook for thermal limitations and considerations of packages. absolute maximum ratings plcc-20 & lcc-20 (top view) q & l packages dil-16, soic-16 (top view) j, n, or dw packages 2
uc1548 uc2548 uc3548 parameter test conditions min typ max units duty cycle clamp max duty cycle v(d max ) = 0.75 v ref 73.5 76.5 79.5 % vcc comparator turn-on threshold 13 14 v turn-off threshold 910 v hysteresis 2.533.5v uv comparator turn-on threshold 4.14.354.6 v r hysteresis vuv = 4.2v 77 90 103 k w reference vref t a = 25 c 4.95 5 5.05 v 0 < i o < 10ma, 12 < vcc < 20 4.93 5.07 v line regulation 12v < v cc < 20v 4 15 mv load regulation 0 < i o < 10ma 3 15 mv short circuit current v ref = 0v 30 50 70 ma output stage rise & fall time (note 1) cl = 1nf 20 45 ns output low saturation i o = 20ma 0.25 0.4 v i o = 200ma 1.2 2.2 v output high saturation i o = -200ma 2.0 3.0 v uvlo output low saturation i o = 20ma 0.8 1.2 v i cc i start vcc = 12v 0.2 0.4 ma i cc (pre-start) vcc = 15v, v(uv) = 0 0.5 1 ma i cc (run) 22 26 ma note 1: guaranteed by design. not 100% tested in production. electrical characteristics (cont.): unless otherwise stated, all specifications are over the junction temperature range of - 55 c to +125 c for the uc1548, - 40 c to +85 c for the uc2548, and 0 c to +70 c for the uc3548. test conditions are: vcc = 12v, ct = 400pf, ci = 100pf, ioff = 100 m a, cdc = 100nf, cvs = 100pf, and ivs = 400 m a, t a = t j . cao: output of the current error amplifier. also the resistor load for the collector of an optocoupler. cdc: connect a charge balance integration capacitor from cdc to gnd to achieve an accurate duty cycle clamp. this capacitor also sets the soft start time. ci: output of the inductor current waveform synthesizer. requires a capacitor to ground. ct: a capacitor from ct to gnd sets the oscillator frequency. dmax: programs maximum duty cycle with a resistive divider from vref to dmax to gnd. gnd: signal ground. inv: inverting input of the current error amplifier. ioff: programs the discharge slope of the capacitor on ci to emulate the down slope of the inductor current waveform. ion: input pin to inductor current waveform synthesizer. apply a voltage proportional to switch current to this pin. ni: noninverting input of the current error amplifier. out : output driver for the gate of a power fet. pgnd: power ground pin for the output driver. this ground circuit should be connected to gnd at a single point. uv: line voltage sense pin to insure the chip only operates with sufficient line voltage. program with a resistive divider from the converter input voltage to uv to gnd. vcc: chip supply voltage. bypass with a 1 m f ceramic capacitor to pgnd. vref: precision voltage reference. bypass with a 1 m f ceramic capacitor to gnd. vs: volt second clamp programming pin and feedforward ramp waveform for the pulse width modulator. connect a resistor to the input line voltage and a capacitor to gnd. pin descriptions 3
uc1548 uc2548 uc3548 figure 1: undervoltage lockout udg-95038 figure 2: oscillator frequency 20 100 1000 2000 100 1000 5000 c (pf) 500 50 500 oscillator frequency as a function of ct frequency decrease as a function of rt rt = open udg-95039 the undervoltage lockout block diagram is shown in fig- ure 1. the vcc comparator monitors chip supply voltage. hysteretic thresholds are set at 13v and 10v to facilitate off-line applications. if the vcc comparator is low, icc is low (<500 m a) and the output is low. the uv comparator monitors input line voltage (v in ). a pair of resistors divides the input line to uv. hysteretic in- put line thresholds are programmed by rv1 and rv2. the thresholds are v in (on) = 4.35v (1 + rv1/rv2 ) and v in (off) = 4.35v (1 + rv1/rv2) where rv2 = rv2 || 90k. the resulting hysteresis is v in (hys) = 4.35v rv1 / 90k. when the uv comparator is low, i cc is low (<500 m a) and the output is low. when both the uv and vcc comparators are high, the in- ternal bias circuitry for the remainder of the chip is activated. the cdc pin (see discussion on maximum duty cycle control and soft start) and the output are held low until vref exceeds the 4.5v threshold of the vref com- parator. when vref is good, control of the output driver is transferred to the pwm circuitry and cdc is allowed to charge. if any of the three uvlo comparators go low, the uvlo latch is set, the output is held low, and cdc is discharged. this state will be maintained until all three comparators are high and the cdc pin is fully discharged. undervoltage lockout 4
figure 3: error amplifier gain and phase response over frequency a capacitor from the ct pin to gnd programs oscillator frequency, as shown in figure 2. frequency is determined by: f = 1 / (10k ct). the sawtooth wave shape is generated by a charging cur- rent of 200 m a and a discharge current of 1800 m a. the discharge time of the sawtooth is guaranteed dead time for the output driver. if the maximum duty cycle control is defeated by connecting dmax to vref, the maximum duty cycle is limited by the oscillator to 90%. if an adjust- ment is required, an additional trim resistor rt from ct to ground can be used to adjust the oscillator frequency. rt should not be less than 40kohms. this will allow up to a 22% decrease in frequency. uc1548 uc2548 uc3548 udg-95040 oscillator inductor current waveform synthesizer average current mode control is a very useful technique to control the value of any current within a switching con- verter. input current, output inductor current, switch current, diode current or almost any other current can be controlled. in order to implement average current mode control, the value of the current must be explicitly known at all times. to control output inductor current (il) in a buck derived isolated converter, switch current provides inductor current information, but only during the on time of the switch. during the off time, switch current drops abruptly to zero, but the inductor current actually dimin- ishes with a slope dil/dt = - vo/l. this down slope must be synthesized in some manner on the primary side to provide the entire inductor current waveform for the con- trol circuit. the patented current waveform synthesizer (figure 4) consists of a unidirectional voltage follower which forces the voltage on capacitor ci to follow the on time switch current waveform. a programmable discharge current synthesizes the off time portion of the waveform. ion is the input to the follower. the discharge current is pro- grammed at ioff. the follower has a one volt offset, so that zero current corresponds to one volt at ci. the best utilization of the uc3548 is to translate maximum average inductor current to a 4 volt signal level. given n and ns (the turns ratio of the power and current sense transformers respectively), proper scaling of il to v(ci) requires a sense resistor rs as calculated from: rs = 4v ns n / il(max). restated, the maximum average inductor current will be limited to: il(max) = 4v ns n/rs. ioff and ci need to be chosen so that the ratio of dv(ci)/dt to dil/dt is the same during switch off time as on time. recommended nominal off current is 100 m a. this requires ci = (100 m a n ns l) / (rs vo(nom)) where l is the output inductor value and vo(nom) is the converter regulated output voltage. 5
uc1548 uc2548 uc3548 there are several methods to program ioff. if accurate maximum current control is required, ioff must track out- put voltage. the method shown in figure 4 derives a voltage proportional to vin d (where d = duty cycle). in a buck converter, output voltage is proportional to vin d. a resistively loaded diode connection to the bootstrap winding yields a square wave whose amplitude is propor- tional to vin and is duty cycle modulated by the control circuit. averaging this waveform with a filter generates a primary side replica of secondary regulated vo. a single pole filter is shown, but in practice a two or three pole filter provides better transient response. filtered voltage is con- verted by roff to a current to the ioff pin to control ci downslope. if accurate system maximum current is not a critical re- quirement, figure 5 shows the simplest method of downslope generation: a single resistor (roff = 40k) from ioff to vref. the discharge current is then 100 m a. the disadvantage to this approach is that the synthesizer continues to generate a down slope when the switch is off even during short circuit conditions. actual inductor downslope is closer to zero during a short circuit. the penalty is that the average current is understated by an amount approximately equal to the nominal inductor rip- ple current. output short circuit is therefore higher than the designed maximum output current. a third method of generating ioff is to add a second winding to the output inductor core (figure 6). when the power switch is off and inductor current flows in the free wheeling diode, the voltage across the inductor is equal to the output voltage plus the diode drop. this voltage is then transformed by the second winding to the primary side of the converter. the advantages to this approach are its inherent accuracy and bandwidth. winding the sec- ond coil on the output inductor core while maintaining the required isolation makes this a more costly solution. in the example, roff = vo / 100 m a. the 4 roff resistor is added to compensate the one volt input level of the ioff pin. without this compensation, a minor current foldback behavior will be observed. inductor current waveform synthesizer (cont.) figure 4: inductor current waveform synthesizer udg-95041 figure 5: fixed ioff figure 6: second inductor winding generation of ioff udg-95042 udg-95043 6
uc1548 uc2548 uc3548 pulse width modulation is achieved by comparing the out- put of the current error amplifier to the feed forward ramp generated at vs (figure 7). the charge slope of the ramp is determined by a resistor (rvs) from vs to vin and a capacitor (cvs) from vs to gnd. in the event that cao is at its maximum voltage, typically 3.3v, the uc3548 will limit the power stage to a volt-second product of: v in t on (max) = 3.3v rvs cvs. an isolated voltage control loop can be implemented with a secondary side reference, error amplifier and an opto- isolator. the optoisolator can be used to override the current amplifier output which is current limited by a 2.5k resistor. in overcurrent situations, the voltage loop turns the optoisolator off and the current error amplifier then as- sumes duty cycle control resulting in accurately limited maximum output current. a patented technique is used to accurately program maxi- mum duty cycle. programming is accomplished by a divider from vref to dmax (figure 7). the value pro- grammed is: d(max) = rd1 / (rd1 + rd2). for proper operation, the integrating capacitor, c dc , should be larger than t(osc) / 80k, where t(osc) is the os- cillator period. c dc also sets the soft start time constant, so values of c dc larger than minimum may be desired. the soft start time constant is approximately: t(ss) = 20k c dc . the output driver on the uc3548 is capable of 2a peak currents. careful layout is essential for correct operation of the chip. a ground plane must be employed (figure 8). a unique section of the ground plane must be designated for high di/dt currents associated with the output stage. this point is the power ground to which to pgnd pin is connected. power ground can be separated from the rest of the ground plane and connected at a single point, al- though this is not strictly necessary if the high di/dt paths are well understood and accounted for. vcc should be bypassed directly to power ground with a good high fre- quency capacitor. the source of the power mosfet should connect to power ground as should the return con- nection for input power to the system and the bulk input capacitor. the output should be clamped with a high cur- rent schottky diode to both vcc and pgnd. nothing else should be connected to power ground. vref should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. low esr/esl ceramic 1 m f capacitors are recommended for both vcc and vref. the capacitors from ct, cdc, ci and vs should likewise be connected to the signal ground plane. feed forward pulse width modulation maximum duty cycle and soft start ground planes figure 7: duty cycle control udg-95044 udg-95045-1 7
uc1548 uc2548 uc3548 unitrode corporation 7 continental blvd. merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 figure 8: ground plane considerations figure 9: typical application - voltage feedforward control isolated forward converter with average current limiting udg-95046 udg-95047-1 8
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