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publication# 080136 rev: d amendment: / 0 issue date: october 1999 am7943 subscriber line interface circuit distinctive characteristics programmable constant-current feed current gain = 200 programmable loop-detect threshold low power standby state performs polarity reversal ground-key detector tip open state for ground-start lines ?19 v to ?58 v battery operation two-wire impedance set by single external impedance on-hook transmission on-chip ring relay driver and relay snubber circuit on-chip thermal management (tmg) feature ideal for dlc and pabx applications block diagram two-wire interface hpa hpb da db bgnd vbat a(tip) b(ring) tmg ground-key detector signal transmission power-feed controller ring-trip detector vcc vee agnd/dgnd ringout c1 c2 c3 e0 e1 det rsn vtx rd rdc cas ring relay driver input decoder and control off-hook detector
2 am7943 data sheet ordering information standard products legerity standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. note: * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ?40 c to +85 c is guaranteed by characterization and periodic sampling of production units. am7943 j performance grade temperature range c=commercial (0 c to 70 c)* package type j = 32-pin plastic leaded chip carrier (pl 032) am7943 subscriber line interface circuit valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on legerity?s standard military? grade products. ?1 = performance grading ?2 = performance grading ?1 c device number/description valid combinations am7943 ?1 ?2 jc
slic products 3 connection diagram top view notes: 1. pin 1 is marked for orientation. 2. tp is a thermal conduction pin tied to substrate. 3. nc = no connect tp tp 32-pin plcc ringout nc tmg vbat c3 e1 c2 det da rd hpb hpa vtx vee rsn nc nc bgnd nc b(ring) a(tip) db vcc nc nc agnd/dgnd 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 cas c1 rdc e0
4 am7943 data sheet pin descriptions pin names type description agnd/dgnd gnd analog and digital ground a(tip) output output of a(tip) power amplifier bgnd gnd battery (power) ground b(ring) output output of b(ring) power amplifier c3 ? c1 input decoder. ttl compatible. c3 is msb and c1 is lsb. cas capacitor anti-saturation pin for capacitor to filter reference voltage when operating in anti- saturation region. da input ring-trip negative. negative input to ring-trip comparator. db input ring-trip positive. positive input to ring-trip comparator. det output switchhook detector. when enabled, a logic low indicates the selected detector is tripped. the detector is selected by the logic inputs (c3?c1, e1?e0). the output is open- collector with a built-in 15 k ? pull-up resistor. e0 input det enable. a logic high enables det . a logic low disables det . (det = logic high). (plcc only) e1 input ground-key enable. e1 = low connects the ground-key or ring-trip detector to det . e1 = high connects the off-hook or ring-trip detector to det . (plcc only) hpa capacitor high-pass filter capacitor. a(tip) side of high-pass filter capacitor. hpb capacitor high-pass filter capacitor. b(ring) side of high-pass filter capacitor. rd resistor detector resistor. threshold modification and filter point for the off-hook detector. rdc resistor dc feed resistor. connection point for the dc feed current programming network. the other end of the network connects to the receiver summing node (rsn). the sign of v rdc is negative for normal polarity and positive for reverse polarity. ringout output ring relay driver. open-collector driver with emitter internally connected to bgnd. rsn input receive summing node. the metallic current (ac and dc) between a(tip) and b(ring) is equal to 200 times the current into this pin. the networks that program receive gain, two-wire impedance, and feed current all connect to this node. tmg ? thermal management. a resistor connected from this pin to vbat reduces the on-chip power dissipation in the normal polarity, active state only. refer to table 2. tp thermal thermal pin. connection for heat dissipation. internally connected to substrate (vbat). leave as open circuit or connected to vbat. in both cases, the tp pins can connect to an area of copper on the board to enhance heat dissipation. vbat battery battery supply vcc power +5 v power supply vee power ? 5 v power supply vtx output transmit audio. this output is a unity gain version of the a(tip) and b(ring) metallic voltage. vtx also sources the two-wire input impedance programming network.
slic products 5 absolute maximum ratings storage temperature . . . . . . . . . . . . ? 55 c to +150 c v cc with respect to agnd/dgnd . . . ? 0.4 v to +7.0 v v ee with respect to agnd/dgnd . . .+0.4 v to ? 7.0 v v bat with respect to agnd/dgnd: continuous . . . . . . . . . . . . . . . . . . +0.4 v to ? 70 v 10 ms . . . . . . . . . . . . . . . . . . . . . . +0.4 v to ? 75 v bgnd with respect to agnd/dgnd . . . .+3 v to ? 3 v a(tip) or b(ring) to bgnd: continuous . . . . . . . . . . . . . . . . . . . . ? 70 v to +1 v 10 ms (f = 0.1 hz) . . . . . . . . . . . . . . . ? 70 v to +5 v 1 ms (f = 0.1 hz) . . . . . . . . . . . . . . . . ? 80 v to +8 v 10 s (f = 0.1 hz) . . . . . . . . . . . . . . ? 90 v to +12 v current from a(tip) or b(ring) . . . . . . . . . . . . 150 ma current from tmg . . . . . . . . . . . . . . . . . . . . . 100 ma voltage on ringout: during transient . . . . . . . . . . . . . . bgnd to +10 v during steady state . . . . . . . . . . . . . bgnd to +7 v current through relay drivers . . . . . . . . . . . . . . 60 ma da and db inputs voltage on ring-trip inputs . . . . . . . . . . .v bat to 0 v current into ring-trip inputs . . . . . . . . . . . . . . 10 ma c3 ? c1, e0, e1 to agnd/dgnd . . . . . . . . . . ? 0.4 v to v cc +0.4 v maximum power dissipation, t a = 85 c no heat sink (see note): in 32-pin plcc package. . . . . . . . . . . . . . . . 1.4 w thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ja in 32-pin plcc package. . . . . . . . . . . .43 c/w typ note: thermal limiting circuitry on chip will shut down the cir- cuit at a junction temperature of about 165 c. the device should never be exposed to this temperature. operation above 145 c junction temperature may degrade device reli- ability. see the slic packaging considerations for more in- formation. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature . . . . . . . . . . . . . . 0 c to +70 c* v cc . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 v to 5.25 v v ee . . . . . . . . . . . . . . . . . . . . . . . . ? 4.75 v to ? 5.25 v v bat . . . . . . . . . . . . . . . . . . . . . . . . . ? 19 v to ? 56.5 v agnd/dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v bgnd with respect to agnd/dgnd . . . . . . . . . . . . ? 100 mv to +100 mv load resistance on vtx to ground . . . . . . . 10 k ? min operating ranges define those limits between which device functionality is guaranteed. * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ? 40 c to +85 c is guaranteed by characterization and periodic sampling of production units.
6 am7943 data sheet electrical characteristics description test conditions (see note 1) min typ max unit note analog (v tx ) output impedance 3 ? analog (v tx ) output offset ? 40 c to +85 c ? 35 ? 40 +35 +40 mv ? 4 analog (rsn) input impedance 300 hz to 3.4 khz 1 20 ? 4 longitudinal impedance at a or b 35 overload level 4-wire and 2-wire active state ? 2.5 +2.5 vpk 2a on-hook, r lac = 900 ?, active or oht state 0.95 vrms 2b transmission performance 2-wire return loss (see test circuit d) 200 to 3400 hz 26 db 4, 8 longitudinal balance (2-wire and 4-wire, see test circuit c); r l = 740 ? at v bat = 48 v longitudinal to metallic l-t, l-4 200 hz to 1 khz ? 1* normal polarity 0 c to +70 c ? 2 normal polarity ? 40 c to +85 c ? 2 reverse polarity ? 2 52 63 58 58 db ? ? 4 ? 1 khz to 3.4 khz ? 1* normal polarity 0 c to +70 c ? 2 normal polarity ? 40 c to +85 c ? 2 reverse polarity ? 2 52 58 54 54 ? ? 4 ? longitudinal signal generation 4-l 300 hz to 800 hz normal polarity 42 longitudinal current per pin active state and oht state 27 35 marms insertion loss (2- to 4-wire and 4- to 2-wire, see test circuits a and b) bat = ? 48 v, r l = 900 ? gain accuracy 0 dbm, 1 khz 0 c to +70 c ? 40 c to +85 c ? 0.15 ? 0.20 +0.15 +0.20 db ? ? 4 gain accuracy, oht state ? 10 dbm, on-hook, r lac = 900 ? ? 0.5 +0.5 4 variation with frequency 300 to 3400 hz relative to 1 khz 0 c to +70 c ? 40 c to +85 c ? 0.10 ? 0.15 +0.10 +0.15 ? ? 4 gain tracking +7 dbm to ? 55 dbm reference: 0 dbm ? 0.1 +0.1 4 ? balance return signal (4- to 4-wire, see test circuit b) bat = ? 48 v, r l = 900 ? gain accuracy 0 dbm, 1 khz 0 c to +70 c ? 40 c to +85 c ? 0.15 ? 0.20 +0.15 +0.20 db ? 3 4 variation with frequency 300 to 3400 hz relative to 1 khz 0 c to +70 c ? 40 c to +85 c ? 0.1 ? 0.15 +0.1 +0.15 ? 3 4 gain tracking +3 dbm to ? 55 dbm reference: 0 dbm 0 c to +70 c ? 40 c to +85 c ? 0.1 ? 0.15 +0.1 +0.15 ? ? 3, 4 4 group delay f = 1 khz 4 s 4, 8 note: * p.g. = performance grade
slic products 7 total harmonic distortion (2- to 4-wire or 4- to 2-wire) (see test circuits a and b) bat = ? 48 v, r l = 900 ? harmonic distortion 300 hz to 3400 hz 2-wire level = 0 dbm 2-wire level = +7 dbm ? 64 ? 55 ? 50 ? 40 db idle channel noise (2-wire and 4-wire) c-message weighted noise 0 c to +85 c ? 40 c to 0 c +7 +7 +10 +12 dbrnc ? 4 psophometric weighted noise 0 c to +85 c ? 40 c to 0 c ? 83 ? 80 ? 78 dbmp ? 4 line characteristics, active state (see figure 1) short loops, active state bat = ? 43 v, r ldc = 600 ? bat = ? 48 v, r ldc = 600 ? 25.0 27.0 29.0 ma long loops, active state bat = ? 43 v, r ldc = 1.4 k ? bat = ? 48 v, r ldc = 1.9 k ? 20.0 18.0 23.8 20.4 oht state bat = ? 48 v, r ldc = 600 ? 16.0 18.0 20.0 standby state t a = 25 c 0.7i l i l 1.3i l r l = 600 ? , bat = ? 48 v t a = 70 o c 15.0 17.4 loop current tip open, r l = 0 disconnect, r l = 0 tip open, bwire to gnd tip open, bwire = v bat + 6 v ? ? 30 30 100 100 ? ? a a ma ma i l lim (itip + iring) tip and ring shorted to gnd 100 130 ma ground-start signaling (tip voltage) active state r tip to ? 48 v = 7.0 k ? r ring to gnd = 100 ? ? 7.5 ? 5.0 v 4 ? ? open circuit voltage active and oht bat = ? 48 v 40.5 42.0 power dissipation, normal loop polarity, bat = ? 48 v on hook, open circuit state 25 70 mw on hook, oht state 120 210 on hook, active state r tmg = open r tmg = 1700 ? 160 195 260 280 on hook, standby state 35 85 off hook, oht state r l = 300 ? , r tmg = bat = ? 48 v 735 1050 off hook, active state r l = 300 ? , r tmg = bat = ? 48 v 1.25 1.45 w r l = 300 ? , r tmg = 0.57 0.85 off hook, standby state r l = 600 ? , t a = 25 c 0.68 1.0 electrical characteristics (continued) description test conditions (see note 1) min typ max unit note i l v bat 3v ? r l 1800 + ------------------------------- =
8 am7943 data sheet supply currents, bat = ? 48 v v cc on-hook supply current open circuit state oht state standby state active state 1.7 4.9 2.2 6.3 2.5 7.5 3.0 8.5 ma v ee on-hook supply current open circuit state oht state standby state active state 0.7 2.0 0.77 2.1 2.0 3.5 2.0 5.0 v bat on-hook supply current open circuit state oht state standby state active state 0.18 1.9 0.45 4.2 1.0 4.7 1.5 5.7 power supply rejection ratio (v ripple = 50 mvrms), active normal state v cc 50 hz to 3400 hz 33 40 db 5 v ee 50 hz to 3400 hz 29 35 v bat 50 hz to 3400 hz 30 50 effective internal resistance cas pin to gnd 85 170 255 k ? 4 rfi rejection 100 khz to 30 mhz (see figure e) 1.0 mvrms 4 off-hook detector current threshold ? 10 +10 % ground-key detector thresholds, active state, bat = ? 48 v ground-key resistance threshold b(ring) to gnd 2.0 5.0 10.0 k ? ground-key current threshold b(ring) to gnd 9 ma ring-trip detector input bias current ? 0.5 ? 0.05 a offset voltage source resistance = 2 m ? ? 50 0 +50 mv 6 logic inputs (c3 ? c1, e0, e1) input high voltage 2.0 v input low voltage 0.8 input high current all inputs except c3 and e1 input c3 input e1 ? 75 ? 75 ? 75 40 200 45 a input low current ? 0.4 ma logic output (det ) output low voltage i out = 0.8 ma 0.4 v output high voltage i out = ? 0.1 ma 2.4 relay driver output (ringout) on voltage 35 ma sink +0.25 +0.4 v off leakage v oh = +5 v 100 a zener breakover 100 a 6 7.2 v zener on voltage 30 ma 10 electrical characteristics (continued) description test conditions (see note 1) min typ max unit note i det 375 r d -------- - =
slic products 9 relay driver schematic switching characteristics (32-pin plcc only) symbol parameter test conditions temperature range min typ max unit note tgkde e1 low to det high (e0 = 1) e1 low to det low (e0 = 1) ground-key detect state r l open, r g connected (see figure g) 0 c to 70 c ? 40 to +85 c 0 c to 70 c ? 40 to +85 c 3.8 4.0 1.1 1.6 s 4 tgkdd e0 high to det low (e1 = 0) 0 c to 70 c ? 40 to +85 c 1.1 1.6 tgkd0 e0 low to det high (e1 = 0) 0 c to 70 c ? 40 to +85 c 3.8 4.0 tshde e1 high to det low (e0 = 1) e1 high to det high (e0 = 1) switchhook detect state r l = 600 ? , r g open (see figure f) 0 c to 70 c ? 40 to +85 c 0 c to 70 c ? 40 to +85 c 1.2 1.7 3.8 4.0 tshdd e0 high to det low (e1 = 1) 0 c to 70 c ? 40 to +85 c 1.1 1.6 tshd0 e0 low to det high (e1 = 1) 0 c to 70 c ? 40 to +85 c 3.8 4.0 ringout bgnd
10 am7943 data sheet switching waveforms det tgkde tshde tgkde tshde e1 e1 to det det tshdd tshd0 tgkd0 tgkdd e1 e0 e0 to det note: all delays measured at 1.4 v level.
slic products 11 notes: 1. unless otherwise noted, test conditions are v cc = +5 v, v ee = ? 5 v, c hp = 0.33 f, r dc1 = r dc2 = 9.26 k ? , c dc = 0.33 f, r d = 35.4 k ? , c cas = 0.33 f, no fuse resistors, bat = ? 48 v, r l = 900 ? , and r tmg = 1700 ? . 2. a. overload level is defined when thd = 1%. b. overload level is defined when thd = 1.5%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes the two-wire ac load impedance matches the programmed impedance. 4. not tested in production. this parameter is guaranteed by characterization or correlation to other tests. 5. this parameter is tested at 1 khz with a termination impedance of 900 ? and an r l of 600 ? in production. performance at other frequencies is guaranteed by characterization. 6. tested with 0 ? source impedance. 2 m ? is specified for system design only. 7. assumes the following z t networks: 8. group delay can be considerably reduced by using a z t network such as that shown in note 7 above. the network reduces the group delay to less than 2 s. the effect of group delay on the linecard performance may be compensated for by using the qslac ? or dslac ? device. table 1. slic decoding det output state c3 c2 c1 two-wire status e1 = 1 e1 = 0 0 0 0 0 open circuit ring trip ring trip 1 0 0 1 ringing ring trip ring trip 2 0 1 0 active loop detector ground key 3 0 1 1 on-hook tx (oht) loop detector ground key 4 1 0 0 tip open loop detector ground key 5 1 0 1 standby loop detector ground key 6 1 1 0 active polarity reversal loop detector ground key 7 1 1 1 oht polarity reversal loop detector ground key note: e0 high enables the det pin. vtx rsn 90 k ? 150 pf 90 k ? vtx rsn 60 k ? 150 pf 60 k ? (600 ? ): (900 ? ):
12 am7943 data sheet table 2. user-programmable components z t is connected between the vtx and rsn pins. the fuse resistors are r f and z 2win is the desired 2-wire ac input impedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z rx is connected from v rx to rsn. z t is defined above and g 42l is the desired receive gain. r dc1 , r dc2 , and c dc form the network connected to the rdc pin. r dc1 and r dc2 are approximately equal. i loop is the desired loop current in the constant-current region. r d and c d form the network connected from rd to ? 5 v and i t is the threshold current between on hook and off hook. oht loop current (constant-current region) c cas is the regulator filter capacitor and f c is the desired filter cut-off frequency. thermal management equations (normal active and tip open states) r tmg is connected from tmg to v bat and is used to limit power dissipation within the slic in normal active and tip open states only. power dissipated in the thermal management resistor, r tmg , during active and tip open states power dissipated in the slic while in active and tip open states thermal management equations (polarity reverse state) note: slic die temperature should not exceed 140 o c. power dissipated in the slic while in the polarity reverse state total die temperature thermal impedance of the 32-pin plastic leaded chip carrier package z t 200 z 2win 2r f ? () = z rx z l g 42l ----------- 200 z t ? z t 200 z l 2r f + () + ------------------------------------------------- ? = r dc1 r dc2 500 i loop ------------- - = + c dc 1.5 ms r dc1 r dc2 + r dc1 r dc2 ? ------------------------------- - ? = r d 375 i t -------- - c d 0.5 ms r d ---------------- - = , = i oht 500 v 0.66 ? r dc1 r dc2 + ------------------------------- - = c cas 1 3.4 10 5 f c ? ----------------------------- = r tmg v bat 6v ? i loop ---------------------------- - = p rtmg v bat 6v ? i l r l ? () ? () 2 r tmg ---------------------------------------------------------------- = p slic v bat i l p rtmg ? ? r l i l () 2 ? 0.12 w + = p slic v bat i l r l i l () ? ? 2 0.12 w + = t slic p slic ja ? t ambient + = theta ja ja () plcc 43 cwatt ? =
slic products 13 dc feed characteristics r dc1 + r dc2 = r dc = 18.52 k ? active state oht state notes: 1. constant-current region: active state, oht state, 2. anti-sat (battery tracking) turn-on: 3. open circuit voltage: 4. anti-sat (battery tracking) region: i l 500 r dc --------- - = i l 2 3 -- - 500 r dc --------- - ? = v ab 1.017 v bat 10.7 ? = v ab 1.017 v bat =6.3 ? v ab 1.017 v bat 6.3 ? i l r dc 120 --------- - ? = 4 1 2 3 3 v bat = 51.3 v v bat = 47.3 v a. v a ? v b (v ab ) voltage vs. loop current (typical)
14 am7943 data sheet dc feed characteristics (continued) c. feed programming a b i l rsn rdc r dc1 r dc2 c dc slic r l a b feed current programmed by r dc1 and r dc2 figure 1. dc feed characteristics r dc1 + r dc2 = r dc = 18.52 k ? v bat = 47.3 v b. loop current vs. load resistance (typical)
slic products 15 test circuits a(tip) vtx b(ring) rsn agnd r t r rx v l v ab r l a(tip) b(ring) rsn agnd vtx r t v rx r rx i l2-4 = ? 20 log (v tx / v ab ) a. two- to four-wire insertion loss i l4-2 = ? 20 log (v ab / v rx ) b. four- to two-wire insertion loss and balance return signal a(tip) vtx b(ring) rsn v ab r t r rx s2 v rx v l c s1 s2 open, s1 closed l-t long. bal. = 20 log (v ab / v l ) s2 closed, s1 open 4-l long. sig. gen. = 20 log (v l / v rx ) l-4 long. bal. = 20 log (v tx / v l ) c. longitudinal balance brs = 20 log (v tx / v rx ) slic slic slic r l 2 r l 2 r l 2 r l 2 1 c -------- v ab v l << r l slic r r v m z in z d v s r t1 r rx b(ring) a (tip) rsn agnd vtx note: z d is the desired impedance (e.g., the characteristic impedance of the line). r l = ? 20 log (2 v m / v s ) r t2 c t1 d. two-wire return loss test circuit
16 am7943 data sheet test circuits (continued) 200 ? e. rfi test circuit 50 ? l 1 200 ? c1 c2 b(ring) hf gen vtx a(tip) slic under test l 2 cax 33 nf cbx 33 nf r f1 r f2 50 ? 50 ? 1.5 vrms 80% amplitude modulated 100 khz to 30 mhz f. loop-detector switching v cc a(tip) b(ring) det e1 6.2 k ? r l = 600 ? 15 pf g. ground-key switching rg: 2 k ? at v bat = ? 48 v rg b(ring) a(tip)
slic products 17 test circuits (continued) h. am7943 test circuit battery ground analog ground digital ground vee vcc rd rd vtx agnd/ dgnd rsn r rx r dc2 r dc1 c dc r t rdc c2 c1 ? 5 v +5 v vbat det d 6 bgnd ringout hpb c hp a(tip) db da a(tip) b(ring) cas c cas bat tmg r tmg 1700 ? 2.2 nf 2.2 nf v tx v rx hpa b(ring) e1 c3
18 am7943 data sheet physical dimension pl032 revision summary revision a to b minor changes were made to the data sheet style and format to conform to legerity standards. revision b to revision c ? in pin description table, inserted/changed tp pin description to: ?thermal pin. connection for heat dissipation. internally connected to substrate (vbat). leave as open circuit or connected to vbat. in both cases, the tp pins can connect to an area of copper on the board to enhance heat dissipation.? minor changes were made to the data sheet style and format to conform to legerity standards. revision c to revision d the physical dimension (pl032) was added to the physical dimension section. deleted the ceramic dip and plastic dip packages and references to them. updated the pin description table to correct inconsistencies. .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530
the contents of this document are provided in connection with legerity, inc. products. legerity makes no representations or war ranties with re- spect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specificati ons and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intelle ctual property rights is granted by this publication. except as set forth in legerity's standard terms and conditions of sale, legerity assumes no li ability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of legerit y's product could create a situation where personal injury, death, or severe property or environmental damage may occur. legerity reserves the right to discontinue or make changes to its products at any time without notice. ? 1999 legerity, inc. all rights reserved. trademarks legerity, the legerity logo and combinations thereof, dslac and qslac are trademarks of legerity, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies.
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