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1/23 april 2000 m48t212y m48t212v 5v/3.3v timekeeper ? controller n converts low power sram into nvrams n year 2000 compliant (4-digit year) n battery low flag n integrated real time clock, power-fail control circuit, battery and crystal n automatic power-fail chip deselect and write protection n watchdog timer n choice of write protect voltages (v pfd = power-fail deselect voltage): m48t212y: 4.2v v pfd 4.5v m48t212v: 2.7v v pfd 3.0v n microprocessor power-on reset n programmable alarm output active in the battery backed-up mode n packaging includes a 44-lead soic and snaphat ? top (to be ordered separately) description the m48t212y/v are self-contained devices that include a real time clock (rtc), programmable alarms, a watchdog timer, and two external chip enable outputs which provide control of up to four (two in parallel) external low-power static rams. access to all timekeeper ? functions and the external ram is the same as conventional byte- wide sram. the 16 timekeeper registers offer century, year, month, date, day, hour, minute, second, calibration, alarm, watchdog, and flags. externally attached static rams are controlled by the m48t212y/v via the e1 con and e2 con sig- nals (see table 4). the 44 pin 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat housing contain- ing the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. figure 1. logic diagram ai03019 4 a0-a3 a dq0-dq7 v cc m48t212y m48t212v g v ss 8 ex e2 con e1 con w rstin2 rstin1 rst irq/ft v out wdi e v ccsw soh44 (mh) snaphat (sh) battery 44 1
m48t212y, m48t212v 2/23 insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. the snaphat housing is keyed to prevent reverse insertion. the soic and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. for the 44 lead soic, the bat- tery/crystal package (i.e. snaphat) part number is om4txx-br12sho (see table 15). caution: do not place the snaphat battery/crys- tal top in conductive foam, as this will drain the lith- ium button-cell battery. automatic backup and write protection for an ex- ternal sram is provided through v out ,e1 con and e2 con pins. (users are urged to insure that voltage specifications, for both the controller chip and external sram chosen, are similar). the snaphat containing the lithium energy source used to permanently power the real time clock is also used to retain ram data in the absence of v cc power through the v out pin. the chip enable outputs to ram (e1 con and e2 con ) are controlled during power transients to prevent data corruption. the date is automatically adjusted for months with less than 31 days and corrects for leap years. the internal watchdog tim- er provides programmable alarm windows. the nine clock bytes (fh - 9h and 1h) are not the actual clock counters, they are memory locations consisting of biport tm read/write memory cells within the static ram array. clock circuitry up- dates the clock bytes with current information once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. byte 8h is the clock control register. this byte con- trols user access to the clock information and also stores the clock calibration setting. byte 7h con- tains the watchdog timer setting. the watchdog timer can generate either a reset or an interrupt, depending on the state of the watchdog steering bit (wds). bytes 6h-2h include bits that, when pro- grammed, provide for clock alarm functionality. alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. byte 1h contains century information. byte 0h contains additional flag information pertaining to the watchdog timer, alarm and battery status. table 1. signal names a0-a3 address inputs dq0-dq7 data inputs/outputs rstin1 reset 1 input rstin2 reset 2 input rst reset output (open drain) wdi watchdog input a bank select input e chip enable input ex external chip enable input g output enable input w write enable input e1 con ram chip enable 1 output e2 con ram chip enable 2 output irq/ft int/freq test output (open drain) vccsw v cc switch output v out supply voltage output v cc supply voltage v ss ground nc not connected internally figure 2. soic connections ai03020 22 44 43 v ss 1 a0 nc nc nc a1 nc a nc e1 con nc nc v out nc g e v cc m48t212y m48t212v 10 2 5 6 7 8 9 11 12 13 14 15 21 40 39 36 35 34 33 32 31 30 29 28 nc nc ex v ccsw 3 4 38 37 42 41 wdi e2 con dq7 dq5 dq0 dq1 dq3 dq4 dq6 16 17 18 19 20 27 26 25 24 23 a2 a3 nc rstin2 nc rst nc nc nc w nc rstin1 dq2 irq/ft
3/23 m48t212y, m48t212v table 2. absolute maximum ratings (1) note: 1. stresses greater than those listed under oabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. soldering temperature not to exceed 260 c for 10 seconds (total thermal budget not to exceed 150 c for longer than 30 seconds). caution: negative undershoots below 0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaph at sockets. table 3. operating modes (1) note: 1. x = v ih or v il . 2. v so = battery back-up swit chover voltage. (see tables 7a and 7b for details). table 4. truth table for sram bank select (1) note: 1. x = v ih or v il . 2. v so = battery back-up swit chover voltage. (see tables 7a and 7b for details). symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) snaphat soic 40 to 85 55 to 125 c t sld (2) lead solder temperature for 10 sec 260 c v io input or output voltages 0.3 to v cc +0.3 v v cc supply voltage m48t212y m48t212v 0.3 to 7 0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w mode v cc e g w dq7-dq0 power deselect 4.5v to 5.5v or 3.0v to 3.6v v ih x x high-z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high-z active deselect v so to v pfd (min) (2) x x x high-z cmos standby deselect v so (2) x x x high-z battery back-up mode v cc ex a e1 con e2 con power select 4.5v to 5.5v or 3.0v to 3.6v low low low high active low high high low active deselect high x high high standby deselect v so to v pfd (min) (2) x x high high cmos standby deselect v so (2) x x high high battery back-up
m48t212y, m48t212v 4/23 figure 3. hardware hookup note: 1. see description in power supply decoupling and undershoot protection. 2. traces connecting e1 con and e2 con to external sram should be as short as possible. ai03046 a0-a3 dq0-dq7 a v cc w g wdi rstin1 rstin2 v ss e v cc a0-axx 0.1 m f 0.1 m f 5v/3.3v e2 con rst irq/ft m48t212y/v cmos sram v out e v cc cmos sram e1 con note 2 motorola mtd20p06hdl v ccsw 1n5817 (1) ex e a0-a18 a0-axx figure 4. ac testing load circuit note: 1. dq0-dq7 2. e1 con and e2 con ai03239 c l = 100pf or 5pf (1) c l =30pf (2) 645 w device under test 1.75v c l includes jig capacitance table 5. ac measurement conditions note that output hi-z is defined as the point where data is no longer driven. input rise and fall times 5ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v
5/23 m48t212y, m48t212v table 6. capacitance (1) (t a =25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. 2. outputs deselected. table 7a. dc characteristics for m48t212v (t a = 0 to 70 c; v cc = 3v to 3.6v) note: 1. outputs deselected. 2. rstin1 and rstin2 internally pulled-up to v cc through 100k w resistor. wdi internally pulled-down to v ss through 100k w resistor. 3. for irq/ft & rst pins (open drain). 4. conditioned outputs (e1 con -e2 con ) can only sustain cmos leakage currents in the battery back-up mode. higher leakage cur- rents will reduce battery life. 5. external sram must match timekee per controller chip v cc specification. symbol parameter test condit ion min max unit c in input capacitance v in =0v 10 pf c out (2) input/output capacitance v out =0v 10 pf symbol parameter test condition min typ max unit i li (1,2) input leakage current 0v v in v cc 1 m a i lo (1) output leakage current 0v v out v cc 1 m a i cc supply current outputs open 4 10 ma i cc1 supply current (standby) ttl e=v ih 3ma i cc2 supply current (standby) cmos e=v cc 0.2 2ma i bat battery current osc on 575 800 na battery current osc off 100 na v il input low voltage 0.3 0.8 v v ih input high voltage 2.0 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v output low voltage (open drain) (3) i ol = 10ma 0.4 v v oh output high voltage i oh = 1.0ma 2.4 v v ohb (4) v oh battery back-up i out2 = 1.0 m a 2.0 3.6 v i out1 (5) v out current (active) v out1 >v cc 0.3 70 ma i out2 v out current (battery back-up) v out2 >v bat 0.3 100 m a v pfd power-fail deselect voltage 2.7 2.9 3.0 v v so battery back-up switchover voltage v pfd 100mv v v bat battery voltage 3.0 v
m48t212y, m48t212v 6/23 table 7b. dc characteristics for m48t212y (t a = 0 to 70 c; v cc = 4.5v to 5.5v) note: 1. outputs deselected. 2. rstin1 and rstin2 internally pulled-up to v cc through 100k w resistor. wdi internally pulled-down to v ss through 100k w resistor. 3. for irq/ft & rst pins (open drain). 4. conditioned outputs (e1 con -e2 con ) can only sustain cmos leakage currents in the battery back-up mode. higher leakage cur- rents will reduce battery life. 5. external sram must match timekee per controller chip v cc specification. symbol parameter test condition min typ max unit i li (1,2) input leakage current 0v v in v cc 1 m a i lo (1) output leakage current 0v v out v cc 1 m a i cc supply current outputs open 8 15 ma i cc1 supply current (standby) ttl e=v ih 5ma i cc2 supply current (standby) cmos e=v cc 0.2 3ma i bat battery current osc on 575 800 na battery current osc off 100 na v il input low voltage 0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v output low voltage (open drain) (3) i ol = 10ma 0.4 v v oh output high voltage i oh = 1.0ma 2.4 v v ohb (4) v oh battery back-up i out2 = 1.0 m a 2.0 3.6 v i out1 (5) v out current (active) v out1 >v cc 0.3 100 ma i out2 v out current (battery back-up) v out2 >v bat 0.3 100 m a v pfd power-fail deselect voltage 4.2 4.35 4.5 v v so battery back-up switchover voltage 3.0 v v bat battery voltage 3.0 v the m48t212y/v also has its own power-fail de- tect circuit. this control circuitry constantly moni- tors the supply voltage for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the timekeeper register data and external sram, providing data security in the midst of unpredictable system operation. as v cc falls, the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored. address decoding the m48t212y/v accommodates 4 address lines (a3-a0) which allow access to the sixteen bytes of the timekeeper clock registers. all timekeep- er registers reside in the controller chip itself. all timekeeper registers are accessed by enabling e (chip enable).
7/23 m48t212y, m48t212v table 8. power down/up ac characteristics (t a = 0 to 70 c) symbol parameter min max unit t f v pfd (max) to v pfd (min) v cc fall time 300 m s t fb v pfd (min) to v ss v cc fall time m48t212y 10 m s m48t212v 150 m s t r v pfd (min) to v pfd (max) v cc rise time 10 m s t rec v pfd (max) to rst high 40 200 ms t rb v ss to v pfd (min) v cc rise time 1 m s figure 5. power down/up ac waveform ai02638 v cc inputs rst outputs don't care high-z tf tfb tr trec trb valid valid v pfd (max) v pfd (min) v so valid valid v ccsw
m48t212y, m48t212v 8/23 figure 6. chip enable control and bank select timing ai02639 texpd tapd texpd ex a e1 con e2 con table 9. chip enable control and bank select characteristics (t a = 0 to 70 c) symbol parameter m48t212y m48t212v unit -70 -85 min max min max t expd ex to e1 con or e2 con (low or high) 10 15 ns t apd atoe1 con or e2 con (low or high) 10 15 ns
9/23 m48t212y, m48t212v figure 7. read cycle timing: rtc control signals ai02640 w dq7-dq0 g data out valid address tavav e telqv tavav tavav read read write data in valid data out valid tavqv twhax tavwl telqx tglqv tghqz twlwh taxqx tglqx table 10. read mode characteristics (t a = 0 to 70 c) note: 1. c l = 5pf symbol parameter m48t212y m48t212v unit -70 -85 min max min max t avav read cycle time 70 85 ns t avqv address valid to output valid 70 85 ns t elqv chip enable low to output valid 70 85 ns t glqv output enable low to output valid 25 35 ns t elqx (1) chip enable low to output transition 5 5 ns t glqx (1) output enable low to output transition 0 0 ns t ehqz (1) chip enable high to output hi-z 20 25 ns t ghqz (1) output enable high to output hi-z 20 25 ns t axqx address transition to output transition 5 5 ns read mode the m48t212y/v executes a read cycle whenev- er w (write enable) is high and e (chip enable) is low. the unique address specified by the address inputs (a3-a0) defines which one of the on-chip timekeeper registers is to be accessed. when the address presented to the m48t212y/v is in the range of 0h-fh, one of the on-board time- keeper registers is accessed and valid data will be available to the eight data output drivers within t avqv after the address input signal is stable, pro- viding that the e and g access times are also sat- isfied.if they are not, then data access must be measured from the latter occurring signal (e or g) and the limiting parameter is either t elqv for e or t glqv for g rather than the address access time. when ex input is low, an external sram location will be selected. note: care should be taken to avoid taking both e and ex low simultaneously to avoid bus conten- tion.
m48t212y, m48t212v 10/23 figure 8. write cycle timing: rtc control signals ai02641 w dq0-dq7 g data in valid address tavav e taveh tavav tavav write write read data out valid data out valid tavwh tavqv twlwh twhdx twhax twhqx twlqz tdvwh tglqv tehqz tdveh data in valid teleh tehax tavel tehdx tavwl write mode the m48t212y/v is in the write mode whenever w (write enable) and e (chip enable) are in a low state after the address inputs are stable. the start of a write is referenced from the latter occurring falling edge of w or e. a write is terminated by the earlier rising edge of w or e. the addresses must be held valid throughout the cycle. e or w must re- turn high for a minimum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g a low on w will disable the outputs t wlqz after w falls. when e is low during the write, one of the on- board timekeeper registers will be selected and data will be written into the device. when ex is low (and e is high) an external sram location is se- lected. note: care should be taken to avoid taking both e and ex low simultaneously to avoid bus conten- tion.
11/23 m48t212y, m48t212v table 11. write mode ac characteristics (t a = 0 to 70 c) note: 1. c l = 5pf. 2. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter m48t212y m48t212v unit -70 -85 min max min max t avav write cycle time 70 85 ns t avwl address valid to write enable low 0 0 ns t avel address valid to chip enable low 0 0 ns t wlwh write enable pulse width 45 55 ns t eleh chip enable low to chip enable high 50 60 ns t whax write enable high to address transition 0 0 ns t ehax chip enable high to address transition 0 0 ns t dvwh input valid to write enable high 25 30 ns t dveh input valid to chip enable high 25 30 ns t whdx write enable high to input transition 0 0 ns t ehdx chip enable high to input transition 0 0 ns t wlqz (1,2) write enable low to output high-z 20 25 ns t avwh address valid to write enable high 55 65 ns t aveh address valid to chip enable high 55 65 ns t whqx (1,2) write enable high to output transition 5 5 ns data retention mode with valid v cc applied, the m48t212y/v can be accessed as described above with read or write cycles. should the supply voltage decay, the m48t212y/v will automatically deselect, write protecting itself (and any external sram) when v cc falls between v pfd (max) and v pfd (min). this is accomplished by internally inhibiting ac- cess to the clock registers via the e signal. at this time, the reset pin (rst) is driven active and will remain active until v cc returns to nominal levels. external ram access is inhibited in a similar man- ner by forcing e1 con and e2 con to a high level. this level is within 0.2 volts of the v bat .e1 con and e2 con will remain at this level as long as v cc remains at an out-of tolerance condition. when v cc falls below the level of the battery (v bat ), power input is switched from the v cc pin to the snaphat battery and the clock registers and external sram are maintained from the at- tached battery supply. all outputs become high im- pedance. the v out pin is capable of supplying 100 m a of current to the attached memory with less than 0.3v drop under this condition. on power up, when v cc returns to a nominal value, write protec- tion continues for 200ms (max) by inhibiting e1 con or e2 con . the rst signal also remains active during this time (see figure 5). note: most low power srams on the market to- day can be used with the m48t212y/v time- keeper controller. there are, however some criteria which should be used in making the final choice of an sram to use. the sram must be de- signed in a way where the chip enable input dis- ables all other inputs to the sram. this allows inputs to the m48t212y/v and srams to be don't care once v cc falls below v pfd (min). the sram should also guarantee data retention down to v cc = 2.0v. the chip enable access time must be sufficient to meet the system needs with the chip enable output propagation delays included.
m48t212y, m48t212v 12/23 if the sram includes a second chip enable pin (e2), this pin should be tied to v out . if data retention lifetime is a critical parameter for the system, it is important to review the data reten- tion current specifications for the particular srams being evaluated. most srams specify a data retention current at 3.0v. manufacturers gen- erally specify a typical condition for room temper- ature along with a worst case condition (generally at elevated temperatures). the system level re- quirements will determine the choice of which val- ue to use. the data retention current value of the srams can then be added to the i bat value of the m48t212y/ v to determine the total current requirements for data retention. the available battery capacity for the snaphat of your choice can then be divided by this current to determine the amount of data re- tention available (see table 15). for a further more detailed review of lifetime calcu- lations, please see application note an1012. figure 9. alarm interrupt reset waveforms ai03021 a0-a3 active flag bit address 0h irq/ft high-z 1h fh table 12. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 1 1 1 1 1 once per second 1 1 1 1 0 once per minute 1 1 1 0 0 once per hour 1 1 0 0 0 once per day 1 0 0 0 0 once per month 0 0 0 0 0 once per year
13/23 m48t212y, m48t212v timekeeper registers the m48t212y/v offers 16 internal registers which contain timekeeper, alarm, watchdog, flag, and control data. these registers are mem- ory locations which contain external (user accessi- ble) and internal copies of the data (usually referred to as biport tm timekeeper cells). the external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. timekeeper and alarm registers store data in bcd. control, watchdog and flags registers store data in binary format. clock operations reading the clock updates to the timekeeper registers should be halted before clock data is read to prevent reading data in transition. because the biport time- keeper cells in the ram array are only data reg- isters, and not the actual clock counters, updating the registers can be halted without disturbing the clock itself. updating is halted when a ` 1' is written to the read bit, d6 in the control register (8h). as long as a `1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was is- sued. all of the timekeeper registers are updated si- multaneously. a halt will not interrupt an update in progress. updating occurs 1 second after the read bit is reset to a ` 0'. setting the clock bit d7 of the control register (8h) is the write bit. setting the write bit to a ` 1', like the read bit, halts updates to the timekeeper registers. the user can then load them with the correct day, date, and time data in 24 hour bcd format (see table 13). resetting the write bit to a `0' then transfers the values of all time registers (fh-9h, 1h) to the actual timekeeper counters and allows normal opera- tion to resume. after the write bit is reset, the next clock update will occur one second later. note: upon power-up following a power failure, the read bit will automatically be set to a `1'. this will prevent the clock from updating the time- keeper registers, and will allow the user to read the exact time of the power-down event. resetting the read bit to a `0' will allow the clock to update these registers with the current time. the write bit will be reset to a ` 0' upon power- up. figure 10. back-up mode alarm waveforms ai03622 v cc irq/ft high-z v pfd (max) v pfd (min) afe bit/abe bit af bit in flags register high-z trec
m48t212y, m48t212v 14/23 stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is located at bit d7 within the seconds register (9h). setting it to a `1' stops the oscillator. when re- set to a `0', the m48t212y/v oscillator starts within one second. note: it is not necessary to set the write bit when setting or resetting the frequency test bit (ft) or the stop bit (st). setting alarm clock address locations 6h-2h contain the alarm set- tings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. it can also be pro- grammed to go off while the m48t212y/v is in the battery back-up to serve as a system wake-up call. bits rpt5-rpt1 put the alarm in the repeat mode of operation. table 12 shows the possible config- urations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. note : user must transition address (or toggle chip enable) to see flag bit change. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5-rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set, the alarm condition activates the irq/ft pin. to disable alarm, write '0' to the alarm date registers and rpt1-4. the irq/ft output is cleared by a read to the flags register as shown in figure 9. a subse- quent read of the flags register will reset the alarm flag (d6; register 0h). the irq/ft pin can also be activated in the bat- tery back-up mode. the irq/ft will go low if an alarm occurs and both abe (alarm in battery back-up mode enable) and afe are set. the abe and afe bits are reset during power-up, therefore an alarm generated during power-up will only set af. the user can read the flag register at system boot-up to determine if an alarm was generated while the m48t212y/v was in the deselect mode during power-up. figure 10 illustrates the back-up mode alarm timing. watchdog timer the watchdog timer can be used to detect an out- of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 7h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolu- tion, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. the amount of time- out is then determined to be the multiplication of the five bit multiplier value with the resolution. (for example: writing 00001110 in the watchdog reg- ister = 3*1 or 3 seconds). note : accuracy of timer is within the selected resolution. if the processor does not reset the timer within the specified period, the m48t212y/v sets the wdf (watchdog flag) and generates a watchdog inter- rupt or a microprocessor reset. wdf is reset by reading the flags register (address 0h). the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a ` 0', the watchdog will activate the irq/ft pin when timed-out. when wds is set to a ` 1', the watchdog will output a negative pulse on the rst pin for 40 to 200 ms. the watchdog register and the ft bit will reset to a `0' at the end of a watch- dog time-out when the wds bit is set to a ` 1'. the watchdog timer can be reset by two methods: 1. a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (wdi) or 2. the microprocessor can perform a write of the watchdog register. the time-out period then starts over. the wdi pin should be tied to v ss if not used. the watchdog will be reset on each transition (edge) seen by the wdi pin. in the order to perform a software reset of the watchdog timer, the original time-out period can be written into the watchdog register, effec- tively restarting the count-down cycle. should the watchdog timer time-out, and the wds bit is programmed to output an interrupt, a value of 00h needs to be written to the watchdog register in order to clear the irq/ft pin. this will also dis- able the watchdog function until it is again pro- grammed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 0h). the watchdog function is automatically disabled upon power-down and the watchdog register is cleared. if the watchdog function is set to output to the irq/ft pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied.
15/23 m48t212y, m48t212v v cc switch output vccsw output goes low when v out switches to v cc turning on a customer supplied p-channel mosfet (see figure 3). the motorola mtd20p06hdl is recommended. this mosfet in turn connects v out to a separate supply when the current requirement is greater than i out1 (see tables 7a and 7b). this output may also be used simply to indicate the status of the internal battery switchover comparator, which controls the source (v cc or battery) of the v out output. power-on reset the m48t212y/v continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for 40 to 200ms after v cc passes v pfd . the rst pin is an open drain output and an appro- priate pull-up resistor to v cc should be chosen to control rise time. note : if the rst output is fed back into either of the rstin inputs (for a microprocessor with a bi- directional reset) then a 1k w (max) pull-up resistor is recommended. reset inputs (rstin1 & rstin2) the m48t212y/v provides two independent in- puts which can generate an output reset. the du- ration and function of these resets is identical to a reset generated by a power cycle. table 14 and figure 12 illustrate the ac reset characteristics of this function. during the time rst is enabled (t r1hrh &t r2hrh ), the reset inputs are ignored. note: rstin1 and rstin2 are each internally pulled up to v cc through a 100k w resistor. table 13. timekeeper register map address function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 fh 10 years year year 00-99 eh 0 0 0 10m month month 01-12 dh 0 0 10 date date: day of month date 01-31 ch 0 ft 0 0 0 day of week day 01-7 bh 0 0 10 hours hours (24 hour format) hour 00-23 ah 0 10 minutes minutes min 00-59 9h st 10 seconds seconds sec 00-59 8h w r s calibration control 7h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 6h afe 0 abe al 10m alarm month a month 01-12 5h rpt4 rpt5 ai 10 date alarm date a date 01-31 4h rpt3 0 ai 10 hour alarm hour a hour 00-23 3h rpt2 alarm 10 minutes alarm minutes a min 00-59 2h rpt1 alarm 10 seconds alarm seconds a sec 00-59 1h 1000 year 100 year century 00-99 0h wdf af y bl y y y y flag keys: s = sign bit ft = frequency test bit r = read bit w = write bit st = stop bit 0 = must be set to zero bl = battery low flag bmb0-bmb4 = watchdog multiplier bits afe = alarm flag enable flag rb0-rb1 = watchdog resolution bits wds = watchdog steering bit abe = alarm in battery back-up mode enable bit rpt1-rpt5 = alarm repeat mode bits wdf = watchdog flag af = alarm flag y = `1' or `0'
m48t212y, m48t212v 16/23 calibrating the clock the m48t212y/v is driven by a quartz controlled oscillator with a nominal frequency of 32,768 hz. the devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25 c, which equates to about 1.53 minutes per month. when the calibration circuit is properly em- ployed, accuracy improves to better than +1/2 ppm at 25 c. the oscillation rate of crystals changes with tem- perature. the m48t212y/v design employs peri- odic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in fig- ure 11. the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register 8h. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; `1' indicates positive calibration, `0' indicates negative calibra- tion. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary `1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modi- fied; if a binary 6 is loaded, the first 12 will be af- fected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or 2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is running at exactly 32,768 hz, each of the 31 increments in the calibration byte would figure 11. calibration waveform ai00594b normal positive calibration negative calibration represent +10.7 or 5.35 seconds per month which corresponds to a total range of +5.5 or 2.75 minutes per month. two methods are available for ascertaining how much calibration a given m48t212y/v may re- quire. the first involves setting the clock, letting it run for a month and comparing it to a known accu- rate reference and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given peri- od, can be found in application note an934: timekeeper calibration. this allows the designer to give the end user the ability to calibrate the clock as the environment re- quires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that accesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of the irq/ft pin. the pin will toggle at 512hz, when the stop bit (st, d7 of 9h) is ` 0',the frequency test bit (ft, d6 of ch) is ` 1', the alarm flag enable bit (afe, d7 of 6h) is ` 0', and the watchdog steering bit (wds, d7 of 7h) is `1' or the watchdog register (7h=0) is reset. any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.010124 hz would indicate a +20 ppm oscilla- tor frequency error, requiring a 10 (wr001010) to be loaded into the calibration byte for correc- tion. note that setting or changing the calibration byte does not affect the frequency test output fre- quency. the irq/ft pin is an open drain output which re- quires a pull-up resistor to v cc for proper opera- tion. a 500-10k w resistor is recommended in order to control the rise time. the ft bit is cleared on power-up.
17/23 m48t212y, m48t212v battery low warning the m48t212y/v automatically performs battery voltage monitoring upon power-up and at factory- programmed time intervals of approximately 24 hours. the battery low (bl) bit, bit d4 of flags register 0h, will be asserted if the battery voltage is found to be less than approximately 2.5v. the bl bit will remain asserted until completion of bat- tery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up se- quence, this indicates that the battery is below ap- proximately 2.5 volts and may not be able to maintain data integrity in the sram. data should be considered suspect and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the bat- tery is near end of life. however, data is not com- promised due to the fact that a nominal vcc is supplied. in order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. the snaphat bat- tery/crystal top should be replaced with v cc pow- ering the device to avoid data loss. note : this will cause the clock to lose time during the time interval the battery crystal is removed. the m48t212y/v only monitors the battery when a nominal vcc is applied to the device. thus appli- cations which require extensive durations in the battery back-up mode should be powered-up peri- odically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data in- tegrity should be verified upon power-up via a checksum or other technique. table 14. reset ac characteristics (t a = 0 to 70 c; v cc = 3v to 3.6v or v cc = 4.5v to 5.5v) note: 1. pulse width less than 50ns will result in no reset (for noise immunity). 2. pulse width less than 20ms will result in no reset (for noise immunity). 3. c l = 5pf (see figure 4). table 15. snaphat battery table symbol parameter min max unit t r1 (1) rstin1 low to rstin1 high 200 ns t r2 (2) rstin2 low to rstin2 high 100 ms t r1hrh (3) rstin1 high to rst high 40 200 ms t r2hrh (3) rstin2 high to rst high 40 200 ms part number description package m4t28-br12sh lithium battery (48mah) snaphat sh m4t32-br12sh lithium battery (120mah) snaphat sh figure 12. rstin1 & rstin2 timing waveforms ai02642 rstin1 rst (1) rstin2 tr1 tr1hrh tr2 tr2hrh
m48t212y, m48t212v 18/23 initial power-on defaults upon application of power to the device, the fol- lowing register bits are set to a `0' state: wds, bmb0-bmb4, rb0-rb1, afe, abe, w and ft. (see table 16) power supply decoupling and undershoot protection note: i cc transients, including those produced by output switching, can produce voltage fluctua- tions, resulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store energy, which stabilizes the v cc bus. the energy stored in the bypass capacitors will be re- leased as low going spikes are generated or ener- gy will be absorbed when overshoots occur. a ceramic bypass capacitor value of 0.1 m f is rec- ommended in order to provide the needed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, st recom- mends connecting a schottky diode from v cc to figure 13. supply voltage protection ai02169 v cc 0.1 m f device v cc v ss v ss (cathode connected to v cc , anode to v ss ). (schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount). table 16. default values note: 1. wds, bmb0-bmb4, rb0, rb1. 2. state of other control bits undefined. 3. state of other control bits remains unchanged. 4. assuming these bits set to `1' prior to power-down. conditi on w r ft afe abe watchdog register (1) initial power-up (battery attach for snaphat) (2) 00000 0 subsequent power-up / reset (3) 00000 0 power-down (4) 00011 0
19/23 m48t212y, m48t212v table 17. ordering information scheme note: 1. the soic package (soh44) requires the battery package (snaphat ) which is ordered separately under the part number am4txx-br12sh1o in plastic tube or om4txx-br12sh1tro in tape & reel form. caution : do not place the snaphat battery package om4txx-br12sh1o in conductive foam since will drain the lithium button-cell battery. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m48t212y -70 mh 1 tr device type m48t supply voltage and write protect voltage 212y = v cc = 4.5v to 5.5v; v pfd = 4.2v to 4.5v 212v = v cc = 3.0v to 3.6v; v pfd = 2.7v to 3.0v speed -70 = 70ns (for m48t212y) -85 = 85ns (for m48t212v) package mh (1) = soh44 temperature range 1=0to70 c 6=40to85 c shipping method for soic blank = tubes tr = tape & reel table 18. revision history date revision details october 1999 first issue 03/01/00 document layout changed default values table added (table 16) 04/21/00 from preliminary data to data sheet
m48t212y, m48t212v 20/23 table 19. soh44 - 44 lead plastic small outline, snaphat, package mechanical data symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.46 0.014 0.018 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 0.81 0.032 eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n44 44 cp 0.10 0.004 figure 14. soh44 - 44 lead plastic small outline, snaphat, package outline drawing is not to scale. soh-a e n d c l a1 a 1 h a cp be a2 eb
21/23 m48t212y, m48t212v table 20. m4t28-br12sh snaphat housing for 48 mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 figure 15. m4t28-br12sh snaphat housing for 48 mah battery & crystal, package outline drawing is not to scale. shtk-a a1 a d e ea eb a2 b l a3
m48t212y, m48t212v 22/23 table 21. m4t32-br12sh snaphat housing for 120 mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 .0335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 .0710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 figure 16. m4t32-br12sh snaphat housing for 120 mah battery & crystal, package outline drawing is not to scale. shtk-a a1 a d e ea eb a2 b l a3
23/23 m48t212y, m48t212v information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a . http://w ww.st.com

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