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general description the gd16131, 32:4 / quad 8:1 mux and the gd16132, 4:32 / quad 1:8 demux are intended for use in 2.5 gbit/s trans - mission systems. the high-speed inter - face is designed to accommodate the requirements of the gd16554 (4:1 mux) and the gd16543 (1:4 demux) both meeting ccitt specifications at 2.5 gbit/s sdh stm-16. the gd16131 and gd16162 take care of the interface between the high-speed devices differen - tial ecl level i/o?s at 622 mbit/s and lower speed cmos gate arrays at 78 mbit/s. hence they are dual supply devices shifting levels between true ecl and ttl. the gd16131 and gd16132 are made as four identical blocks of 8 bit and a clock driver circuit. the 8 bit blocks are implemented as shift registers to obtain the best speed/power ratio of the process technology used. also this means easy clock distribution with small delay be- tween incoming and outgoing signals. for the gd16131 the 622 mbit/s data outputs are re-timed at the chip edge to cut down delay from clock-in to data-out, allowing counter directional clocking. thus the on-chip delay, except output buffer load dependant delay, is kept be - low 1 ns. a 622 mhz output clock with close timing relation to the data outputs also allows co-directional clocking. on both mux and demux, the subdivided 78 mhz clock are also re-timed at the chip edge to cut down delay from the 622 mhz input clock. the phase relation between low-speed data and the subdi - vided output clock are selectable in four phases. the gd16131 and gd16132 are pack- aged in 68 pin multi layer ceramic (mlc) packages, yielding excellent high- speed signal accommodation and ther- mal conditions. the chip set is designed for an operating temperature between ?5 c and +85 c, case temperature. with power consumption of 1.3 w typical for both gd16131 and gd16132, only little or no heat sink is required. bit naming convention naming of pins on parallel ports is made assuming the transfer bit order to be in - creasing starting with position d0, d1, ..., d31. features gd16131 l quad 8:1 mux l all high-speed i/o?s are differential, ecl level. l all low-speed i/o?s are ttl level, outputs drive 10 pf at 78 mhz. l subdivided output clock to data rela - tion selectable in four phases. l dual supply: +5 v, -5.2 v. l 68 pin mlc flat package. l high-speed pins on single side of package for easy pcb routing. l power consumption: 1.3 w typical. gd16132 l quad 1:8 demux l all high-speed i/o?s are differential, ecl level. l all low-speed i/o?s are ttl level, outputs drive 10 pf at 78 mhz. l subdivided output clock to data relation selectable in four phases. l dual supply: +5 v, -5.2 v. l 68 pin mlc flat package. l high-speed pins on single side of package for easy pcb routing. l power consumption: 1.3 w typical. 622 mbit/s mux/demux chip set gd16131/gd16132 data sheet rev.: 12 d0 d4 : d24 d28 d1 d5 : d25 d29 d2 d6 : d26 d30 d3 d7 : d27 d31 ckop clock generator ckip sel1 ckout vcc vdd vee vtt do3p do3n do2p do2n do1p do1n do0p do0n ckon ckin sel2 reset sel1 sel2 reset clock generator ckip ckout vcc vdd vee d0 d4 : d24 d28 d1 d5 : d25 d29 d2 d6 : d26 d30 d3 d7 : d27 d31 di0p di1p di2p di3p di0n di1n di2n di3n ckin
function description gd16131 - mux the first bit shifted out is the one with the lowest number. the first internal 8:1 mux of the gd16131 services bits 0-4-8-12-16-20-24-28. neighboring input pins in the pin-out go to the same mux. gd16132 - demux the first bit received is shifted out on the lowest pin number. the first of the 4 internal 1:8 demux of the gd16132 drives outputs 0-4-8-12-16-20- 24-28. neighboring output pins go to the same demux. pin list ? gd16131 mnemonic: pin no.: pin type: description: d0 .. d31 22, 32, 56, 66, 23, 33, 54, 64, 24, 36, 53, 63, 25, 37, 50, 62, 27, 39, 49, 61, 28, 40, 47, 59, 29, 41, 46, 58, 30, 42, 45, 57 ttl in parallel data input port to mux. do0p, do0n do1p, do1n do2p, do2n do3p, do3n 10, 11 7, 8 5, 6 2, 3 ecl out differential serial data outputs from mux. ckip, ckin 12, 13 ecl in differential clock input, 622 mhz. ckop, ckon 15, 16 ecl out differential clock output with timing related to data outputs, 622 mhz. ckout 44 ttl out subdivided output clock, 78 mhz. maximum load 10 pf. sel1, sel2 19, 20 ttl in ckout clock phase select: sel2 sel1 00 t del =0 01 t del = 270 (-90) 10 t del = 180 11 t del =90 reset 67 ttl in test reset. not needed on power up, the device is self synchro - nising. reset is used for test only. vdd 4, 9, 14, 21, 26, 31, 38, 43, 48, 55, 60, 65 pwr 0 v power for core and ecl i/o. vcc 18, 52 pwr +5 v power for core and ttl i/o. all power pins must be connected. decoupling should be made close to package body. vee 1, 34, 51 pwr -5.2 v power for core and ecl i/o. all power pins must be connected. decoupling should be made close to package body . nc 17, 35, 68 not connected data sheet rev.: 12 gd16131/gd16132 page 2 of 11
pin list ? gd16132 mnemonic: pin no.: pin type: description: d0 .. d31 29, 41, 45, 57, 28, 40, 46, 58, 27, 39, 47, 59, 25, 37, 49, 61, 24, 36, 50, 62, 23, 33, 53, 63, 22, 32, 54, 64, 20, 30, 56, 66 ttl out parallel data output from demux. maximum load 10 pf. di0p, di0n di1p, di1n di2p, di2n di3p, di3n 10, 11 12, 13 2, 3 5, 6 ecl in differential serial data inputs. ckip, ckin 7, 8 ecl in differential clock input, 622 mhz. ckout 42 ttl out subdivided output clock, 78 mhz. maximum load 10 pf. sel1, sel2 16, 15 ttl in ckout clock phase select: sel2 sel1 00 t del =0 01 t del = 270 (-90) 10 t del = 180 11 t del =90 reset 67 ttl in test reset. not needed on power up, the device is self synchro - nising. reset is used for test only. vdd 4, 9, 14, 21, 26, 31, 38, 43, 48, 55, 60, 65 pwr 0 v power for core and ecl i/o. vcc 1, 34, 35, 52, 68 pwr +5 v power for core and ttl i/o. all power pins must be connected. decoupling should be made close to package body. vee 17, 51 pwr -5.2 v power for core and ecl i/o. all power pins must be connected. decoupling should be made close to package body. nc 18, 19, 44 not connected. data sheet rev.: 12 gd16131/gd16132 page 3 of 11
package pinout figure 1. package pinout, gd16131 ? top view figure 2. package pinout, gd16132 ? top view data sheet rev.: 12 gd16131/gd16132 page 4 of 11 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 nc ckon ckop vdd ckin ckip do0n do0p vdd do1n do1p do2n do2p vdd do3n do3p vee nc reset d3 vdd d7 d11 d15 d19 vdd d23 d27 d31 d2 vdd d6 d10 vcc vee d14 d18 vdd d22 d26 d30 ckout vdd d29 d25 d21 d17 vdd d13 d9 nc vee d5 d1 vdd d28 d24 d20 d16 vdd d12 d8 d4 d0 vdd sel2 sel1 vcc 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 vee sel1 sel2 vdd di1n di1p di0n di0p vdd ckin ckip di3n di3p vdd di2n di2p vcc vcc reset d31 vdd d27 d23 d19 d15 vdd d11 d7 d3 d30 vdd d26 d22 vcc vee d18 d14 vdd d10 d6 d2 nc vdd ckout d1 d5 d9 vdd d13 d17 vcc vcc d21 d25 vdd d29 d0 d4 d8 vdd d12 d16 d20 d24 vdd d28 nc nc
maximum ratings these are the limits beyond which the component may be damaged. all voltages in table are referred to vdd. all currents in table are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit: v ee negative supply -7 0 v v cc positive supply 0 +7 v v o max ecl output voltage ecl v ee -0.5 0.5 v v o max ttl output voltage ttl -0.5 v cc +0.5 v i o max ecl output current ecl 40 ma i o max ttl output current ttl 20 ma v i max ecl input voltage ecl v ee -0.5 0.5 v v i max ttl input voltage ttl -0.5 v cc +0.5 v i i max ecl input current ecl -1.0 1.0 ma i i max ttl input current ttl -1.0 1.0 ma t s operating temperature channel -55 +150 c t o storage temperature -65 +175 c q j-a thermal resistance junction - case 6 c/w data sheet rev.: 12 gd16131/gd16132 page 5 of 11
dc characteristics t case =-5 cto+85 c, appropriate heat sinking may be required. all voltages in table are referred to vdd. all currents in table are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit: v ee negative supply voltage -5.40 -5.20 -5.00 v v cc positive supply voltage 4.75 5.25 v i ee,gd16131 negative supply current (gd16131) -286 ma i cc,gd16131 positive supply current (gd16131) 26 ma i ee,gd16132 negative supply current (gd16132) -234 ma i cc,gd16132 positive supply current (gd16132) 78 ma v ih , ecl ecl input hi voltage -1100 -700 mv v il , ecl ecl input lo voltage note 1 v tt -1500 mv i ih , ecl ecl input hi current v ih max 25 m a i il , ecl ecl input lo current v il max -25 m a v oh , ecl ecl output hi voltage note 2 -1000 -500 mv v ol , ecl ecl output lo voltage note 2 v tt - 100 -1600 mv i oh , ecl ecl output hi current note 3 20 23 30 ma i ol , ecl ecl output lo current note 3 -2 5 8 ma v ih , ttl ttl input hi voltage 2 v cc v v il , ttl ttl input lo voltage 0 0.8 v i ih , ttl ttl input hi current v ih max 100 m a i il , ttl ttl input lo current v il min -100 m a v oh , ttl ttl output hi voltage i oh =3ma 2.4 v cc v v ol , ttl ttl output lo voltage i ol =3ma 0 0.8 v note 1: v tt = -2.0 v. note 2: r load =50 w to v tt . note 3: not tested, consistent with v oh and v ol tests. data sheet rev.: 12 gd16131/gd16132 page 6 of 11
ac characteristics ? gd16131 t case =-5 cto+85 c, appropriate heat sinking may be required. symbol: characteristic: conditions: min.: typ.: max.: unit: t icd doxp/n output from ckip/n 300 530 920 ps t cd ckop/n shift from doxp/n -100 100 ps t sa dyy set-up from ckout sel2/1: 0,0 -2000 ps t ha dyy hold from ckout sel2/1: 0,0 500 ps t sb dyy set-up from ckout sel2/1: 0,1 3x -2000 ps t hb dyy hold from ckout sel2/1: 0,1 3x +500 ps t sc dyy set-up from ckout sel2/1: 1,0 2x -2000 ps t hc dyy hold from ckout sel2/1: 1,0 2x +500 ps t sd dyy set-up from ckout sel2/1: 1,1 x -2000 ps t hd dyy hold from ckout sel2/1: 1,1 x +500 ps note: the value x is dependant of the clock frequency :x=1/f1/48=2/f data sheet rev.: 12 gd16131/gd16132 page 7 of 11 t sa t hd t sb t hc t cd t icd t sc t sb t sd t hd ckip dout ckop ckout d0..d31
ac characteristics ? gd16132 t case =-5 cto+85 c, appropriate heat sinking may be required. symbol: characteristic: conditions: min.: typ.: max.: unit: t s dixp/n output from ckip/n 800 ps t h dixp/n hold from ckip/n 0 ps t a dyy output from ckout sel2/1: 0,0 250 1500 ps t b dyy output from ckout sel2/1: 0,1 3x +250 3x+1500 ps t c dyy output from ckout sel2/1: 1,0 2x +250 2x+1500 ps t d dyy output from ckout sel2/1: 1,1 x +250 x+1500 ps note: the value x is dependant of the clock frequency :x=1/f1/48=2/f data sheet rev.: 12 gd16131/gd16132 page 8 of 11 t a t b t h t c t s t d ckip dip ckout d0..d31
counter-directional clocking schema ? gd16131/gd16054 symbol: characteristic: conditions: min.: typ.: max.: unit: t bd board propagation delay between gd16554 and gd16131 (sum of clock and data del.) note 1 0 400 ps t su gd16054 data input set-up from clock output note 1 280 400 600 ps t ho gd16054 data input hold from clock output note 1 -175 -250 -375 ps t cd gd16131 data output from clock input note 1 300 530 920 ps note 1: the above figures are based on layout parameters extractions and best assumptions. they give a hint of the magnitude of the figures and feasibility of the counter-directional clocking method. the maximal t bd is calculated as follows: t bd max = t bda max + t bdb max = 1.5 1/622mh z?4( t pack + t bond )? t su max ? t cd max 0> t bd min = 0.5 1/622mh z?4( t pack + t bond )+ t ho min ? t cd min all efforts to keep t cd as low as possible have been made. please note that t bd is the total round-trip board delay for both clock and data path. data sheet rev.: 12 gd16131/gd16132 page 9 of 11 t cd t su t bdb t ho t bda ck04 d40..43 (spec.) ckip gd16054 gd16131 gd16131 gd16054 doxp/n d40..43 100ps bond wires bond wires package board gd16131 gd16054 d40..43 ck04 do0...3 cki package 100ps 20ps anticipated board delay 250ps on-chip delay ck - data 1000ps wc 20ps
package outline figure 3. package 68 pin mlc (gullwings) - all dimensions are in inch. device marking figure 4. device marking - bottom view data sheet rev.: 12 gd16131/gd16132 page 10 of 11 gd16131(132) wwyy pin 1
ordering information to order, please specify as shown below: product name: type: package type: case temperature range: GD16131-GLP mux 68 pin mlc -5...+85 c gd16132-glp demux 68 pin mlc -5...+85 c gd16131/gd16132, data sheet rev.: 12 - date: 23 may 2000 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.giga.dk please check our internet web site for latest version of this data sheet. distributor: copyright ? 2000 giga a/s all rights reserved

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