PM7382 frame engine and data link manager 32p256 freedm-32p256 pmc-2011578 (r2) proprietary and confidential to pmc - sierra, inc., and for its customers ? internal use ? copyright pmc - sierra, inc. 2001 overview the freedm-32p256 chip offers the following features: ? single-chip multi-channel hdlc controller with a 66 mhz, 32-bit peripheral component interconnect (pci) 2.1 compatible bus for configuration, monitoring, and transfer of packet data. an on-chip dma controller with scatter/gather capabilities. supports up to 256 bi-directional hdlc channels assigned to a maximum of 32 channelized t1/j1/e1 links. you can program the number of time-slots assigned to an hdlc channel from 1 to 24 (for t1/j1) and from 1 to 31 (for e1). supports up to 256 bi-directional hdlc channels assigned to a maximum of 32 mvip digital telephony buses at 2.048 mbit/s per link, or 8 h-mvip buses at 8.192 mbit/s per link. supports up to 32 bi-directional hdlc channels, each assigned to an unchannelized arbitrary-rate link, subject to a maximum aggregate link clock-rate of 64 mhz in each direction. channels assigned to links 0 to 2 support clock rates up to 52 mhz. channels assigned to links 3 to 31 support clock rates up to 10 mhz. in the special case where no more than 3 high-speed links are used, the maximum aggregate link clock-rate is 156 mhz. links configured for channelized t1/j1/e1 or unchannelized operation support the gapped-clock method for determining time-slots, which is backwards compatible with the freedm-8 and freedm-32 devices. for each channel, the hdlc receiver supports programmable flag-sequence detection, bit de-stuffing and frame-check sequence validation. the receiver supports the validation of both crc-ccitt and crc-32 frame-check sequences. for each channel, the hdlc transmitter supports programmable flag-sequence generation, bit stuffing and frame-check sequence generation. the transmitter supports the generation of both crc-ccitt and crc-32 frame-check sequences. the transmitter also aborts packets under the direction of the host or automatically when the channel underflows. provides 32 kbytes of on-chip memory for partial packet buffering in both the transmit and receive directions. you can configure this memory to support a variety of different channel configurations: from a single channel with 32 kbytes of buffering, to 256 channels, each with a minimum of 48 bytes of buffering. provides a standard five signal p1149.1 jtag test-port for boundary scan board-test purposes. receive channel assigner (rcas256) receive dma controller (rmac256) transmit dma controller (tmac256) serrb pciintb pciclk m66en pciclko perrb tbclk tbd jtag port trstb tms tdi tck tdo pci controller (gpic256) transmit channel assigner (tcas256) devselb idsel lockb gntb reqb stopb irdyb trdyb frameb par c/beb[3:0] ad[31:0] rstb sysclk pmctest receive hdlc processor/partial packet buffer (rhdl256) performance monitor (pmon) transmit hdlc processor/ partial packet buffer (thdl256) rmv8fpc rfp8b rmv8dc rmvck[3:0] rfpb[3:0] rclk[31:0] rd[31:0] tfpb[3:0] tmvck[3:0] tmv8dc tfp8b tmv8fpc tclk[31:0] td[31:0] rbclk rbd block diagram
head office: pmc-sierra, inc. 8555 baxter place burnaby, b.c. v5a 4v7 canada tel: 604.415.6000 fax: 604.415.6200 frame engine and data link manager 32p256 to order documentation, send email to: document@pmc-sierra.com or contact the head office, attn: document coordinator pmc-2011578 (r2) ? copyright pmc-sierra, inc. 2001. all rights reserved. august 2001 freedm-32, freedm-8, octliu, te-32, sbi, any-phy, and pmc-sierra are trademarks of pmc-sierra, inc. proprietary and confidential to pmc-sierra, inc., and for its customers ? internal use PM7382 freedm-32p256 all product documentation is available on our web site at: http://www.pmc-sierra.com for corporate information, send email to: info@pmc-sierra.com supports 5 volt tolerant i/os for non- pci signals. supports a 3.3 volt pci signaling environment. 329-pin plastic ball grid-array (pbga) package. applications ietf ppp interfaces for routers. frame relay interfaces for atm or frame relay switches and multiplexers. funi or frame relay service inter- working interfaces for atm switches and multiplexers. internet/intranet access equipment. packet-based dslam equipment. high density t1/e1 line card pm4318 octliu pm4318 octliu pm4318 octliu pm4318 octliu sbi pci bus 32xt1/e1/j1 8 8 8 8 pm4332 te-32 PM7382 freedm- 32p256 packet mamory processor
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