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rev. 0.1 5/10 copyright ? 2010 by silicon laboratories SI5317-EVB SI5317-EVB si5317 e valuation b oard u ser ? s g uide description the SI5317-EVB user?s guide provides a complete and simple evaluation of the functions, features, and performance of the si5317. the si5317 is a pin-controlled 1:1 jitter-attenuating clock for high-performance applications. the si5317 is based on s ilicon laboratories' 3rd- generation dspll? technology, which provides any- rate jitter attenuation in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the dspll loop bandwidth is user programmable, providing jitte r performance optimization at the application level. features ? no software required. si mple jumpers for device configuration ? fully powered from either a single usb port or an external power supply ? selectable external reference clock or on-board crystal ? status leds ? header to connect to external test equipment for automated testing
SI5317-EVB 2 rev. 0.1 1. functional block diagram a functional block diagram of the evb is shown in figure 1. the si5317- evb provides alarm and status outputs, programmable output cloc k signal format (lvpecl, lvds, cml, cmos), selectable loop ba ndwidths, and ultra low jitter. the si5317 accepts a single clock input ranging from 1 m hz to 710 mhz and generates two equal frequency clock outputs ranging from 1 to 710 mhz. the clock frequency range and loop bandwidth are selectable from a simple look-up table. the SI5317-EVB has a differential clock i nput that is ac terminated to 50 ? and then ac-coupled to the si5317. the two clock outputs are ac-coupled. the xa- xb reference is usually a 114.285 mhz crystal; but there are provisions for an external xa-xb reference (eit her differential or single-ended). the device status are available on a ribbon header and leds. control pins are strapped using jumper headers for device configuration and various board options. the board can be powered usi ng either external power supplies or from a pc's usb port. refer to the si5317 data sheet for technical details of the device. figure 1. si5317 evb block diagram si5317 ckin+ ckin- ckout1+ ckout1- ckout2+ ckout2- frqtbl frqsel[3:0] bwsel[1:0] rate[1:0] sfout[1:0] dbl2_by xa xb inc dec los lol rst_b 2x5 jumper header 2x15 jumper header l e d term* term* term* control status/ control vdd gnd header usb + regulator dut power 3.3v term*
SI5317-EVB rev. 0.1 3 2. SI5317-EVB inpu t and output clocks 2.1. input clocks the SI5317-EVB has a differential clock input that is ac terminat ed and ac coupled before being presented to the si5317. if the input clock frequencies are low (below 10 mhz), there are extra considerations that should be taken into account. the si5317 has a maximum clock input rise time specification of 11 ns that must be met (see ckntrf in the si5317 data sheet). also, if the input clock is lvcmos, it might be advantageous to replace the input coupling capacitors (c7, c12, c16. and c18) with 0 ? resistors. when using lvcmos inputs, the user should consider removing the ac termination and using source series termination located at the driving source. regardless of the input format, if the clock inputs are no t approximately 50% duty cycle, it is highly recommended to avoid ac coupling. for input clocks that are far off of 50% duty cycle, the average value of the signal that passes through the coupling capacitor will be significantly off of the midpoint be tween the maximum and minimum value of the clock signal, resulting in a mismatch with the common mode input threshold voltage (see vicm, in the si5317 data sheet). 2.2. xa-xb reference to achieve a very low jitter generati on and for stability during holdover, the si5317 requires a stable, low jitter reference at its xa-xb pins. to that end, the evb is configured with a 1 14.285 mhz third ov ertone crystal connected between pins 6 and 7 of the si5317. however, the SI5317-EVB is also capable of using an external xa- xb reference oscillator, either differential or single-ended. for details concerni ng the allowed xa-xb reference frequencies and their rate settings, see the si5317 da ta sheet. j1 and j2 are the sma connectors with ac termination. ac coupling is also provided that needs to be installed at c6 and c8. table 1 explains the component changes that are needed to implement an external xa-xb reference oscillator. table 1. xa-xb reference connections mode xtal ext ref ext ref in+ nc j1 ext ref in- nc j2 c6, c8 nopop install r8 install nopop rate0 (see note 4) mh rate1 (see note 4) mm notes: 1. xtal is 114.285 mhz. 2. nc - no connect. 3. nopop - do not install. 4. j12 jumper, see table 3. 5. c6 on bottom of the board.
SI5317-EVB 4 rev. 0.1 2.3. output clock the clock outputs are ac-coupled and are available on smas j5, j7, j9 and j11. for lvcmos outputs, it might be desirable to replace the ac coupling ca pacitors (c9,c14,c17, and c20) with 0 ? resistors. also, if greater drive strength is desired for an lvcmos output, r6 and r10 can be installed. 2.4. pin configuration j12 is the large jumper header in the center left of the board that implements the jumper plugs that configure the pins of the si5317. each pin can be strapped to become ei ther h, m, or l. the h level is achieved by installing a jumper plug between the appropriate mi ddle row pin and its vdd row pin. l is achieved by installing a jumper plug between the appropriat e middle row pin and its gnd row pin. m is achieved by installing no jumper plug. 2.5. evaluation board power the evb can be powered from tw o possible sources: usb or ex ternal supplies. a 3.3 v su pply is required to run the leds because of their rather large forward drop. the si5317 power supply can be separated from the 3.3 v supply so that the si5317 can be evaluated at a voltage ot her than 3.3 v. it is important to note that when the usb supply is being used, the evb uses the usb port only for po wer and that the resu lting power supply is strictly 3.3 v. here are the instructions for the various possibilities: 2.5.1. external power supplies install a jumper between j16.1 and j16.2 (labeled ext). there should be no usb connection. if the si5317 is not being operated at 3.3 v, two supplies s hould be connected to j14. connect the 3.3 v supply to j14.1 and j14.2 (labeled 3.3 v and gnd). connect the si 5317 power supply between j14.2 and j14.3 (labeled gnd and dut). if the si5317 is to be operated at 3.3 v, j15 (labeled one pwr) can be installed, requiring only one external supply. connect 3.3 v power between j14.2 and j14.3 (labeled gnd and dut). 2.5.2. usb power install a jumper between j16.2 and j16.3 (labeled usb). install a jumper at j15 (labeled one pwr). with a usb cable, plug the evb into a powered usb port. 2.5.3. usb 3.3v power, external si5317 power install a jumper between j16.2 and j16.3 (labeled usb). no jumper at j15 (labeled one pwr). connect the si5317 power supply between j14.2 and j14.3 (labeled gnd and dut).
SI5317-EVB rev. 0.1 5 3. connectors and leds 3.1. leds 3.2. jumpers, head ers, and connectors refer to figure 2 to lo cate the items described in this section. figure 2. evb jumper locations table 2. led descriptions led label significance d1 cs_ca not used d2 los2 not used d3 los1 on = no valid clock input d4 lol on = si5317 is not locked d5 dut_pwr on = si5317 power is present d6 3.3v on = 3.3 v power is present j14 c8, r8 j13 j12 j15 j16 si5317
SI5317-EVB 6 rev. 0.1 table 3. configuration header, j12 j12 pin j12.1 not used j12.2 sfout0 j12.3 sfout1 j12.4 frqsel0 j12.5 frqsel1 j12.6 frqsel2 j12.7 frqsel3 j12.8 frqtbl j12.9 bwsel0 j12.10 bswel1 j12.11 dbl2_by j12.12 not used j12.13 rate0 j12.14 rate1 table 4. status indication header, j13 j13 signal j13.1 inc j13.3 dec j13.5 los j13.7 not used j13.9 not used j13.11 lol j13.13 rst_b
SI5317-EVB rev. 0.1 7 4. schematic frqtbl rate0 autosel dbl2_by sfout1 bwsel1 sfout0 cs_ca lol rst_b los1 bwsel0 rate1 filt_dut_pwr inc dec frqsel0 frqsel3 frqsel2 frqsel1 los2 dut_pwr dut_pwr dut_pwr los2 los1 lol cs_ca ckin1+ to measure dut supply ckout1+ ckout1- ckout2- ckout2+ ckin1- ckin2+ ckin2- ext ref in + ext ref in - to power plane status, control mper ugs optionally install for cmos outputs see option list option list see option list see option l inc dec los1 los2 cs_ca lol rst_b c15 10nf c15 10nf c6 10nf nopop c6 10nf nopop r1149.9 r1149.9 j2 sma_edge j2 sma_edge 1 3 2 r13 0 ohm r13 0 ohm r2 0 ohm r2 0 ohm r10 0 ohm nopop r10 0 ohm nopop r949.9 r949.9 j9 sma_edge j9 sma_edge 1 3 2 c10 100n c10 100n c8 10nf nopop c8 10nf nopop j5 sma_edge j5 sma_edge 1 3 2 j12 14x3_m_hdr_thru j12 14x3_m_hdr_thru 8a 8b 7c 9a 9b 8c 10a 10b 9c 5c 5a 6c 6b 6a 7b 5b 7a 1a 2a 1b 3b 4c 1c 3a 3c 2c 2b 13b 13c 11c 12a 11a 14b 10c 11b 14a 13a 12b 12c 14c 4a 4b c9 100n c9 100n tp1 tp1 1 2 c5 1uf c5 1uf c19 10nf c19 10nf c17 100n c17 100n si5315/17 u1 si5315/17 u1 vdd1 5 vdd2 10 gnd1 8 gnd2 31 ckin1+ 16 ckin1- 17 ckin_2+ 12 ckin_2- 13 rate0 11 rate1 15 xa 6 xb 7 ckout1+ 28 ckout1- 29 ckout2+ 35 ckout2- 34 dbl2_by 14 los1 3 los2 4 cs_ca 21 rst 1 lol 18 autosel 9 nc 36 bwsel1 23 bwsel0 22 frqtbl 2 frqsel3 27 frqsel2 26 frqsel1 25 frqsel0 24 sfout1 30 sfout0 33 inc 20 dec 19 gnd3 37 vdd3 32 c7100n c7100n j4 sma_edge j4 sma_edge 1 3 2 j7 sma_edge j7 sma_edge 1 3 2 j11 sma_edge j11 sma_edge 1 3 2 c16 100n c16 100n c3 10nf c3 10nf r8 0 ohm r8 0 ohm j10 sma_edge j10 sma_edge 1 3 2 r6 0 ohm nopop r6 0 ohm nopop j1 sma_edge j1 sma_edge 1 3 2 c2 10nf c2 10nf j13 14_m_header j13 14_m_header 1 2 3 4 5 6 7 8 9 10 11 12 13 14 r15 10k r15 10k c1 10nf c1 10nf j3 nopop j3 nopop 1 2 r549.9 r549.9 c11 100n c11 100n c18 100n c18 100n c12 100n c12 100n tp2 tp2 1 2 c4 100n c4 100n c14 100n c14 100n r12 0 ohm nopop r12 0 ohm nopop r749.9 r749.9 r14 10 r14 10 r3 49.9 r3 49.9 j6 sma_edge j6 sma_edge 1 3 2 l1 ferrite l1 ferrite 1 2 r1100 nopop r1100 nopop c13 10nf c13 10nf gnd x1 114.285 mhz gnd x1 114.285 mhz 1 3 2 4 j8 sma_edge j8 sma_edge 1 3 2 r4 49.9 r4 49.9 c20 100n c20 100n figure 3. SI5317-EVB
SI5317-EVB 8 rev. 0.1 led_pwr raw_3p3v vbus dut_pwr usb_3p3v phoenix_3p3v v3p3 dut_pwr dut_pwr cs_ca los2 los1 lol dut_pwr gnd 3.3v evb main power usb power ground pins mounting holes power source selection single 3.3v supply dut power see option list install jumper to run dut from 3.3v select 3.3v from either usb or from j14 h1 #4 h1 #4 1 j23 j23 1 c25 1uf c25 1uf q2 bss138 q2 bss138 1 2 3 q5 bss138 q5 bss138 1 2 3 ac d1 yel cs_ca ac d1 yel cs_ca 1 2 a c d6 grn 3.3v a c d6 grn 3.3v 1 2 j20 j20 1 a c d2red los2 a c d2red los2 2 1 * * * j14 phoenix_3_screw * * * j14 phoenix_3_screw 1 2 3 h4 #4 h4 #4 1 q4 bss138 q4 bss138 1 2 3 + c26 33uf + c26 33uf j21 j21 1 j15 j15 1 2 r17 150 r17 150 + c23 33uf + c23 33uf a c d3red los1 a c d3red los1 2 1 h2 #4 h2 #4 1 q1 bss138 q1 bss138 1 2 3 a c d4red lol a c d4red lol 2 1 j17 usb j17 usb v 1 gnd 4 d- 2 d+ 3 s1 5 s2 6 r18 150 r18 150 j16 j16 1 2 3 j19 j19 1 q3 bss138 q3 bss138 1 2 3 r16 0 ohm r16 0 ohm j25 j25 1 a c d5 grn dut_pwr a c d5 grn dut_pwr 1 2 r19 r150x4 r19 r150x4 1 8 2 7 3 6 4 5 u2 fan1540b u2 fan1540b nc1 1 vout 2 vin 3 gnd 6 nc3 5 nc2 4 pad 7 l2 ferrite l2 ferrite 1 2 j26 j26 1 j24 j24 1 + c21 220uf + c21 220uf h3 #4 h3 #4 1 r20 10k r20 10k j22 j22 1 j18 j18 1 c22 1uf c22 1uf + c24 220uf + c24 220uf figure 4. led and power/usb
SI5317-EVB rev. 0.1 9 5. bill of materials item qty reference part mfr mfrpartnum bom digikey footprint 1 6 c1,c2,c3, c13,c15, c19 10nf venkel c0603x7r160- 103kne 603 2 11 c4,c7,c9, c10,c11, c12,c14, 100n venkel c0603x7r160- 104kne 603 c16,c17, c18,c20 3 3 c5,c22,c25 1uf venkel c0603x7r6r3- 105kne 603 5 2 c21,c24 220uf kemet t494b227m004a t 399-4631- 1-nd sm_c_3528_21 6 2 c23,c26 33uf venkel ta006tcm336m br 3528 7 1 d1 yel panasonic ln1471ytr p11125ct -nd led_gull 8 3 d2,d3,d4 red lumex ln1271ral p493ct- nd led_gull 9 2 d5,d6 grn panasonic ln1371g p491ct- nd led_gull 11 10 j1,j2,j4,j5, j6,j7,j8,j9, sma_ edge johnson 142-0701-801 j502-nd sma_edge_p062 j10,j11 13 1 j12 14x3_m_h dr_thru any two and one row side by side 20x3_m_hdr_thru 15 1 j14 phoenix_3 _screw phoenix mkdsn 1.5/3- 5.08 277-1248- nd phoenix3pinm_p2pitch 16 1 j15 jmpr_2pin 17 1 j16 jmpr_3pin 3pin_p1pitch 18 1 j17 usb fci 61729-0010blf 609-1039- nd usb_typeb 19 4 j19,j20,j24, j26 jmpr_1pin 1pin_p1pitch 20 2 l1,l2 ferrite venkel fbc1206-471h 1206 21 5 q1,q2,q3, q4,q5 bss138 on semi bss138lt1g bss138l t10sct- nd sot23
SI5317-EVB 10 rev. 0.1 23 4 r2,r8,r13, r16 0 ohm venkel cr0603-16w- 000t 603 24 6 r3,r4,r5, r7,r9,r11 49.9 venkel cr0603-16w- 49r9ft 603 26 1 r14 10 venkel cr0603-16w- 10r0ft 603 27 2 r15,r20 10k venkel cr603-16w- 1002ft 603 28 2 r17,r18 150 venkel cr0603-16w- 1500ft 603 29 1 r19 r150x4 panasonic exb-38v151jv y9151ct- nd 1206x4 31 1 u1 si5317 silicon labs si5317a-c-gm qfn-36 32 1 u2 fan1540b fairchild fan1540bpmx fan1540 bmpxct- nd mlp6 33 1 x1 114.285 mhz txc 7ma1400014 xtal 3.2 x 2.5 34 3 standoff spc tech 2397 35 3 spacer richco nss-4-4-01 4 2 c6,c8 10nf venkel c0603x7r160- 103kne nopop 603 12 1 j3 jmpr_2pin nopop 22 1 r1 100 venkel cr0603-16w- 1000ft nopop 603 25 3 r6,r10,r12 0 ? venkel cr0603-16w- 000t nopop 603 30 2 tp1,tp2 test_points nopop 14 1 j13 14_m_ header 3m n2514-6002rb nopop mhc14k- nd 14pinmdualheader_p1 pitch 19 9 j18,j21,j22, j23,j25 jmpr_1pin nopop 1pin_p1pitch item qty reference part mfr mfrpartnum bom digikey footprint
SI5317-EVB rev. 0.1 11 6. layout figure 5. silkscreen top
SI5317-EVB 12 rev. 0.1 figure 6. layer 1
SI5317-EVB rev. 0.1 13 figure 7. layer 2?ground plane
SI5317-EVB 14 rev. 0.1 figure 8. layer 3
SI5317-EVB rev. 0.1 15 figure 9. layer 4
SI5317-EVB 16 rev. 0.1 figure 10. layer 5, filt_dut_pwr
SI5317-EVB rev. 0.1 17 figure 11. layer 6, bottom
SI5317-EVB 18 rev. 0.1 figure 12. bottom silkscreen
SI5317-EVB rev. 0.1 19 7. factory defau lt configuration the above jumper settings result in the following: ? sfout = cmos output ? 10.0 mhz input clock ? 10.0 mhz output clock ? bw =88 hz ? rate[1:0] = 114.285 mhz 3rd overtone crystal j12 pin jumper j12.1 not used ? j12.2 sfout0 h j12.3 sfout1 l j12.4 frqsel0 l j12.5 frqsel1 m j12.6 frqsel2 m j12.7 frqsel3 h j12.8 frqtbl l j12.9 bwsel0 m j12.10 bswel1 h j12.11 dbl2_by l j12.12 not used ? j12.13 rate0 m j12.14 rate1 m
SI5317-EVB 20 rev. 0.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of t he silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.

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