AE45X h h i i g g h h s s e e c c u u r r i i t t y y 1 1 6 6 - - b b i i t t d d u u a a l l i i n n t t e e r r f f a a c c e e s s m m a a r r t t c c a a r r d d m m i i c c r r o o c c o o n n t t r r o o l l l l e e r r features iso/iec 14443 t ype b or c contactless inte r face data t r ansmission up to 212 kbit/s iso 7816 inte r face 32.5 kbytes eep r om 128 kbytes r om 5 kbytes ram 1024 bit coprocessor integ r ated security concept (isc) october 2001 20-071 dual inte r face: the dual inte r face chip AE45X belongs to the high security sma r t card controller family of hitachi. it combines the security features of the iso 7816 compliant standard ae4 products, with the advantages of an additional contactless inte r face according to the iso 14443 type b or c. the AE45X is manufactured using a highly reliable 0.35 ? shrink cmos process providing outstanding memo r y sizes. in contactless mode the power su p ply and bi-directional data t r ansmission is done via a coil connected to the AE45X. the coil is tuned to an ope r ating frequency of 13.56 mhz, basis of a proximity card system. it provides a high data t r ansfer r ate of 212 kbit/s (max) at a distance of up to 10 cm, and ful f ils the requirements of most of the contactless sma r t card a p plications in terms of pe r formance and cost. compared to standard contact based sma r t cards, this system wo r ks without any physical contact between the terminal and the sma r t card, resulting in low maintenance costs and reliable functionality in adve r se environmental conditions. the fast and high security data t r ansfer combined with its convenient handling makes it best suited for various a p plications. additionall y , by using the integ r ated anti-collision method seve r al cards can be ope r ated on one terminal simultaneousl y . integrated security concep t : the AE45X designed under hitachi? integ r ated security concept is ideally suited for high security a p plications. the isc means that security is not just an add-on feature to standard modules or cores, security has been built-in from the sta r t, forming an integ r al pa r t of the whole sma r t card design concept. the whole isc process e.g. secure chip design environment, secured production facilities and secure handling during shipment to the customer are constantly reviewed in order to maximise the ove r all security package. all devices of the ae-series will be evaluated and ce r ti f ied by independent evaluation authorities. many security features such as integ r ated senso r s, distributed layout, r andom number gene r ation, watchdog time r , des engine, firewall management unit (fmu) and power analysis attack protection are included providing a strong on-chip hardware security structure. uniquel y , hitachi sma r t card devices are fabricated using a monos (metal oxide nitride oxide silicon) eep r om structure. monos advantages compared to standard eep r om structures are: high resistance to r adiation disturbance, high reliability and endu r ance. a high pe r formance coprocessor is complementa r y to the design concept ensuring f inal ope r ation system e f f icienc y , a p plication integrity and pe r formance that meet tomorrow? needs toda y . applications: the AE45X ful f ils the requirement of sma r t card a p plications for la r ge memories, high security and high- speed secure authentication, data enc r yption or electronic signature, as well as secure contactless data t r ansmission. this multi-a p plication capability combines the standard
speci f ication item speci f ication process 0.35 ? shrink cmos process cpu ae-4 - high pe r formance 16-bit cpu 16 mbytes linear address space minimum instruction timing: 400 ns for 32-bit addition 2.8 us for 16 x 16-bit multiplication contactless rf inte r face iso 14443 t ype b / c functions carrier frequency 13.56 mhz data r ate up to 212 kbit/s anticollision protocol for usage of seve r al cards simultaneously 512 byte ram eep r om mono s eep r o m process 32 kbytes eep r om 512 bytes ext r a eep r om easy access by single instruction 1 to 64 byte prog r amming with one instruction protected against accidental writing and e r asing data retention minimum 10 yea r s prog r amming & e r asing voltage gene r ation onchip endu r ance greater than 100,000 times e r ase tim e 2ms w rite time 4ms ove r write tim e 2ms r om 128 kbytes ram 4.5 kbytes coprocessor 1024 bit key length 512 byte ram rsa / ecc c r yptog r aphy onchip seve r al security features such as senso r s functions des-engine for calculation of 56 bit des key by hardware minimum e xecution time is 18 clock cycle. w atchdog timer su p po r ts real time os & a p plications with e xact time measurements rng to provide hardware r andom numbe r s fmu firewall management unit to su p po r t multi-a p plication u art pll (phase lock loop) power single voltage power su p ply 4.5 v to 5.5 v 2.7 v to 3.3 v power consumption max 10 ma in ope r ation max 100? in sleep mode (clock stoped) external cloc k input fclk = 1 to 10 mhz at 5 v , fclk = 1 to 5 mhz at 3v ope r ating tempe r ature: standard -25 to +85 c shi p ping form 8 inch wafer sawn wafe r , unsawn wafer chip on tape (cot) module http://ww w .hitach.com/semiconductor/smartcard.html www.hitachi.com/semiconductor to order literature: (800) 285-1601 fax: (510) 683-9700 hitachi semiconductor (america) inc. u.s. headquarters 179 east tasman drive, san jose, ca 95134 sales offices: please visit our website for contact details of other hitachi sales o f f ices:- sma r t card usage such as bankcards with contactless based a p plications for vending machines or passenger tickets. the anti-collision method of the contactless inte r face is pa r ticularly suitable for automatic public t r anspo r t fare collection where one terminal can ope r ate seve r al cards simultaneousl y , preventing queues at the ent r ance gates. other contactless a p plications include access control to a netwo r k or a building, and labelling and logistics involving process t r acking and identi f ication. the move from a single to multi-a p plication on a single chip requires not only additional memo r y for a p plication data sto r age but also features such as firewall management units to provide data integrity between a p plications. the AE45X includes these features and its high speed coprocessor ensures the pe r formance needed for processing of arithmetical data required in today? high security a p plications.
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