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192-macrocell max? epld cy7c341 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 july 19, 2000 features ? 192 macrocells in 12 labs 8 dedicated inputs, 64 bidirectional i/o pin 0.8-micron double-metal cmos eprom technology programmable interconnect array 384 expander product terms available in 84-pin hlcc, plcc, and pga packages functional description the cy7c341 is an erasable programmable logic device (epld) in which cmos eprom cells are used to configure logic functions within the device. the max architecture is 100% user-configurable, allowing the devices to accommo- date a variety of independent logic functions. the 192 macrocells in the cy7c341 are divided into 12 logic array blocks (labs), 16 per lab. there are 384 expander product terms, 32 per lab, to be used and shared by the mac- rocells within each lab. each lab is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. the speed and density of the cy7c341 allows them to be used in a wide range of applications, from replacement of large amounts of 7400-series ttl logic, to complex controllers and multifunction chips. with greater than 37 times the functionality of 20-pin plds, the cy7c341 allows the replacement of over 75 ttl devices. by replacing large amounts of logic, the cy7c341 reduces board space and part count, and increases system reliability. each lab contains 16 macrocells. in labs a, f, g, and l, 8 macrocells are connected to i/o pins and 8 are buried, while for labs b, c, d, e, h, i, j, and k, 4 macrocells are connected to i/o pins and 12 are buried. moreover, in addition to the i/o and buried macrocells, there are 32 single product term logic expanders in each lab. their use greatly enhances the capa- bility of the macrocells without increasing the number of prod- uct terms in each macrocell. logic array blocks there are 12 logic array blocks in the cy7c341. each lab consists of a macrocell array containing 16 macrocells, an ex- pander product term array containing 32 expanders, and an i/o block. the lab is fed by the programmable interconnect array and the dedicated input bus. all macrocell feedbacks go to the macrocell array, the expander array, and the program- mable interconnect array. expanders feed themselves and the macrocell array. all i/o feedbacks go to the programmable in- terconnect array so that they may be accessed by macrocells in other labs as well as the macrocells in the lab in which they are situated. externally, the cy7c341 provides 8 dedicated inputs, one of which may be used as a system clock. there are 64 i/o pins that may be individually configured for input, output, or bidirec- tional data flow. programmable interconnect array the programmable interconnect array (pia) solves intercon- nect limitations by routing only the signals needed by each logic array block. the inputs to the pia are the outputs of every macrocell within the device and the i/o pin feedback of every pin on the device. unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the pia has a fixed delay. this eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. the fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or rac- es are avoided. the result is ease of design implementation, often in a single pass, without the multiple internal logic place- ment and routing iterations required for a programmable gate array to achieve design timing objectives. timing delays timing delays within the cy7c341 may be easily determined using warp ?, warp professional?, or warp enterprise? software. the cy7c341 has fixed internal delays, allowing the user to determine the worst case timing delays for any design. design recommendations for proper operation, input and output pins must be con- strained to the range gnd < (v in or v out ) < v cc . unused inputs must always be tied to an appropriate logic level (either v cc or gnd). each set of v cc and gnd pins must be connect- ed together directly at the device. power supply decoupling capacitors of at least 0.2 f must be connected between v cc and gnd. for the most effective decoupling, each v cc pin should be separately decoupled to gnd, directly at the device. decoupling capacitors should have good frequency response, such as monolithic ceramic types. design security the cy7c341 contains a programmable design security fea- ture that controls the access to the data programmed into the device. if this programmable feature is used, a proprietary de- sign implemented in the device cannot be copied or retrieved. this enables a high level of design control to be obtained since programmed data within eprom cells is invisible. the bit that controls this function, along with all other program data, may be reset simply by erasing the device. max is a registered trademark of altera corporation. warp , warp professional, and warp enterprise are trademarks of cypress semiconductor corporation.
cy7c341 2 selection guide 7c341-25 7c341-30 7c341-35 maximum access time (ns) 25 30 35 maximum operating current (ma) commercial 380 380 380 industrial 480 480 480 military 480 480 480 maximum standby current (ma) commercial 360 360 360 industrial 435 435 435 military 435 435 435
cy7c341 3 p i a macrocell 1 macrocell 2 macrocell 3 macrocell 4 macrocell 5 macrocell 6 macrocell 7 macrocell 8 macrocell 97 macrocell 98 macrocell 99 macrocell 100 macrocell 101 macrocell 102 macrocell 103 macrocell 104 macrocell 9 ? 16 macrocell 105 ? 112 macrocell 17 macrocell 18 macrocell 19 macrocell 20 macrocell 113 macrocell 114 macrocell 115 macrocell 116 macrocell 21 ? 32 macrocell 117 ? 128 macrocell 33 macrocell 34 macrocell 35 macrocell 36 macrocell 129 macrocell 130 macrocell 131 macrocell 132 macrocell 37 ? 48 macrocell 133 ? 144 macrocell 49 macrocell 50 macrocell 51 macrocell 52 macrocell 145 macrocell 146 macrocell 147 macrocell 148 macrocell 53 ? 64 macrocell 149 ? 160 macrocell 65 macrocell 66 macrocell 67 macrocell 68 macrocell 161 macrocell 162 macrocell 163 macrocell 164 macrocell 69 ? 80 macrocell 165 ? 176 macrocell 81 macrocell 82 macrocell 83 macrocell 84 macrocell 85 macrocell 86 macrocell 87 macrocell 88 macrocell 177 macrocell 178 macrocell 179 macrocell 180 macrocell 181 macrocell 182 macrocell 183 macrocell 184 macrocell 89 ? 96 macrocell 185 ? 192 input (c6) 84 input (c7) 83 input (l7) 44 input (j7) 43 1 (a6) input/clk 2 (a5) input 41 (k6) input 42 (j6) input 4(c5) 5(a4) 6(b4) 7(a3) 8(a2) 9(b3) 10 (a1) 11 (b2) 12 (c2) 13 (b1) 14 (c1) 15 (d2) 16 (d1) 17 (e3) 20 (f2) 21 (f3) 22 (g3) 23 (g1) 25 (f1) 26 (h1) 27 (h2) 28 (j1) 29 (k1) 30 (j2) 31 (l1) 32 (k2) 33 (k3) 34 (l2) 35 (l3) 36 (k4) 37 (l4) 38 (j5) 46 (l6) 47 (l8) 48 (k8) 49 (l9) 50 (l10) 51 (k9) 52 (l11) 53 (k10) 54 (j10) 55 (k11) 56 (j11) 57 (h10) 58 (h11) 59 (f10) 62 (g9) 63 (f9) 64 (f11) 65 (e11) 67 (e9) 68 (d11) 69 (d10) 70 (c11) 71 (b11) 72 (c10) 73 (a11) 74 (b10) 75 (b9) 76 (a10) 77 (a9) 78 (b8) 79 (a8) 80 (b6) system clock 3, 24, 45, 66 (b5, g2, k7, e10) 18, 19, 39, 40, 60, 61, 81, 82 (e1, e2, k5, l5, g10, g11, a7, b7) v cc gnd ( ) ? pertain to 84-pin pga package lab a lab b lab c lab d lab e lab f lab g lab h lab i lab j lab k lab l c341-1 logic block diagram
cy7c341 4 design security (continued) the cy7c341 is fully functionally tested and guaranteed through complete testing of each programmable eprom bit and all internal logic elements thus ensuring 100% programming yield. the erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. the devices also contain on-board logic test circuitry to allow verification of function and ac specification once encapsulat- ed in non-windowed packages. pin configurations i/o top view plcc/hlcc 9 8 6 7 5 13 14 12 11 10 49 48 58 59 60 23 24 26 25 27 15 16 47 46 43 28 33 20 21 19 18 17 22 34 35 37 36 38 39 42 41 43 44 45 40 66 65 63 64 62 61 v cc 7c341 c341-2 67 68 69 74 72 73 71 70 84 83 81 82 80 21 79 i/o input i/o input/clk input input gnd gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o v cc v cc input gnd gnd input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o v cc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc input input/ clk gnd i/o i/o i/o i/o v cc i/o i/o i/o gnd gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc input i/o gnd gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc i/o i/o i/o gnd gnd i/o i/o i/o i/o i/o i/o pga bottom view 7c341 c341-3 input gnd i/o i/o i/o i/o i/o i/o i/o l k j h g f e d c b a 123456 78910 11 i/o i/o i/o i/o i/o input input input input i/o i/o i/o i/o i/o i/o i/o i/o 53 52 51 50 30 29 31 32 i/o i/o i/o i/o i/o i/o i/o i/o 54 55 56 57 i/o i/o i/o i/o 77 78 76 75 i/o i/o i/o i/o i/o gnd input input gnd i/o figure 1. cy7c341 internal timing model logic array control delay t lac expander delay t exp clock delay t ic t rd t comb t latch input delay t in pia delay t pia register output delay t od t xz t zx logic array delay t lad logic array delay t fd i/o delay t io input/ output input c341-4 system clock delay t ics t rh t rsu t pre t clr
cy7c341 5 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .......................................? 65 c to +150 c ambient temperature with power applied .................................................... 0 c to +70 c maximum junction temperature (under bias)................................................................. 150 c supply voltage to ground potential ..................? 2.0v to +7.0v maximum power dissipation...................................2500 mw dc v cc or gnd current......................................................500 ma dc output current, per pin ........................ ? 25 ma to +25 ma dc input voltage [1] ................................................? 3.0v to +7.0v dc program voltage..................................................... 13.0v static discharge voltage ................................................. > 1100v (per mil-std-883, method 3015) operating range range ambient temperature v cc commercial 0 c to +70 c 5v 5% industrial ? 40 c to +85 c 5v 10% military ? 55 c to +125 c (case) 5v 10% electrical characteristics over the operating range [2] parameter description test conditions min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8 ma 0.45 v v ih input high level 2.2 v cc +0.3 v v il input low level ? 0.3 0.8 v i ix input current gnd v in v cc ? 10 +10 a i oz output leakage current v o = v cc or gnd ? 40 +40 a i os output short circuit current v cc = max., v out = gnd [3, 4] ? 30 ? 90 ma i cc1 power supply current (standby) v i = v cc or gnd (no load) com ? l 360 ma mil/ind 435 ma i cc2 power supply current [5] v i = v cc or gnd (no load) f = 1.0 mhz [3, 5] com ? l 380 ma mil/ind 480 ma t r (recommended) input rise time 100 ns t f (recommended) input fall time 100 ns capacitance [6] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 20 pf notes: 1. minimum dc input is ? 0.3v. during transitions, the inputs may undershoot to ? 2.0v for periods less than 20 ns. 2. typical values are for t a = 25 c and v cc = 5v. 3. guaranteed but not 100% tested. 4. not more than one output should be tested at a time. duration of the short circuit should not be more than one second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. 5. this parameter is measured with device programmed as a 16-bit counter in each lab and is tested periodically by sampling prod uction material. 6. part (a) in ac test load and waveforms is used for all parameters except t er and t xz , which is used for part (b) in ac test load and waveforms. all external timing parameters are measured referenced to external pins of the device.
cy7c341 6 ac test loads and waveforms 3.0v 5v output r1 464 ? r2 250 ? 50 pf including jig and scope gnd 90% 10% 90% 10% <6ns <6 ns 5v output r1 464 ? r2 250 ? (a) (b) output 1.75v equivalent to: th venin equivalent (commercial/military) c341-5 c341-6 all input pulses t r t f 5pf 163 ? external synchronous switching characteristics over the operating range [6] parameter description 7c341-25 7c341-30 7c341-35 min. max min. max min. max unit t pd1 dedicated input to combinatorial output delay [7] com ? l253035ns mil 253035 t pd2 i/o input to combinatorial output delay [8] com ? l404555ns mil 404555 t pd3 dedicated input to combinatorial output delay with expander delay [9] com ? l374455ns mil 374455 t pd4 i/o input to combinatorial output delay with expander delay [3, 10] com ? l525975ns mil 525975 t ea input to output enable delay [3, 7] com ? l253035ns mil 253035 t er input to output disable delay [6] com ? l253035ns mil 253035 t co1 synchronous clock input to output delay com ? l141620ns mil 141620 t co2 synchronous clock to local feedback to combinatorial output [3, 11] com ? l303542ns mil 303542 t s1 dedicated input or feedback set-up time to synchronous clock output [6, 12] com ? l152025ns mil 15 20 25 t s2 i/o input set-up time to synchronous clock input [8] com ? l303945ns mil 30 39 45 notes: 7. this specification is a measure of the delay from input signal applied to a dedicated input to combinatorial output on any ou tput pin. this delay assumes no expander terms are used to form the logic function. when this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. if an input signal is applied to an i/o pin an additional delay equal to t pia should be added to the comparable delay for a dedicated input. if expanders are used, add the maximum expander delay t exp to the overall delay for the comparable delay without expanders. 8. this specification is a measure of the delay from input signal applied to an i/o macrocell pin to any output. this delay assu mes no expander terms are used to form the logic function. 9. this specification is a measure of the delay from an input signal applied to a dedicated input to combinatorial output on any output pin. this delay assumes expander terms are used to form the logic functions and includes the worst-case expander logic delay for one pass through the e xpander logic. 10. this specification is a measure of the delay from an input signal applied to an i/o macrocell pin to any output. this delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. this param eter is tested periodically by sampling production material. 11. this specification is a measure of the delay from synchronous register clock to internal feedback of the register output sig nal to the input of the lab logic array and then to a combinatorial output. this delay assumes no expanders are used, register is synchronously clocked and all feedbac k is within the same lab. this parameter is tested periodically by sampling production material. 12. if data is applied to an i/o input for capture by a macrocell register, the i/o pin set-up time minimums should be observed. these parameters are t s2 for synchronous operation and t as2 for asynchronous operation.
cy7c341 7 t h input hold time from synchronous clock input [6] com ? l0 0 0 ns mil 0 0 0 t wh synchronous clock input high time com ? l 8 10 12.5 ns mil 8 10 12.5 t wl synchronous clock input low time com ? l 8 10 12.5 ns mil 8 10 12.5 t rw asynchronous clear width [3, 6] com ? l253035ns mil 25 30 35 t ro asynchronous clear to registered output delay [5] com ? l253035ns mil 253035 t rr asynchronous clear recovery [3, 7] com ? l253035ns mil 25 30 35 t pw asynchronous preset width [3, 6] com ? l253035ns mil 25 30 35 t pr asynchronous preset recovery time [3, 6] com ? l253035ns mil 25 30 35 t po asynchronous preset to registered output delay [6] com ? l253035ns mil 253035 t cf synchronous clock to local feedback input [3, 13] com ? l335ns mil 335 t p external synchronous clock period (1/f max3 ) [3] com ? l162025ns mil 16 20 25 f max1 external feedback maximum frequency (1/(t co1 + t s1 )) [3, 14] com ? l 34.5 27.7 22.2 mhz mil 34.5 27.7 22.2 f max2 internal local feedback maximum frequency, lesser of (1/(t s1 + t cf )) or (1/t co1 ) [3, 15] com ? l55.5 43 33 mhz mil 55.5 43 33 f max3 data path maximum frequency, least of 1/(t wl + t wh ), 1/(t s1 + t h ), or (1/t co1 ) [3, 16] com ? l62.55040.0mhz mil62.55040.0 f max4 maximum register toggle frequency (1/(t wl + t wh )) [3, 17] com ? l62.55040.0mhz mil62.55040.0 t oh output data stable time from syn- chronous clock input [3, 18] com ? l3 3 3 ns mil 3 3 3 notes: 13. this specification is a measure of the delay associated with the internal register feedback path. this is the delay from syn chronous clock to lab logic array input. this delay plus the register set-up time, t s1 , is the minimum internal period for an internal synchronous state machine configuration. this delay is for feedback within the same lab. this parameter is tested periodically by sampling production material. 14. this specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration w ith external feedback can operate. it is assumed that all data inputs and feedback signals are applied to dedicated inputs. all feedback is assumed to be local originating within the same lab. 15. this specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can ope rate. if register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/t co1 . 16. this frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to out put pin). this assumes data input signals are applied to dedicated input pins and no expander logic is used. if any of the data inputs are i/o pins, t s2 is the appropriate t s for calculation. 17. this specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycle by a clock signal applied to the dedicated clock input pin. 18. this parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin. external synchronous switching characteristics over the operating range [6] (continued) parameter description 7c341-25 7c341-30 7c341-35 min. max min. max min. max unit
cy7c341 8 t aco1 dedicated asynchronous clock input to output delay [6] com ? l253035ns mil 253035 t aco2 asynchronous clock input to local feedback to combinatorial output [19] com ? l404655ns mil 404655 t as1 dedicated input or feedback set-up time to asynchronous clock input [6] com ? l5 6 8 ns mil 5 6 8 t as2 i/o input set-up time to asynchronous clock input [6] com ? l202730ns mil 20 27 30 t ah input hold time from asynchronous clock input [6] com ? l6 8 10 ns mil 6 8 10 t awh asynchronous clock input high time [6] com ? l111416ns mil 11 14 16 t awl asynchronous clock input low time [6, 20] com ? l 9 11 14 ns mil 9 11 14 t acf asynchronous clock to local feedback input [21] com ? l151822ns mil 151822 t ap external asynchronous clock period (1/f max4 ) com ? l202530ns mil 20 25 30 f maxa1 external feedback maximum fre- quency in asynchronous mode 1/(t aco1 + t as1 ) [22] com ? l33.3 27 23 mhz mil 33.3 27 23 f maxa2 maximum internal asynchronous frequency [23] com ? l 50 40 33.3 mhz mil 50 40 33.3 f maxa3 data path maximum frequency in asynchronous mode [24] com ? l 40 33.3 28.5 mhz mil 40 33.3 28.5 f maxa4 maximum asynchronous register toggle frequency 1/(t awh + t awl ) [25] com ? l 50 40 33.3 mhz mil 50 40 33.3 t aoh output data stable time from asyn- chronous clock input [26] com ? l151515ns mil 15 15 15 notes: 19. this specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the lab logic array and then to a combinatorial output. this delay assumes no expanders are used in the logic of combinatorial output o r the asynchronous clock input. the clock signal is applied to the dedicated clock input pin and all feedback is within a single lab. this parameter is tested periodically by sampling production material. 20. this parameter is measured with a positive-edge-triggered clock at the register. for negative-edge triggering, the t awh and t awl parameters must be swapped. if a given input is used to clock multiple registers with both positive and negative polarity, t awh should be used for both t awh and t awl . 21. this specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock t o lab logic array input. this delay plus the asynchronous register set-up time, t as1 , is the minimum internal period for an internal asynchronously clocked state machine configuration. this delay is for feedback within the same lab, and assumes there is no expander logic in the clock path and the clock input signal is applied to a dedicated input pin. this parameter is tested periodically by sampling production material. 22. this specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. it is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no ex pander logic is employed in the clock signal path or data path. 23. this specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal -only feedback can operate. this parameter is determined by the lesser of (1/t acf + t as1 )) or (1/(t awh +t awl )). if register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/t aco1 . 24. this frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. this s pecification is determined by the least of 1/(t awh + t awl ), 1/(t as1 + t ah ) or 1/t aco1 . it assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 25. this specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 26. this parameter indicates the minimum time that the previous register output data is maintained on the output after an asynch ronous register clock input applied to an external dedicated input pin. external synchronous switching characteristics over the operating range [6] (continued) parameter description 7c341-25 7c341-30 7c341-35 min. max min. max min. max unit
cy7c341 9 internal switching characteristics over the operating range [2] 7c341-25 7c341-30 7c341-35 parameter description min. max min. max min. max unit t in dedicated input pad and buffer delay com ? l579ns mil 5 7 9 t io i/o input pad and buffer delay com ? l669ns mil 6 6 9 t exp expander array delay com ? l 121420ns mil 121420 t lad logic array data delay com ? l 121416ns mil 121416 t lac logic array control delay com ? l 101213ns mil 101213 t od output buffer and pad delay com ? l556ns mil 5 5 6 t zx output buffer enable delay [27] com ? l 101113ns mil 101113 t xz output buffer disable delay com ? l 101113ns mil 101113 t rsu register set-up time relative to clock signal at register com ? l6 8 10 ns mil 6 8 10 t rh register hold time relative to clock signal at register com ? l6 8 10 ns mil 6 8 10 t latch flow-through latch delay com ? l344ns mil 3 4 4 t rd register delay com ? l122ns mil 1 2 2 t comb transparent mode delay [28] com ? l344ns mil 3 4 4 t ch clock high time com ? l 8 10 12.5 ns mil 8 10 12.5 t cl clock low time com ? l 8 10 12.5 ns mil 8 10 12.5 t ic asynchronous clock logic delay com ? l 141618ns mil 141618 t ics synchronous clock delay com ? l223ns mil 2 2 3 t fd feedback delay com ? l112ns mil 1 1 2 t pre asynchronous register preset time com ? l567ns mil 5 6 7 t clr asynchronous register clear time com ? l567ns mil 5 6 7
cy7c341 10 t pcw asynchronous preset and clear pulse width com ? l567ns mil567 t pcr asynchronous preset and clear recovery time com ? l567ns mil567 t pia programmable interconnect array delay com ? l 141620ns mil 16 20 notes: 27. sample tested only for an output change of 500 mv. 28. this specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macroce ll is configured for combi- natorial operation. internal switching characteristics over the operating range [2] (continued) 7c341-25 7c341-30 7c341-35 parameter description min. max min. max min. max unit switching waveforms external combinatorial valid output dedicated input/ i/o input combinatorial output combinatorial registered output c341-7 high impedance 3-state high-impedance 3-st ate t er t ea t pd1 /t pd2 external synchronous t h t s1 t wh t wl t rr /t pr t rw /t pw t oh t co1 t ro /t po t co2 c341-8 dedicated input/ i/o input synchronous clock asynchronous clear/preset registered outputs combinatorial output from registered feedback [7] [7] [10]
cy7c341 11 switching waveforms (continued) external asynchronous t ah t as1 t awh t awl t rr /t pr t rw /t pw t aoh t aco1 t ro /t po t aco2 asynchronous clock input asynchronous registered outputs dedicatedinput/ i/oinput asynchronous clear/preset combinatorial output from asynch. registered c341-9 [7] [7] feedback internal combinatorial t in t io t pia t exp t lac ,t lad c341-10 input pin expander i/o pin logic array array delay output logic array input
cy7c341 12 switching waveforms (continued) internal asynchronous t io t awh t awl t f t in t ic t rsu t rh t rd ,t latch t fd t clr ,t pre t fd clock pin logic array logic array clock from data from clock into logic array register output to another lab t pia to local lab register output logic array c341-11 t r internal synchronous t ch t cl t ih t ics t rsu t rh c341-12 system cl ock pin system clock at register data from logic array internal synchronous c341-13 t xz t xz t zx t od high impedance state clock from logic array logic array data from output pin t rd
cy7c341 13 military specifications group a subgroup testing document #: 38-00499-b ordering information speed (ns) ordering code package name package type operating range 25 cy7c341-25hc/hi h84 84-lead windowed leaded chip carrier commercial/industrial cy7c341-25jc/ji j83 84-lead plastic leaded chip carrier cy7c341-25rc/ri r84 84-lead windowed pin grid array 30 cy7c341-30hc/hi h84 84-lead windowed leaded chip carrier commercial/industrial cy7c341-30jc/ji j83 84-lead plastic leaded chip carrier cy7c341-30rc/ri r84 84-lead windowed pin grid array cy7c341-30hmb h84 84-lead windowed leaded chip carrier military cy7c341-30rmb r84 84-lead windowed pin grid array 35 cy7c341-35hc/hi h84 84-lead windowed leaded chip carrier commercial/industrial cy7c341-35jc/ji j83 84-lead plastic leaded chip carrier cy7c341-35rc/ri r84 84-lead windowed pin grid array cy7c341-35hmb h84 84-lead windowed leaded chip carrier military cy7c341-35rmb r84 84-lead windowed pin grid array dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc1 1, 2, 3 switching characteristics parameter subgroups t pd1 7, 8, 9, 10, 11 t pd2 7, 8, 9, 10, 11 t pd3 7, 8, 9, 10, 11 t co1 7, 8, 9, 10, 11 t s1 7, 8, 9, 10, 11 t h 7, 8, 9, 10, 11 t aco1 7, 8, 9, 10, 11 t aco2 7, 8, 9, 10, 11 t as1 7, 8, 9, 10, 11 t ah 7, 8, 9, 10, 11
cy7c341 14 package diagrams 84-leaded windowed leaded chip carrier h84 51-80081
cy7c341 ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 84-lead plastic leaded chip carrier j83 51-85006-a 84-lead windowed pin grid array r84 51-80026-a

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