itpm - er02 - it8172 date:06/17/2002 IT8172G v0.6 errata 02 released on 6/17/2002 1 errata v0.2 for i t 8172g v0.6 note: the corrections have been highlighted in red in the corresponding pages attached. errata version section correction page 0.2 4 in table 4 - 2, the signal vlmdown/gpio14 should be corrected to vlmdown/gpio13 and the signal vlmmute/gpio13 should be corrected to vlmmute/ gpio14. 1 5 0.1 1 in the ata 33 ide bus controller features, one note will be added: there is one special condition in pci ide function bit decoding. please refer to the IT8172G application note, ittm - an - 0104 0. 1 6 in table 6 - 7, added one note for ide controller: ? there is one special condition in pci ide function bit decoding. please refer to the IT8172G application note, ittm - an - 01040.? 39
www.ite.com.tw IT8172G v0.6 errata 02 released on 6/17/2002 pin configuration table 4 - 2. pin - out tables in alphabetical order [continued] si gnal pin signal pin signal pin signal pin md18 ac18 par k3 pcrw# ad15 tck d5 md19 ad18 pca0/fra0 ac8 pe d10 tdi a3 md20 af20 pca1/fra1 ae8 pme# t1 tdo b4 md21 ae20 pca2/fra2 af7 ppd0 a6 test0 d6 md22 ad19 pca3/fra3 ad8 ppd1 b7 test1 ad22 md23 ae21 pc a4/fra4 ae7 ppd2 c8 test2 ac21 md24 ab26 pca5/fra5 af6 ppd3 a7 test3 ae23 md25 y24 pca6/fra6 ad7 ppd4 a10 tms c4 md26 aa26 pca7/fra7 ae6 ppd5 c11 trdy# l3 md27 w24 pca8/fra8 af5 ppd6 e11 trst# b3 md28 v23 pca9/fra9 af4 ppd7 b11 txd d8 md29 v24 pca10 /fra10 ae5 pwrbtm d16 usbd1m b18 md30 v25 pca11/fra11 ad6 pwron# b16 usbd1p d17 md31 t22 pca12/fra12 ac7 ras# af25 usbd2m c18 mwe# af23 pca13/fra13 af3 rdwr#/ validin#/evalid# k26 usbd2p a19 nmi# c26 pca14/fra14 ae4 rdy#/rdrdy# p23 usbovr# a20 pad0 g4 pca15/fra15 ad5 req0# v3 usbpen# d18 pad1 e1 pca16/fra16 ac6 req1# u1 vccrtc b17 pad2 f2 pca17/fra17 af2 req2# t3 vcc3 ab10 pad3 g3 pca18/fra18 ae3 reset# m22 vcc3 ab17 pad4 h4 pca19/fra19 ad4 ri# a5 vcc3 e10 pad5 f1 pca20/fra20 ac5 romsiz1 d13 vcc3 e17 pad6 g2 pca21/fra21 af1 rtcrst# a16 vcc3 k5 pad7 h3 pca22/fra22 ae2 rts# c7 vcc3 k22 pad8 g1 pca23/fra23 ad3 rxd a4 vcc3 u5 pad9 h2 pca24/fra24 ac4 scrclk0 a14 vcc3 u22 pad10 j3 pca25/fra25 ae1 scrclk1/gnt3# a15 vcc5 e12 pad11 l5 pcas# ae16 scrio 0 b14 vcc5 e13 pad12 h1 pcd0/frd0 af11 scrio1/req3# d14 vcch e14 pad13 k4 pcd1/frd1 ae11 scrpfet0# a13 vlmdown/ gpio13 a1 pad14 m5 pcd2/frd2 ad11 scrpfet1#/ req4# b15 vlmmute/ gpio14 d4 pad15 j2 pcd3/frd3 af10 scrpres0# c14 vlmup/gpio1 2 b2 pad16 m3 pc d4/frd4 ab11 scrpres1#/ intd# e15 vss m12 pad17 m2 pcd5/frd5 ad10 scrrst0# b13 vss m13 pad18 m1 pcd6/frd6 ac9 scrrst1#/ gnt4# c15 vss m14 pad19 n4 pcd7/frd7 ad9 serirq c13 vss m15 pad20 p5 pcd8/frd8 ab4 serr# k2 vss n12 pad21 n3 pcd9/frd9 ac2 siz0 ac 1 5 vss n13 pad22 n2 pcd10/frd10 aa4 siz1 ae15 vss n14 pad23 n1 pcd11/frd11 ab2 slct b9 vss n15 pad24 p4 pcd12/frd12 y4 slin# b10 vss p12 pad25 p2 pcd13/frd13 aa2 spdifo b1 vss p13 pad26 p1 pcd14/frd14 aa1 stb# a8 vss p1 4 pad27 r1 pcd15/frd15 y2 stop# k1 vss p15 pad28 r5 pcds# af16 swrst# v26 vss r12 pad29 r2 pciclk u4 sz0/cmd6 l23 vss r13 pad30 r3 pcirst# w1 sz1/cmd7 j25 vss r14 pad31 r4 pclk ad16 sz2/cmd8 l22 vss r15
www.it e.com.tw IT8172G v0.6 errata 01 released on 12/25/2001 1 fea tures 1. features n cpu interface - directly connects the following 32 - bit risc micropro cessor interfaces mips 5 ? nec vr5432, qed rm5231, rm5230 mips 4 ? nec vr4310 hitachi ? sh4 (7750) - supports cpu bus frequency up to 100 mhz n sdram controller - 32 - bit data bus interface - supports two banks of sdram, up to 128 mb in size - provides deep buffer for cpu to sdram burst transfer - provides deep buffer for pci to sdram burst transfer - supports bus frequency at up to 100 mhz n flash/rom interface - flash memory area support up to 64m bytes, with 8 - bit, 16 - bit and 32 - bit data access capability - rom area size up to 4m bytes, with 8 - bit, 16 - bit and 32 - bit data access capability - maximum 12 chip - select signals supported - shared with 68k like peripheral bus n peripheral bus controller * - glueless 68k like bus interface - no external latch require d for addressing - 8 - bit and 16 - bit data bus interface - shared with the flash/rom interface - supports up to four dma channels - cycle posting to avoid performance hit from slow device n pci bus controller - provides cpu to pci buffers for burst transfer - pci arbiter supports up to 5 individual bus master devices - 33 mhz bus frequency - 32 - bit data bus interface n interrupt controller - supports a maskable interrupt (int0#) to cpu - supports a non - maskable interrupt (nmi#) to cpu for severe events - the priority order of interrupt request lines can be assigned by software - module interrupts can be masked on/off independently by setting the corresponding mask registers n dma controller - supports four channels request for lpc or ecp dma mode data transfer - supports pci bus master accessing to sdram n chaining dma controller - supports four independent software dma channels for transferring data between the sdram and pci devices - supports chaining and non - chaining modes - supports rotating and fixed priori ty types n timers - two 16 - bit auto - reload counters with pre - scale (1,1/4,1/8,1/16) from dividing of the cpu clock - supports the interrupt generation upon the timer time - out - provides one watchdog timer to monitor validout# signal n smart card interface - compliant with personal computer smart card (pc/sc) working group standard - compliant with smart card (iso 7816) protocols - card present detection - supports smart card insertion power on feature - supports one programmable clock frequency, and 7.1 mhz and 3.5 mhz (default) card clocks - supports two channels of smart card interface - supports t=0, t=1 protocol n ata 33 ide bus controller - one channel ide controller for two devices - supports master/dma/slave mode ide - supports any 16 - bit and 32 - bit or dering access to ide data port in bus - slave access mode - built in with 8 - level 32 - bit post - write buffer - built in with 16 - level 16 - bit pre - fetch buffer - compatible with ata/atapi - 4 - compatible to ansi ata proposal pio modes 0, 1, 2, 3, 4 with flow con trol, dma modes 0, 1, 2 and udma modes 0, 1, 2 note 1. there are some special conditions. please refer to the it8172 application note v 2.1, ittm - an - 01033. note 2. there is one special condition in pci ide function bit decoding. please refer to t he IT8172G application note, ittm - an - 01040.
n n n n n n n n n n n n www.ite.com.tw IT8172G v0.6 errata 01 released on 12/25/2001 39 cpu interface table 6 - 7. mapping relation between ad lines and device function bus number device number function number device function ad line 0 0 0 cpu/pci bridge 11 0 1 0 audio digital controller 12 0 1 1 dma controll er 12 0 1 2 chain - dma controller 12 0 1 3 usb host 12 0 1 4 pci/internal bus bridge 12 0 1 5 ide controller * 12 0 1 6 68k controller 12 0 2 - external device #1 13 0 3 - external device #2 14 0 4 - external device #3 15 0 5 - external device #4 16 0 6 - external device #5 17 0 7 - external device #6 18 0 8 - external device #7 19 0 9 - external device #8 20 0 10 - external device #9 21 0 11 - external device #10 22 0 12 - external device #11 23 0 13 - external device #12 24 0 14 - external device #13 25 0 15 - external device #14 26 0 16 - external device #15 27 0 17 - external device #16 28 0 18 - external device #17 29 0 19 - external device #18 30 0 20 - external device #19 31 type 1 configuration access ? if the bus number field of confaddr is not 0, a type 1 configuration is performed on pci bus. the confaddr[23:2] is mapped directly to ad[23:2]. ad[1:0] are driven to 2 01 2 to indicate a type 1 configuration cycle. all other ad lines are driven to 0. * there is one special condition in pci ide function bit decoding. please refer to the IT8172G application note, ittm - an - 01040.
|
