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general description the MAX9392/max9393 dual 2 x 2 crosspoint switches perform high-speed, low-power, and low-noise signal distribution. the MAX9392/max9393 multiplex one of two differential input pairs to either or both low-voltage differ- ential signaling (lvds) outputs for each channel. independent enable inputs turn on or turn off each differ- ential output pair. four lvcmos/lvttl logic inputs (two per channel) con- trol the internal connections between inputs and outputs. this flexibility allows for the following configurations: 2 x 2 crosspoint switch, 2:1 mux, 1:2 splitter, or dual repeater. this makes the MAX9392/max9393 ideal for protection switching in fault-tolerant systems, loopback switching for diagnostics, fanout buffering for clock/data distribution, and signal regeneration. fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the common- mode voltage exceeds the specified range. the MAX9392 provides high-level input fail-safe detection for lvds, hstl, and other gnd-referenced differential inputs. the max9393 provides low-level input fail-safe detection for lvpecl, cml, and other v cc -referenced differential inputs. ultra-low 98ps ( p-p) (max) pseudorandom bit sequence (prbs) jitter ensures reliable communications in high- speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. the high-speed switch- ing performance guarantees 1.5ghz operation and less than 67ps (max) skew between channels. lvds inputs and outputs are compatible with the tia/eia-644 lvds standard. the lvds outputs drive 100 loads. the MAX9392/ max9 393 are offered in a 32-pin tqfp package and operate over the extended temperature range (-40? to +85?). also see the max9390/max9391 for the crossflow version. applications high-speed telecom/datacom equipment central-office backplane clock distribution dslam protection switching fault-tolerant systems features ? 1.5ghz operation with 250mv differential output swing ? 2ps rms (max) random jitter ? ac specifications guaranteed for 150mv differential input ? signal inputs accept any differential signaling standard ? lvds outputs for clock or high-speed data ? high-level input fail-safe detection (MAX9392) ? low-level input fail-safe detection (max9393) ? 3.0v to 3.6v supply voltage range ? lvcmos/lvttl logic inputs control signal routing MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches ________________________________________________________________ maxim integrated products 1 top view MAX9392 max9393 tqfp 32 28 29 30 31 25 26 27 ina1 ina1 v cc asel0 asel1 ina0 ina0 gnd 10 13 15 14 16 11 12 9 enb1 outb1 outb1 gnd enb0 outb0 outb0 v cc 17 18 19 20 21 22 23 outa0 24 v cc outa0 ena0 gnd outa1 outa1 ena1 2 3 4 5 6 7 8 bsel1 inb1 inb1 bsel0 inb0 inb0 1 gnd v cc + part temp range pin- package pkg code MAX9392 ehj -40? to +85? 32 tqfp h32-1 MAX9392ehj+ -40? to +85? 32 tqfp h32-1 max9393 ehj -40? to +85? 32 tqfp h32-1 max9393ehj+ -40? to +85? 32 tqfp h32-1 pin configurations ordering information 19-2913; rev 1; 5/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead-free package. functional diagram and typical operating circuit appear at end of data sheet.
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = 3.0v to 3.6v, r l = 100 1%, en_ _ = v cc , v cm = 0.05v to (v cc - 0.6v) (MAX9392), v cm = 0.6v to (v cc - 0.05v) (max9393), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = 3.3v, |v id | = 0.2v, v cm = 1.2v, t a = +25?, unless otherwise noted.) (notes 1, 2, and 3) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.3v to +4.1v in_ _, in_ _ , out_ _, out_ _ , en_ _, _sel_ to gnd..........................................-0.3v to (v cc + 0.3v) in_ _ to in_ _ .......................................................................... 3v short-circuit duration (out_ _, out_ _ ) ...................continuous continuous power dissipation (t a = +70?) 32-pin tqfp (derate 13.1mw/? above +70?).............................................................1047mw junction-to-ambient thermal resistance in still air 32-pin tqfp............................................................+76.4?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? soldering temperature (10s) ...........................................+300? parameter sym b o l conditions min typ max units lvcmos/lvttl inputs (en_ _, _sel_) input high voltage v ih 2.0 v cc v input low voltage v il 0 0.8 v input high current i ih v in = 2.0v to v cc 020a input low current i il v in = 0 to 0.8v 0 10 a differential inputs (in_ _, ii i i n n n n _ _ _ _ _ _ _ _ ) differential input voltage v id v ild > 0 and v ihd < v cc , figure 1 0.1 3.0 v MAX9392 0.05 v cc - 0.6 input common-mode range v cm max9393 0.6 v cc - 0.05 v MAX9392 |v id | < 3.0v -50 +10 input current i in_ _ , i in_ _ max9393 |v id | < 3.0v -10 +90 ? lvds outputs (out_ _, o o o o u u u u t t t t _ _ _ _ _ _ _ _ ) differential output voltage v od r l = 100 , figure 2 250 350 450 mv change in magnitude of v od between complementary output states v od figure 2 1.0 50 mv offset common-mode voltage v os figure 2 1.125 1.25 1.375 v change in magnitude of v os between complementary output states v os figure 2 1.0 50 mv
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches _______________________________________________________________________________________ 3 ac electrical characteristics (v cc = 3.0v to 3.6v, f in 1.34ghz, t r_in = t f_in = 125ps, r l = 100 ? 1%, |v id | 150mv, v cm = 0.075v to (v cc - 0.6v) (MAX9392 only), v cm = 0.6v to (v cc - 0.075v) (max9393 only), en_ _ = v cc , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = 3.3v, |v id | = 0.2v, v cm = 1.2v, f in = 1.34ghz, t a = +25?, unless otherwise noted.) (note 5) note 1: measurements obtained with the device in thermal equilibrium. all voltages referenced to gnd except v id , v od , and v od . note 2: current into the device defined as positive. current out of the device defined as negative. note 3: dc parameters tested at t a = +25? and guaranteed by design and characterization for t a = -40? to +85?. note 4: current through either output. note 5: guaranteed by design and characterization. limits set at 6 sigma. note 6: t skew is the magnitude difference of differential propagation delays for the same output over same conditions. t skew = |t phl - t plh |. note 7: measured between outputs of the same device at the signal crossing points for a same-edge transition, under the same conditions. note 8: device jitter added to the differential input signal. dc electrical characteristics (continued) (v cc = 3.0v to 3.6v, r l = 100 ? 1%, en_ _ = v cc , v cm = 0.05v to (v cc - 0.6v) (MAX9392), v cm = 0.6v to (v cc - 0.05v) (max9393), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = 3.3v, |v id | = 0.2v, v cm = 1.2v, t a = +25?, unless otherwise noted.) (notes 1, 2, and 3) parameter sym b o l conditions min typ max units v out_ _ or v out_ _ = 0 30 40 output short-circuit current (either output shorted to gnd) |i os | v id = 100m v ( n ote 4) v out_ _ = v out_ _ = 0 18 24 ma output short-circuit current (outputs shorted together) |i osb | v id = 100mv, v out_ _ = v out_ _ (note 4) 5.0 12 ma supply current supply current i cc r l = 100 , en_ _ = v cc 68 98 ma parameter sym b o l conditions min typ max units _sel_ to switched output t switch figure 3 1.1 ns disable time to differential output low t phd figure 4 1.7 ns enable time to differential output high t pdh figure 4 1.7 ns switching frequency f max v od > 250mv 1.5 2.2 ghz low-to-high propagation delay t plh figures 1, 5 294 410 574 ps high-to-low propagation delay t phl figures 1, 5 286 402 555 ps pulse skew |t plh - t phl |t skew figures 1, 5 (note 6) 17 104 ps output-to-output skew t ccs figures 5, 6 (note 7) 4 67 ps output low-to-high transition time (20% to 80%) t r figures 1, 5; f in = 100mhz 112 142 185 ps output high-to-low transition time (80% to 20%) t f figures 1, 5; f in = 100mhz 112 145 185 ps added random jitter t rj f in_ _ = 1.34ghz, clock pattern (note 8) 2 ps rms added deterministic jitter t dj 1.34gbps, 2 23 - 1 prbs (note 8) 60 98 ps p-p
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches 4 _______________________________________________________________________________________ typical operating characteristics (v cc = +3.3v, |v id | = 0.2v, v cm = +1.2v, f in = 1.34ghz, t a = +25?, unless otherwise noted.) supply current vs. temperature MAX9392 toc01 temperature ( c) supply current (ma) 60 35 10 -15 55 60 65 70 75 80 50 -40 85 v cc = 3.6v v cc = 3.0v v cc = 3.3v 0 150 100 50 200 250 350 300 400 0 0.4 0.6 0.2 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 output amplitude vs. frequency MAX9392 toc02 frequency (ghz) output amplitude (mv) output rise and fall times vs. temperature MAX9392 toc03 temperature ( c) rise/fall time (ps) 60 35 10 -15 130 140 150 160 170 180 120 -40 85 f in = 100mhz t f t r 350 380 370 360 390 400 410 420 430 440 450 -40 10 -15 356085 propagation delay vs. temperature MAX9392 toc04 temperature ( c) propagation delay (ps) MAX9392 differential input current vs. temperature MAX9392 toc05 temperature ( c) input current ( a) 60 35 10 -15 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 -50 -40 85 v in = 3.0v v in = 0.1v max9393 differential input current vs. temperature MAX9392 toc06 temperature ( c) input current ( a) 60 35 10 -15 10 20 30 40 50 60 70 0 -40 85 v in = 3.2v v in = 0.3v MAX9392 input current vs. v ihd MAX9392 toc07 v ihd (v) input current ( a) 3.3 3.0 2.4 2.7 0.6 0.9 1.2 1.5 1.8 2.1 0.3 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 -50 0 3.6 v cc = 3v in_ _ or in_ _ = gnd v cc = 3.6v max9393 input current vs. v ild MAX9392 toc08 v ild (v) input current ( a) 3.3 3.0 2.4 2.7 0.6 0.9 1.2 1.5 1.8 2.1 0.3 0 10 20 30 40 50 60 70 80 -10 03.6 v cc = 3v v cc = 3.6v in_ _ or in_ _ = v cc
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches _______________________________________________________________________________________ 5 pin name function 1, 12, 20, 25 gnd ground 2 inb0 lvds/hstl (MAX9392) or lvpecl/cml (max9393) noninverting input. an internal 128k resistor to v cc pulls the input high when unconnected (MAX9392). an internal 68k resistor to gnd pulls the input low when unconnected (max9393). 3 inb0 lvds/hstl (MAX9392) or lvpecl/cml (max9393) inverting input. an internal 128k resistor to v cc pulls the input high when unconnected (MAX9392). an internal 68k resistor to gnd pulls the input low when unconnected (max9393). 4 bsel0 input select for b0 output. selects the differential input to reproduce at the b0 differential outputs. connect bsel0 to gnd or leave open to select the inb0 ( inb0 ) set of inputs. connect bsel0 to v cc to select the inb1 ( inb1 ) set of inputs. an internal 435k resistor pulls bsel0 low when unconnected. 5, 16, 24, 29 v cc power-supply input. bypass each v cc to gnd with 0.1? and 0.01? ceramic capacitors. install both bypass capacitors as close to the device as possible, with the 0.01? capacitor closest to the device. 6 inb1 lvds/hstl (MAX9392) or lvpecl/cml (max9393) noninverting input. an internal 128k resistor to v cc pulls the input high when unconnected (MAX9392). an internal 68k resistor to gnd pulls the input low when unconnected (max9393). 7 inb1 lvds/hstl (MAX9392) or lvpecl/cml (max9393) inverting input. an internal 128k resistor to v cc pulls the input high when unconnected (MAX9392). an internal 68k resistor to gnd pulls the input low when unconnected (max9393). 8 bsel1 input select for b1 output. selects the differential input to reproduce at the b1 differential outputs. connect bsel1 to gnd or leave open to select the inb0 ( inb0 ) set of inputs. connect bsel1 to v cc to select the inb1 ( inb1 ) set of inputs. an internal 435k resistor pulls bsel1 low when unconnected. 9 enb1 b1 output enable. drive enb1 high to enable the b1 lvds outputs. an internal 435k resistor pulls enb1 low when unconnected. 10 outb1 b1 lvds inverting output. connect a 100 termination resistor between outb1 and outb1 at the receiver inputs to ensure proper operation. 11 outb1 b1 lvds noninverting output. connect a 100 termination resistor between outb1 and outb1 at the receiver inputs to ensure proper operation. 13 enb0 b0 output enable. drive enb0 high to enable the b0 lvds outputs. an internal 435k resistor pulls enb0 low when unconnected. 14 outb0 b0 lvds inverting output. connect a 100 termination resistor between outb0 and outb0 at the receiver inputs to ensure proper operation. 15 outb0 b0 lvds noninverting output. connect a 100 termination resistor between outb0 and outb0 at the receiver inputs to ensure proper operation. pin description
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches 6 _______________________________________________________________________________________ pin name function 17 ena1 a1 output enable. drive ena1 high to enable the a1 lvds outputs. an internal 435k resistor pulls ena1 low when unconnected. 18 outa1 a1 lvds inverting output. connect a 100 termination resistor between outa1 and outa1 at the receiver inputs to ensure proper operation. 19 outa1 a1 lvds noninverting output. connect a 100 termination resistor between outa1 and outa1 at the receiver inputs to ensure proper operation. 21 ena0 a0 output enable. drive ena0 high to enable the a0 lvds outputs. an internal 435k resistor pulls ena0 low when unconnected. 22 outa0 a0 lvds inverting output. connect a 100 termination resistor between outa0 and outa0 at the receiver inputs to ensure proper operation. 23 outa0 a0 lvds noninverting output. connect a 100 termination resistor between outa0 and outa0 at the receiver inputs to ensure proper operation. 26 ina0 lvds/hstl (MAX9392) or lvpecl/cml (max9393) noninverting input. an internal 128k resistor to v cc pulls the input high when unconnected (MAX9392). an internal 68k resistor to gnd pulls the input low when unconnected (max9393). 27 ina0 lvds/hstl (MAX9392) or lvpecl/cml (max9393) inverting input. an internal 128k resistor to v cc pulls the input high when unconnected (MAX9392). an internal 68k resistor to gnd pulls the input low when unconnected (max9393). 28 asel0 input select for a0 output. selects the differential input to reproduce at the a0 differential outputs. connect asel0 to gnd or leave open to select the ina0 ( ina0 ) set of inputs. connect asel0 to v cc to select the ina1 ( ina1 ) set of inputs. an internal 435k resistor pulls asel0 low when unconnected. 30 ina1 lvds/hstl (MAX9392) or lvpecl/cml (max9393) noninverting input. an internal 128k resistor to v cc pulls the input high when unconnected (MAX9392). an internal 68k resistor to gnd pulls the input low when unconnected (max9393). 31 ina1 lvds/hstl (MAX9392) or lvpecl/cml (max9393) inverting input. an internal 128k resistor to v cc pulls the input high when unconnected (MAX9392). an internal 68k resistor to gnd pulls the input low when unconnected (max9393). 32 asel1 input select for a1 output. selects the differential input to reproduce at the a1 differential outputs. connect asel1 to gnd or leave open to select the ina0 ( ina0 ) set of inputs. connect asel1 to v cc to select the ina1 ( ina1 ) set of inputs. an internal 435k resistor pulls asel1 low when unconnected. pin description (continued)
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches _______________________________________________________________________________________ 7 t phl t plh 80% 20% 20% 80% 50% v od = 0 v od = 0 v id = 0 v od = 0 v od = 0 v id = 0 50% v id = v in_ _ - v in_ _ v od = v out_ _ - v out_ _ t plh and t phl measured for any combination of _sel0 and _sel1. v in_ _ v ihd v ild v in_ _ v out_ _ v out_ _ t f t r v ihd v ild v ihd v ild v ih v il v od = 0 t switch t switch in_0 in_0 in_1 in_1 v id = 0 v id = 0 _sel_ 1.5v in_1 out_ _ out_ _ en_0 = en_1 = high v id = v in_ _ - v in_ _ in_0 in_0 1.5v v od = 0 v id = v in_ _ - v in_ _ v od = ? v od - v od * ? v os = ? v os - v os * ? v od and v os are measured with v id = +100mv v od * and v os * are measured with v id = -100mv in_ _ in_ _ r l /2 r l /2 v od out_ _ out_ _ 1/4 MAX9392/max9393 en_ _ = high v os figure 1. output transition time and propagation delay timing diagram figure 3. input to rising/falling edge select and mux switch timing diagram figure 2. test circuit for v od and v os
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches 8 _______________________________________________________________________________________ v id = v in_ _ - v in_ _ 0 3v 1.5v 1.5v v en_ _ t phd t phd t pdh t pdh 50% 50% 50% 50% v out_ _ when v id = +100mv v out_ _ when v id = -100mv c l pulse generator in_ _ in_ _ r l /2 r l /2 50 out_ _ out_ _ 1.25v c l 1/4 MAX9392/max9393 v out_ _ when v id = -100mv v out_ _ when v id = +100mv r l = 100 1% c l = 1.0pf _sel0 _sel1 0 1 0 1 in_1 in_1 pulse generator out_0 out_0 out_1 out_1 c l r l r l in_0 in_0 50 c l 50 c l c l MAX9392 max9393 en_0 = en_1 = high 1 channel shown r l = 100 1% c l = 1.0pf figure 4. output active-to-disable and disable-to-active test circuit and timing diagram figure 5. output transition time, propagation delay, and output channel-to-channel skew test circuit
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches _______________________________________________________________________________________ 9 detailed description the lvds interface standard provides a signaling method for point-to-point communication over a con- trolled-impedance medium as defined by the ansi tia/eia-644 standard. lvds utilizes a lower voltage swing than other communication standards, achieving higher data rates with reduced power consumption, while reducing emi emissions and system susceptibility to noise. the MAX9392/max9393 1.5ghz dual 2 x 2 crosspoint switches optimize high-speed, low-power, point-to- point interfaces. the MAX9392 accepts lvds and hstl signals, while the max9393 accepts lvpecl and cml signals. both devices route the input signals to either or both lvds outputs. when configured as a 1:2 splitter, the outputs repeat the selected inputs. this configuration creates copies of signals for protection switching. when configured as a repeater, the device operates as a two-channel buffer. repeating restores signal amplitude, allowing isolation of media segments or longer media drive. when configured as a 2:1 mux, select primary or back- up signals to provide a protection-switched, fault-toler- ant application. input fail-safe the differential inputs of the MAX9392/max9393 pos- sess internal fail-safe protection. fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the common-mode voltage exceeds the specified range. the MAX9392 provides high-level input fail-safe detection for lvds, hstl, and other gnd-referenced differential inputs. the max9393 provides low-level input fail-safe detection for lvpecl, cml, and other v cc -referenced differential inputs. select function the _sel_ logic inputs control the input and output sig- nal connections. two logic inputs control the signal rout- ing for each channel. _sel0 and _sel1 allow the devices to be configured as a differential crosspoint switch, 2:1 mux, dual repeater, or 1:2 splitter (figure 7). see table 1 for mode-selection settings (insert a or b for the _). channels a and b possess separate select inputs, allowing different configurations for each channel. enable function the en_ _ logic inputs enable and disable each set of differential outputs. connect en_ 0 to v cc to enable the out_0/ out_0 differential output pair. connect en_0 to gnd to disable the out_0/ out_0 differential output pair. the differential output pairs assert to a dif- ferential low condition when disabled. v od = v out_ _ - v out_ _ v od = 0 t ccs v od = 0 v od = 0 v od = 0 t ccs v out_0 v out_0 v out_1 v out_1 t ccs measured with _sel0 = _sel1 = high or low (1:2 splitter configuration). figure 6. output channel-to-channel skew out_0 out_0 or out_1 out_1 2 x 2 crosspoint 2:1 mux 1:2 splitter dual repeater out_0 out_1 out_0 out_1 in_0 in_1 in_0 in_1 in_0 in_1 in_0 or in_1 figure 7. programmable configurations
MAX9392/max9393 applications information differential inputs the MAX9392/max9393 inputs accept any differential signaling standard within the specified common-mode voltage range. the fail-safe feature detects common- mode input signal levels and generates a differential output low condition for undriven inputs or when the common-mode voltage exceeds the specified range. leave unused inputs unconnected or connect to v cc for the MAX9392 or to gnd for the max9393. differential outputs the output common-mode voltage is not properly established if the lvds output is higher than 0.6v when the supply voltage is ramping up at power-on. this condition can occur when an lvds output drives an lvds input on the same chip. to avoid this situation for the MAX9392/max9393, connect a 10k resistor from the noninverting output (out_) to ground, and connect a 10k resistor from the inverting output ( out_ ) to ground. these pulldown resistors keep the output below 0.6v when the supply is ramping up (figure 8). expanding the number of lvds output ports cascade devices to make larger switches. consider the total propagation delay and total jitter when deter- mining the maximum allowable switch size. power-supply bypassing bypass each v cc to gnd with high-frequency surface- mount ceramic 0.1? and 0.01? capacitors in parallel as close to the device as possible. install the 0.01? capacitor closest to the device. differential traces input and output trace characteristics affect the perfor- mance of the MAX9392/max9393. connect each input and output to a 50 characteristic impedance trace. maintain the distance between differential traces and eliminate sharp corners to avoid discontinuities in dif- ferential impedance and maximize common-mode noise immunity. minimize the number of vias on the dif- ferential input and output traces to prevent impedance discontinuities. reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables. minimize skew by matching the electri- cal length of the traces. output termination terminate lvds outputs with a 100 resistor between the differential outputs at the receiver inputs. lvds out- puts require 100 termination for proper operation. ensure that the output currents do not exceed the cur- rent limits specified in the absolute maximum ratings . observe the total thermal limits of the MAX9392/ max9393 under all operating conditions. cables and connectors use matched differential impedance for transmission media. use cables and connectors with matched differ- ential impedance to minimize impedance discontinu- ities. avoid the use of unbalanced cables. balanced cables such as twisted pair offer superior signal quality and tend to generate less emi due to canceling effects. board layout use a four-layer printed circuit (pc) board providing separate signal, power, and ground planes for high- speed signaling applications. bypass v cc to gnd as close to the device as possible. install termination resistors as close to receiver inputs as possible. match the electrical length of the differential traces to minimize signal skew. anything-to-lvds dual 2 x 2 crosspoint switches 10 ______________________________________________________________________________________ table 1. input/output function table _sel0 _sel1 out_0 / out_0 out_1 / out_1 mode 0 0 in_0 / in_0 in_0 / in_0 1:2 splitter 0 1 in_0 / in_0 in_1 / in_1 repeater 1 0 in_1 / in_1 in_0 / in_0 switch 1 1 in_1 / in_1 in_1 / in_1 1:2 splitter 100 differential transmission line 100 termination resistor 10k gnd 10k out_ out_ MAX9392 max9393 figure 8. pulldown resistor configuration for lvds outputs
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches ______________________________________________________________________________________ 11 typical operating circuit 0.1 f 0.01 f 3.0v to 3.6v outa0 outa0 lvds receiver ina0 ina0 ena0 ena1 enb0 enb1 gnd gnd gnd gnd outa1 outa1 outb0 outb0 outb1 outb1 asel0 lvcmos/lvttl logic inputs asel1 bsel0 bsel1 ina1 inb0 inb0 100 z 0 = 50 z 0 = 50 MAX9392 max9393 v cc inb1 ina1 inb1 z 0 = 50 z 0 = 50 100 z 0 = 50 z 0 = 50 z 0 = 50 z 0 = 50 z 0 = 50 z 0 = 50 max9173
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches 12 ______________________________________________________________________________________ chip information transistor count: 1565 process: bipolar functional diagram 0 1 0 1 ina1 ina1 outa0 ena0 asel0 ena1 asel1 outa0 outa1 outa1 ina0 ina0 MAX9392 max9393 inb1 inb1 inb0 inb0 outb0 enb0 bsel0 enb1 bsel1 outb0 outb1 outb1 0 1 0 1
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches ______________________________________________________________________________________ 13 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 32l tqfp, 5x5x01.0.eps b 1 2 21-0110 package outline, 32l tqfp, 5x5x1.0mm
MAX9392/max9393 anything-to-lvds dual 2 x 2 crosspoint switches maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) b 2 2 21-0110 package outline, 32l tqfp, 5x5x1.0mm revision history pages changed at rev 1: 1?, 6, 8, 10?4

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