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1 of 40 062701 features incorporates industry sta ndard ds1287 pc clock plus enhanced features: y2k-compliant +3 or +5v operation 64-bit silicon serial number power control circuitry supports system power-on from date/time alarm or key closure 32khz output for power management crystal select bit allows rtc to operate with 6pf or 12.5pf crystal smi recovery stack 242 bytes user nv ram auxiliary battery input ram clear input century register date alarm register compatible with existing bios for original ds1287 functions available as chip (ds1685) or standalone module with embedded battery and crystal (ds1687) pin assignment timekeeping algorithm includes leap-year compensation valid up to 2100 ds1685/ds1687 3-volt/5-volt real-time clock www.maxim-ic.com 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 v cc sqw v baux rclr nc irq ks rd nc wr pwr nc nc ad0 ad1 ad2 ad3 ad4 ad5 ad6 ds1687 24-pin enca p sulated 11 12 14 13 ad7 gnd a le cs 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 v cc sq w v baux rcl r v bat ir q ks rd gnd w r pwr x1 x2 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ds1685 24-pin dip ds1685s 24-pin soic ds1685e 24-pin tssop 11 12 14 13 ad7 gnd ale cs x2 x1 pwr nc v cc sqw ds1685 q 28-pin plcc ad0 ad1 ad2 ad3 ad4 ad5 rcl r v bat ir q ks rd gnd nc w r ad6 nc ad7 gnd cs ale nc 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 12 13 14 15 16 17 18 v baux
ds1685/ds1687 2 of 40 3 +3v operating range 5 +5v operating range ordering information part # description ds1685xx-x rtc chip ds1687x-x rtc module; 24-pin dip pin description x1 - crystal input x2 - crystal output rclr - ram clear input ad0-ad7 - multiplexed address/data bus pwr - power-on interrupt output (open drain) ks - kickstart input cs - rtc chip select input ale - rtc address strobe wr - rtc write data strobe rd - rtc read data strobe irq - interrupt request output (open drain) sqw - square wave output v cc - +3 or +5v main supply gnd - ground v bat - battery + supply v baux - auxiliary battery supply nc - no connection description the ds1685/ds1687 is a real-time cl ock (rtc) designed as a successor to the industry standard ds1285, ds1385, ds1485, and ds1585 pc real -time clocks. this device provides the industry standard ds1285 clock function with either +3.0 or +5.0-volt operation. the ds 1685 also incorporates a number of enhanced features including a silicon serial number, power on/off control circuitry, 242 bytes of user nv sram, and 32.768khz output for sustai ning power mana gement activities. 3 +3v operating range 5 +5v operating range blank commercial temp range n industrial b lan k commercial temp range n industrial temp range blank 24-pin dip e 24- pin tsop s 24- pin soic q 28-pin plcc
ds1685/ds1687 3 of 40 the ds1685/ds1687 power control circuitry allows th e system to be powered on via an external stimulus, such as a keyboard or by a time and date (wake-up) alarm. the pwr output pin can be triggered by one or either of these events, and can be used to turn on an external power supply. the pwr pin is under software control, so that when a task is complete, the system power can then be shut down. the ds1685 is a clock/calendar chip with the features described above . an external crystal and battery are the only components required to maintain time-of-day and memory status in the absence of power. the ds1687 incorporates the ds1685 chip, a 32.768khz crysta l, and a lithium battery in a complete, self- contained timekeeping module. the entire unit is fu lly tested at dallas semiconductor such that a minimum of 10 years of timekeeping and data retention in the absence of v cc is guaranteed. operation the block diagram in figure 1 shows the pin connec tions with the major internal functions of the ds1685/ds1687. the following paragraphs de scribe the function of each pin. signal descriptions gnd, v cc - dc power is provided to the device on these pins. v cc is the +3 volt or +5 volt input. sqw (square wave output) - the sqw pin will provide a 32khz square wave output, t rec , after a power-up condition has been detecte d. this condition sets the following bits, enabling the 32khz output; dv1=1, and e32k=1. a square wave will be output on this pin if either sqwe=1 or e32k=1. if e32k=1, then 32khz will be output regardless of the other control bits. if e32k=0, then the output frequency is dependent on the control bits in register a. the sqw pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the real-time clock. the frequency of the sqw pin can be changed by programming register a as shown in table 2. the sqw signal can be turned on and off using the sqwe bit in register b or the e32k bit in extended register 4bh. a 32khz sqw signal is output when the enable 32khz (e32k) bit in extended register 4bh is a logic 1, and v cc is above v pf . a 32khz square wave is also available when v cc is less than v pf if e32k=1, abe=1, and voltage is applied to the v baux pin. ad0-ad7 (multiplexed bidirectional address/data bus) - multiplexed buses save pins because address information and data information time share the same signal paths. the addresses are present during the first portion of the bus cycle and the same pi ns and signal paths are used for data in the second portion of the cycle. address/data multiplexing does not slow the access time of the ds1685 since the bus change from address to data occurs during the internal ram access time. addresses must be valid prior to the latter portion of ale, at which time the ds 1685/ds1687 latches the address. valid write data must be present and held stable during the latter portion of the wr pulse. in a read cycle the ds1685/ds1687 outputs 8 bits of data durin g the latter portion of the rd pulse. the read cycle is terminated and the bus returns to a high impedance state as rd transitions high. the address/data bus also serves as a bidirectional data path fo r the external extended ram. ale (rtc address strobe input; active high) - a pulse on the address strobe pin serves to demultiplex the bus. the falling edge of ale causes the rtc address to be latched within the ds1685/ds1687. rd (rtc read input; active low) - rd identifies the time period when the ds1685/ds1687 drives the bus with rtc read data. the rd signal is an enable signal fo r the output buffers of the clock.
ds1685/ds1687 4 of 40 wr (rtc write input; active low) - the wr signal is an active low signal. the wr signal defines the time period during which data is written to the addressed register. cs (rtc chip select input; active low) - the chip select signal must be asserted low during a bus cycle for the rtc portion of the ds1685/ds1687 to be accessed. cs must be kept in the active state during rd and wr timing. bus cycles which take place w ith ale asserted but without asserting cs will latch addresses. however, no data transfer will occur. irq (interrupt request output; open drain, active low) - the irq pin is an active low output of the ds1685/ds1687 that can be tied to the in terrupt input of a processor. the irq output remains low as long as the status bit causing the interrupt is pres ent and the corresponding interrupt-enable bit is set. to clear the irq pin, the application software must clear all enabled flag bits contributing to irq ?s active state. when no interrupt conditions are present, the irq level is in the high impedance state. multiple interrupting devices can be connected to an irq bus. the irq pin is an open drain output and requires an external pullup resistor. the voltage on the pull up supply should be no greater than v cc + 0.2 volt. pwr (power on output; open drain, active low) - the pwr pin is intended for use as an on/off control for the system power. with v cc voltage removed from the ds1685/ds1687, pwr may be automatically activated from a kickstart input via the ks pin or from a wake-up interrupt. once the system is powered on, the state of pwr can be controlled via bits in the dallas registers. the pwr pin may be connected through a pull up resistor to a positive supply. for 5-volt operation, the voltage of the pull up supply should be no greater than 5.7 volts. fo r 3-volt operation, the voltage of the pull up supply should be no greater than 3.9 volts. ks (kickstart input; active low) - when v cc is removed from the ds1685/ds1687, the system can be powered on in response to an active low transition on the ks pin, as might be generated from a key closure. v baux must be present and auxiliary battery enable bit (abe) must be set to 1 if the kickstart function is used, and the ks pin must be pulled up to the v baux supply. while v cc is applied, the ks pin can be used as an interrupt input. rclr (ram clear input; active low) - if enabled by software, taking rclr low will result in the clearing of the 242 bytes of user ram. when enabled, rclr can be activated whether or not v cc is present. v baux - auxiliary battery input required for kickstart and wake-up features. this input also supports clock/ calendar and user ram if v bat is at lower voltage or is not present. a standard +3 volt lithium cell or other energy source can be used. battery voltage must be held between + 2.5 and +3.7 volts for proper operation. if v baux is not going to be used it should be ground ed and auxiliary battery enable bit bank 1, register 4bh, should=0.
ds1685/ds1687 5 of 40 ds1685/ds1687 block diagram figure 1
ds1685/ds1687 6 of 40 ds1685 only x1, x2 - connections for a standard 32.768khz quartz crys tal. for greatest accuracy, the ds1685 must be used with a crystal that has a specified load capacitance of either 6pf or 12.5pf. the crystal select (cs) bit in extended control register 4b is used to select operation with a 6pf or 12.5pf crystal. the crystal is attached directly to the x1 and x2 pins. there is no need for external capacitors or resistors. note: x1 and x2 are very high impedance nodes. it is recommended that they and the crystal be guard- ringed with ground and that high frequency si gnals be kept away from the crystal area. for more information on crystal selection and crysta l layout considerations, please consult application note 58, ?crystal considerations with dallas real-time clocks.? th e ds1685 can also be driven by an external 32.768 khz oscillator. in th is configuration, the x1 pin is c onnected to the external oscillator signal and the x2 pin is floated. v bat - battery input for any standard 3-volt lithium cell or other energy source. battery voltage must be held between 2.5 and 3.7 volts for proper operation. power-down/power-up considerations the real-time clock function will continue to operate and all of the ram, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the v cc input. when v cc is applied to the ds1685/ds1687 and reaches a level of greater than v pf (power fail trip point), the device becomes accessible after t rec , provided that the oscillator is running and the oscillator countdown chain is not in reset (see register a). this time period allows the system to stabilize after power is applied. the ds1685/ds1687 is available in e ither a 3 volt or a 5 volt device. the 5-volt device is fully accessible and data can be written and read only when v cc is greater than 4.5 volts. when v cc is below 4.5 volts, read and writes are i nhibited. however, the timekeeping function continues unaffected by the lower input voltage. as v cc falls below the greater of v bat and v baux , the ram and timekeeper are switched over to a lith ium battery connected either to the v bat pin or v baux pin. the 3-volt device is fully accessible and data can be written or read only when v cc is greater than 2.7 volts. when v cc falls below v pf , access to the device is inhibited. if v pf is less than v bat and v baux , the power supply is switched from v cc to the backup supply (the greater of v bat and v baux ) when v cc drops below v pf . if v pf is greater than v bat and v baux , the power supply is switched from v cc to the backup supply when v cc drops below the larger of v bat and v baux . when v cc falls below v pf , the chip is write-protected. with the possible exception of the ks , pwr , and sqw pins, all inputs are ignored and a ll outputs are in a high impedance state.
ds1685/ds1687 7 of 40 rtc address map the address map for the rtc registers of the ds 1685/ds1687 is shown in figure 2. the address map consists of the 14 clock/calendar registers. ten registers contain the time, calendar, and alarm data, and four bytes are used for control and status. all registers can be directly written or read except for the following: 1. registers c and d are read-only. 2. bit 7 of register a is read-only. 3. the high order bit of the seconds byte is read-only. ds1685 real-time clock address map figure 2 0 00h 0 seconds 1 seconds alarm 13 clock/ calendar 14 bytes 0dh 2 minutes 14 0eh 3 minutes alarm 63 50 bytes user ram 03fh 4 hours 64 040h 5 hours alarm 6 day of the week 7 day of the month 8 month 9 year bank0, bank 1 registers, ram 10 register a 11 register b 12 register c 127 07fh 13 register d binary or bcd inputs time, calendar and alarm locations the time and calendar information is obtained by reading the appropriate register bytes shown in table 1. the time, calendar, and alarm are set or initialized by writing the appropriate register bytes. the contents of the time, calendar, and alarm registers can be either binary or binary-coded decimal (bcd) format. table 1 shows the binary and bcd formats of the ten time, calendar, and alarm locations that reside in both bank 0 and in bank 1, plus the two extended regist ers that reside in bank 1 only (bank 0 and bank 1 switching will be explained later in this text). before writing the internal time, calendar, and alarm re gisters, the set bit in register b should be written to a logic 1 to prevent updates from occurring while ac cess is being attempted. al so at this time, the data format (binary or bcd), should be set via the data m ode bit (dm) of register b. all time, calendar, and alarm registers must use the same data mode. the se t bit in register b should be cleared after the data mode bit has been written to allow the real- time clock to update the time and calendar bytes. once initialized, the real-time clock makes all updates in the selected mode. the data mode cannot be changed without reinitializing the 10 data bytes. th e 24/12 bit cannot be changed without reinitializing the hour locations. when the 12-hour format is select ed, the high order bit of the hours byte represents pm when it is a logic 1. the time, calendar, and alarm bytes are always accessible because they are
ds1685/ds1687 8 of 40 double buffered. once per second the ten bytes are adva nced by one second and checked for an alarm condition. if a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc., may not correlate. the probability of reading in correct time and calendar data is low. severa l methods of avoiding any possible incorrect time and calendar reads are covered later in this text. the three time alarm bytes can be used in two ways. first, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm in terrupt is initiated at the specified time each day if the alarm enable bit is high. the s econd use condition is to insert a ?don?t care? state in one or more of the three time alarm bytes. the ? don?t care? code is any hexadecimal value from c0 to ff. the two most significant bits of each byte set the ?don?t care? condition when at logic 1. an alarm will be generated each hour when the ?don?t care? b its are set in the hours byte. similarly, an alarm is generated every minute with ?don?t care? codes in th e hours and minute alarm bytes. the ?don?t care? codes in all three time alarm bytes create an inte rrupt every second. the three time alarm bytes may be used in conjunction with the date alarm as desc ribed in the wake-up/kickstart section. the century counter will be discusse d later in this text. time, calendar and alarm data modes table 1 range address location function decimal range binary data mode bcd data mode 00h seconds 0-59 00-3b 00-59 01h seconds alarm 0-59 00-3b 00-59 02h minutes 0-59 00-3b 00-59 03h minutes alarm 0-59 00-3b 00-59 04h hours 12-hr. mode 1-12 01-0c am, 81-8c pm 01-12 am, 81-92 pm hours 24-hour mode 0-23 00-17 00-23 05h hours alarm 12-hr. mode 1-12 01-0c am, 81-8c pm 01-12am, 81-92 pm hours alarm 24-hr. mode 0-23 00-17 00-23 06h day of week sunday = 1 1-7 01-07 01-07 07h date of month 1-31 01-1f 01-31 08h month 1-12 01-0c 01-12 09h year 0-99 00-63 00-99 bank 1, 48h century 0-99 00-63 00-99 bank 1, 49h date alarm 1-31 01-1f 01-31
ds1685/ds1687 9 of 40 control registers the four control registers a, b, c, and d reside in both bank 0 and bank 1. these registers are accessible at all times, even during the update cycle. register a msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uip dv2 dv1 dv0 rs3 rs2 rs1 rs0 uip - the update in progress (uip) bit is a status flag that can be monitored. when the uip bit is a one, the update transfer will soon occur. when uip is a 0, the update transfer will not occur for at least 244 s. the time, calendar, and alarm information in ram is fu lly available for access when the uip bit is 0. the uip bit is read only. writing the set bit in register b to a 1 inhibits any update transfer and clears the uip status bit. dv2, dv1, dv0 - these bits are defined as follows: dv2 = countdown chain 1 - resets countdown chain only if dv1=1 0 - countdown chain enabled dv1 = oscillator enable 0 - oscillator off 1 - oscillator on dv0 = bank select 0 - original bank a pattern of 01x is the only combination of bits that will turn the oscillator on and allow the rtc to keep time. a pattern of 11x will enable the oscillator but holds the countdow n chain in reset. the next update will occur at 500ms after a pattern of 01x is written to dv2, dv1, and dv0. rs3, rs2, rs1, rs0 - these four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. the tap se lected can be used to generate an output square wave (sqw pin) and/or a periodic interrupt. the user can do one of the following: enable the interrupt with the pie bit; enable the sqw output pin with the sqwe or e32k bits; enable both at the same time and the same rate; or enable neither. table 2 lists the periodic interrupt rates and the square wave frequencies that can be chosen with the rs bits.
ds1685/ds1687 10 of 40 register b msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set pie aie uie sqwe dm 24/12 dse set - when the set bit is a 0, the update transfer fu nctions normally by advancing the counts once per second. when the set bit is written to a 1, any update transfer is inhibited a nd the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. read cycles can be executed in a similar manner. set is a read/write bit that is not modified by internal functions of the ds1685/ds1687. pie - the periodic interrupt enable bit is a read/write bit which allows the periodic interrupt flag (pf) bit in register c to drive the irq pin low. hen the pie bit is set to 1, periodic interrupts are generated by driving the irq pin low at a rate specified by the rs3-rs0 b its of register a. a 0 in the pie bit blocks the irq output from being driven by a periodic interrupt, but the periodic flag (pf) bit is still set at the periodic rate. pie is not modified by any internal ds1685/ds1687 functions. aie - the alarm interrupt enable (aie) bit is a read/write bit which, when set to a 1, permits the alarm flag (af) bit in register c to assert irq . an alarm interrupt occurs for each second that the 3 time bytes equal the 3 alarm bytes including a ?don?t care? alar m code of binary 11xxxxxx. when the aie bit is set to 0, the af bit does not initiate the irq signal. the internal func tions of the ds1685/ds1687 do not affect the aie bit. uie - the update ended interrupt enable (uie) bit is a read/write bit that enables the update end flag (uf) bit in register c to assert irq . the set bit going high clears the uie bit. sqwe - when the square wave enable (sqwe) bit is se t to a one and e32k=0, a square wave signal at the frequency set by the rate-selection bits rs3 th rough rs0 is driven out on the sqw pin. when the sqwe bit is set to 0 and e32k=0, the sqw pi n is held low. sqwe is a read/write bit. dm - the data mode (dm) bit indicates whether time and calendar information is in binary or bcd format. the dm bit is set by the program to the approp riate format and can be read as required. this bit is not modified by internal functions. a 1 in dm sign ifies binary data while a 0 in dm specifies binary coded decimal (bcd) data. 24/12 - the 24/12 control bit establishes the format of the hours byte. a 1 indicates the 24-hour mode and a 0 indicates the 12-hour mode. this bit is read/write. dse - the daylight savings enable (dse) bit is a read /write bit which enable s two special updates when dse is set to 1. on the first sunday in april th e time increments from 1:59:59 am to 3:00:00 am. on the last sunday in october when the time first reaches 1:59:59 am it changes to 1:00:00 am. these special updates do not occur when the dse bit is a 0. this bit is not affected by internal functions.
ds1685/ds1687 11 of 40 register c msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iqrf pf af uf 0 0 0 0 irqf - the interrupt request flag (irqf) bit is set to a 1 when one or more of the following are true: pf = pie = 1 wf = wie= 1 af = aie = 1 kf = kse= 1 uf = uie = 1 rf = rie = 1 i.e., irqf = (pf pie) + (af aie) + (uf uie) + (wf wie) + (kf kse) + (rf rie) any time the irqf bit is a 1, the irq pin is driven low. flag bits pf, af, and uf are cleared after register c is read by the program. pf - the periodic interrupt flag (pf) is a read-only bit wh ich is set to a 1 when an edge is detected on the selected tap of the divider chain. th e rs3 through rs0 bits establish the periodic rate. pf is set to a 1 independent of the state of the pie bit. when both pf and pie are 1?s, the irq signal is active and will set the irqf bit. the pf bit is cleared by a software read of register c. af - a one in the alarm interrupt flag (af) bit indicates that the current time has matched the alarm time. if the aie bit is also a 1, the irq pin will go low and a 1 will appear in the irqf bit. a read of register c will clear af. uf - the update ended interrupt flag (uf) bit is set after each update cycle. when the uie bit is set to 1, the one in uf causes the irqf bit to be a 1 which will assert the irq pin. uf is cleared by reading register c. bit 3 through bit 0 - these are unused bits of the status regi ster c. these bits always read 0 and cannot be written. register d msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vrt 0 0 0 0 0 0 0 vrt - the valid ram and time (vrt) bit indicates the condition of the battery connected to the v bat pin or the battery connected to v baux , whichever is at a higher voltage. this bit is not writable and should always be a 1 when read. if a 0 is ever present, an exhausted lithium energy source is indicated and both the contents of the rtc data and ram data are questionable. bit 6 through bit 0 - the remaining bits of register d are not usable. they cannot be written and when read will always read 0.
ds1685/ds1687 12 of 40 nonvolatile ram - rtc the 242 general purpose nonvolatile ram bytes are not dedicated to any special function within the ds1685/ds1687. they can be used by the applicati on program as nonvolatile memory and are fully available during the update cycle. the user ram is divided into two separate memory banks. when the bank 0 is selected, the 14 real-time clock registers and 114 bytes of user ram are acce ssible. when bank 1 is selected, an additional 128 bytes of user ram are accessible through th e extended ram address and data registers. interrupt control the ds1685/ds1687 includes six separate, fully auto matic sources of interrupt for a processor: 1. alarm interrupt 2. periodic interrupt 3. update-ended interrupt 4. wake-up interrupt 5. kickstart interrupt 6. ram clear interrupt the conditions that generate each of these independen t interrupt conditions are described in greater detail elsewhere in this data sheet. this section de scribes the overall control of the interrupts. the application software can select which interrupts, if any, are to be used. there are a total of 6 bits including 3 bits in register b and 3 bits in extende d register b which enable the interrupts. the extended register locations are described later. writing a logic 1 to an interrupt enable bit permits that interrupt to be initiated when the event occurs. a logic 0 in the interrupt enable bit prohibits the irq pin from being asserted from that interrupt conditi on. if an interrupt flag is already set when an interrupt is enabled, irq will immediately be set at an active level, even t hough the event initiating the interrupt condition may have occurred much earlier. as a result, there ar e cases where the software should clear these earlier generated interrupts before first enabling new interrupts . when an interrupt event occurs, the relating flag bit is set to a logic 1 in register c or in extended register a. these flag bits are set regardless of th e setting of the corresponding enable bit located either in register b or in extended register b. the flag b its can be used in a polling mode without enabling the corresponding enable bits. however, care should be taken when using the flag bits of register c as they are automatically cleared to 0 immediately after they are read. double latching is imp lemented on these bits so that bits which are set remain stable throughout the read cycle. all bits wh ich were set are cleared when read and new interrupts which are pending during the read cycle are held until after the cycle is completed. one, 2, or 3 bits can be set when reading register c. each utilized flag bit should be examined when read to ensure that no interrupts are lost. the flag bits in extended register a are not automatically cleared following a read. instead, each flag bit can be cleared to 0 only by writing 0 to that bit.
ds1685/ds1687 13 of 40 when using the flag bits with fully enabled interrupts, the irq line will be driven low when an interrupt flag bit is set and its corresponding enable bit is also set. irq will be held low as long as at least one of the six possible interrupt sources has it s flag and enable bits both set. the irqf bit in register c is a 1 whenever the irq pin is being driven low as a result of on e of the six possible active sources. therefore, determination that the ds1685/ds1687 initiated an interrupt is accomplis hed by reading register c and finding irqf=1. irqf will remain set until all enabled interrupt flag bits are cleared to 0. square wave output selection the sqw pin can be programmed to output a vari ety of frequencies divided down from the 32.768khz crystal tied to x1 and x2. the square wave output is enabled and disabled via the sqwe bit in register b or the e32k bit in extended register 4bh. if the square wave is enabled (sqwe=1 or e32k=1), then the output frequency will be determined by the settings of the e32k bit in extended register 4bh and by the rs3-0 bits in register a. if e32k=1, then a 32.768khz square wave will be output on the sqw pin regardless of the settings of rs3-0 and sqwe. if e32k = 0, then the square wave output frequency is determined by the rs3-0 bits. these bits control a 1-of-15 decoder, which selects one of 13 taps that divide th e 32.768khz frequency. the rs3-0 bits establish the sqw output frequency as shown in tabl e 2. in addition, rs3-0 bits control the periodic interrupt selection as described below. if e32k=1, and the auxiliary battery enable bit (abe, bank 1; register 04bh) is enabled, and voltage is applied to v baux then the 32 khz square wave output signal will be output on the sqw pin in the absence of v cc . this facility is provided to clock external power management circuitry. if any of the above requirements are not met, no square wave output signal will be generated on the sqw pin in the absence of v cc . a pattern of 01x in the dv2, dv1, and dv0, bits respectively, will turn the oscillator on and enable the countdown chain. note that this is different than the ds1287, which required a pattern of 010 in these bits. dv0 is now a ?don?t care? because it is used for selection between register banks 0 and 1. a pattern of 11x will turn the oscillator on, but the os cillator?s countdown chain w ill be held in reset, as it was in the ds1287. any other bit combination for dv2 and dv1 will keep the oscillator off. periodic interrupt selection the periodic interrupt will cause the irq pin to go to an active state from once every 500 ms to once every 122 s. this function is separate from the alarm interrupt which can be output from once per second to once per day. the periodic interrupt rate is selected using the same rs3-0 bits in register a, which select the square wave frequency (see table 2). changi ng the bits affects both the square wave frequency and the periodic interrupt output. however, each functi on has a separate enable bit in register b. the sqwe and e32k bits control the square wave output. similarly, the periodic interrupt is enabled by the pie bit in register b. the periodic interrupt can be used with software counters to measure inputs, create output intervals, or await the next needed software function.
ds1685/ds1687 14 of 40 periodic interrupt rate and square wave output frequency table 2 ext. select bits register e32k rs3 rs2 rs1 rs0 t pi periodic interrupt rate sqw output frequency 0 0 0 0 0 none none 0 0 0 0 1 3.90625ms 256hz 0 0 0 1 0 7.8125ms 128hz 0 0 0 1 1 122.070 s 8.192khz 0 0 1 0 0 244.141 s 4.096khz 0 0 1 0 1 488.281 s 2.048khz 0 0 1 1 0 976.5625 s 1.024khz 0 0 1 1 1 1.953125ms 512hz 0 1 0 0 0 3.90625ms 256hz 0 1 0 0 1 7.8125ms 128hz 0 1 0 1 0 15.625ms 64hz 0 1 0 1 1 31.25ms 32hz 0 1 1 0 0 62.5ms 16hz 0 1 1 0 1 125ms 8hz 0 1 1 1 0 250ms 4hz 0 1 1 1 1 500ms 2hz 1 x x x x * 32.768khz *rs3-rs0 determine periodic interr upt rates as listed for e32k=0.
ds1685/ds1687 15 of 40 update cycle the serialized rtc executes an update cycle once pe r second regardless of the set bit in register b. when the set bit in register b is set to 1, the us er copy of the double buffered time, calendar, alarm and elapsed time byte is frozen and will not update as the time increments. however, the time countdown chain continues to update the internal copy of th e buffer. this feature allows the time to maintain accuracy independent of reading or writing the time, cal endar, and alarm buffers and also guarantees that time and calendar information is consistent. the update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a ?don?t ca re? code is present in all alarm locations. there are three methods that can handle access of the real-time clock that avoid any possibility of accessing inconsistent time and calendar data. the first method us es the update-ended interrupt. if enabled, an interrupt occurs after every update cycle that indicates that over 999ms are available to read valid time and date informa tion. if this interrupt is used, the irqf bit in register c should be cleared before leaving the interrupt routine. a second method uses the update-in-progress bit (uip) in register a to determine if the update cycle is in progress. the uip bit will pulse onc e per second. after the uip bit goes high, the update transfer occurs 244 s later. if a low is read on the uip bit, the user has at least 244 s before the time/calendar data will be changed. therefore, the user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244 s. the third method uses a periodic interrupt to determin e if an update cycle is in progress. the uip bit in register a is set high between the setting of the pf bit in register c (see figure 3). periodic interrupts that occur at a rate of greater than t buc allow valid time and date information to be reached at each occurrence of the periodic interrupt. th e reads should be complete within (t pi / 2 + t buc ) to ensure that data is not read during the update cycle. update-ended and periodic interrupt relationship figure 3 t t p1/2 t p1/2 t buc uip bit in register a uf bit in register c pf bit in register c t pi = periodic interrupt time internal per table 1 t buc = delay time before update cycle = 244 s
ds1685/ds1687 16 of 40 extended functions the extended functions provided by the ds1685/ds1687 that are new to the ramified rtc family are accessed via a software controlled bank switching scheme, as illustrated in figure 4. in bank 0, the clock/calendar registers and 50 bytes of user ram are in the same locations as for the ds1287. as a result, existing routines implemented within bios, dos, or application software packages can gain access to the ds1685/ds1687 clock registers with no chan ges. also in bank 0, an extra 64 bytes of ram are provided at addresses just above the original loca tions for a total of 114 directly addressable bytes of user ram. when bank 1 is selected, the clock/calendar registers and the original 50 bytes of user ram still appear as bank 0. however, the dallas registers which provide control and status for the extended functions will be accessed in place of the additional 64 bytes of user ram. the major extended functions controlled by the dallas registers are listed below: 1. 64-bit silicon serial number 2. century counter 3. date alarm 4. auxiliary battery control/status 5. wake-up 6. kickstart 7. ram clear control/status 8. 128-bytes extended ram access the bank selection is controlled by the state of the dv0 bit in register a. to access bank 0 the dv0 bit should be written to a 0. to access bank 1, dv0 should be written to a 1. register locations designated as reserved in the bank 1 map are reserved for future use by dallas semiconductor. bits in these locations cannot be written and will return a 0 if read. silicon serial number a unique 64-bit lasered serial number is located in bank 1, registers 40h to 47h. this serial number is divided into three parts. the first byte in register 40h contains a model number to identify the device type and revision of the ds1685/ds1687. registers 41h to 46h contain a unique binary number. register 47h contains a crc byte used to validate the data in registers 40h to 46h. all 8 bytes of the serial number are read-only registers. the ds1685/ds1687 is manufactured such that no tw o devices will contain an identical number in locations 41h to 47h. century counter a register has been added in bank 1, location 48h, to k eep track of centuries. the value is read in either binary or bcd according to the setting of the dm bit.
ds1685/ds1687 17 of 40 auxiliary battery the v baux input is provided to supply power from an auxiliary battery for the ds1685/ds1687 kickstart, wake-up, and sqw output features in the absence of v cc . this power source must be available in order to use these auxiliary features when no v cc is applied to the device. the auxiliary battery enable (abe; bank 1, register 04bh) bit in extended control register b is used to turn on and off the auxiliary battery for the above functions in the absence of v cc . when set to a 1, v baux battery power is enabled, and when cleared to 0, v baux battery power is disabled to these functions. in the ds1685/ds1687, this auxiliary battery may be used as the primary backup power source for maintaining the clock/calendar, user ram, and extended external ram functions. this occurs if the v bat pin is at a lower voltage than v baux . if the ds1685 is to be backed-up using a single battery with the auxiliary features enabled, then v baux should be used and v bat should be grounded. if v baux is not to be used, it should be grounded and abe should be cleared to 0. wake-up/kickstart the ds1685/ds1687 incorporates a wake -up feature that can power the system on at a pre-determined date and time through activation of the pwr output pin. in addition, the ki ckstart feature can allow the system to be powered up in response to a low going transition on the ks pin, without operating voltage applied to the v cc pin. as a result, system power may be a pplied upon such events as a key closure or modem ring detect signal. in order to use eith er the wake-up or the kickstart features, the ds1685/ds1687 must have an auxiliary battery connected to the v baux pin and the oscillator must be running and the countdown chain must not be in reset (register a dv2, dv1, dv0 = 01x). if dv2, dv1, and dv0 are not in this required state, the pwr pin will not be driven low in response to a kickstart or wake-up condition, while in battery-backed mode. the wake-up feature is controlled through the wake-up interrupt enable bit in ex tended control register b (wie, bank 1, 04bh). setting wie to 1 enables the wake-up feature, clearing wie to 0 disables it. similarly, the kick-start feature is controlled thr ough the kickstart interrupt enable bit in extended control register b (kse, bank 1, 04bh). a wake-up sequence will occur as follows: when wake-up is enabled via wie = 1 while the system is powered down (no v cc voltage), the clock/calendar will monito r the current date for a match condition with the date alarm register (bank 1, register 049h). in conjunction with the date alarm register, the hours, minutes, and seconds alarm bytes in the clock/cale ndar register map (bank 0, registers 05h, 03h, and 01h) are also monitored. as a result, a wake-up will occur at the date and time specified by the date, hours, minutes, and seconds alarm register values. this additional alarm will occur regardless of the programming of the aie bit (bank 0, register b, 0bh). when the match condition occurs, the pwr pin will automatically be driven low. this output can be used to turn on the main system power supply, which provides v cc voltage to the ds1685/ds1687 as well as th e other major components in the system. also at this time, the wake-up flag (wf, bank 1, register 04ah) will be set, indicating that a wake-up condition has occurred.
ds1685/ds1687 18 of 40 a kickstart sequence will occur when kickstarting is enabled via kse = 1. while the system is powered down, the ks input pin will be monitored for a low going transition of minimum pulse width t kspw . when such a transition is detected, the pwr line will be pulled low, as it is for a wake-up condition. also at this time, the kickstart flag (kf, bank 1, register 04ah) will be set, indicating that a kickstart condition has occurred. the timing associated with both the wake-up and kickstarting sequences is illustrated in the wake-up/ kickstart timing diagram in the electrical specificati ons section of this data sheet. the timing associated with these functions is divided into 5 intervals, labeled 1-5 on the diagram. the occurrence of either a kickstart or wake-up condition will cause the pwr pin to be driven low, as described above. during interval 1, if the supply voltage on the ds1685/ds1687 v cc pin rises above the greater of v bat or v pf before the power on timeout period (t poto ) expires, then pwr will remain at the active low level. if v cc does not rise above the greater of v bat or v pf in this time, then the pwr output pin will be turned off and will return to its high impedance level. in this event, the irq pin will also remain tri-stated. the interrupt flag bit (either wf or kf) associated with the attempted power on sequence will remain set until cleared by software during a subsequent system power on. if v cc is applied within the timeout period, then the sy stem power on sequence will continue as shown in intervals 2-5 in the timing diagram. during interval 2, pwr will remain active and irq will be driven to its active low level, indicating that either wf or kf was set in in itiating the power on. in the diagram ks is assumed to be pulled up to the v baux supply. also at this time, the pab bit will be automatically cleared to 0 in response to a successful power on. the pwr line will remain active as long as the pab remains cleared to 0. at the beginning of interval 3, the system proce ssor has begun code execution and clears the interrupt condition of wf and/or kf by writing zeroes to both of these control bits. as long as no other interrupt within the ds1685/ds1687 is pending, the irq line will be taken inactive once these bits are reset. execution of the application software may proceed. during this time, both the wake-up and kickstart functions may be used to generate status and inte rrupts. wf will be set in response to a date, hours, minutes, and seconds match condition. kf will be set in response to a low going transition on ks. if the associated interrupt enable bit is set (wie and/or kse) then the irq line will driven active low in response to enabled event. in addition, the othe r possible interrupt sour ces within the ds1685/ds1687 may cause irq to be driven low. while system power is applied, the on chip logic will always attempt to drive the pwr pin active in response to the enabled kickstar t or wake-up condition. this is true even if pwr was previously inactive as the result of power be ing applied by some means other than wake-up or kickstart. the system may be powered down under software control by setting the pab bit to a logic 1. this causes the open-drain pwr pin to be placed in a high impedance state, as shown at the beginning of interval 4 in the timing diagram. s v cc voltage decays, the irq output pin will be placed in a high impedance state when v cc goes below v pf . if the system is to be again powered on in response to a wake-up or kickstart, then the both the wf and kf flags should be clear ed and wie and/or kse should be enabled prior to setting the pab bit.
ds1685/ds1687 19 of 40 during interval 5, the system is fully powere d down. battery backup of the clock calendar and nonvolatile ram is in effect and irq is tri-stated, and monitoring of wake-up and kickstart takes place. if prs=1, pwr stays active, otherwise if prs=0 pwr is tri-stated. ram clear the ds1685/ds1687 provides a ram clear function for th e 242 bytes of user ram. when enabled, this function can be performed regardless of the condition of the v cc pin. the ram clear function is enabled or disabled vi a the ram clear enable bit (rce; bank 1, register 04bh). when this bit is set to a logic 1, the 242 bytes of user ram will be cleared (all bits set to 1) when an active low transition is sensed on the rclr pin. this action will have no effect on either the clock/calendar settings or upon the contents of th e extended ram. the ram clear flag (rf, bank 1, register 04ah) will be set when the ram clear operation has been completed. if v cc is present at the time of the ram clear and rie=1, the irq line will also be driven low upon completion. the interrupt condition can be cleared by writing a 0 to the rf bit. the irq line will then return to its inactive high level provided there are no other pending interrupts. once the rclr pin is activated, all read/write accesses are locked out for a minimum recover time, specified as t rec in the electrical characteristics section. when rce is cleared to 0, the ram clear function is disabled. the state of the rclr pin will have no effect on the contents of the user ram, and transitions on the rclr pin have no effect on rf. 128 x 8 extended ram the ds1685/ds1687 provides 128 x 8 of on-chip sram which is controlled as nonvolatile storage sustained from a lithium battery. on power-up, the ram is taken out of write protect status by the internal power ok signal (pok) genera ted from the write protect circuitry. the on-chip 128 x 8 nonvolatile sram is accessed via the eight multiplexed addr ess/data lines ad7 to ad0. access to the sram is controlled by two on-chip latch registers. one register is used to hold the sram address, and the other register is used to hold read/write data. the sram address space is from 00h to 7fh. access to the extended 128 x 8 ram is controlled via tw o of the dallas registers shown in figure 4. the dallas registers in bank 1 must first be selected by setting the dv0 bit in register a to a logic 1. the 7-bit address of the ram location to be accessed must be loaded into the extended ram address register located at 50h. data in the addressed location may be read by performing a read operation from location 53h, or written to by performing a wr ite operation to location 53h. data in any addressed location may be read or written repeatedly without changing the address in location 50h.
ds1685/ds1687 20 of 40 ds1685/ds1687 extended regist er bank definition figure 4 msb bank 0 dv0 = 0 lsb msb bank 1 dv0 = 1 lsb 00 00 0d timekeeping and control 0d timekeeping and control 0e 0e 3f 50 bytes-user ram 3f 50 bytes-user ram 40 model number byte 41 1st byte serial number 42 2nd byte serial number 43 3rd byte serial number 44 4th byte serial number 45 5th byte serial numbber 46 6th byte serial number 47 crc byte 48 century byte 49 date alarm 4a extended control reg 4a 4b extended control reg 4b 4c reserved 4d reserved 4e rtc address-2 4f rtc address-3 50 extended ram address 51 reserved 52 reserved 53 extended ram data port 54 reserved 7f 64 bytes-user ram 7f extended ram 128 x 8
ds1685/ds1687 21 of 40 extended control registers two extended control registers are provided to supply controls and st atus information for the extended features offered by the ds1685/ds1687. these are designated as extended control registers a and b and are located in register bank 1, locations 04ah and 04 bh, respectively. the functions of the bits within these registers are described as follows. extended control register 4a msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vrt2 incr * * pab rf wf kf vrt2 - this status bit gives the condition of the auxiliary battery. it is set to a logic 1 condition when the external lithium battery is connected to the v baux . if this bit is read as a logic 0, the external battery should be replaced. incr - increment in progress status bit. this bit is set to a 1 when an increment to the time/date registers is in progress and the alarm checks are being made . incr will be set to a 1 at 122ms before the update cycle starts and will be cleared to 0 at the end of each update cycle. pab - power active bar control bit. when this bit is 0, the pwr pin is in the active low state. when this bit is 1, the pwr pin is in the high impedance state. this bit can be written to a logic 1 or 0 by the user. if either wf and wie = 1 or kf and kse = 1, the pab bit will be cleared to 0. rf - ram clear flag. this bit will be set to a logic 1 when a high to low transition occurs on the rclr input if rce=1. the rf bit is cleared by writing it to a logic 0. this bit can also be written to a logic 1 to force an interrupt condition. wf ? wake-up alarm flag - this bit is set to 1 when a wake-up alarm condition occurs or when the user writes it to a 1. wf is cleared by writing it to a 0. kf - kickstart flag - this bit is set to a 1 when a kickstart condition occurs or when the user writes it to a 1. this bit is cleared by writing it to a logic 0. * reserved bits. these bits are reserved for future use by dallas semiconductor. they can be read and written, but have no effect on operation.
ds1685/ds1687 22 of 40 extended control register 4b msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 abe e32k cs rce prs rie wie kse abe - auxiliary battery enable. this bit when written to a logic 1 will enable the v baux pin for extended functions. e32k - enable 32.768khz output. this bit when written to a logic 1 will enable the 32.768khz oscillator frequency to be output on the sqw pin. cs - crystal select bit. when cs is set to a 0, the osc illator is configured for operation with a crystal that has a 6 pf specified load capacitance. when cs=1, th e oscillator is configured for a 12.5pf crystal. cs is disabled in the ds1687 module and should be set to cs=0. rce - ram clear enable bit. when set to a 1, this bit enables a low level on rclr to clear all 242 bytes of user ram. when rce = 0, rclr and the ram clear function are disabled. prs - pab reset select bit. when set to a 0 the pw r pin will be set hi-z when the ds1685 goes into power fail. when set to a 1, the pwr pin will remain active upon entering power fail. rie - ram clear interrupt enable. when rie is set to a 1, the irq pin will be driven low when a ram clear function is completed. wie ? wake-up alarm interrupt enable. when v cc voltage is absent and wie is set to a 1, the pwr pin will be driven active low when a wake-up condition o ccurs, causing the wf bit to be set to 1. when v cc is then applied, the irq pin will also be driven low. if wie is set while system power is applied, both irq and pwr will be driven low in response to wf being set to 1. when wie is cleared to a 0, the wf bit will have no effect on the pwr or irq pins. kse - kickstart interrupt enable. when v cc voltage is absent and kse is set to a 1, the pwr pin will be driven active low when a kickstart condition occurs (ks pulsed low), causing the kf bit to be set to 1. when v cc is then applied, the irq pin will also be driven low. if kse is set to 1 while system power is applied, both irq and pwr will be driven low in response to kf being set to 1. when kse is cleared to a 0, the kf bit will have no effect on the pwr or irq pins.
ds1685/ds1687 23 of 40 system maintenance interrupt (smi) recovery stack an smi recovery register stack is located in th e extended register bank, locations 4eh and 4fh. this register stack, shown below, can be used by the bi os to recover from an smi occurring during an rtc read or write. rtc address rtc address-1 4eh rtc address-2 4fh rtc address-3 smi recovery stack 7 6 5 4 3 2 1 0 dv0 ad6 ad5 ad4 ad3 ad2 ad1 ad0 register bit definition the rtc address is latched on the falling edge of the ale signal. each time an rtc address is latched, the register address stack is pushed. the stack is only four registers deep, holding the three previous rtc addresses in addition to the current rtc address being accessed. the following waveform illustrates how the bios could recover the rtc address when an smi occurs. 1. the rtc address is latched. 2. an smi is generated before an rtc read or write occurs. 3. rtc address 0ah is latched and the address from 1 is pushed to the rtc address - 1 stack location. this step is necessary to change the bank select bit, dv0=1. 4. rtc address 4eh is latche d and the address from ?1" is pushed to location "4eh,? ?rtc address - 2? while 0ah is pushed to the ?rtc address - 1? loca tion. the data in this register, 4eh, is the rtc address lost due to the smi. 1 2 3 4 ale
ds1685/ds1687 24 of 40 absolute maximum ratings* voltage on any pin relativ e to ground -0.3v to +6v operating temperature, commercial 0c to 70c operating temperature, industrial -40 c to 85 c storage temperature -40c to +85c soldering temperature 260c for 10 seconds (see note 12) * this is a stress rating only and f unctional operation of the device at th ese or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) (-40 c to 85 c) parameter symbol min typ max units notes power supply voltage 5voperation v cc 4.5 5.0 5.5 v 1 power supply voltage 3v operation v cc 2.7 3.0 3.7 v 1 input logic 1 v ih 2.2 v cc +0.3 v 1 input logic 0 v il -0.3 0.6 v 1 battery voltage v bat 2.5 3.7 v 1 auxiliary battery voltage; v cc = 5.0v v baux 2.5 5.2 v 1 auxiliary battery voltage; v cc =3.0v v baux 2.5 3.7 v 1
ds1685/ds1687 25 of 40 dc electrical characteristics (0 c to 70 c; v cc =5.0v 10%) (-40 c to 85 c; v cc =5.0v 10%) parameter symbol min typ max units notes average v cc power supply current i cc1 7 15 ma 2, 3 cmos standby current ( cs =v cc -0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current i ol -1 +1 a 6 output logic 1 voltage (i out = -1.0 ma) v oh 2.4 v output logic 0 voltage (i out = +2.1 ma) v ol 0.4 v power fail trip point v pf 4.25 4.37 4.5 v 4 battery switch voltage v sw v bat , v baux v 9 battery leakage osc on i bat1 500 na 13 battery leakage osc off i bat2 200 na 13 i/o leakage i lo -1 +1 a 5 pwr output @ 0.4v i olpwr 10.0 ma 1 irq output @ 0.4v i olirq 2.1 ma 1
ds1685/ds1687 26 of 40 dc electrical characteristics (0 c to 70 c; v cc =3.0v 10%) (-40 c to 85 c; v cc =3.0v 10%) parameter symbol min typ max units notes average v cc power supply current i cc1 5 10 ma 2, 3 cmos standby current ( cs =v cc -0.2v) i cc2 0.5 2 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current i ol -1 +1 a 6 output logic 1 voltage @ = -0.4 ma v oh 2.4 v output logic 0 voltage @ = +0.8 ma v ol 0.4 v power fail trip point v pf 2.5 2.6 2.7 v 4 battery leakage osc on i bat1 500 na 13 battery leakage osc off i bat2 200 na 13 i/o leakage i lo -1 +1 a 5 pwr output @ 0.4v i olpwr 4 ma 1 irq output @ 0.4v i olirq 0.8 ma 1
ds1685/ds1687 27 of 40 rtc ac timing characteristics (0 c to 70 c; v cc =3.0v 10%) (-40 c to 85 c; v cc =3.0v 10%) parameter symbol min typ max units notes cycle time t cyc 260 dc ns pulse width, rd / wr low pw rwl 100 ns pulse width, rd / wr high pw rwh 100 ns input rise and fall time t r , t f 30 ns chip select setup time before wr , or rd t cs 20 ns chip select hold time t ch 0 ns read data hold time t dhr 10 50 ns write data hold time t dhw 0 ns muxed address valid time to ale fall t asl 30 ns muxed address hold time from ale fall t ahl 15 ns rd or wr high setup to ale rise t asd 30 ns pulse width ale high pw ash 80 ns ale low setup to rd or wr fall t ased 30 ns output data delay time from rd t ddr 20 80 ns 7 data setup time t dsw 60 ns irq release from rd t ird 2 s ac test conditions out put load: 50pf input pulse levels: 0-3.0v timing measurement reference levels input : 1.5v output: 1.5v input pulse rise and fall times: 5ns
ds1685/ds1687 28 of 40 rtc ac timing characteristics (0 c to 70 c; v cc =5.0v 10%) (-40 c to 85 c; v cc =5.0v 10%) parameter symbol min typ max units notes cycle time t cyc 195 dc ns pulse width, rd / wr low pw rwl 75 ns pulse width, rd / wr high pw rwh 75 ns input rise and fall time t r , t f 30 ns chip select setup time before wr , or rd t cs 20 ns chip select hold time t ch 0 ns read data hold time t dhr 10 50 ns write data hold time t dhw 0 ns muxed address valid time to ale fall t asl 30 ns muxed address hold time from ale fall t ahl 15 ns rd or wr high setup to ale rise t asd 25 ns pulse width ale high pw ash 40 ns ale low setup to rd or wr fall t ased 30 ns output data delay time from rd t ddr 20 60 ns 7 data setup time t dsw 60 ns irq release from rd t ird 2 s ac test conditions out put load: 50pf input pulse levels: 0-3.0v timing measurement reference levels input : 1.5v output: 1.5v input pulse rise and fall times: 5ns
ds1685/ds1687 29 of 40 ds1685/ds1667 bus timing for read cycle to rtc and rtc registers ds1685/ds1687 bus timing for write cycle to rtc and rtc registers
ds1685/ds1687 30 of 40 power-up power-down timing 5-volt device (t a = 25 c) parameter symbol min typ max units notes cs high to power-fail t pf 0 ns recovery at power-up t rec 150 ms v cc slew rate power- down t f 4.0 v cc 4.5v 300 s v cc slew rate power- down t fb 3.0 v cc 4.0v 10 s v cc slew rate power-up t r 4.5v v cc 4.0v 0 s expected data retention t dr 10 years 10, 11 power-up power-down timing 3-volt device (t a = 25 c) parameter symbol min typ max units notes cs high to power-fail t pf 0 ns recovery at power-up t rec 150 ms v cc slew rate power- down t f 2.6 v cc 2.7v 300 s v cc slew rate power-up t r 2.7v v cc 2.6v 0 s expected data retention t dr 10 years 10, 11 warning under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery back-up mode. capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 12 pf output capacitance c out 12 pf wake-up/kickstart timing (t a = 25 c) parameter symbol min typ max units notes kickstart input pulse width t kspw 2 s
ds1685/ds1687 31 of 40 wake-up/kickstart power on timeout t poto 2 seconds 8 power-up condition 3-volt device power-down conditi on 3-volt device cs v ih t rec 2.7v 2.6v 2.5v v cc power fail t r cs power fail v cc v ih t pf t f 2.7v 2.6v 2.5v
ds1685/ds1687 32 of 40
ds1685/ds1687 33 of 40 power-up condition 5.0-volt device power-down conditi on 5.0-volt device cs v ih t rec 4.5v 4.25v 4.0v v cc power fail t r power fail v cc cs v ih t pf t f 4.5v 4.25v 4.0v
ds1685/ds1687 34 of 40 wake-up/kickstart timing note: time intervals shown above are refere nced in wake-up/kickstart section. * this condition can occur with the 3-volt device.
ds1685/ds1687 35 of 40 notes: 1. all voltages are referenced to ground. 2. typical values are at 25c and nominal supplies. 3. outputs are open. 4. write protection trip point occurs durin g power-fail prior to switchover from v cc to v bat . 5. applies to the ad0-ad7 pins and the sqw pin when each is in a high impedance state. 6. the irq and pwr pins are open drain outputs. 7. measured with a load of 50pf + 1 ttl gate. 8. wake-up kickstart timeout generate d only when the oscillator is enabled and the countdown chain is not reset. 9. v sw is determined by the larger of v bat and v baux . 10. the ds1687 will keep time to an accuracy of 1 mi nute per month during data retention time for the period of t dr . 11. t dr is the amount of time that the internal battery can power the internal oscillator and internal registers of the ds1687. 12. real-time clock modules can be successfully processed through conv entional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85c. post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. 13. i bat1 and i bat2 are measured at v batt = 3.5v.
ds1685/ds1687 36 of 40 ds1685 24-pin dip pkg 24-pin dim min max a in. mm 1.245 31.62 1.270 32.25 b in. mm 0.530 13.46 0.550 13.97 c in. mm 0.140 3.56 0.160 4.06 d in. mm 0.600 15.24 0.625 15.88 e in. mm 0.015 0.380 0.050 1.27 f in. mm 0.120 3.05 0.145 3.68 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.625 15.88 0.675 17.15 j in. mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.022 0.56
ds1685/ds1687 37 of 40 ds1685 24-pin soic the chamfer on the body is optional. if it is not present, a terminal 1 identifier must be positioned so that 1/2 or more of its area is contained in the hatched zone. pkg 24-pin dim min max a in. mm 0.094 2.38 0.105 2.68 a1 in. mm 0.004 0.102 0.012 0.30 a2 in. mm 0.089 2.26 0.095 2.41 b in. mm 0.013 0.33 0.020 0.51 c in. mm 0.009 0.229 0.013 0.33 d in. mm 0.598 15.19 6.12 15.54 e in. mm 0.050 bsc 1.27 bsc e1 in. mm 0.290 7.37 0.300 7.62 h in. mm 0.398 10.11 0.416 10.57 l in. mm 0.016 0.40 0.040 1.02 phi 0 8
ds1685/ds1687 38 of 40 ds1685q 28-pin plcc pkg 28-pin dim min max a in. mm 0.300 bsc 7.62 b in. mm 0.445 11.30 0.460 11.68 b1 in. mm 0.013 0.33 0.021 0.53 c in. mm 0.027 0.68 0.33 0.84 d in. mm 0.480 12.19 0.500 12.70 d2 in. mm 0.390 9.91 0.430 10.92 e in. mm 0.090 2.29 0.120 3.05 e2 in. mm 0.390 9.91 0.430 10.92 f in. mm 0.020 0.51 g in. mm 0.480 12.19 0.500 12.70 h in. mm 0.165 4.19 0.180 4.57
ds1685/ds1687 39 of 40 ds1685e 24-pin tssop dim min max a - 1.10 a1 0.05 - a2 0.75 1.05 c 0.09 0.18 phi 0 8 l 0.50 0.70 e1 0.65 bsc b 0.18 0.30 d 7.55 8.00 e 4.40 nom g 0.25 ref h 6.25 6.55
ds1685/ds1687 40 of 40 ds1687 real-time clock plus ram note: pins 2, 3, 16 and 20 are missing by design. pkg 24-pin dim min max a in. mm 1.320 33.53 1.335 33.91 b in. mm 0.720 18.29 0.740 18.80 c in. mm 0.345 8.76 0.370 9.40 d in. mm 0.100 2.54 0.130 3.30 e in. mm 0.015 0.38 0.030 0.76 f in. mm 0.110 2.79 0.140 3.56 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.021 0.53

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