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lc868901/51 no.6710-1/20 overview the lc868901 sereis is a common driver for the liquid crystal dot-matrix graphic display. it generates 65 commons maximum. the lc868901series has the rc-oscillator circuit attached resistor and the capacitor outside, and generates the timing signals and lcd powers for the lc868900 segmentdrivers. as the lc868901 series is fabricated using cmos process technology, combining it with a cmos microcontroller produces an lcd device of low power demand. features ? classification interfacing allowed for 80-family and our lc868000 microcontroller :lc868901 interfacing allowed for motorola family :LC868951 ? 65 common outputs ? automatic lcd display controller duty 1 / 1 to 1 / 65 (programmable) bias 1 / 5, 1 / 7 and 1 / 9 (programmable) contrasts 32-step programmable instructions display on / off horizontal display bit control [horizontal display number] 5 [display pitch (bit length)] busy flag readable ? built-in power booster ? stand-by function two kinds of stand-by setting 1. applying low level to stb 2. programming stand-by releasing read after applying low level to cs and rd ? oscillator rc oscillator must be attached resistor and the capacitor outside. ? power supply logic circuit 3v to 5v (v dd ) ? cmos process ? factory shipment chip delivery form qfp100e package sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan lc868901/51 d2800 rm (im) fs any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. cmos ic ver. 1.01 61295 row driver ic for dot matrix graphic lcd preliminary ordering number : enn*6710
lc868901/51 no.6710-2/20 pin assignment package dimension (unit : mm) 3151 21.6 0.8 3.0max 1.6 17.2 0.825 130 31 50 51 80 81 1.6 0.575 0.575 0.15 2.7 15.6 0.3 20.0 23.2 14.0 0.65 0.825 100 0.8 0.65 0.1 sanyo : qip-100e (flp100) 50 c22 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 c21 c9 c7 c8 c6 c5 c3 c4 c2 c1 cap2 cap1 vot1 vot2 v ee 2 v ee 1 (nc) v3 62 61 60 59 58 57 56 55 54 53 52 51 64 63 65 66 67 68 70 69 72 71 73 74 75 77 76 78 79 22 21 20 23 24 25 26 27 28 29 30 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 c43 c54 c53 c52 c51 c50 c49 c48 c47 c46 c45 c44 c55 c58 c57 c56 c61 c60 c59 c62 c63 c64 c65 stb m cl2 rs wr rd cs 100 80 c23 c24 c25 c26 c27 c28 c29 c30 c31 c32 c33 c34 c35 c36 c37 c38 c39 c40 c41 c42 xv5 xv4 xv3 xv2 xv1 res v dd osc1 osc2 v ss db0 db1 db2 db3 db4 db5 db6 db7 82 81 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 (nc) (nc) ilc00202 sanyo : qip-100e
lc868901/51 no.6710-3/20 pads pin no. pad no. name pad axis pin no. pad no. name pad axis x m my m mx m my m m 1 1 cs -- 2113 -- 1645 51 51 c22 2478 1764 2 2 rd -- 1950 -- 1645 52 52 c21 2315 1764 3 3 wr -- 1788 -- 1645 53 53 c20 2153 1764 4 4 rs -- 1625 -- 1645 54 54 c19 1990 1764 5 5 cl2 -- 1463 -- 1645 55 55 c18 1828 1764 6 6 m -- 1300 -- 1645 56 56 c17 1665 1764 7 7 stb -- 1138 -- 1645 57 57 c16 1503 1764 8 8 c65 -- 914 -- 1794 58 58 c15 1340 1764 9 9 c64 -- 752 -- 1794 59 59 c14 1178 1764 10 10 c63 -- 589 -- 1794 60 60 c13 1015 1764 11 11 c62 -- 427 -1794 61 61 c12 853 1764 12 12 c61 -- 264 -- 1794 62 62 c11 690 1764 13 13 c60 -- 102 -- 1794 63 63 c10 528 1764 14 14 c59 61 -- 1794 64 64 c9 365 1764 15 15 c58 223 -- 1794 65 65 c8 203 1764 16 16 c57 386 -- 1794 66 66 c7 40 1764 17 17 c56 548 -- 1794 67 67 c6 -- 122 1764 18 18 c55 711 -- 1794 68 68 c5 -- 285 1764 19 19 c54 873 -1794 69 69 c4 -- 447 1764 20 20 c53 1036 -- 1794 70 70 c3 -- 610 1764 21 21 c52 1198 -- 1794 71 71 c2 -- 772 1764 22 22 c51 1361 -- 1794 72 72 c1 -- 935 1764 23 23 c50 1523 -- 1794 73 73 cap2 -- 1569 1617 24 24 c49 1686 -- 1794 74 74 cap1 -- 1732 1617 25 25 c48 1848 -- 1794 75 75 vot2 -- 1894 1617 26 26 c47 2011 -- 1794 76 76 vot1 -- 2057 1617 27 27 c46 2173 -- 1794 77 77 v ee 2 -- 2278 1617 28 28 c45 2336 -- 1794 78 78 v ee 1 -- 2441 1617 29 29 c44 2498 -- 1794 79 -- nc 30 30 c43 2661 -- 1794 80 79 v3 -- 2603 1617 31 31 c42 2690 -- 1482 81 80 xv5 -- 2526 1156 32 32 c41 2690 -- 1320 82 81 xv4 -- 2526 993 33 33 c40 2690 -- 1157 83 82 xv3 -- 2526 831 34 34 c39 2690 -- 995 84 83 xv2 -- 2526 668 35 35 c38 2690 -- 832 85 84 xv1 -- 2526 506 36 36 c37 2690 -- 670 86 85 res -- 2556 316 37 37 c36 2690 -- 507 87 86 v dd -- 2556 153 38 38 c35 2690 -- 345 88 87 osc1 -- 2556 -- 9 39 39 c34 2690 -- 182 89 88 osc2 -- 2556 -- 172 40 40 c33 2690 -- 20 90 89 v ss -- 2556 -- 334 41 41 c32 2690 143 91 90 db0 -- 2556 -- 497 42 42 c31 2690 305 92 91 db1 -- 2556 -- 659 43 43 c30 2690 468 93 92 db2 -- 2556 -- 822 44 44 c29 2690 630 94 93 db3 -- 2556 -- 984 45 45 c28 2690 793 95 94 db4 -- 2556 -- 1147 46 46 c27 2690 955 96 95 db5 -- 2556 -- 1309 47 47 c26 2690 1118 97 96 db6 -- 2556 -- 1472 48 48 c25 2690 1280 98 97 db7 -- 2556 -- 1634 49 49 c24 2690 1443 99 -- nc 50 50 c23 2690 1605 100 -- nc notes 1. using for chip, the substrate must be shortened to v dd , or left open. 2. ask the solder-soaking condition for qfp100e package.
lc868901/51 no.6710-4/20 block diagram c1 c65 lcd drivers oscillator timing generator power booster lcd power circuit contrast control circuit contrast control register time division register display number register display pitch register mode register data register instruction register busy flag vot1 vot2 cap1 cap2 v3 xv1 xv2 xv3 xv4 xv5 v ee 1 v ee 2 osc1 osc2 stb rs cs rd wr res cl2 m v dd v ss db0 db1 db2 db3 db4 db5 db6 db7 mode register system clock 1 system clock 2 ilc00203 pin function pin name pin no. i / o description pin form type v ss 90 -- negative power pin (-- ) v dd 87 -- positive power pin (+) v ee 1, 2 78, 77 -- lcd power pins vot1, 2 76, 75 -- power booster pins cap1, 2 74, 73 -- capacitor connecting pins for power booster db0 91 i / o data bus db0-4, 7 : c to db5, 6 : d db7 98 res 86 input reset (active low) b cs 1 input chip select (active low) a rd 2 input read (active low) a wr 3 input write (active low) a rs 4 input register select a rs=1 : instruction register rs=0 : data register cl2 5 output lcd clock for data shifting e m 6 output lcd clock for synchronizing e stb 7 input stand-by (active low) b v3 80 output monitor pin for lcd power xv1 to xv5 85 to 81 output lcd power suppliers c1 to c65 72 to 8 output common outputs for lcd display f
lc868901/51 no.6710-5/20 pin forms a type b type c type cs, rd, wr, rs pins res, stb pins db0 to db4, db7 d type e type f type db5, db6 cl2, m c1 to c65 in v dd v ss ilc00204 v dd in ilc00205 in / out v dd v ss data output control ilc00206 out v dd v ss data output control ilc00207 out v dd v ss ilc00208 out v dd v1 v4 v5 ilc00209
lc868901/51 no.6710-6/20 1. absolute maximum ratings at ta=25 c, v ss =0v parameter symbol pins conditions ratings v dd [v] min. typ. max. unit supply voltage v dd max v dd -- 0.3 +7.0 v input voltage vi(1) cs, rd, wr, rs, -- 0.3 vdd+0.3 res v i (2) db0 to db7 at input mode -- 0.3 v dd +0.3 v i (3) v ee 1, v ee 2v dd -- 21 v dd +0.3 output voltage v o (1) c1 to c65 v ee 2-- 0.3 v dd +0.3 v o (2) db0 to db7 at output mode -- 0.3 v dd +0.3 v o (3) m, cl2 -- 0.3 v dd +0.3 v o (4) vot1, vot2, v dd -- 21 v dd +0.3 cap1, cap2 high-level output ? ioah c1 to c65 the total all pins -- 25 ma current low-level output ? ioal c1 to c65 the total all pins 30 ma current maximum power pdmax qfp100e ta= -- 30 to + 70 c 200 mw dissipation operating topg -- 30 70 c temperature limits storage tstg -- 55 150 temperature limits 2. recommended operating limits at ta= -- 30 c to +70 c, v ss =0v parameter symbol pins conditions ratings v dd [v] min. typ. max. unit operating supply v dd v dd 2.5 6.0 v voltage limits lcd power supply v ee v ee 1, v ee 2 4.5 to 6.0 -- 2v dd v dd voltage limits 2.5 to 4.5 -- v dd v dd input high voltage v ih (1) db0 to db7 at input mode 4.5 to 6.0 2.2 v dd 2.5 to 4.5 0.75v dd v dd vih(2) cs, rd, wr, rs 4.5 to 6.0 2.2 vdd 2.5 to 4.5 0.75v dd v dd vih(3) res (schmitt), 4.5 to 6.0 0.75vdd vdd stb (schmitt) 2.5 to 4.5 0.75v dd v dd input low voltage v il (1) db0 to db7 at input mode 4.5 to 6.0 0 0.8 2.5 to 4.5 0 0.25v dd v il (2) cs, rd, wr, rs 4.5 to 6.0 0 0.8 2.5 to 4.5 0 0.25v dd vil(3) res (schmitt), 4.5 to 6.0 0 0.25vdd stb (schmitt) 2.5 to 4.5 0 0.25v dd oscillation frc osc1, osc2 ?rc oscillation 2.5 to 6.0 20 500 khz frequency limits ?fig. 1 osc1 osc2 rext cext fig.1 rc-oscillator circuit ilc00210
lc868901/51 no.6710-7/20 3. electrical characteristics at ta= -- 30 c to +70 c parameter symbol pins conditions ratings v dd [v] min. typ. max. unit output high v oh (1) db80 to db7 ?output mode 4.5 to 6.0 v dd -- 1.0 v voltage ?i oh = -- 1ma ?output mode 2.5 to 6.0 v dd -- 0.5 ?i oh = -- 0.1ma v oh (2) m, cl2 i oh = -- 0.4ma 4.5 to 6.0 v dd -- 0.4 i oh = -- 0.1ma 2.5 to 6.0 v dd -- 0.5 output low v ol (1) db0 to db7 ?output mode 4.5 to 6.0 0.4 voltage ?i ol =+0.6ma ?output mode 2.5 to 6.0 0.4 ?i oh =+0.1ma v ol (2) m, cl2 i ol =+0.4ma 4.5 to 6.0 0.4 i ol =+0.1ma 2.5 to 6.0 0.5 pull-up rpu(1) db0 to db7 ?input mode 4.5 to 6.0 150 500 900 k w resistance ?v in =0v ?input mode 2.5 to 4.5 300 750 1500 ?v in =0v rpu(2) cs, rd, wr, rs, vin=0v 4.5 to 6.0 150 500 900 res, stb v in =0v 2.5 to 4.5 300 750 1500 drop voltage v d (1) c1 to c65 ?-- 100 m a at each 4.5 to 6.0 150 mv between ci pin v dd and ci ? v dd --v ee 2=11v (i : 1 to 65) ?-- 15 m a at each 2.5 to 6.0 120 ci pin ? v dd --v ee 2=11v drop voltage v d (2) c1 to c65 ?-- 100 m a at each 4.5 to 6.0 150 mv between ci pin vx and ci ? v dd --v ee 2=11v (x : 1, 4) ?-- 15 m a at each 2.5 to 6.0 120 (i : 1 to 65) ci pin ? v dd --v ee 2=11v drop voltage v d (3) c1 to c65 ?+100 m a at each 4.5 to 6.0 -- 150 mv between ci pin vx and ci ? v dd --v ee 2=11v (x : 1, 4) ?+15 m a at each 2.5 to 6.0 -- 120 (i : 1 to 65) ci pin ? v dd --v ee 2=11v boosted voltage vot1 ?vot1 load current 5.0 -- 4.5 v ?fig. 2 =500 m a load current -- 4.0 =800 m a load current 2.9 -- 2.6 v =100 m a load current -- 2.3 =200 m a vot2 ?vot2 load current 5.0 -- 8.0 v ?fig. 3 =500 m a load current -- 6.0 =800 m a
lc868901/51 no.6710-8/20 parameter symbol pins conditions ratings v dd [v] min. typ. max. unit hysterisis voltage vhis res, stb 2.5 to 6.0 0.1vdd v xv1 output voltage vv1 xv1 ?lcd on 2.5 to 6.0 0.75v dd 0.80v dd 0.85v dd v ?1 / 5 bias xv2 output voltage vv2 xv2 ?xv5=0v 2.5 to 6.0 0.55v dd 0.60v dd 0.65v dd ?lcd clock xv3 output voltage vv3 xv3 frequency=0hz 2.5 to 6.0 0.35v dd 0.40v dd 0.45v dd ?fig. 4 xv4 output voltage vv4 xv4 2.5 to 6.0 0.15v dd 0.20v dd 0.25v dd lcd power ilcd1 ?v ee 1, v ee 2 ?lcd on 5.0 25 50 100 m a current ?1 / 5 bias ?v ee 1=open 2.9 15 29 60 ilcd2 ?v ee 1, v ee 2?v ee 2=0v 5.0 18 35.7 70 ?1 / 7 bias ? xv1-xv5=open 2.9 10 20.7 40 ilcd3 ?v ee 1, v ee 2 ?fig. 5 5.0 14 27.8 56 ?1 / 9 bias ?ccr0-4=0 2.9 8 16 32 contrast current ilc1 ?v ee 1, v ee 2 ?lcd on 5.0 750 1000 1500 m a ?ccr=01h ?v ee 1=open 2.9 750 1000 1500 ilc2 ?v ee 1, v ee 2?v ee 2=-- 3v 5.0 370 500 750 ?ccr=02h ?xv5=0v 2.9 370 500 750 ilc3 ?v ee 1, v ee 2 ?fig. 6 5.0 200 250 400 ?ccr=04h 2.9 200 250 400 ilc4 ?v ee 1, v ee 2 5.0 100 125 200 ?ccr=08h 2.9 100 125 200 ilc5 ?v ee 1, v ee 2 5.0 50 62 100 ?ccr=10h 2.9 50 62 100 operation current idd(1) ?frc=500khz 4.5 to 6.0 200 400 m a dissipation ?lcd off 2.5 to 4.5 100 300 ?fig. 7 stand-by current idd(2) ?frc=0hz 4.5 to 6.0 0.05 30 m a dissipation ?lcd off 2.5 to 4.5 0.02 20 ?fig. 7 [notes] the specifications above are for a die mounted in a qfp100e type package. however, we ship this product as a die only, not a package chip. therefore, the operational characteristics may vary depending on the user's packaging techniques.
lc868901/51 no.6710-9/20 v dd v dd cap1 cap2 vot1 v ss osc1 osc2 v ee 1 v ee 2 v3 v dd v dd cap1 cap2 vot1 vot2 v ss osc1 osc2 v ee 1 v ee 2 xv1 xv4 v dd v dd v ss osc1 osc2 v ee 1 v ee 2 v3 v open xv5 v v dd v dd cap1 cap2 vot1 vot2 v ss osc1 osc2 v ee 1 v ee 2 v3 xv1 xv4 a xv5 -- 3 v v dd v dd v ss osc1 osc2 v ee 1 v ee 2 v3 a open cap1 cap2 vot1 vot2 cap1 cap2 vot1 vot2 a xv1 xv5 xv1 xv5 xv1 xv5 v dd v dd cap1 cap2 vot1 vot2 v ss osc1 osc2 v ee 1 v ee 2 v3 v xv1 xv5 v3 open open open open open open open open open open open open open fig.2 measurement circuit for boosted voltage (1) ilc00211 fig.4 measurement circuit for xv1 to xv4 ilc00213 fig.5 measurement circuit for lcd power current ilc00214 fig.6 measurement circuit for contrast current ilc00215 fig.7 measurement circuit for current dissiation ilc00216 fig.3 measurement circuit for boosted voltage (2) ilc00212
lc868901/51 no.6710-10/20 ac characteristics at ta= -- 30 c to +70 c ? reading cycle ? writing cycle no. item symbol pins and conditions value v dd [v] min. max. unit 1 rd, wr cycle time tcyc1 rd 4.5 to 6.0 (500) ns 2.5 to 4.5 tcyc2 wr 4.5 to 6.0 (500) ns 2.5 to 4.5 2 rd pulse width tpw1 rd 4.5 to 6.0 (220) ns wr pulse width wr 2.5 to 4.5 3 rise / fall time tr1, tf1 rd 4.5 to 6.0 (20) ns 2.5 to 4.5 4 address set-up time tas1 cs, rs, rd 4.5 to 6.0 (40) ns 2.5 to 4.5 tas2 cs, rs, wr 4.5 to 6.0 (40) ns 2.5 to 4.5 5 address hold time tah1 cs, rs, rd 4.5 to 6.0 (10) ns 2.5 to 4.5 tah2 cs, rs, wr 4.5 to 6.0 (10) ns 2.5 to 4.5 6 data delay time tddr1 rd, db0 to db7, cl=50pf 4.5 to 6.0 (120) ns 2.5 to 4.5 7 data hold time tdhr1 rd, db0 to db7, cl=50pf 4.5 to 6.0 (20) ns 2.5 to 4.5 8 data set-up time tdsw1 wr, db0 to db7, cl=50pf 4.5 to 6.0 (60) ns 2.5 to 4.5 9 data hold time tdhw1 wr, db0 to db7, cl=50pf 4.5 to 6.0 (10) ns 2.5 to 4.5 tcyc1 tpw1 tr1 tf1 tddr1 tdhr1 tas1 tah1 rd cs, rs db0 to 7 tcyc2 tpw1 tr1 tf1 tdhw1 tas2 tah2 tdsw1 db0 to 7 cs, rs wr ilc00217 ilc00218
lc868901/51 no.6710-11/20 applications 1. 64 5 160-dot display 2. 65 5 160-dot display db cs rs rd wr cl2 m lcd powers db cs rs rd wr cl2 m lcd powers db cs rs rd wr cl2 m lcd powers 1-64 com 1-80 seg lcd panel 64x160 dots seg 81-160 lc868900 lc868900 lc868901 p0 p46 p47 lc868901 db cs rs rd wr cl2 m lcd powers db cs rs rd wr cl2 m lcd powers db cs rs rd wr cl2 m lcd powers 1-65 com 1-80 seg lcd panel 65x160 dots seg 81-160 lc868910 lc868910 lc868901 p0 p46 p47 lc868901 ilc00219 ilc00220
lc868901/51 no.6710-12/20 block descriptions 1. interfacing block the interfacing block is composed by an instruction register and five data registers. the instruction register selects the data register to transfer the following data. a. instruction register the instruction register specifies five kinds of the data registers and holds the data until other instruction data is set to the instruction register. also, this instruction register can be read a busy flag. ? instruction setting conditions 1. set cs to 0 (low level). for chip selecting 2. set wr to 0. for write operating 3. set rs to 1. for instruction specifying 4. set db to the instruction data b. data registers the five data-registers specify the parameters for displaying lcd, which are five of mode, display pitches, display number, time division, and contrast. ? data setting conditions 1. set cs to 0 (low level). for chip selecting 2. set wr to 0. for write operating 3. set rs to 0. for parameter specifying 4. set db to the parameter data note that the instruction and data can be written while the rc oscillation runs. busy flag should be set during writing to the data register. the instruction data, code, is shown below. specified register r/w rs db7 db6 db5 db4 db3 db2 db1 db0 notes mode register 0 1 0 0 0 0 0 0 0 0 addressing 0 0 mode data data setting display pitch register 0 1 0 0 0 0 0 0 0 1 addressing 00 vopon vrsel - - - dp - 1 data setting display number register 0 1 0 0 0 0 0 0 1 0 addressing 0 0 dn - 1 data setting time division register 0 1 0 0 0 0 0 0 1 1 addressing 0 0 0 0 nx - 1 data setting contrast control register 0 1 0 0 0 0 0 1 0 0 addressing 00 bias1 bias0 boost contrast data data setting read busy flag 1 1 busy no meaning data reading 2. timing control block the timing control block is composed by the oscillator circuit and the timing generator circuit. a. oscillator resistor and capacitor must be mounted externally. the oscillator should be stop in stand-by state. see later chapter for more details. b. timing generator the timing generator generates two system clocks and the several signals for lcd displaying. s1, system clock 1, runs for reading, writing and transferring data when the lc868901 is not in stand-by state and s2, system clock 2, runs while the lcd controller works. osc1 osc2 stb s1 s2 reset system clock1 generator system clock2 generator oscillation control mode register 76543210 oscillation circuit ilc00221
lc868901/51 no.6710-13/20 cl2, m for lcd displaying should be generated to the lc868900 segment driver. in stand-by state, all the generated signals freeze. 3. busy flag busy flag is outputted to db7 when reading operation is established with rs = 1. the busy flag should be set to 1 during writing to the data register, not the instruction register. when the writing operation is completed, the busy flag should be reset to 0. when the busy flag is set to 1, new parameter data cannot be written. thus, write the data after reading the busy flag and making sure that it is 0. ? busy-flag reading condition 1. set cs to 0 (low level). for chip selecting 2. set rd to 0. for read operating 3. set rs to 1. for busy-flag reading reading operation need not to set the instruction register. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 busy 1 1 busy no meaning 4. data registers a. mode register write code 00h into the instruction register and specify the mode register. register r/w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0 1 0 0 0 0 0 0 0 0 mode 0 0 -- mode data mode0 (bit0 of mode register) lcd controller operation mode0=1 lcd controller starts to work. (s1 and s2 run) mode0=0 lcd controller stops. (s1 runs) mode0=0 when resetting or at stand-by state mode1 (bit1 of mode register) lcd display mode1=1 lcd display enable (on) mode1=0 lcd display disable (off) mode1=0 when resetting or at stand-by state mode2 (bit2 of mode register) stand-by mode2=1 stand-by state mode2=0 operation state mode3 (bit3 of mode register) scanning direction mode3=1 c1 to c65 in 1 / 65 duty mode3=0 c65 to c1 in 1 / 65 duty mode3=0 when resetting
lc868901/51 no.6710-14/20 ? waveforms in case of c1 to c65 ? waveforms in case of c65 to c1 mode4 to mode6 (bit4 to bit6 of mode register) time division the following table shows the time division value. time division mode6 mode5 mode4 1 / 1 0 0 0 1 / 2 0 0 1 1 / 4 0 1 0 1 / 8 0 1 1 1 / 16 1 0 0 1 / 32 1 0 1 1 / 64 1 1 0 1 / 128 1 1 1 note that mode1 should be set to 1 after setting the required lc868901-registers and the registers and ram data of the equipped lc868900. next shows the setting sequence for displaying on. 1. set mode0 to 1 for starting the controller operation. 2. set the registers of the lc868901/lc868900 and ram data of the lc868900. 3. set mode1 to 1 for displaying on. next shows the sequence for displaying off. 1. set mode1 to 0 for displaying off. 2. set mode0 to 0 for stopping the controller operation. com1 com2 com3 v4 v4 v4 v dd v5 v1 v1 v1 v1 v5 v1 v5 v1 com65 v dd v4 v dd v4 v4 v dd v4 v4 v4 v5 v1 v5 v1 v1 v5 v1 v1 v5 v1 v dd ilc00222 com65 com64 com63 v4 v4 v4 v dd v5 v1 v1 v1 v1 v5 v1 v5 v1 com1 v dd v4 v dd v4 v4 v dd v4 v4 v4 v5 v1 v5 v1 v1 v5 v1 v1 v5 v1 v dd ilc00223 osc1 osc2 divider reset multiplexer 1 / 1 to 1 / 128 clock for lcd display oscillation circuit ilc00224
lc868901/51 no.6710-15/20 b. horizontal pitch register write code 01h into the instruction register and specify the horizontal pitch register. the horizontal pitch register specifies the horizontal pitch, the lcd power output and ladder resistor value. register r/w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0 1 0 0 0 0 0 0 0 1 pitch 0 0 vopon vrsel -- -- -- dp-1 ? vopon specifies the lcd power source. when vopon=1, the lcd powers, xv1 to xv5, are provided through the op-amps. when vopon=0, the lcd powers are provided by the ladder resistors directly. ? vrsel specifies resistance of the ladder resistors. see the following table. when vrsel=1, all resistance of the ladder resistors is specified to 4kohms. when vrsel=0, all resistance is specified to 20kohms. ? dp indicates how many bits from the lc868900 ram data appear in an 1-byte display. dp must be set one of the following three values. dp db2 db1 db0 display pitch 61 0 1 6 71 1 0 7 81 1 1 8 note that rv23 varies according to the specified bias. (c.f. rv23=60k ohms at vrsel = 0 in 1 / 7-bias specification) c. horizontal number register write code 02h into the instruction register and specify the horizontal number register. the horizontal number register specifies the horizontal display number. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0 1 0 0 0 0 0 0 1 0 number 0 0 dn - 1 ? dn indicates the number of bytes in the horizontal direction. ? n, the total number of dots positioned horizontally on the screen, is given by the following formula. n=dp * dn (n 80) ? numbers in range 2 to 10 in decimal can be set as dn. d. time division register write code 03h into the instruction register and specify the time division register. the time division register specifies the display duty. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0 1 0 0 0 0 0 0 1 1 division 0 0 0 nx - 1 rvd1 rv12 rv23 rv34 rv45 20k 20k 20k 20k 20k 4k 4k 4k 4k 4k vrsel 0 1 rvd1 rv12 rv23 rv34 rv45 v1 v2 v3 v4 v5 ilc00225
lc868901/51 no.6710-16/20 ? nx represents the number of the time divisions. ? consequently, 1 / nx value means the display duty. ? numbers in range 2 to 65 in decimal can be set as nx. e. contrast control register write code 04h into the instruction register and specify the contrast control register. the contrast control register specifies the contrast resistor value, the display bias and the power booster. register r/w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0100 001 000 contrast 0 0 bias1 bias0 boost contrast ? contrast(ccr4-0) specifies in 32-step contrast resistor value. see the following table. ccr4 ccr3 ccr2 ccr1 ccr0 value 00000 0 00001 1r 00010 2r 11110 30r 11111 31r ? external contrast control available 1. contrast=0for setting the contrast control resistance to 0 ohm. 2. variable resistor must be connected between v ee 2 and the negative lcd power to adjust the lcd contrast. ? boost specifies the lcd power booster function. when boost = 1, the double power booster (doubler) functions. when boost = 0, the triple power booster (tripler) functions. (a) tripler (b) doubler boost=0 boost=1 see 6. lcd power unit ? biases specify the displayed lcd bias. bias1 bias0 bias 0 0 1 / 5 0 1 1 / 5 1 0 1 / 7 1 1 1 / 9 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ccr0 ccr1 ccr2 ccr3 ccr4 1r 2r 4r 8r 16r v5 v ee 1 mode1 v ee 2 ilc00226 cap1 cap2 v dd vot1 vot2 v ee 2 cap1 cap2 v dd vot1 vot2 v ee 2 ilc00228 ilc00227
lc868901/51 no.6710-17/20 5. lcd driver unit next shows the common driver block diagram. common waves (mode3=1, 1 / 65 duty) scanning direction can be set by mode3, bit 3 of mode register. mode3=1 from c1 to c65 mode3=0 from c65 to c1 ex.1. mode3=1 and 1 / 64 duty scanning direction c1 to c64 available commons c1 to c64 nonuse commons c65 ex.2. mode3=0 and 1 / 32 duty scanning direction c65 to c34 available commons c34 to c65 nonuse commons c1 to c33 ex.3. mode3=0 and 1 / 64 duty scanning direction c65 to c2 available commons c2 to c65 nonuse commons c1 alternating signal to lcd common driver v dd v1 v4 v5 shift clock frame signal mode3=0 mode3=1 shift r egister common drivers c1 c2 c3 c4 c5 c6 c7 c8 c9 c56 c57 c58 c59 c60 c61 c62 c63 c64 c65 ilc00229 com1 com2 com3 v4 v4 v4 v dd v5 v1 v1 v1 v1 v5 v1 v5 v1 com65 v dd v4 v dd v4 v4 v dd v4 v4 v4 v5 v1 v5 v1 v1 v5 v1 v1 v5 v1 v dd cl2 m 1234 65 64 1234 65 64 1234 ilc00230
lc868901/51 no.6710-18/20 6. lcd power unit the lcd power unit provides the lcd powers to the attached drivers according to the specified bias. xv1 to xv5 pins are used. ? bias biases specify the displayed lcd bias. bias1 bias0 bias 0 0 1 / 5 0 1 1 / 5 1 0 1 / 7 1 1 1 / 9 ? lcd powers the voltage of v ee 2 must be set according to the specified duty or the specification of an lcd panel. the following four connections can be allowed. 1. v ee 2=v ss 1 / 16 duty or less (according to the lcd-panel characteristics) v dd -- v ss 3 5v 2. v ee 2=vot1 the power booster provides two times of (v dd - v ss ) voltage to vot1. the power booster must be attached two a capacitors. the boosted powers are supplied to the following blocks. ?lcd drivers ?ladder resistors ?lcd contrast controller the lcd-drive current is specified by the capacitance of the attached capacitor. [notes] select doubler on program (boost = 1) when using vot1.never use vot2 when selecting doubler. open open open lc868901 v dd v ss v ee 1 v ee 2 cap1 cap2 vot1 vot2 ilc00231 open open lc868901 v dd v ss v ee 1 v ee 2 cap1 cap2 vot1 vot2 ilc00232
lc868901/51 no.6710-19/20 3. v ee 2=vot2 set boost to 0 to use the tripler function. the power booster provides three times of (v dd -- v ss ) voltage to vot2. the power booster must be attached three capacitors. the boosted powers are supplied to the following blocks. ?lcd drivers ?ladder resistors ?lcd contrast controller the lcd-drive current is specified by the capacitance of the attached capacitors. 4. v ee 2 supplied by the external power unit the external power unit must be attached between v ss and v ee 2 if the lcd display voltage must be provided to the v dd -- v ss voltage or more without using built- in power booster. see the following figure. set the external voltage as below. 0 v > [ external power supply ] > -- 3 x (v dd -- v ss ) ? contrast control the lcd contrast can be specified by ccr, which is allowed to 32-step contrast. if more than 32-step contrast must be needed, attach and adjust a variable resistor between v ee 2 and the specified power supply. see contrast control register. open lc868901 v dd v ss v ee 1 v ee 2 cap1 cap2 vot1 vot2 ilc00233 open open open lc868901 v dd v ss v ee 1 v ee 2 cap1 cap2 vot1 vot2 external power open open ilc00234 ccr0 ccr1 ccr2 ccr3 ccr4 1r 2r 4r 8r 16r v5 v ee 1 mode1 v ee 2 v dd v1 v2 v3 v4 ilc00235
lc868901/51 no.6710-20/20 specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co. , ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of december, 2000. specifications and information herein are subject to change without notice. ps 7. stand-by function stand-by function is prepared to reduce the dissipation current while lcd off. stand-by means all the lc868901 function freeze. thus, in stand-by state, the lcd controller and drivers stop operation. two ways to make the lc868901 stand-by is prepared. 1) set mode2 (bit2 of mode register) to 1. 2) supply stb to low. also, two ways to release stand-by is prepared. 1) reset supply res to low. it makes the lc868901 reset. supply res to high to make the lc868901 run. 2) reading read the target lc868901. (i.e., cs = 0 and rd = 0) [notes] db7 should be set output state at reading. so, ports connected to db7 of the lc868901 must be set to the input state. 8. reset function reset to initialize when the power is turned on. initialized value and state 1. busy flag reset 2. oscillator operate 3. stand-by release 4. lcd controller stop 5. lcd display off 6. lcd power xv1 to xv5=v dd , v ee 1=v dd 7. scanning direction c65 to c1 8. power booster stop 9. lcd power source ladder resisters directly note that resetting may make all bits of each register except mode3 to mode0 change during the operation. re-set all of registers to re-display or re-operate.

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