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OPA569 rail-to-rail i/o, 2a power amplifier description the OPA569 is a low-cost, high-current, operational amplifier designed for driving a wide variety of loads while operating on low-voltage supplies. it operates from either single or dual supplies for design flexibility and has rail-to-rail swing on the input and output. typical output swing is within 200mv of the supply rails, with output current of 2a. output swing closer to the rails is achievable with lighter loads. the OPA569 is unity gain stable, has low dc errors, is easy to use, and free from the phase inversion problems found in some power amplifiers. high performance is maintained at voltage swings near the output rails. the OPA569 provides an accurate user-selected current limit that is set with an external resistor, or digitally adjusted via a digital-to-analog converter. the OPA569 output can be independently disabled using the enable pin, saving power and protecting the load. the i monitor pin provides a 1:475 bidirectional copy of the output current. this eliminates the need for a series current shunt resistor, allowing more voltage to be applied to the load. this pin can be used for simple monitoring, or feedback control to establish constant output current. two flags are provided: one for warning of thermal over- stress, and one for current limit condition. the thermal flag pin can be connected to the enable pin to provide a thermal shutdown solution. packaged in the texas instruments powerpad package, it is small and easy to heat sink. the OPA569 is specified for operation over the extended industrial temperature range, ?0 c to +85 c. features high output current: 2a output swings to: 200mv of rails with i o = 2a thermal protection adjustable current limit two flags: current limit and temperature warning low supply voltage operation: 2.7v to 5.5v shutdown function with output disable small power package: so-20 powerpad? applications thermoelectric cooler driver laser diode pump driver valve, actuator driver synchro, servo driver transducer excitation general linear power booster for op amps paralleling option for higher current applications www.ti.com production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ?2002, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. sbos264 ?december 2002 powerpad is a trademark of texas instruments. o p a 5 6 9 OPA569 thermal flag v v o parallel out 1 parallel out 2 note: (1) connect for thermal protection. in +in v+ 5 12,13 17, 18 7 4 8 2 14, 15 9 3 19 6 current limit set r set (1) current limit flag i monitor enable i = i o /475
OPA569 sbos264 2 www.ti.com pin # name description 1, 10, 11, 20 powerpad powerpad connection pins 2 parallel out 1 connection for paralleling multiple amplifiers 3 current limit set current limit set pin 4 current limit flag indicates when part is in current limit (active low). 5 in inverting input 6 +in noninverting input 7 thermal flag indicates thermal stress (active low) 8 enable enabled high. shut down low. 9 parallel out 2 connection for paralleling multiple amplifiers 12, 13 v+ positive power-supply voltage 14, 15 v o output 16 nc no internal connection 17, 18 v negative power-supply voltage 19 i monitor provides 1:475 bidirectional copy of output current. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper han- dling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. supply voltage ................................................................................. +7.5v output current ................................................................. see soa curve signal input terminals (pins 2, 5, 6, and 9): voltage (2) ............................................... (v ) 0.5v to (v+) + 0.5v current (2) ................................................................................ 10ma output short-circuit (3) ........ continuous when thermal protection enabled current monitor (pin 19) short-circuit ..................................... continuous enable pin (pin 8) .......................................... (v ) 0.5v to (v ) + 7.5v powerpad (pins 1, 10, 11, 20, and pad) ...... (v ) 0.5v to (v ) + 0.5v current limit set (pin 3) ................................. (v ) 0.5v to (v+) + 0.5v operating temperature .................................................. 55 c to +125 c storage temperature ..................................................... 65 c to +150 c junction temperature .................................................................... +150 c lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may de- grade device reliability. these are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those specified is not implied. (2) input terminals are diode-clamped to the power-supply rails. input signals that can swing more than 0.5v beyond the supply rails should be current limited to 10ma or less. (3) short-circuit to ground. pin configuration specified package temperature package ordering transport product package-lead designator (1) range marking number media, quantity OPA569 so-20 powerpad dwp 40 c to +85 c OPA569a OPA569aidwp rails, 38 " """" OPA569aidwpr tape and reel, 1000 note: (1) for the most current specifications and package information, refer to our web site at www.ti.com. package/ordering information absolute maximum ratings (1) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 powerpad (1) parallel out 1 current limit set current limit flag in +in thermal flag enable parallel out 2 powerpad (1) powerpad (1) i monitor v (3) v (3) nc (2) v o (3) v o (3) v+ (3) v+ (3) powerpad (1) OPA569 metal powerpad heat sink (located on bottom side) notes: (1) powerpad pins 1, 10, 11, and 20 and the powerpad should be connected to the most negative supply (v ) in either single or split supply configurations. (2) nc means no internal connection. (3) the following pin pairs must be connected together: 12 and 13; 14 and 15; 17 and 18. top view so pin descriptions
OPA569 sbos264 3 www.ti.com electrical characteristics: v s = +2.7v to +5.5v boldface limits apply over the specified temperature range, t a = C 40 c to +85 c. at t case = +25 c, r l = 1k ? , and connected to v s /2, unless otherwise noted. notes: (1) see typical characteristic maximum output voltage vs frequency . (2) see the typical characteristic total harmonic distortion + noise vs frequency . (3) swing to the rail is measured in final test. under those conditions, the a ol is derived from characterization. (4) see safe operating area (soa) plot. (5) see typical characteristic overshoot vs load capacitance . (6) external current limit setting resistor is required. see figure 1. (7) i limit is the value of the desired current limit and is equal to 9800 (i set ), where i set is the current through the current limit set pin (pin 3). errors from this parameter can be calibrated out see applications information section. (8) v set is a voltage reference that equals the difference between the voltage of the current limit set pin and v , and is referenced to the negative rail. errors from this parameter can be calibrated out see applications information section. (9) % tolerance = [(i out /475) i monitor ] 100/i monitor . OPA569ai parameter condition min typ max units offset voltage input offset voltage v os i o = 0v, v s = +5v 0.5 2mv vs temperature dv os /dt t a = C 40 c to +85 c 1.3 v/ c vs power supply psrr v s = +2.7v to +5.5v, v cm = (v ) +0.55v 12 60 v/v input bias current input bias current i b 1 10 pa vs temperature (doubles every 10 c) input offset current i os 2 10 pa noise input voltage noise density, f = 1khz e n 12 nv/ hz f = 0.1hz to 10hz 8 vp-p current noise density, f = 1khz i n 0.6 fa/ hz input voltage range common-mode voltage range v cm linear operation (v ) 0.1 (v+) + 0.1 v common-mode rejection ratio cmrr v s = +5v, 0.1v < v cm < 3.2v 80 100 db v s = +5v, 0.1v < v cm < 5.1v 60 80 db input impedance differential 10 13 || 4.5 ? || pf common-mode 10 13 || 9 ? || pf open-loop gain open-loop voltage gain a ol 0.2v < v o < 4.8v, r l = 1k ? , v s = +5v 100 126 db 0.3v < v o < 4.7v, r l = 1.15 ? , v s = +5v 90 db frequency response gain bandwidth product gbw 1.2 mhz slew rate sr g = +1, v o = 4.0v step 1.2 v/ s full-power bandwidth (1) see typical characteristics settling time: 0.1% g = 1, v o = 4.0v step 5 s total harmonic distortion + noise (2) thd+n see typical characteristics output voltage output swing from rail v o r l = 1k ? , a ol > 100db (v ) + 0.2 (v s ) 0.02 (v+) 0.2 v i o = 2a, v s = +5v, a ol > 80db (3) (v ) + 0.3 (v s ) 0.15 (v+) 0.3 v maximum continuous current output: dc (4) 2.4 a capacitive load drive (5) c load see typical characteristics output disabled output impedance 12m || 570 ? || pf current limit output current limit (6) externally adjustable 0.2 to 2.2 a current limit equation i limit = i set 9800 a r set equation r set = 9800 (1.18v/i limit ) ? current limit tolerance (7) , positive i limit = 1a 3 10 % negative i limit = 1a 3 15 % voltage on current limit set pin t olerance (8) (v ) + 1.05 (v ) + 1.18 (v ) + 1.3 v output current monitor (pin 19) output current monitor i m i m = i o /475 a output current monitor tolerance (9) , positive i o = +1a, r monitor = 400 ? 3 10 % negative i o = 1a, r monitor = 400 ? 3 15 % compliance voltage range linear operation see d iscussion on current monitor section
OPA569 sbos264 4 www.ti.com enable/shutdown input (pin 8) enable pin b ias current v sd = 0v 0.2 a high (output enabled) v sd pin open or forced high (v ) + 2.5 v low (output disabled) v sd pin forced low (v ) + 0.8 v output disable time r l = 1 ? 0.5 s output enable time r l = 1 ? 15 s thermal flag pin (pin 7) junction temperature: t j alarm (thermal flag pin low) thermal overstress +147 c return to normal operation (thermal flag pin high) normal operation +130 c thermal flag pin v oltage normal operation i 7 = +25 a(v+) 0.8v v+ v during thermal overstress, i 7 = 25 av (v ) + 0.8 v current limit flag pin (pin 4) current limit flag pin v oltage normal operation, i 4 = +25 a(v+) 0.8v v+ v during c urrent limit, i 4 = 25 av (v ) + 0.8 v power supply specified voltage r ange v s +2.7 +5.5 v operating voltage range +2.7 +5.5 v quiescent current (10) i q i o = 0, i limit = 200ma, v s = 5v +3.4 +6 ma i o = 0, i limit = 2a, v s = 5v +9 +11 ma quiescent current in shutdown mode i o = 0, v sd = 0.8v, v s = 5v +0.01 ma temperature range specified range junction temperature 40 +85 c operating range junction temperature 55 +125 c storage range 65 +150 c thermal resistance, junction-to-case jc 0.37 c/w thermal resistance, junction-to-ambient ja 2oz trace and 9in 2 copper pad 21.5 c/w with solder electrical characteristics: v s = +2.7v to +5.5v (cont.) boldface limits apply over the specified temperature range, t a = C 40 c to +85 c. at t case = +25 c, r l = 1k ? , and connected to v s /2, unless otherwise noted. OPA569ai parameter condition min typ max units note: (10) quiescent current is a function of the current limit setting. see application section adjustable current limit and current limit flag pin .
OPA569 sbos264 5 www.ti.com typical characteristics at t a = +25 c, v s = +5v, unless otherwise noted. 180 160 140 120 100 80 60 40 20 0 20 open-loop gain and phase vs frequency frequency (hz) 1 10 100 1k 10k 100k 10m 1m 0.1 0 20 40 60 80 100 120 140 160 180 200 phase ( ) a ol (db) 120 100 80 60 40 20 0 power-supply and common-mode rejection ratio vs frequency frequency (hz) psrr and cmrr (db) 1 10 100 1k 10k 100k cmrr psrr 300 250 200 150 100 50 0 output swing to positive rail vs supply voltage supply voltage (v) swing to rail (mv) 2.7 3.0 3.5 4.0 4.5 5.0 5.5 i out = 200ma i out = 2a i out = 1a 300 250 200 150 100 50 0 output swing to negative rail vs supply voltage supply voltage (v) swing to rail (mv) 2.7 3.0 3.5 4.0 4.5 5.0 5.5 i out = 200ma i out = 2a i out = 1a 300 250 200 150 100 50 0 output swing to positive rail vs temperature temperature ( c) swing to rail (mv) 55 35 15 5 25 45 65 85 v s = 2.7v, i o = 2a v s = 5v, i o = 1a v s = 2.7v, i o = 200ma v s = 5v, i o = 2a v s = 2.7v, i o = 1a v s = 5v, i o = 200ma 300 250 200 150 100 50 0 output swing to negative rail vs temperature temperature ( c) swing to rail (mv) 55 35 15 5 25 45 65 85 v s = 2.7v, i o = 2a v s = 5v, i o = 1a v s = 5v, i o = 200ma v s = 5v, i o = 2a v s = 2.7v, i o = 1a v s = 2.7v, i o = 200ma
OPA569 sbos264 6 www.ti.com typical characteristics (cont.) at t a = +25 c, v s = +5v, unless otherwise noted. 1000 100 10 1 input voltage noise spectral density vs frequency frequency (hz) input voltage noise (nv hz) 10 100 1k 10k 100k 0.1hz to 10hz input voltage noise 1 v/div 1s/div 6 5 4 3 2 1 0 maximum output voltage vs frequency frequency (hz) output voltage (vp-p) 100 1k 100k 10k 1m v s = 5v r l = 1k ? r l = 1 ? r l = 1k ? v s = 2.7v r l = 1 ? 10 1 0.1 0.01 0.001 total harmonic distortion+noise vs frequency frequency (hz) thd+n (%) 20 100 1k 10k 20k r l = 2 ? r l = 8 ? r l = 1k ? 10 8 6 4 2 0 quiescent current vs supply voltage supply voltage (v) quiescent current (ma) 2.7 3 3.5 4 4.5 5 5.5 current limit = 1a current limit = 2a current limit = 200ma 10 8 6 4 2 0 quiescent current vs temperature temperature ( c) quiescent current (ma) 55 35 5 15 25 45 65 105 85 125 i q (i limit = 2a) i q (i limit = 200ma)
OPA569 sbos264 7 www.ti.com typical characteristics (cont.) at t a = +25 c, v s = +5v, unless otherwise noted. 12 10 8 6 4 2 0 shutdown current vs supply voltage supply voltage (v) shutdown current ( a) 2.7 3 3.5 4 4.5 5 5.5 i limit = 200ma, 1a, and 2a shutdown current vs temperature temperature ( c) shutdown current ( a) 12 10 8 6 4 2 0 55 35 5 15 25 45 65 105 85 125 10 8 6 4 2 0 quiescent current vs current limit setting current limit setting (a) quiescent current (ma) 0 0.5 1 1.5 2 2.5 10000 1000 100 10 1 0.1 0.01 input bias current vs temperature temperature ( c) ? input bias current ? (pa) 55 35 15 5 25 45 65 85 105 125 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 slew rate vs load resistance load resistance ( ? ) slew rate (v/ s) 110 sr sr+ 100 1000 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 slew rate vs temperature temperature ( c) slew rate (v/ s) 55 5 25 45 35 15 65 85 105 125 sr sr+
OPA569 sbos264 8 www.ti.com typical characteristics (cont.) at t a = +25 c, v s = +5v, unless otherwise noted. 1.2 1.19 1.18 1.17 1.16 voltage on current limit set pin vs temperature temperature ( c) [v set (v )] (v) 55 35 15 5 65 85 105 25 45 125 1.25 1.2 1.15 1.1 1.05 voltage on current limit set pin vs supply voltage supply voltage (v) [v set (v )] 2.7 3 3.5 4 4.5 5 5.5 current limit = 1a current limit = 2a current limit = 200ma offset voltage production distribution offset voltage (mv) 2 1.8 1.6 1.4 1.2 1.0 population 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2 typical production distribution of packaged units. offset voltage drift production distribution population drift ( v/ c) 10 9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 typical production distribution of packaged units. small-signal step response (g = +1, r l = 1k ? ) 50mv/div 10 s/div large-signal step response (g = +1, r l = 1k ? ) 1v/div 20 s/div
OPA569 sbos264 9 www.ti.com typical characteristics (cont.) at t a = +25 c, v s = +5v, unless otherwise noted. small-signal step response (g = +1, r l = 10 ? ) 50mv/div 10 s/div large-signal step response (g = +1, r l = 10 ? ) 1v/div 20 s/div small-signal step response (g = +1, r l = 1 ? ) 50mv/div 20 s/div large-signal step response (g = +1, r l = 1 ? ) 1v/div 20 s/div enable (10 ? load) 2v/div 1v/div 4 s/div enable/disable 0.8 to 2.5v above negative supply output driven to +2v enable (1 ? load) 10 s/div enable/disable 0.8 to 2.5v above negative supply output driven to +2v 1v/div 2v/div
OPA569 sbos264 10 www.ti.com typical characteristics (cont.) at t a = +25 c, v s = +5v, unless otherwise noted. disable (10 ? load) 200ns/div enable/disable 0.8 to 2.5v above negative supply output driven to +2v 2v/div 1v/div disable (1 ? load) 200ns/div enable/disable 0.8 to 2.5v above negative supply output driven to +2v 2v/div 1v/div power on (1 ? load) 1ms/div output driven to +2v supply 0v to 5v 5v/div 1v/div power off (1 ? load) 1ms/div 1v/div 5v/div output driven to +2v supply 5v to 0v in and out of current limit transient (r l = 0.75 ? , current limit = 2a) v out (2v/div) current limit flag (5v/div) 200 s/div in and out of current limit transient (r l = 7.5 ? , current limit = 200ma) v out (2v/div) current limit flag (5v/div) 200 s/div
OPA569 sbos264 11 www.ti.com typical characteristics (cont.) at t a = +25 c, v s = +5v, unless otherwise noted. overload recovery (g = +1) 1v/div 40 s/div v in v out no phase inversion with inputs larger than supply voltage (g = +1, r l = 10 ? ) 1v/div 1ms/div v in v out 15 10 5 0 5 10 15 current monitor and current limit error vs supply voltage supply voltage (v) current monitor and current limit error (%) i limit + i limit i monitor i monitor + 2.7 3 3.5 4 4.5 5 5.5 15 10 5 0 5 10 15 current monitor and current limit error vs temperature temperature ( c) current monitor and current limit error (%) 55 35 i limit + i limit 15 5 25 45 65 85 i monitor + i monitor 15 10 5 0 5 10 15 current monitor and current limit error vs output current output current (a) current monitor and current limit error (%) 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 i limit i monitor + i limit + i monitor 50 40 30 20 10 0 overshoot vs load capacitance (g = +1, r l = 1k ? ) load capacitance (pf) overshoot (%) 10 100 1k 10k
OPA569 sbos264 12 www.ti.com applications information basic configuration figure 1 shows the OPA569 connected as a basic non- inverting amplifier, however the OPA569 can be used in virtually any op amp configuration. a current limit setting resistor (r set , in figure 1) is essential to the OPA569 s operation, and cannot be omitted. power-supply terminals should be bypassed with low series impedance capacitors. using a larger tantalum and smaller ceramic type in parallel is recommended. power-supply wiring should have low series impedance. power supplies the OPA569 operates with excellent performance from a single (+2.7v to +5.5v) supply or from dual supplies. power supply voltages do not need to be equal as long as the total voltage remains below 5.5v. parameters that vary signifi- cantly with operating voltage are shown in the typical charac- teristics section. adjustable current limit and current limit flag pin the OPA569 provides over-current protection to the load through its accurate, user-adjustable current limit (pin 3). the current limit value, i limit , can be set from 0.2a to 2.2a by controlling the current through the current limit set pin. the current limit, i limit , will be 9800 i set ; where i set is the current through the current limit set pin. setting the current limit requires no special power resistors. the output current does not flow through this pin. setting the current limit as illustrated in figure 2, the simplest method of setting the current limit is to connect a resistor or potentiometer between figure 1. basic connections. figure 2. setting the current limit resistor method. v in r 1 r 2 47 f enable (2) 47 f 0.1 f current limit set 47 f 12, 13 14, 15 19 5 6 8 3 17, 18 0.1 f r set ( ? )i limit (a) 23.2k 11.5k 7.68k 5.76k 0.5 1.0 1.5 2.0 r set (1) v+ notes: (1) r set sets the current limit value from 0.2a to 2.2a. r set can be a potentiometer to easily adjust current limit and calibrate out errors at the current limit node. (2) enable pull low to disable output. v o i monitor v OPA569 r set v adjust (1) (b) resistor/voltage source method note: (1) this voltage source must be able to sink the current from the current limit set pin, which is i limit /9800. 1.18v v i limit = 9800 (1.18v v adjust ) r set 5 6 3 14, 15 17, 18 5 6 3 14, 15 17, 18 r pot (a) resistor or potentiometer method putting a set resistor in series with the potentiometer will prevent potential short-circuit on pin. 1.18v v i limit = 9800 (1.18v/r set ) the current limit set pin and v , the negative supply, accord- ing to the formula: i limit = 9800 (1.18v/r set ) alternatively, the output current limit can be set by applying a voltage source in series with a resistance using the equa- tion: i limit = 9800 [(1.18v v adjust )/r set ]
OPA569 sbos264 13 www.ti.com current limit accuracy internally separate circuits monitor the positive and negative current limits. each circuit output is compared to a single internal reference that is set by the user with an external resistor or a resistor/voltage source combination. the OPA569 employs a patented circuit technique to achieve an accurate and stable current limit throughout the full output range. the initial accuracy of the current limit is typically within 3%; however, due to internal matching limitations, the error can be as much as 15%. the variation of the current limit with factors such as output current level, output voltage and temperature is shown in the typical characteristics section. when the accuracy of one current limit (sourcing or sinking) is more important than the other, it is possible to set its accuracy to better than 1% by adjusting the external resistor or the applied voltage. the accuracy of the other current limit will still be affected by internal matching. current limit flag pin the OPA569 features a current limit flag pin (pin 4) that can be monitored to determine when the part is in current limit. the output signal of the current limit flag pin is compat- ible to standard logic in single supply applications. the output signal is a cmos logic gate that switches from v+ to v to indicate that the amplifier is in current limit. this flag output pin can source and sink up to 25 a. additional parasitic capacitance between pins 3 and 4 can cause instability at the edge of the current limit. avoid routing these traces in parallel close to each other. quiescent current dependence on the current limit setting the OPA569 is a low power amplifier, with a typical 3.4ma quiescent current (with the current limit configured for 200ma). the quiescent current varies with on the current limit set- ting it increases 0.5ma for each additional 200ma in- crease in the current limit, as shown in figure 3. figure 3. quiescent current vs current limit setting. 10 8 6 4 2 0 quiescent current vs current limit setting current limit setting (a) quiescent current (ma) 0 0.5 1 1.5 2 2.5 figure 4. transimpedance amplifier to monitor load current. OPA569 r l i o i o /475 i monitor v o v o = 1v at i o = 1a 2.5v 5 6 19 14, 15 12, 13 r = 475 ? c in +in +2.5v opa348 17, 18 current monitor the OPA569 features an accurate output current monitor (i monitor ) without requiring the use of series resistance with the load. this increases efficiency significantly and provides better overall swing-to-supply performance. an internal circuit creates a 1:475 copy of the output current. this copy of the output current can be monitored indepen- dently or it can be used in applications such as current control drive, setting non-symmetric positive and negative current limits or paralleling two or more devices for increased output current drive. when not being used, the current monitor pin may be left floating. some restrictions apply when using the current monitor function. when the main amplifier is sourcing current, the current monitor circuit must be sourcing current. likewise, when the main amplifier is sinking current, the current moni- tor circuit must also be sinking current. additionally, the swing on the i monitor pin is smaller than the output swing. when the amplifier is sourcing current, the voltage of the current monitor pin must be at least two hundred millivolts less than the output voltage of the amplifier. conversely, when the amplifier is sinking current, the voltage of the current monitor pin must be at least two hundred millivolts greater than the output voltage of the amplifier. resistive loads are able to meet these restrictions. other types of loads may cause invalid current monitor values. a simple way to monitor the load current and meet these requirements is to connect a resistor (with resistance less than 400 r l ) from the i monitor pin to the same potential to which the other side of the load is connected. another method is to use a transimpedance amplifier, as shown in figure 4. this circuit must assure that the potential of the i monitor pin remains in the valid voltage range by connecting it to the same potential to which the load is connected most likely ground for dual supply or mid-supply for single-supply applications.
OPA569 sbos264 14 www.ti.com the accuracy of the current copy is reduced with small output currents. an internal circuit monitors the direction of the output current and enables the positive or the negative current monitoring circuitry accordingly. there is an approxi- mate 20 s delay in the change of current direction. the switching point is near quiescent conditions and may cause current monitor inaccuracy with small output currents. enable pin output disable the enable pin can disable the OPA569 within microsec- onds. when disabled, the amplifier draws less than 10 a and its output enters a high-impedance state that allows multi- plexing. it is important to note that when the amplifier is disabled, the thermal flag pin circuitry continues to operate. this feature allows use of the thermal flag pin output to implement thermal protection strategies. for more details, please see the section on thermal protection. the OPA569 enable pin has an internal pull-up circuit, so it does not have to be connected to the positive supply for normal operation. to disable the amplifier, the enable pin must be connected to no more than (v ) + 0.8v. to enable the amplifier, either allow the enable pin to float or connect it to at least (v ) + 2.5v. the enable pin is referenced to the negative supply (v ). therefore, shutdown operation is slightly different in single- supply and dual-supply applications. in single-supply operation, v typically equals common ground, thus the enable/disable logic signal and the OPA569 enable pin are referenced to the same potential. in this configuration, the logic level and the OPA569 enable pin can simply be tied together. disable occurs for voltage levels of less than 0.8v. the OPA569 is enabled at logic levels greater than 2.5v. in dual-supply operation, the logic level is referenced to a logic ground. however, the OPA569 enable pin is still refer- enced to v . to disable the OPA569, the voltage level of the logic signal needs to be level-shifted. this can be done using an optocoupler, as shown in figure 5. examples of output behavior during disabled and enabled conditions with various load impedances are shown in the typical characteristics section. please note that this behavior is a function of board layout, load impedances and bypass strategies. for sensitive loads, the use of a low-pass filter or other protection strategy is recommended. ensuring microcontroller compatibility not all microcontrollers output the same logic state after power-up or reset. 8051-type microcontrollers, for example, output logic high levels on their ports while other models power up with logic low levels after reset. in configuration (a) shown in figure 5, the enable/disable signal is applied on the cathode side of the photodiode within the optocoupler. a logic high level causes the OPA569 to be enabled, and a logic low level disables the OPA569. in configuration (b) of figure 5, with the logic signal applied on the anode side, a high level disables the OPA569 and a low level enables the op amp. rail to rail output range the OPA569 has a class ab output stage with common source transistors that are used to achieve rail-to-rail output swing. it was designed to be able to swing closer to the rail than other existing linear amplifiers, even with high output current levels. a quick way to estimate the output swing with various output current requirements is by using the equation: v swing [typical] = 0.1 i o plots of the output swing vs output current, supply voltage, and temperature are provided in the typical characteristics section. optocoupler 4n38 note: (1) optional may be required to limit leakage current of octocoupler at high temperatures. enable v+ v o 5 6 8 14, 15 17, 18 12, 13 (a) +5v (b) hct or ttl in hct or ttl in (a) (b) OPA569 (1) v figure 5. OPA569 shutdown configuration for dual supplies.
OPA569 sbos264 15 www.ti.com rail to rail input range the input common-mode voltage range of the OPA569 extends 100mv beyond the supply rails. this is achieved by a complementary input stage with an n-channel input differ- ential pair in parallel with a p-channel differential pair. the n-channel input pair is active for input voltages close to the positive rail while the p-channel input pair is active for input voltages close to the negative rail. the transition point is typically at (v+) 1.3v, and there is a small transition region around the switching point where both transistors are on. it is important to note that the two input pairs can have offsets of different signs and magnitudes. therefore, as the transi- tion point is crossed, the offset of the amplifier changes. this offset shift accounts for the reduced common-mode rejection ratio over the full input common-mode range. output protection reactive and emf-generating loads can return load current to the amplifier, causing the output voltage to exceed the power-supply voltage. this damaging condition can be avoided with clamp diodes from the output terminal to the power supplies, as shown in figure 6. schottky rectifier diodes with a 3a or greater continuous rating are recom- mended. thermal flag the OPA569 has thermal sensing circuitry that provides a warning signal when the die temperature exceeds safe limits. unless the thermal flag is connected to the enable pin, when this flag is triggered, the part continues to operate even figure 6. output protection diode. OPA569 output protection diode output protection diode current limit set r set v o +v 12, 13 3 17, 18 in +in 14, 15 v enable pin 14, 15 8 5 6 thermal flag pin disable on 7 and OPA569 figure 7. enable/shutdown control using thermal flag pin and external control signal. though the junction temperature exceeds 150 c. this allows maximum usable operation in very harsh conditions but degrades reliability. the thermal flag pin can be used to provide for orderly system shutdown before failure occurs. it can be also used to evaluate the thermal environment to determine need for and appropriate design of a shutdown mechanism. the output signal is a cmos logic gate that switches from v+ to v to indicate that the amplifier is in thermal limit. this flag output pin can source and sink up to 25 a. the thermal flag pin is high during normal operation. power dissipated in the amplifier will cause the junction temperature to rise. when the junction temperature exceeds 150 c, the thermal flag pin will go low, and remain low until the amplifier has cooled to 130 c. despite this hysteresis, with a method of orderly shutdown, the thermal flag pin can cycle on and off, depending on load and signal conditions. this limits the dissipation of the amplifier but may have an undesirable effect on the load. it is possible to connect the thermal flag pin directly to the enable pin for automatic shutdown protection. when both thermal shutdown and the amplifier enable/disable functions are desired, the externally generated control signal and the thermal flag pin outputs should be combined with an and gate, as shown on figure 7. the temperature protection was designed to protect against overload conditions. it was not intended to replace proper heatsinking. continuously running the OPA569 in and out of thermal shutdown will degrade reliability.
OPA569 sbos264 16 www.ti.com any tendency to activate the thermal protection circuit indi- cates excessive power dissipation or an inadequate heat sink. for reliable, long term, continuous operation, the junc- tion temperature should be limited to 125 c maximum. to estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the ther- mal protection is triggered. use worst-case loading and signal conditions. for good, long-term reliability, thermal protection should trigger more than 25 c above the maxi- mum expected ambient conditions of your application. this produces a junction temperature of 125 c at the maximum expected ambient condition. fast transients of large output current swings (for example switching from sourcing 2a to sinking 2a fast) may cause a glitch on the thermal flag pin. when switching large currents is expected, the use of extra bypass between the supplies or a low-pass filter on the thermal flag pin is recommended. power dissipation and safe operating area power dissipation depends on power supply, signal and load conditions. it is dominated by the power dissipation of the output transistors. for dc signals, power dissipation is equal to the product of output current, i out and the output voltage across the conducting output transistor (v s -v out ). dissipa- tion with ac signals is lower. application bulletin ab-039 (sboa022) explains how to calculate or measure power dissipation with unusual signals and loads and can be found at the ti web site (www.ti.com). output short-circuits are a particularly demanding for the amplifier as the full supply voltage is seen across the con- ducting transistor. it is very important to note that the tem- perature protection will not shut the part down in over- temperature conditions, unless the thermal flag pin is con- nected to the enable pin; see the section on thermal flag. figure 8 shows the safe operating area at room temperature with various heatsinking efforts. note that the safe output current decreases as (v s v out ) increases. figure 9 shows the safe operating area at various temperatures with the powerpad being soldered to a 2 oz copper pad. the power that can be safely dissipated in the package is related to the ambient temperature and the heatsink design. the powerpad package was specifically designed to pro- vide excellent power dissipation, but board layout greatly influences the heat dissipation of the package. refer to the powerpad thermally enhanced package section for further details. the OPA569 has a junction-to-ambient thermal resistance ( ja ) value of 21.6 c/w when soldered to 2 oz copper plane. this value can be further decreased to 12 c/w by the addition of forced air. figure 10 shows the junction-to- ambient thermal resistance of the 20-pin dwp package. figure 10. junction-to-ambient thermal resistance with various heatsinking efforts. figure 8. safe operating area at room temperature. figure 9. safe operating area at various ambient tempera- tures. powerpad soldered to a 2oz copper pad. 10 1 0.1 ? v s v out ? (v) safe operating area at room temperature output current (a) 0123456 no copper copper unsoldered. copper soldered, without forced air. copper soldered, with 150lfm airflow. copper soldered, with 500lfm airflow. current is limited by the maximum output current. copper soldered, with 250lfm airflow. 10 1 0.1 ? v s v out ? (v) safe operating area at various ambient temperatures output current (a) 0123456 t a = +125 c t a = +85 c t a = +25 c t a = 40 c t a = 0 c current is limited by the maximum output current. no copper plate on the board contacting the exposed pad. 2 oz copper pad under the exposed pad, but the part is not soldered to it. the part is soldered to a 2 oz copper pad under the exposed pad. soldered to copper pad with forced airflow (150lfm). soldered to copper pad with forced airflow (250lfm). soldered to copper pad with forced airflow (500lfm). 92.4 43.9 21.5 15.1 13.2 12 heatsinking method ja
OPA569 sbos264 17 www.ti.com junction temperature should be kept below 125 c for reliable operation. the junction temperature can be calculated by: t j = t a + p d ja where ja = jc + ca t j = junction temperature ( c) t a = ambient temperature ( c) p d = power dissipated (w) ja = junction-to-ambient thermal resistance jc = junction-to-case thermal resistance ca = case-to-air thermal resistance the maximum power dissipation vs temperature for the above heatsinking methods is shown in figure 11. to appropriately determine required heatsink area, required power dissipation should be calculated and the relationship between power dissipation and thermal resistance should be considered to minimize shutdown conditions and allow for proper long-term operation (junction temperature of 125 c). once the heatsink area has been selected, worst-case load conditions should be tested to ensure proper thermal protec- tion. for applications with limited board size, refer to figure 12 for the approximate thermal resistance relative to heatsink area. increasing the heatsink area beyond 2in 2 provides little improvement in thermal resistance. to achieve the 21.5 c/w stated in the electrical characteristics, a copper plane size of 9in 2 was used. the so-20 powerpad package is well suited for continuous power levels, as shown in figure 11. higher power levels may be achieved in applications with a low on/off duty cycle. figure 11. maximum power dissipation vs temperature. feedback capacitor improves response for optimum settling time and stability with higher impedance feedback networks (r f > 50k ? ), it may be necessary to add a feedback capacitor across the feedback resistor, r f , as shown in figure 13. this capacitor compensates for the zero created by the feedback network impedance and the OPA569 input capacitance (and any parasitic layout capacitance). the effect becomes more significant with higher impedance networks. the size of the capacitor needed is estimated using the equation: r in c in = r f c f where c in is the sum of the input capacitance of the OPA569 plus the parasitic layout capacitance. 14 12 10 8 6 4 2 0 temperature ( c) maximum power dissipation vs temperature power dissipated in package (w) 55 30 20 5 45 70 95 120 copper soldered with 250lfm airlow copper soldered with 150lfm airlow copper soldered without forced air no copper copper unsoldered copper soldered with 500lfm airlow figure 12. thermal resistance vs circuit board copper area. 35 30 25 20 15 10 thermal resistance, ja ( c/w) 012345 copper area (inches 2 ) thermal resistance vs copper area OPA569 surface-mount package OPA569 v+ v v out v in r in 5 12, 13 14, 15 17, 18 6 r in c in = r f c f r f c l c in c in c f where c in is equal to the OPA569 s input capacitance (approximately 9pf) plus any parasitic layout capacitance. figure 13. feedback capacitor for use with higher imped- ance networks.
OPA569 sbos264 18 www.ti.com parallel operation the OPA569 allows parallel operation of multiple op amps to extend output current capability or improve the output volt- age swing to the rail. special internal circuitry causes the load current to be shared equally between two (or more) op amps. figure 14 shows two ways to connect the input terminals. when the amplifier inputs are connected in parallel, the effective offset voltage is averaged and the bandwidth and slew rate performance are the same as that of a single amplifier. it is also possible to use one amplifier to be the master and connect the other inputs to a voltage within the common-mode input range of the amplifier; however, slew rate and bandwidth performance will be degraded. for best performance, keep additional capacitance at the parallel out pins to a minimum and avoid routing these lines close to other lines that might see large voltage swings. figure 14. parallel operation. mold compound (epoxy) leadframe die pad exposed at base of the package leadframe (copper alloy) ic (silicon) die attach (epoxy) figure 15. section view of a powerpad package. powerpad thermally enhanced package the OPA569 uses the so-20 powerpad package, a ther- mally enhanced, standard size ic package designed to eliminate the use of bulky heatsinks and slugs traditionally used in thermal packages. this package can be easily mounted using standard pcb assembly techniques. the powerpad package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of the ic, as shown in figure 15. this provides an extremely low thermal resistance ( jc ) path between the die and the exterior of the package. the thermal pad on the bottom of the ic can then be soldered directly to the pcb, using the pcb as a heatsink. in addition, plated-through holes (vias) provide a low thermal resistance heat flow path to the back side of the pcb. OPA569 (a2) v+ v in v (a) inputs connected in parallel. 17, 18 12, 13 5 6 2 9 14, 15 r l parallel out 2 parallel out 1 OPA569 (a1) v+ v 17, 18 12, 13 5 6 2 9 14, 15 parallel out 2 parallel out 1 OPA569 (a2) v+ v in v (b) amplifier a1 as master , a2 as slave . 17, 18 12, 13 5 6 2 9 14, 15 r l parallel out 2 parallel out 1 OPA569 (a1) v+ v 17, 18 12, 13 5 6 2 9 14, 15 parallel out 2 parallel out 1 powerpad assembly process 1. the powerpad must be connected to the most negative supply voltage of the device, which will be ground in single- supply applications and v in split-supply applications. 2. prepare the pcb with a top-side etch pattern, as shown in figure 16. there should be etch for the leads as well as etch for the thermal land. 3. place the recommended number of plated-through holes (or thermal vias) in the area of the thermal pad. these holes should be 13 mils in diameter. they are kept small so that solder wicking through the holes is not a problem during reflow. the minimum recommended number of holes for the so-20 powerpad package is 24, as shown in figure 16. 4. it is recommended, but not required, to place a small number of additional holes under the package and outside the thermal pad area. these holes provide an additional heat path between the copper land and the ground plane. they may be larger because they are not in the area to be soldered, so wicking is not a problem. this is illustrated in figure 16.
OPA569 sbos264 19 www.ti.com 5. connect all holes, including those within the thermal pad area and outside the pad area, to the internal ground plane or other internal copper plane for single supply applications, and v for split-supply applications. 6. when laying out these holes to the ground plane, do not use the typical web or spoke via connection methodology, as shown in figure 17. web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. this makes soldering the vias that have ground plane connections easier. however, in this application, low thermal resis- tance is desired for the most efficient heat transfer. therefore, the holes under the powerpad package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. figure 16. 20-pin dwp powerpad pcb etch and via pattern. web or spoke via solid via not recommended recommended figure 17. via connection. thermal land 299 mils x 510 mils minimum area (7.59mm x 12.95mm) (copper) optional: additional 4 vias outside of thermal pad area but under the package (via diameter = 25 mils) required: thermal pad area: 140 mils x 176 mils (3.56mm x 4.47mm) with 24 vias (via diameter = 13 mils) 9. with these preparatory steps in place, the powerpad ic is simply placed in position and run through the solder reflow operation as any standard surface-mount compo- nent. this results in a part that is properly installed. for detailed information on the powerpad package including thermal modeling considerations and repair procedures, please see technical brief slma002, powerpad thermally enhanced package, located at www.ti.com. layout guidelines the OPA569 is a power amplifier that requires proper layout for best performance. figure 18 shows an example of proper layout. keep power-supply leads as short as possible. this will keep inductance low and resistive losses at a minimum. a mini- mum of 18 gauge wire thickness is recommended for power- supply leads. the wire length should be less than 8 inches. proper power-supply bypassing with low esr capacitors is essential to achieve good performance. a parallel combina- tion of small (around 100nf) ceramic and bigger (47 f) tantalum bypass capacitors will provide low impedance over a wide frequency range. bypass capacitors should be placed as close as practical to the power-supply pins of the OPA569. pcb traces conducting high currents, such as from output to load or from the power-supply connector to the power-supply pins of the OPA569 should be kept as wide and short as possible. the twenty-four holes in the landing pattern for the OPA569 are for the thermal vias that connect the powerpad of the OPA569 to the heatsink area on the pcb. the additional four larger vias further enhance the heat conduction into the heatsink area. all traces conducting high currents are very wide for lowest inductance and minimal resistive losses. note that the negative supply ( v) pin on the OPA569 can be connected through the powerpad to allow for maximum trace width for high current paths. 7. the top-side solder mask should leave the terminals of the pad connections and the thermal pad area exposed. the thermal pad area should leave the 13 mil holes exposed. the larger holes outside the thermal pad area should be covered with solder mask. 8. apply solder paste to the exposed thermal pad area and all of the package terminals. v parellel out 1 current limit set current limit flag in +in thermal flag enable i monitor v v out v+ parallel out 2 pin 1 note: avoid routing current limit set and current limit flag traces closely in parallel. figure 18. 20-pin dwp powerpad pcb etch and via pattern.
OPA569 sbos264 20 www.ti.com figure 21. single power amplifier driving bidirectional current through a tec using asymmetrical bipolar power supplies. figure 19. grounded anode led driver. application circuits figure 20. bridge tied load driver. luxeon star-0 high-power led 12, 13 5 6 17, 18 (1) 14, 15 v o f o = 10khz v in OPA569 r 1 49.9k ? r shunt 1 ? i o r 2 4.99k ? 4.99k ? 0.0033 f r 3 49.9k ? 5v +1v 0v 0ma 100ma 0v 2.5v feedback for constant current, 1v input per 100ma output as shown. note: (1) bypass as recommended. r set r m i m = + i tec 475 v set optional to monitor the load current. tec OPA569 1k ? heat/cool v tec v tec = 2 (v in v set ) + 5 12, 13 17, 18 14, 15 current limit set current limit set 17, 18 5 6 3 3 12, 13 14, 15 19 i monitor r set note: (1) bypass as recommended. 5v (1) 5v 6 1k ? v in OPA569 v m (1) OPA569 5 12, 13 17, 18 19 1.2v 14, 15 note: total supply must be < 5.5v cooling/heating. note: (1) bypass as recommended. r monitor i monitor +3.3v (1) 6 v in tec i l
OPA569 sbos264 21 www.ti.com 1m ? opt101 (4) 5 4 3pf r 1 10k ? r 2 10k ? OPA569 c 1 3.3nf +5v ref3025 led luxeon star 0 high power led +5v 3 2 1 12, 13 3 17, 18 19 +2.5v +0.5v note: (1) bypass as recommended. (2) r set establishes current limit. (3) r monitor used to measure led current. (4) opt101 pin numbers for dip package. r 3 2.5k ? c 2 0.01 f led opt101 glass microscope slide approximately 92% light available for application. optical calibration 8% v b 8pf pd 2 1 5 (1) 6 14, 15 3 8 r set (2) r monitor (3) figure 22. power booster for precision op amp. figure 23. led output regulation circuit for constant optical power. r l 2a max 6 7 4 2 3 1k ? v in opa335 +5v (1) 14, 15 12, 13 17, 18 5 6 OPA569 +5v (1) 1k ? note: (1) bypass as recommended.
OPA569 sbos264 22 www.ti.com package drawing dwp (r-pdso-g**) powerpad ? plastic small-outline package gage plane 0.419 (10,65) 0.400 (10,16) 0.010 (0,25) nom thermal pad (see note d) 0.010 (0,25) 0.016 (0,40) 0.050 (1,27) seating plane 4147575/a 04/98 11 10 a 20 pins shown 20 1 0.104 (2,65) max 0.293 (7,45) 0.299 (7,59) 0.020 (0,51) 0.014 (0,35) 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 C 8 0.710 28 0.510 20 0.610 24 0.700 (18,03) (17,78) 0.500 (15,49) (15,24) 0.600 0.410 16 dim pins ** (10,41) (10,16) 0.400 a min a max (12,95) (12,70) 0.006 (0,15) 0.002 (0,05) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). d. the package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. this pad is electrically and thermally connected to the backside of the die and possibly selected leads.
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