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STV0117 pal/ntsc digital encoder may 1996 plcc44 (plastic chip carrier) order code : STV0117 . ntsc-m, pal-m, pal-b, d, g, h, i, pal-n easily programmable video outputs . u/v and q/i matrixing for respec- tively pal and ntsc encoding . digital frame sync input/output (oddeven) . digital frame sync extraction from multiplexed 8-bit input port . digital field sync output (fsync) . digital composite sync output (vcs/hsync = vcs) . digital horizontal sync input/out- put (vcs/hsync = hsync) . 3 slave or 2 master operation modes . dual mode ccir601/square_pixel en- coding with easily programmable color subcarrier frequencies . interlaced or non-interlaced operation mode . 625lines/50hz or 525lines/60hz 8-bit multiplexed cb-y-cr digital input . osd insertion interface and 3 x 8 x 6-bit clut . closed captioning . macrovision ? copy protection process ( version 6.0/6.1 ) allowed on cvbs, ys & c . luminance filtering with 2 times oversampling and sinx/x correc- tion . programmable delay on luminance path to digitally compensate c/l de- lays . chrominance filtering with 4 times oversampling . switchable dedicated filter for q component . 22-bit direct digital frequency syn- thesizer for color subcarrier modulation . serial input for color subcarrier frequency control (cfc) . cvbs, ys and c simultaneous analog outputs through 9-bit dacs . controlled rise/fall times of ana- log synchronization output . power-down mode available inde- pendently on each dac . 9-bit digital input for digitized ana- log video with direct access to cvbs dac . easily controlled via i 2 c bus . 2 hardware i 2 c chip addresses . on-chip color bar pattern generator . high testability with full scan methodology (fault coverage 98%) . pin compatibility with stv0116 (pal/ntsc digital encoder with r, g, b outputs) . applications : satellite & cable de- coders, multimedia terminals description the STV0117 is a digital video device implemented in pure cmos technology for multimedia, digital tv and computer applications. the STV0117 converts the digital output of a video mpeg decoder into a standard analog baseband ntsc/pal signal with color subcarrier modulation. the STV0117 can handle interlaced mode (with 525 or 625 line standards), or non-interlaced mode (with 524 or 624 line standards), with square or rectangular pixels encoding. the STV0117 per- forms closed captions encoding and allows macrovision ? 6.0/6.1copy protection process. both composite and svhs format video signals are simultaneously issued to three analog outputs, re- spectively cvbs, ys and c. note : this device is protected by us patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. this device is protected by u.s. patent numbers 4,631,603, 4,577,216 and 4,819,098 and other intellectual property rights. the use of macrovision?s copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by macrovision. reverse engineering or disassembly is prohibited. please contact your nearest sgs-thomson microelectronics sales office for more information. 1/45
39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 ycrcb3 ycrcb2 ycrcb1 ycrcb0 dvid0 testauto ys i ref c cvbs v dda v ssa dvid1 dvid2 dvid3 dvid4 ckref dvid5 dvid6 dvid7 dvid8 v ssc oddeven vcs/hsync ycrcb7 ycrcb6 ycrcb5 ycrcb4 v ddc nreset sda scl ri gi bi fb testscan h6osd v ssp v ddp csi2c fsync cfc edvid 0117-01.eps pin connections STV0117 2/45
pin symbol type function 1 gi input second pixel index for 3 x 1-bit osd input. minimu m osd_pixel width is one h6osd period. 2 ri input first pixel index (msb) for 3 x 1-bit osd input. minimu m osd_pixel width is one h6osd period. 3 scl triggered input i 2 c serial clock line (internal 5-bit majority logic). 4 sda i/o i 2 c serial data line triggered input (internal 5-bit majority logic). open drain output, minimum low level duration 200ns. 5 nreset input asynchronous reset, active low. it has priority over software reset (see i 2 c register4). nreset imposes default states (see i 2 c registers description and reset procedure in functional description). minimu m low level required duration is 5 ckref periods. 6v ddc supply digital positive supply voltage for core (+5v). 7 oddeven i/o oddeven video frame signal : - input in slave modes, except when sync is extracted from ycrcb data, - output in master modes and when sync is extracted from ycrcb data. synchronous to rising edge of ckref. default polarity : - odd(top) field : high level, - even(bottom) field : low level. default mode is slave by oddeven and hsync, both with rising active edge. 8 vcs/hsync i/o composite or horizontal synchronization signal : - input in one slave mode : hsync input (defined by sym2 = 1), - output in other modes : vcs or hsync. synchronous to rising edge of ckref. default polarity : leading edge of the pulse is rising default mode is slave by oddeven and hsync, both with rising active edge. 9 10 11 12 13 14 15 16 ycrcb7 ycrcb6 ycrcb5 ycrcb4 ycrcb3 ycrcb2 ycrcb1 ycrcb0 input time multiplexed 4:2:2 luminance and chrominance data as defined in ccir rec601-2 and rec656 (except for ttl input levels). timing rec656-partii for ccir rectangular pixels ; for square pixels data see chapter data input format in functional description. this bus interfaces with mpeg video decoder output port. 17 18 19 20 21 dvid0 dvid1 dvid2 dvid3 dvid4 i/o input (default mode) : 5 lsbs of digitized analog video for direct access to cvbs 9-bit dac inputs. enabled by software or/and by hardware. tristate output for test purpose only. 22 v ddp supply digital positive supply voltage for pad ring (+5v). 23 ckref input clock reference signal : rising edge is the reference for setup and hold times of all inputs, and for propagation delay of all outputs (except for sda output). frequency is 27mhz in ccir601 and in square pixel mode : 24.5454mhz or 29.50mhz. 24 v ssc supply digital ground for core. 25 26 27 28 dvid5 dvid6 dvid7 dvid8 i/o input (default mode) : 4 msbs of digitized analog video for direct access to cvbs 9-bit dac inputs. enabled by software or/and by hardware. tristate output for test purpose only. 29 edvid input hardware control signal for dvid inputs select when this control is allowed by software : - if edvid is high level, then dvid data is enabled and dvid data is an input for cvbs 9-bit dac, - if edvid is low level, then dvid data is disabled and dvid data is ignored for cvbs 9-bit dac. when this control is disabled by software : dvid[8:0] inputs are controlled by software whatever the level on edvid input. 0117-01.tbl pin description STV0117 3/45
pin symbol type function 30 cfc input color subcarrier frequency control line : 23-bit stream line, synchronous to ckref. in standby mode, cfc must be at high level. reception starts with one low level bit and then a 22-bit word is received for increment of color subcarrier direct digital frequency synthesizer, and then line returns to standby mode i.e at high level. this real time control is enabled by software and is a color lock interface. this line is ignored by default. 31 fsync output field synchronization signal, synchronous to ckref. it is a horizontal sync signal generated every field beginning. default polarity is positive (like hsync). 32 csi2c input hardware i 2 c chip address select : - when low, i 2 c chip addresses are 40 and 41 hexadecimal, - when high, i 2 c chip addresses are 42 and 43 hexadecimal. 33 v ssa supply analog ground for 3 dacs. 34 v dda supply analog positive supply voltage for 3 dacs (+5v). 35 cvbs output current analog video composite signal : cvbs must be connected to analog ground over a load resistor (r l ). between the load resistor and the video equipment, an analog low pass filter may be necessary to suppress the alias signal. cvbs amplitude is typically 2.48v pp on r l and is proportional to i ref . 36 c output current analog chrominance signal : s-vhs output for a vcr or a tv set. c must be connected to analog ground over a load resistor (r l ). between the load resistor and the video equipment, an analog low pass filter may be necessary to suppress the alias signal. c amplitude is typically 1.6v pp on r l and is proportional to i ref . 37 i ref input reference current source for the 3 x 9-bit dacs cvbs,ys,c. i ref must be connected to analog ground over a reference resistor (r ref ). i ref range is from 2 up to 6ma. 38 ys output current analog luminance with composite synchronization signal : s-vhs output for a vcr or a tv set. ys must be connected to analog ground over a load resistor (r l ). between the load resistor and the video equipment, an analog low pass filter may be necessary to suppress the alias signal. ys amplitude is typically 2.0v pp on r l and is proportional to i ref . 39 testauto input hardware autotest mode control, active high. testauto input forces the master mode with color bar pattern outputs. 40 v ssp supply digital ground for pad ring. 41 h6osd output ckref/4 clock signal for external osd generator clock output stage. synchronous to ckref and controlled by software : inactive by default (low level). 42 testscan input full scan test mode control, active high. testscan must be ground ed for normal operation. 43 fb input fast blanking signal to control 3x1bit osd inputs, active high. synchronous to h6osd or ckref. fb must be low level in autotest mode. 44 bi input third pixel index (lsb) for 3 x 1-bit osd input. minimu m osd_pixel width is one h6osd period. 0117-01.tbl pin description (continued) STV0117 4/45
bus bus bus bus bus bus bus 2 1 44 43 ri gi bi fb clut cb y cr 6 3 int color bars bus 8 6mhz bus cb cr q v/i matrix 8 8 cr cb y demux 8 8 int ckref offset int ckref int ckref modulator and gain c 9 bit d/a 9 9 9 bit d/a 9 bit d/a 38 35 36 9 78 vcs/hsync sync gen d/a ref bus ycrcb i c bus decoder 3 4 sda scl reset test 9 nreset dvid 23 ckref oddeven ys cvbs c STV0117 pins 9 to 16 5 pins 17 to 21 25 to 28 37 6 6 2 41 h6osd clock gen closed-caption generator copy protection generator 39 testauto testscan 42 synchro reset delay 24 v ssc dvid 9 v dd 32 csi2c color burst gen 30 cfc delay u/q 0.5mhz 1.8 or 1.3mhz bus v/i u/q bus bus 622 31 fsync v ddp v ddc 34 v dda v ssp 40 33 v ssa 29 bus 0 1 edvid dvid output stage 75 ? output stage 75 ? output stage 75 ? i ref int : interpolation by 2 color subcarrier synthesizer bi bi 9 r l r l r l 0117-02.eps block diagram STV0117 5/45
the STV0117 can operate either in slave mode by locking onto a vertical parity synchronization signal received from mpeg video decoder, or in master mode by supplying the sync signal to this device. by using an i 2 c bus, it is allowed to control the following main functions : - selection of the standard, - synchronization mode and polarity, - ccir601 or square pixel data format, - interlaced or non-interlaced mode, - reset of the synchronization, - luminance delay adjustment, - chrominance filter selection, - reset of the oscillator, - subcarrier phase and frequency adjustment, - color killer, - closed captions encoding, - macrovision ? 6.0/6.1 copy protection proc- essing, - osd insertion, - power-down mode for each dac. 1 - data input format the digital input is a time multiplexed [[cb,y,cr], y], 8-bit stream. input samples are taken into ac- count on the rising edge of ckref clock input signal (see figure 1). dual mode ccir601/square_pixelencoding is per- formed with semi-automaticprogrammation of sub- carrier frequencies from master clock (ckref) as shown in table 1. table 1 standard application ckref frequency (mhz) pixel rate (mhz) field rate (hz) vertical resolution pal-b, d, g, h, i, pal-n ccir601 27 13.5 50 625 ntsc-m, pal-m ccir601 27 13.5 60 525 pal-b, d, g, h, i, pal-n square pixel (graphics) 29.50 14.75 50 625 ntsc-m, pal-m square pixel (graphics) 24.5454 12.2727 60 525 the input pixel data for STV0117 has an integer relationship to the number of clock cycles per hori- zontal line as detailed in table 2. table 2 standard application pixel clock (mhz) total pixels per line active pixels per line pal-b, d, g, h, i, pal-n ccir601 13.5 864 720 ntsc-m, pal-m ccir601 13.5 858 720 pal-b, d, g, h, i, pal-n square pixel (graphics) 14.75 944 768 ntsc-m, pal-m square pixel (graphics) 12.2727 780 640 square pixel and/or non-interlaced modes are updated on the beginning of the frame (see figure 2). in non-interlaced mode, it is a 624/2 = 312 line mode or a 524/2 = 262 line mode with waveforms like the first field of ccir or smpte specifications (see figures 3 to 10). 2 - video timing the STV0117 outputs interlaced or non-interlaced video in pal-b, d, g, h, i, pal-n, pal-m or ntsc- m standards. the 8 field (for pal) or 4 field (for ntsc) burst sequences are internally generated, with ckref as reference. rise and fall times of synchronization tip, blanking and burst envelope areinternally controlledaccord- ing to the composite video specification. lines inside vertical interval are blanked and oth- ers included in blanking interval can be blanked via i 2 c controls (not assumed by default). vertical blanking interval corresponds to the follow- ing lines : - in 525/60 system : lines 1-19 and 2nd half of line 263 to line 282 (smpte line number convention), - in 625/50 system : 2nd half of line 623 to line 22 and lines 311-335 (ccir line number convention). video half lines are assumed only when preceding vertical interval. this is the case for the following lines : - in 525/60 system : line 263 (smpte line number convention), - in 625/50 system : line 623 (ccir line number convention). functional description STV0117 6/45
e a v s a v e a v 4t 4t 28t 244t 128t 1716t 1440t digital active line 137t 146t (pal m) ntsc, pal m 20t 264t 128t 1728t 1440t 151t palb,g,h,i,n 40t 236t 115t 1560t 1280t 131t square pixel 525/60 system 48t 300t 139t 1888t 1536t 169t square pixel 625/50 system t = clock period pal & ntsc : 37.037ns square pixel pal : 33.898ns square pixel ntsc : 40.75ns 0 h 0117-03.eps note : the burst envelope shown here indicates the location from which the first subcarrier positive zero crossing is seeked (with respect to the 0 h reference). the burst always start with such a positive zero crossing. figure 1 : data input format in a ccir656 compliant digital tv line, the ?active? portion of the line is the portion included between the sav (start of active video) and eav (end of active video) words. however, this digital active line starts somewhat earlier than the active line usually defined by ana- logue standards. the approach retained in the STV0117 is to encode the full digital line. thus, the output waveform will reflect the full ycrcb stream included between sav and eav as figure 1 re- flects. should it be absolutely necessary to obtain an analogue active line that starts later than the digital active line, a solution is to input a ycrcb stream that starts with samples at black level after the sav word. autotest mode is operating when allowed by testauto pin (high level) or by i 2 c program- ming. this mode is a master mode which encodes a color bar pattern in the appropriate selected standard (see figure 11). functional description (continued) STV0117 7/45
field2 field1 clock period chang e if square pixel mode switches oddeven (output) ckref hsync (output) master mode field1 clock period chang e if square pixel mode switches oddeven (input) ckref hsync (input) slave mode by oddeven and hsync field1 clock period chang e if square pixel mode switches oddeven (input) ckref slave mode by oddeven only update of sqpix and intrl bit s update of sqpix and nintrl bits update of sqpix and nintrl bits (see figure 12 for other timings) (see figure 13 for other timings) (see figure 15 for other timings) 0117-04.eps notes : 1. these diagrams are valid with contents of ?delay? and ?synchro-delay? registers equal to default value. 2. if on-the-fly format changing is required, clock switching must be synchronized onto the start of frame as shown in the above waveforms. internally, ?sqpix? and ?nintrl? bits update is taken into account on beginning of new frame. figure 2 : square pixel and/or non-interlaced mode switch functional description (continued) STV0117 8/45
hsync fsync oddeven line number 4 1 267 314 4 1 frame active edge odd even smpte 525 ccir 625 266 313 3 625 0117-05.eps figure 3 : interlaced mode (nintrl = 0 - i 2 c) - master mode hsync fsync oddeven line number 4 1 4 1 4 1 frame active edge 3 312 3 312 odd even smpte-like ccir-like ..262,1.. ..262,1.. 0117-06.eps notes : 1. these diagrams are valid for sys0 = 1 and sys1 = 0 in register 0 (i.e. synchro active edges defined as rising). 2. in slave mode, only one edge (the ?active edge?) of the incoming oddeven is taken into account for synchronization. the ?non-active edge? is not critical and its position may differ by up to half a line from the location shown in master mode. figure 4 : non-interlaced mode (nintrl = 1 - i 2 c) - master mode functional description (continued) STV0117 9/45
1 vbi1 23 3h 456 3h 789 3h 10 18 19 h 0.5h h h 282 273 272 271 270 269 268 267 266 265 264 263 262 h h 0.5h vbi2 vbi3 12345678910 1819 525 282 273 272 271 270 269 268 267 266 265 264 263 vbi4 0117-39.eps figure 5 : ntsc-m typical vbi waveforms (interlaced mode) (smpte-525 line numbering convention) 1 vbi 23 3h 456 3h 789 3h 10 18 19 h 0.5h h h 262 h 0117-40.eps figure 6 : ntsc-m typical vbi waveforms (non-interlaced mode) (?smpte-like? line numbering convention) functional description (continued) STV0117 10/45
f? 519 f 520 f? 521 f 522 523 524 525 1 2 3 4 5 6 7 8 9 ab ab ab 261 262 263 264 265 266 267 268 269 270 271 272 523 524 525 1 2 3 4 5 6 7 8 9 f 519 f? 520 f 521 522 f 257 f? 258 f 259 260 ab 261 262 263 264 265 266 267 268 269 270 271 272 f? 257 f 258 259 260 0 v iv i ii iii iv iii ii i c 0 v : i, ii, iii, iv : a: b: c: frame synchronizationreference 1 st and 5 th ,2 nd and 6 th ,3 rd and 7 th ,4 th and 8 th fields burst phase : nominal value +135 burst phase : nominal value -135 burst suppressioninternal 0117-41.eps figure 7 : pal-m typical vbi waveforms (interlaced mode) (ccir-525 line numbering convention) 256 257 258 259 260 261 262 1 2 3 4 5 6 7 8 9 ab 0 v i burst phase toggles every line 0117-42.eps figure 8 : pal-m typical vbi waveforms (non-interlaced mode) (?ccir-like? line numbering convention) functional description (continued) STV0117 11/45
308 309 310 311 312 313 314 315 316 317 318 319 320 ab ab ab 62462512345678 311 312 313 314 315 316 317 318 319 320 308 309 310 621 622 623 ab 62462512345678 621 622 623 0 v iii i ii iii iv ii i iv c 0 v : i, ii, iii, iv : a: b: c: frame synchronizationreference 1 st and 5 th ,2 nd and 6 th ,3 rd and 7 th ,4 th and 8 th fields burst phase : nominal value +135 burst phase : nominal value -135 burst suppression internal 0117-43.eps figure 9 : pal-bghi typical vbi waveforms (interlaced mode) (ccir-625 line numbering convention) ab 311 312 1 2 3 4 5 6 7 8 308 309 310 0 v i burst phase toggles every line 0117-44.eps figure 10 : pal-bghi typical vbi waveforms (non-interlaced mode) (?ccir-like? line numbering convention) -40 -20 0 20 40 60 80 100 ire t 1 line 0117-07.eps figure 11 : video timing - master mode = auto-test mode - ntsc - cvbs signal functional description (continued) STV0117 12/45
3 - reset procedure a hardware reset is performed by grounding the pin nreset. this will set the STV0117 in slave mode driven by oddeven and hsync input pins, in ntsc-m standard, with ccir601 rectangular pixel and interlaced mode encoding. after power-on reset, macrovision ? copy pro- tection process is disabled and no closed captions are encoded ; then, any i 2 c bus programming and/or software reset will set the STV0117 in a customized operation mode in a partially or fully automatic way. a few i 2 c registers are never reset, their contents is unknown until the first loading (see i 2 c registers description). during reset hardware operation and after reset released, all digital i/o stages are set to input mode. this is the case for oddeven, hsync signals and dvid[8:0] data. it is also possible to perform a software reset by setting bit ?softrst? in register 4. the ic?s response in that case is similar to its response after a hard- ware reset, except that control and configuration registers are not altered (register 0 to 4). note that after writing a ?1? into bit ?softrst? (register 4), it is necessary to stop the i 2 c se- quence after register 4 and start a new i 2 c transfer sequence to send the data for next registers. 4 - master mode after a software reset, the synchronization gener- ator starts counting the ckref clock pulses and provides a complete repetitive composite synchro- nization pulse sequence. in that mode, the time base of the circuit runs continuously. this is a 4 field sequence in ntsc-m and a 8 field sequence in pal. whatever the standard, oddeven signal and composite or horizontal synchronization signal (vcs/hsync pin) are delivered to control an mpeg video decoder. non-interlaced and/or square pixel encoding is performed when selected by programmation. the timings of sync signals depend on whether or not square pixel or non-interlaced modes have been selected and are also affected by the ?delay- registers? and ?synchro-delay-registers? (see fig- ure 12). 5 - slave modes three slave modes are selectable by the i 2 c bus, bit ?mod? (register 0) should be set to ?0? to enable slave mode. 5.1 - line-locked sync (sym2 = sym1 = ?1? in register 0) after a sofware reset, the synchronization counter waits for the rising edge of oddeven and hsync signals sent by a video source. in slave mode by oddeven and hsync, the first active transition of oddeven initializes the inter- nal line counter and the simultaneous or first follow- ing active transition of hsync intializes a sample counter. - if line length is shorter or equal to nominal value : sample counter is reinitialized and all internal active signals depending on sample counter are set inactive. the last pixels of the digital line are not output in that case ; however the encoded video is within the analog video requirements. - if line length is longer than nominal value: sample counter is stopped when reaching nominal end of line and is waiting for next hsync active edge to reinitialize itself. note that the phase relationship between hsync and the incoming ycrcb data should be such that the first clock rising edge following the hsync active edge always samples ?cb? (see figure 13). field count is incremented on each oddeven transition. line counter is reset on each active edge of oddeven. 5.2 - frame-locked sync (sym2 = sym1 = ?0? in register 0) alternatively, slave mode can be performed with oddeven input only, or STV0117 can be set to extract the synchronizationfrom ycrcb input data sequence (f : oddeven signal from eav se- quence (see figure 14)). after a sofware reset, the synchronization counter waits for the first active edge of oddeven or f first falling edge sent by a digital video source. once the appropriate sync signals have been selected, a sequence identical to that in master mode can start and is repeated until 3 consecutive checks on oddeven location fail. in the latter case, the ic stops outputting hsync and, if applicable, odd- even, and blanks the video outputs until a new rising edge occurs on oddeven onto which it locks again (see figure 15). note that the phase relationship between odd- even and the incoming ycrcb data should be such that the first clock rising edge following the oddeven active edge always samples ?cb?. functional description (continued) STV0117 13/45
mastersignal (2) 0h = 0v oddeve n fsync 0h oddeve n hsync fsync oddeve n output hsync output fsync ckre f 0h d odd d sync 4.7 s (1) ycrc b cb0 y0 xx cr0 cr0 y1 y2 cb2 synchro-delay registers synchro-delay registers delay register s 0117-09.eps notes : 1. these diagrams are valid when delay registers not loaded (default values) : if delay register value < 0, then oddeven edge is shifted left, else oddeven edge is shifted right. if synchro_delay register value < 0, then hsync and fsync edges are shifted right, else they are shifted left. 2. master signal goes to 1 when soft/hard autotest mode or master mode is selected. 3. to keep the cb, y, cr sequence correct, synchro-delay register must be changed four steps by four steps. figure 12 : master (with sys0 = 0 and sys1 = 0 - i 2 c register 0) functional description (continued) STV0117 14/45
hs ync odde ven ckref ycrcb cb y cr y? cb de lay registers 0117-45.eps notes : 1. diagram valid for contents of ?delay? and ?synchro-delay? register = default. 2. in oddeven + hsync synchronization mode, oddeven and hsync may change level at the same time, alternatively oddeven can change first and the next hsync flags the start of the first line of the frame. figure 13 : hsync + oddeven based slave mode sync signals ycrcb inp ut b6 cb0 y0 cr0 ya cb1 y1 cr1 yb cb2 cr128 yu cb129 y129 eav ckref f (internal signal) odde ven (1) output fs ync (1) output hs ync (1) output adjustment via i 2 c bus (s ynchro-de lay re giste rs ) de lay re gisters 0117-10.eps note : 1. diagram valid if both registers delay and synchro-delay are not loaded (default values). figure 14 : slave mode, synchro by f (extracted from eav) (1) ycrcb inp u t cb0 y0 cr0 ya cb1 y1 cr1 yb cb2 cr128 yu cb129 y129 ckref oddeven (1) inp u t fsync (1) ou tpu t hs ync (1) ou tpu t y2 cr2 adjus tment via i 2 c bus (synchro-de lay registe rs) delay re gisters 0117-11.eps note : 1. diagram valid if both registers delay and synchro-delay are not loaded (default values). figure 15 : slave mode, synchro by oddeven functional description (continued) STV0117 15/45
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 (db) 014 24 6 81012 x10 6 (hz) 0117-12.eps figure 16 : chroma q filter 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 (db) 9 8 7 6 5 4 3 2 x10 5 (hz) 1 0 0117-13.eps figure 17 : chroma q filter (zoom) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 (db) 014 24 6 81012 1.75mhz 1.25mhz x10 6 (hz) 0117-14.eps figure 18 : chroma filters 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 (db) 3 2.8 2.6 2.4 2.2 2 1.8 1.6 x10 6 (hz) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.75mhz 1.25mhz 0117-15.eps figure 19 : chroma filters (zoom) note : those filter curves include the sinx/x attenuation of dacs. 6 - chrominance encoding functional description (continued) the demultiplexed cb, cr samples feed a chromi- nance q/i matrix for ntsc-m (or a u/v matrix for pal). the q/i or u/v signals are then band limited according to ccir rec624 and interpolated at ckref clock rate. this processing makes easier the filtering for d/a conversion and allows a more accu- rate encoding. for modulation with the color subcarrier signal, the u/v or q/i components are band limited to 1.3mhz for u/v and i, and to 0.5mhz for q. in case of data issued from a graphics source, bandwidth can be extended to 1.8mhz for all components (see fig- ures 16, 17, 18 and 19 for curves of the different filters). STV0117 16/45
7 - color subcarrier generator a direct digital frequency synthesizer (ddfs), using a 22-bit phase accumulator, generates the required color subcarrier frequency. this oscillator feeds a quadrature modulator which modulates the baseband chrominance signal components. color subcarrier frequency is computed according to the following equation : fsc = (22-bit increment word/2 22 ) x ckref the phase and frequency of the color subcarrier can be adjusted by software. the external clock is considered to be sufficiently stable to ensure correct encoding. when performing external gen-locking, the fre- quency reference of the generated clock may slightly deviate dependingon the line length meas- urement. to prevent this drift from corrupting the colors, the color subcarrier frequency control line (cfc pin) can be used to update the 22-bit incre- ment of the ddfs and keep the color subcarrier stable (see figure 20). internal i 2 c options provide a reset of color subcar- rier phase every 2, 4 or 8 fields to compensate for any drift introduced by the finite accuracy of the calculations. 8 - burst insertion the start time of the color burst is at the positive zero crossing of the color subcarrier sinuso?dal waveform that follows a burst window. this window location is given in table 3. the first and last half cycles have a reduced ampli- tude so that the burst envelope starts and ends smoothly. table 3 standard application ckref frequency (mhz) burst window location from 0h pal-b, d, g, h, i, pal-n ccir601 27 +151 ckref periods ntsn-m ccir601 27 +137 ckref periods pal-m ccir601 27 +146 ckref periods pal-b, d, g, h, i, pal-n square pixel (graphics) 29.50 +169 ckref periods ntsn-m, pal-m square pixel (graphics) 24.5454 +131 ckref periods the burst is inserted for 9 (m and pal-n standards) or 10 (pal-b, d, g, h, i) subcarrier cycles. phase shift is directly performed within the ddfs during the burst insertion as specified in table 4. table 4 standard subcarrier freq. (mhz) ccir601/ square pixel phase shift per line (degrees) pal-b, d, g, h, i 4.43361875 -90 (plus line alternance) pal-n 3.5820558 +90 (plus line alternance) ntsc-m 3.5795452 +180 pal-m 3.57561149 +90 (plus line alternance) note that except in square pixel mode, subcarrier frequencies can readily be customized with the following procedure : - program the required increment in registers 10 to 12. - set bit ?selrst? to ?1? in register 2. - perform a software reset (register 5). 9 - luminance encoding the demultiplexed y samples are band limited and are interpolated at ckref clock rate. then a gain and offset compensation is applied to the lumi- nance signal before inserting closed captions data, macrovision copy protection signals and synchro- nization pulses. a 7.5 ire pedestal is selected automatically in the 60hz field rate mode and may be added in 50hz field rate mode to distinguish 2 pal-n standards (see i 2 c registers description). the interpolation filter compensates the sinx/x at- tenuation of d/a conversion and greatly simplifies the external output stage filter (see figures 21 and 22 for curves). a programmable delay is inserted on the luminance data pathto offset any chroma/luma delay introduc- tion by off-chip filtering (see i 2 c registers des- cription). by default, luminance and chrominance transitions are aligned on analogue outputs. functional description (continued) STV0117 17/45
22-bit increment (absolute value) ckref msb lsb cfc start bit stand-by level stand-by level possible parallel load for 22-bit increment update active edge for ckref is rising edge. color subcarrier frequency control word update burst location hsync input hsync output cfc loading oscillator 22-bit increment update (1) (2) (3) 53 x t ckref (1) : immediate update after serial loading (+1 ckref period) (2) : update on the next line start (hsync active edge) (3) : update on the next burst start (0) : cfc word ignored 0117-28.eps figure 20 : color subcarrier frequency control word transmission format functional description (continued) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 (db) 014 24 6 81012 x10 6 (hz) 0117-16.eps figure 21 : luma filters -9 -8 -7 -6 -5 -4 -3 -2 -1 0 (db) 07 12 3 45 6 x10 6 (hz) 1 0117-17.eps figure 22 : luma filters (zoom) note : those filter curves include the sinx/x attenuation of dacs. STV0117 18/45
10 - closed captions encoding functional description (continued) data, according to the closed caption specifica- tions, or extended data service can be encoded by the circuit. the closed caption data is delivered to the circuit through the i 2 c bus control interface. two dedicated pairs of bytes (two bytes per field), each pair preceded by a clock run-in and a start bit can be encoded and inserted on the luminance path on a selected line. the serial i 2 c loading should be performed odd-parity bit first, then msb of the us-ascii 7-bit character and lsb last. i 2 c register 39 (resp. register 41) is the first byte sent (lsb first) after the start bit on the appropriate tv line in field1 (resp. field2), and register 40 (resp. register 42) is the second byte. the tv line number where data is to be encoded is programmable (see i 2 c registers description). a direct digital frequency synthesizer (ddfs), using a phase accumulator, generates the required run-in fre- quency. the phase and frequency of the run-in oscillator are generated for different standards. the nominal instantaneousdata rate is 503496.5hz (i.e. 32 times the ntsc line frequency). should closed- captioning be needed in conjunction with pal, this same data clock frequency would still be used, and all closed-caption absolute timings would be un- changed. closed captions can also be encoded in square pixel mode and the nominal data rate keeps the same. data low corresponds nominally to 0 ire, data high corresponds to 50 ire at the dac outputs. when closed-captioning is on, the micro- controller should load the relevant registers (reg. 39 and 40, or 41 and 42) once every frame (possi- bly less) in average. the closed caption encoder considers that the closed caption data has been loaded and is valid on completion of the write operation into register 40 for field1, into register 42 for field 2. if closed caption encoding is on and no new data bytes have been written into the closed caption dataregisters when the closed caption data slot starts on the appropriate tv line, then the circuit outputs two us-ascii null characters with odd parity after the start bit (see figures 23, 24, 25 and 26). -40 -20 0 20 40 60 80 100 120 t ire 50% 61 s 27.35 s 13.9 s 7 cycles of 504khz 10 s transition time : 220ns 50% 2 characters null 0117-21.eps figure 23 : closed caption line ckref = 27mhz - ntsc-m cvbs analog signal 0 200 400 600 800 1000 mv t 50% 61 s 27.35 s 13.9 s 7 cycles of 504khz 10 s transition time : 220ns 50% 0117-22.eps figure 24 : closed caption line ckref = 27mhz - pal/ccir cvbs analog signal -40 -20 0 20 40 60 80 100 120 t ire 50% 61.2 s 27.4 s 13.9 s 7 cycles of 504khz 10 s transition time : 240ns 50% 2 characters null 0117-23.eps figure 25 : closed caption line ckref = 24.5454mhz - ntsc-m cvbs analog signal - square pixel 0 200 400 600 800 1000 1200 t mv 50% 61.2 s 27.5 s 13.9 s 7 cycles of 504khz 10.2 s transition time : 200ns 50% 0117-24.eps figure 26 : closed caption line ckref = 29.5mhz - pal 625 lines cvbs analog signal - square pixel STV0117 19/45
11 - cvbs and svhs outputs functional description (continued) 370 323 293 247 217 170 400 120 20 ire 20 ire 7.5 ire 40 ire 100 ire 34 ire 120 8lsb 56 3.58mhz colour burst (9 cycles) sync level blank level black level white level white yellow cyan green magenta red blue black blank level 120 140 1205 980 430 280 130 0 mv 0117-25.eps figure 27 : m composite ntsc output (100% saturation, 100% amplitude color bars) no luminance band-stop filter is implemented to remove chrominance from the luminance part of the composite video channel. each digital video signal drives a 9-bit d/a con- verter operating at ckref clock rate. the outputs are current sources and are propor- tional to the current reference source (i ref pin). the integrated oversampling stages make the ex- ternal antialiasing low pass filters simpler (see fig- ures 27, 28 and 29). unused dac must be connected to ground and dis- abled via i 2 c control (separate power-down modes). table 5 signal resolution maximum voltage (i ref = 2ma, r l = 300 ? ) cvbs 9 bits 1.24v pp c 9 bits 1.24v pp (0.8v pp nominal for 100/0/100 625l color bar) ys 9 bits 1.24v pp (1.0v pp nominal for 100/0/100 625l color bar) STV0117 20/45
375 324 292 242 210 159 408 43 ire 100 ire 33 ire 128 8lsb 4.43mhz colour burst (10 cycles) * sync level black/blank level 128 white level 21.5 ire 60 21.5 ire 33 ire white yellow cyan green magenta red blue black mv 1240 1000 450 300 150 50 0 * 9 cycles at 3.58mhz for pal-n 0117-26.eps figure 28 : composite pal-b, g, d, h, i, pal-n (if no setup) output (100% saturation, 100% amplitude color bars) 370 323 293 247 217 170 400 33 ire 40 ire 100 ire 34 ire 120 8lsb 3.58mhz colour burst (9 cycles) sync level black level white level 21.5 ire 21.5 ire 60 white yellow cyan green magenta red blue blank level 7.5 ire 140 120 black 1205 980 430 280 130 0 mv 0117-27.eps figure 29 : composite pal-m output (100% saturation, 100% amplitude color bars) functional description (continued) 12 - osd inputs fb (fast blanking) input controls the switching from ycrcb normal input data to ri, gi, bi transcoded inputs. these inputs must be locked to hsync, oddeven and ckref or h6osd signals. they are latched on the rising edge of ckref clock signal. ri, gi, bi inputs allow 8 color combinations that will address a 3 x 8 x 6-bit clut. each of the 8 values will address 3 x 6-bit samples cb, y, cr that will be extended to 8-bit samples to fit with normal input samples. y samples will be filtered to make sure that their bandwith is similar to ycrcb input sam- ples. mixing between osd data and ycrcb nor- mal input is performed before filtering stages. h6osd output clock signal is dedicated to output stage of external osd generator. the latter is synchronized with hsync and oddeven (or fsync) signals (see figures 30, 31 and 32). STV0117 21/45
functional description (continued) ? t=58?2xt c kref vide o outputs fb h6osd ri, gi, bi ck ri, gi, b i h6osd phas e is s oftware depende nt : clock is ena bled by i 2 c progra mming, the n h6osd is a continuous clock. ck r i, gi, bi pha s e is frame s ynchroniza tion de pe nde nt (ic m us t be locke d). this is a ga te d inte rna l clock. ckref h6osd ck ri, gi, b i (in te rn a l clock) pos s ible c a s e s : osd d e lay : 14 x t h6osd ? t 15 x t h6osd ie ? t = 58 ?2t c kref 0117-29.eps figure 30 : osd data insertion line 1 (fields 1 & 2) hsync line 2 60 t ckref max. 60 t ckref min. fb fsync hsync output ckref adjustment via i 2 c bus (synchro-delay registers) 1 st line interlaced 1 264 or 314 1 st line non-interlaced 1 262 or 312 field1 field2 fb position limits 0117-30.eps figure 31 : osd synchronization timing : master mode or slave mode (by oddeven or f from ycrcb data) hsync input 56t ckref 56t ckref fsync ckref 0117-38.eps figure 32 : osd synchronization timing : slave mode (oddeven and hsync) STV0117 22/45
13 - hamming decoding if the timing reference sequence is present in ycrcb input data, then eav and sav are ham- ming decoded.only f signal is extracted from eav and can be used in slave mode as the frame synchronization input signal. hamming decoding on eav and sav words give an information on signal transmission; multiples errors are detected and a flag is set to inform the microcontroller if it is interestedin hamming decod- ing results (see status i 2 c register). 14 - digitized video input dvid 9-bit digital input from a digitized analog video source can be directly routed to cvbs dac input. dvid data is latched on the rising edge of ckref clock signal. this access is controlled by hardware (edvid pin) or by i 2 c programmation (see figures 33 and 34). 15 - pinning compatibility with stv0116 the stv0116 is a pal/ntsc digital encoder de- vice that has 3 additional d/a converters for r, g, b encoded analog outputs. it does not support either closed captions encoding or macrovi- sion ? copy protection process. it is a ccir601 interlaced mode encoder. it does not offer the possibility to convert a digitized video input into an analog cvbs output, (like dvid in STV0117). it does not support the slave mode by oddeven and hsync, (it has no hsync input) (see fig- ure 35). 16 - i 2 c bus waveforms STV0117 ic is controlled by an i 2 c bus and internal 8-bit registers can be addressed in write or read mode. write and read operations are detailed in figures 36 and 37. functional description (continued) 2xt ckref max. cvbs ckref edvid (with i 2 c hardware control enabled) cvbs num. (internal) d1 d2 d3 d4 d5 d6 d0 d7 d8 d0 d1 d2 d3 di1 di0 di0 di1 dvid[8:0] 0117-31.eps figure 33 : digitized video timing 0 1 cvbs internal 9 9 dvid 0 1 0 d q d/a cvbs i ref ckref downcvbs (i 2 c) or reset (i 2 c or reset) 0 1 dvidc (i 2 c) edvid dvids (i 2 c) 0117-32.eps figure 34 : digitized video interface STV0117 23/45
39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 ycrcb3 ycrcb2 ycrcb1 ycrcb0 test8 testauto ys i ref1 c cvbs v dda v ssa r i ref2 g b test7 test6 test5 test4 h27 test3 test2 test1 test0 v ssc odd/even vcs ycrcb7 ycrcb6 ycrcb5 ycrcb4 v ddc nreset sda scl ri gi bi fb testscan h6osd v ssp v ddp stv0116 modified function on that pin 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 ycrcb3 ycrcb2 ycrcb1 ycrcb0 dvid0 testauto ys i ref c cvbs v dda v ssa csi2c fsync cfc edvid dvid1 dvid2 dvid3 dvid4 ckref dvid5 dvid6 dvid7 dvid8 v ssc odd/even vcs/hsync ycrcb7 ycrcb6 ycrcb5 ycrcb4 v ddc nreset sda scl ri gi bi fb testscan h6osd v ssp v ddp STV0117 0117-33.eps figure 35 : pinning compatibility with stv0116 functional description (continued) STV0117 24/45
functional description (continued) scl sda r/w a7 a6 a5 a4 a3 a2 a1 a0 d5 d4 d3 d2 d1 d0 i 2 c slave address 40h ack by STV0117 lsb address start d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 data byte 2 data byte 3 data byte n stop scl sda data byte 1 d6 d7 ack by STV0117 ack by STV0117 ack by STV0117 ack by STV0117 ack by STV0117 0117-34.ai figure 36 : STV0117/i 2 c write operation (csi2c = 0) scl sda r/w a7 a6 a5 a4 a3 a2 a1 a0 i 2 c slave address 40h lsb address start scl sda r/w d7 d6 d5 d4 d3 d2 d1 d0 data byte n start d7 d6 d5 d4 d3 d2 d1 d0 stop data byte 1 i 2 c slave address 41h stop ack by STV0117 ack by STV0117 ack by micro ack by STV0117 ack by micro 0117-35.eps figure 37 : STV0117/i 2 c read operation (csi2c = 0) when enabled, the chrominance, the luminance and the composite video signals are simultane- ously modified according to the macrovision ? copy protection process for ppv applications, revi- sion 6.0/6.1 dated september, 18, 1995. the control of this process is performed via i 2 c bus. for more information , please contact your nearest sgs-thomson microelectronics sales office. the programming document is provided to only those customers of sgs-thomson who have executed a license or a non-disclosure agreement with macrovision corporation. sample request and sales orders require the following procedure : sample requests procedure for non-licensed customers - contact vp sales & marketing, acp-ppv macrovision corporation phone : (408) 743-86-00 fax : (408) 743-86-10 - macrovisionwill send an ndato the customer - the nda will initiate the sampling process whereby the customer may receive macrovi- sion capable ics from sgs-thomson - samples will then be sent to the customer sales orders - if the customer has a macrovision ? license : the customer provides sgs-thomson with a written confirmation of the license. marketing will retain the written confirmation. customer can then purchase part. - if the customer does not have a macrovi- sion ? license : the customer must obtain a license or waiver from macrovision. the customer must provide sgs-thomson with a written confirmation of the license or waiver from macrovision. marketing retains the written confirmation. customer purchases part. neither parts nor programming information will be sent to the customer until the above conditions are met. macrovision ? copy protection process macrovision ? 6.0/6.1 copy protection process programming guide (a confidential document). contact video marketing sgs-thomson microelectronics - grenoble (france) - fax : (33) 76-58-56-10 note : for customers who do not need macrovision ? copy protection process, a modified version of STV0117 device can be available upon specific request. STV0117 25/45
absolute maximum ratings symbol parameter value unit v ddx dc supply voltage -0.3, 7.0 v v in digital input voltage -0.3, v dd + 0.3 v v out digital output voltage 0, v dd v i ref analog input reference current 7 ma i out analog output current 15 ma t oper operating temperature 0, +70 o c t stg storage temperature -40, +150 o c p tot total power dissipation 1000 mw 0117-02.tbl thermal data symbol parameter value unit r th(j-a) dc junction-ambient thermal resistance with sample soldered on a pcb typ. 54 c/w 0117-03.tbl dc electrical characteristics (t amb =25 c/70 o c, v dda =v ddc =v ddp = 5v, unless otherwise specified) symbol parameter test conditions min. typ. max. unit supply v dda analog positive supply voltage 4.75 5 5.25 v v ddp digital output buffer supply voltage 4.75 5 5.25 v v ddc digital core supply voltage 4.75 5 5.25 v i dda analog current consumption i ref = 3.5ma, r l = 300 ? , c l = 50pf, ckref = 30mhz, autotest mode, static input signals 10 28 ma i dd digital current consumption 40 90 ma digital inputs v il input voltage low level (any other pins) -0.3 0.8 v v ih input voltage high level (any other pins) 2.4 v dd -0.5 v i l input leakage current v il min or v ih max 10 a c in input capacitance 10 pf sda output v l output voltage low level, i o = 3ma 0.4 v i o output current during acknowledge 3 ma digital output v oh output voltage high level (standard ttl load) 2.4 v dd v v ol output voltage low level (standard ttl load) 0 0.6 v d/a converter i ref reference current source for 3 d/a converters 23 6 ma r l external load resistance with i ref = 2.9ma 300 ? i g current gain i ref = 2.9ma, r l = 300 ? , max. code 1.9 2.1 2.3 ge dac to dac gain matching (ys, c) i ref = 2.9ma, r l = 300 ? 0.5 3 3.5 % ile lf integral non-linearity i ref = 2.9ma, r l = 300 ? 2 lsb dle lf differential non-linearity i ref = 2.9ma, r l = 300 ? 1 lsb 0117-04.tbl STV0117 26/45
ac electrical characteristics (t amb =25 c/70 o c, v dda =v ddc =v ddp = 5v, unless otherwise specified) symbol parameter test conditions min. typ. max. unit digital input (ycrcb[7:0], scl, sda, nreset, oddeven, hsync, dvid[8:0], edvid, cfc) tsu input data set-up time ckref rising edge, ckref = 30mhz 5 ns tho input data hold time ckref rising edge, ckref = 30mhz 5 ns active period for nreset trstl input low time 210 ns osd digital inputs : ri, gi, bi, fb (other inputs are static : testscan, testauto, csi2c) tsu input data set-up time ckref rising edge, ckref = 30mhz 15 ns tho input data hold time ckref rising edge, ckref = 30mhz 0 ns reference clock : ckref tc_ref clock cycle time ccir601 application square pixel/525lines square pixel/625lines 37.04 40.75 33.90 ns ns ns td_ref clock duty cycle 50 % tr_ref clock rise time 5 ns tf_ref clock fall time 5ns i 2 c clock : scl tc_scl clock cycle time rpull_up = 4.7k ? 2 mhz td_scl clock duty cycle 50 % tl_scl low level cycle rpull_up = 4.7k ? 250 ns digital outputs td_h6osd delay time ckref rising edge ckref = 30mhz, c l = 50pf 10 25 ns td_fsync delay time ckref rising edge ckref = 30mhz, c l = 50pf 10 22 ns td_oddeven delay time ckref rising edge ckref = 30mhz, c l = 50pf 10 22 ns td_vcs_hsync delay time ckref rising edge ckref = 30mhz, c l = 50pf 10 22 ns 0117-05.tbl STV0117 27/45
i 2 c registers description STV0117 ic is controlled by an i 2 c bus and internal registers can be read or written by an external microcontroller. encoder addresses are : if csi2c pin = ?0? then : write 8-bit address read 8-bit address is is 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 (40 hex) (41 hex) if csi2c pin = ?1? then : write 8-bit address read 8-bit address is is 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 (42 hex) (43 hex) registers are organized as follows : reg 0 standard selection, sync mode selection, sync polarity selection, master/slave mode reg 1 sync output selection, vbi lines blanking, filter selection, sync enable in free-run, color killer, palnsetup, closed caption/extended data encoding mode reg 2 non-interlaced mode, autotest, burst control, square pixel mode, oscillator reset value selection, oscillator reset, phase reset cycle definition reg 3 color frequency control, dvid controls, luma delay adjustment reg 4 software reset, power-down mode for dacs, h6osd control reg 5-6 programmable delay for time base with reference to data reg 7-8 synchro delay for time base with reference to synchronization mode reg 9-10-11 increment for color subcarrier frequencies reg 12-13-14 offset for color subcarrier phase reg 15-...-22 y clut for ri, gi, bi inputs encoding reg 23-...-30 cr clut for ri, gi, bi inputs encoding reg 31-...-38 cb clut for ri, gi, bi inputs encoding reg 39-40 closed caption characters/extended data for field 1 (odd) reg 41-42 closed caption characters/extended data for field 2 (even) reg 43 closed caption/extended data line insertion select for field 1 (odd) reg 44 closed caption/extended data line insertion select for field 2 (even) reg 45-...-60 reserved reg 61 chip part identification number reg 62 chip revision identification number reg 63 status : hamming decoding, frame synchro flag, closed caption data access, field counter, limit of adjustment value in registers 5-6 reg 64 i 2 c read control and reserved modes STV0117 28/45
i 2 c registers description (continued) register access address msb lsb control r/w 00 std1 std0 sym2 sym1 sym0 sys1 sys0 mod configuration1 r/w 01 syncsel blkli filred syncok coki palnsetup cc2 cc1 configuration2 r/w 02 nintrl testauto bursten sqpix selrst rstosc valrst1 valrst0 configuration3 r/w 03 cfc1 cfc0 dvids dvidc del3 del2 del1 del0 configuration4 r/w 04 softrst downcvbs downys downc enh6osd xx xx xx delay_msb r/w 05 d11 d10 d9 d8 d7 d6 d5 d4 delay_lsb r/w 06 d3 d2 d1 d0 xx xx xx xx sync_delay_msb r/w 07 d11 d10 d9 d8 d7 d6 d5 d4 sync_delay_lsb r/w 08 d3 d2 d1 d0 xx xx xx xx increment fsc r/w 09 xx xx d21 d20 d19 d18 d17 d16 increment fsc r/w 10 d15 d14 d13 d12 d11 d10 d9 d8 increment fsc r/w 11 d7 d6 d5 d4 d3 d2 d1 d0 phase fsc r/w 12 xx xx o21 o20 o19 o18 o17 o16 phase fsc r/w 13 o15 o14 o13 o12 o11 o10 o9 o8 phase fsc r/w 14 o7 o6 o5 o4 o3 o2 o1 o0 palety r/w 15 y75 y74 y73 y72 y71 y70 xx xx palety r/w 16 y65 y64 y63 y62 y61 y60 xx xx palety r/w 17 y55 y54 y53 y52 y51 y50 xx xx palety r/w 18 y45 y44 y43 y42 y41 y40 xx xx palety r/w 19 y35 y34 y33 y32 y31 y30 xx xx palety r/w 20 y25 y24 y23 y22 y21 y20 xx xx palety r/w 21 y15 y14 y13 y12 y11 y10 xx xx palety r/w 22 y05 y04 y03 y02 y01 y00 xx xx paletcr r/w 23 cr75 cr74 cr73 cr72 cr71 cr70 xx xx paletcr r/w 24 cr65 cr64 cr63 cr62 cr61 cr60 xx xx paletcr r/w 25 cr55 cr54 cr53 cr52 cr51 cr50 xx xx paletcr r/w 26 cr45 cr44 cr43 cr42 cr41 cr40 xx xx paletcr r/w 27 cr35 cr34 cr33 cr32 cr31 cr30 xx xx paletcr r/w 28 cr25 cr24 cr23 cr22 cr21 cr20 xx xx paletcr r/w 29 cr15 cr14 cr13 cr12 cr11 cr10 xx xx paletcr r/w 30 cr05 cr04 cr03 cr02 cr01 cr00 xx xx paletcb r/w 31 cb75 cb74 cb73 cb72 cb71 cb70 xx xx paletcb r/w 32 cb65 cb64 cb63 cb62 cb61 cb60 xx xx paletcb r/w 33 cb55 cb54 cb53 cb52 cb51 cb50 xx xx paletcb r/w 34 cb45 cb44 cb43 cb42 cb41 cb40 xx xx paletcb r/w 35 cb35 cb34 cb33 cb32 cb31 cb30 xx xx paletcb r/w 36 cb25 cb24 cb23 cb22 cb21 cb20 xx xx paletcb r/w 37 cb15 cb14 cb13 cb12 cb11 cb10 xx xx paletcb r/w 38 cb05 cb04 cb03 cb02 cb01 cb00 xx xx c. c. char f1 r/w 39 opc11 c117 c116 c115 c114 c113 c112 c111 c. c. char f1 r/w 40 opc12 c127 c126 c125 c124 c123 c122 c121 c. c. char f2 r/w 41 opc21 c217 c216 c215 c214 c213 c212 c211 c. c. char f2 r/w 42 opc22 c227 c226 c225 c224 c223 c222 c221 c. c. line f1 r/w 43 xx xx xx l14 l13 l12 l11 l10 c. c. line f2 r/w 44 xx xx xx l24 l23 l22 l21 l20 reserved reg ... 45 reserved ... ... ... ... reserved reg ... 60 reserved chipid r 61 01110 101 revid r 62 xxxxx xxx status r 63 hok atfr b2_free b1_free fldct2 fldct1 fldct0 over_delay test r/w 64 t7 t6 t5 t4 t3 t2 t1 t0 reserved reg ... ... STV0117 29/45
i 2 c registers description (continued) i 2 c format write mode (all registers except status, chipid, revid) : in case of csi2c pin = ?0? : s slave address w a sub-address a data 0 a ... data n a p s start condition slave address 0100000 w = ?0? write flag a acknowledge, generated by slave (STV0117) when ok a = ?0? else ?1? sub-address sub-address register (content is made of one byte) data 0 first data byte data n continued data bytes ( address is automaticaly incremented) and a?s p stop condition read mode (status, chipid and revid registers) : in case of csi2c pin = ?0? : s slave address w ac sub-address n ac p then : s slave address r ac data n am data n + 1 ... am p s start condition slave address 7-bit address for STV0117 : 0100000 w = ?0? write flag ac acknowledge, generated by slave (STV0117) when ok a = ?0?, else ?1? r = ?1? read flag sub-address n 8-bit register sub-address data n data byte of register n, sent by STV0117 data n +1 data byte of register n+1 (address automaticaly incremented) am acknowledge, generated by the microcontroller am = ?0? when acknowledge is ok, else ?1? p stop condition (when last am = ?1?) remarks in case of csi2c pin = ?0? : writing of a register : registers 0, 1, ..., 44 dec can be loaded sequentiallywith only one start/stop condition followed by the sub-address of the first register desired. example : loading of the 4 configuration registers : start followed by address 40 hexa and sub-address 1 and then 4 bytes of data and stop. as specified, the i 2 c registers can be loaded sequentially in one run in most cases. however, when this would involve performing a soft reset by writing a ?1? into the ?softrst? bit of register 4, it is necessary to stop after register 4 and start a new i 2 c transfer sequence to send the next registers. reading of a register : example : reading of register 63 dec (status) : start followed by address 40 hexa, ac = ?0? then sub-address 63 dec, ac= 0? and stop. then start, address 41 hexa, ac = ?0?, and then data of register 63 dec, am = ?1? and stop condition. STV0117 30/45
registers mapping and description (*) default mode when nreset pin is active (low level) register 0 : control (read/write) msb lsb std1 std0 sym2 sym1 sym0 sys1 sys0 mod (*) std1 0 0 1 1 std0 0 1 0 1 standard selection (see note 1) pal bdghi pal n (argentina or paraguay/uruguay - see setup bit in register1) ntsc m pal m (*) sym2 0 1 synchronization source in slave mode synchro source defined by sym0, vcs/hsync is output only line-based synchronization, STV0117 locks on hinput + oddeven inputs (*) sym1 0 1 must contains same value as sym2 (*) sym0 0 1 frame synchronization input source in slave mode (see note 2) oddeven is the synchro input, vcs/hsync is an output ycrcb[7:0] input (extraction of f from eav) : oddeven and vcs/hsync are output signals (*) sys1 0 1 synchro : polarity of outputs : vcs/hsync (when sym2 = ?0?), fsync positive (leading edge is the rising edge) negative (leading edge is the falling edge) (*) sys0 0 1 synchro polarity selection 0 : defines the polarity of oddeven in all cases, and of hsync when hsync is an input (i.e. sym2 = 1 and mod = 0) oddeven falling edge flags start of field 1 (odd field) and (if sym2 = 1 and mod = 0) hsync falling edge is line synchro input active edge oddeven rising edge flags start of field 1 (odd field) and (if sym2 = 1 and mod = 0) hsync rising edge is line synchro input active edge (*) mod 0 1 slave master (freerun forced) (see note 3) notes : 1. standard on hardware reset is ntsc ; any standard modification must be followed by a software reset in order to select the right parameters for color subcarrier frequency. 2. sym0 is not taken into account when sym2 = ?1?, or when master mode is active (mod = ?0? or testauto = ?1?). 3. master mode is forced when testauto pin is high or when bit testauto of register2 is set to ?1?. STV0117 31/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) register 1 : configuration 1 (read/write) msb lsb syncsel blkli filred syncok coki palnsetup cc2 cc1 (*) syncsel 0 1 signal selection for vcs/hsync output : useful in master mode, or in slave mode with sym2 = ?0? composite sync : vcs/hsync = vcs horizontal sync : vcs/hsync = hsync (*) blkli 0 1 blanking lines selection for active video lines area (see note 1 ) only following lines inside vertical interval are blanked - in 525/60 system : lines 1-9 and lines 263 (half)-272 (smpte line number convention) - in 625/50 system : lines 623 (half)-5 and lines 311-318 (ccir line number convention) all lines inside vbi are blanked - in 525/60 system : lines 1-19 and lines 263 (half)-282 (smpte line number convention) - in 625/50 system : lines 623(half)-22 and lines 311-335 (ccir line number convention) (*) filred 1 0 chroma pass band filter select (see note 2 ) 1.3mhz (for u/v in pal), in ntsc : 1.3mhz for i and 0.5mhz for q 1.8mhz (extended bandwidth for u/v in pal, or q/i in ntsc) (*) syncok 0 1 synchros availability in case of input synchronization loss with no free-run active (if sym1 = 0) no synchro output signals output synchros available on vcs/hsync, oddeven, ys, cvbs : i.e same behaviour as free-run except that video output is still blanked (luminance and chrominance are at black level) (*) coki 0 1 color killer color on color suppressed on cvbs output signal (cvbs = ys) but color still exists on c output (*) palnsetup 0 1 pedestal to make difference between 2 pal-n when std[1:0] = 01 blanking level and black level are identical on all lines. this is only valid for pal-n (argentina). black level is 7.5 ire above blanking level on all un-blanked lines. this is only valid for pal-n (paraguay and uruguay). in pal-n (paraguay and uruguay), black level is 28 lsb above blanking level for lines 23-310 and 336-623 only (ccir line number convention). in all cases, gain factor is fixed to obtain chrominance required levels. for other standards, this bit is ignored and setup is automatically performed for pal-m and ntsc-m (*) cc2 0 0 1 1 cc1 0 1 0 1 closed caption/extended data encoding mode closed caption/extended data encoding disabled closed caption/extended data encoding enabled in field 1 (odd) closed caption/extended data encoding enabled in field 2 (even) closed caption/extended data encoding enabled in both fields notes : 1. blkli must be set to ?0? when closed captions are to be encoded : - in 525/60 system : before line 20 (smpte) or before line 283 (smpte) - in 625/50 system : before line 23 (ccir) or before line 336 (ccir) (reduced blanking allows preservation of analogue wide screen signalling (line 23), video programing service (line 16), etc) 2. three filters for encoding : with ckref = 27mhz (chroma bw becomes 1.7mhz/1.2mhz, 0.45mhz with sin(x)/x dac). when synchro is lost (frame synchro flag (=atfr bit) is low), filred is forced to ?0?. STV0117 32/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) register 2 : configuration 2 (read/write) msb lsb nintrl testauto bursten sqpix selrst rstosc valrst1 valrst0 (*) nintrl 0 1 non-interlaced mode select (see note 1) interlaced mode (625/50 or 525/60 system) non-interlaced mode (*) testauto 0 1 color bar pattern software control color bar pattern is off if hardware testauto (pin 39) is low. color bar pattern is enabled (100% luma, 75% chroma), whatever the value on pin testauto. (*) bursten 0 1 chrominance burst control burst is turned off, chrominance output is not affected by this bit burst is enabled (*) sqpix 0 1 square pixel mode select (see note 2) ccir 601 pixel rate (13.5mhz) (pixel with 4:3 aspect ratio) square pixel rate (pixel with 1:1 aspect ratio , pixel clock frequency is defined according to pal or ntsc) (*) selrst 0 1 selects set of reset values for direct digital frequency synthesizer (see note 5) hardware reset values for phase and increment of subcarrier oscillator i 2 c loaded reset values selected (see contents of registers 9 up to 14) (*) rstosc 0to1 0 software phase reset of ddfs (direct digital frequency synthesizer) (see note 3) transition generates a pulse reset for oscillator phase (only) (*) valrst1 0 0 1 1 valrst0 0 1 0 1 selects the phase reset cycle of ddfs (see note 4) no reset on the phase of the oscillator reset of the oscillator with phase_value every 2 fields reset of the oscillator with phase_value every 4 fields reset of the oscillator with phase_value every 8 fields notes : 1. in non-interlaced mode, it is a 624/2 = 312 line mode or a 524/2 = 262 line mode with waveforms same as the first field of ccir or smpte. nintrl update is synchronized to beginning of next frame. to use the circuit in non-interlaced mode in conjunction with one of the 625-line pal standards, the circuit should first be initialised in pal interlaced mode, and then switched to non-interlaced mode. 2. sqpix update is synchronized to beginning of next frame. 3. rstosc is automatically disabled (rstosc forced to ?0?) after generation of phase reset pulse; rstosc is active during 1 ckref period. 4. phase_value is the default phase or that one loaded in registers 12,13 and 14. 5. in square pixel format, it is not possible to modify by i 2 c loading the d.d.f.s. increment used for color subcarrier frequency generator. STV0117 33/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) register 3 : configuration 3 (read/write) msb lsb cfc1 cfc0 dvids dvidc del3 del2 del1 del0 (*) cfc1 0 0 1 1 cfc0 0 1 0 1 color frequency control via cfc line disable (update is done by loading of registers 9, 10 and 11) update of increment for ddfs just after serial loading via cfc update of increment for ddfs on next active edge of hsync update of increment for ddfs just before next color burst (*) dvids 0 1 digitized video data control select software control (see bit dvidc) hardware control (pin edvid, same role as bit dvidc) (*) dvidc 0 1 digitized video data multiplexer controlled by software : dvidc is taken into account when dvids = ?0? dvid[8:0] ignored dvid[8:0] selected del(3:0) delay on luma path with reference to chroma path (*) 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 + 4 pixel clock period delay on luma + 3 pixel clock period delay on luma + 2 pixel clock period delay on luma + 1 pixel clock period delay on luma + 0 pixel clock period delay on luma - 1 pixel clock period delay on luma - 2 pixel clock period delay on luma - 3 pixel clock period delay on luma - 4 pixel clock period delay on luma others + 0 pixel clock period delay on luma in ccir601 mode, one pixel clock period is 1/13.5mhz (74.04ns) in square pixel 525 lines mode, a pixel clock period is 1/12.27mhz (81.5ns) in square pixel 625 lines mode, a pixel clock period is 1/14.75mhz (67.8ns) STV0117 34/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) register 4 : configuration 4 (read/write) msb lsb softrst downcvbs downys downc enh6osd xx xx xx (*) softrst 0 1 software reset no reset software reset (*) downcvbs 0 1 down mode on 9-bit dac cvbs cvbs dac in normal operation cvbs dac input forced to 000000000 to reduce consumption and have lowest analog output (*) downys 0 1 down mode on 9-bit dac ys ys dac in normal operation ys dac input forced to 000000000 to reduce consumption and have lowest analog output (*) downc 0 1 down mode on 9-bit dac c c dac in normal operation c dac input forced to 000000000 to reduce consumption and have lowest analog output (*) enh6osd 0 1 h6osd output enable control h6osd is not generated (h6osd = ?0?) h6osd is generated (phase is defined by reset operation) clock period is equal to ckref/4 clock period note : softrst bit is automatically reset at i 2 c stop condition, software reset is active during 4 ckref periods when softrst is activated, all the device is reset as with hardware reset except for the first five i 2 c registers (control and configurations). STV0117 35/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) register 5 : delay_msb (read/write) register 6 : delay_lsb (read/write) msb lsb register 5 d11 d10 d9 d8 d7 d6 d5 d4 register 6 d3 d2 d1 d0 xx xx xx xx note : when adjustment is needed (default values do not fit the application), these delay registers can be loaded anytime (remember however that a software reset forces the default values). in master mode (mod = 1 or autotest modes) (see figure 13) position of oddeven as output signal is adjusted with reference to analog horizontal sync according to the 2?s complement value loaded in these registers : the value must be within range : [-1536,+1536]. if it is not the case, the value taken into account is the maximum allowed depending on d11 for sign. oddeven transition occurs on sample number : (max line length + 1 + delay(11:0) + 2) modulo [max line length]. thus, by changing ?delay?, it is possible to shift the location of oddeven with reference to the analogue video outputs (or equivalently, to the ycrcb input data samples). d[11:0] is a 2?s complement value d[11] : when ?0? oddeven lags with reference to main sample counter of n (=d[10:0]) samples. oddeven is closer to analog horizontal sync output signal. d[11] : when ?1? oddeven leads with reference to main sample counter of n (=not d[10:0] + 1) samples. oddeven is further away from analog horizontal sync output signal. default value is d[11:4] = 00 hexa, d[3:0], xxxx = 00 hexa, so that oddeven signal toggles when main sample 11-bit-counter value is 003 hexa. in slave mode (mod = 0) if sym2 = 0 (vcs/hsync is not an input) : main sample counter is loaded with value d[10:0] when either oddeven (as input signal), or f signal (extracted from eav on ycrcb[7:0] input) changes with the programmed transition for the frame beginning. main sample counter is loaded with the value:(max line length + 1 + delay(11:0)) modulo [max line length], 2 ckref clock periods after frame synchro input (f or oddeven). thus position of analog synchronization output signal can be adjusted with reference to ycrcb[7:0] input data. position of oddeven (as output signal, only when in slave by f from ycrcb) is also defined with d[11:0] as in master mode (see figure 14). d[11:0] is a 2?s complement value d[11] : when ?0?, analog synchronization output signal leads with reference to ycrcb[7:0] input data of n (= d[10:0]) samples. d[11] : when ?1?, analog synchronization output signal lags with reference to ycrcb[7:0] input data of n (= not d[10:0] + 1) samples. (*) hardware reset values : when sym0 = 0 (synchro by oddeven), default value of delay registers is 0000h when sym0 = 1 (synchro by f from eav in ycrcb[7:0]), default value of delay registers is : in 525/60 systems :fe60 hexa (1st byte:254 2nd byte:96) in 625/50 systems :fee0 hexa (1st byte:254 2nd byte:224) with these default values, oddeven output signal is the image of timing reference frame transmitted on ycrcb[7:0] input data (eav decoding)) if sym2 = 1 (vcs/hsync = hsync is a synchro input with oddeven) : the allowed values for delay registers are within range : [-44..-1,0,..+43]. if it is not the case, the value taken into account is the maximum allowed depending on d11 for sign. STV0117 36/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) register 7 : synchro_delay_msb (read/write) register 8 : synchro_delay_lsb (read/write) msb lsb register 7 d11 d10 d9 d8 d7 d6 d5 d4 register 8 d3 d2 d1 d0 xx xx xx xx if sym2 = 0 (vcs/hsync is a synchro output) : the synchro_delay register is used to adjust the position of the vcs/hsync and fsync output signals with reference to the analog video outputs. vcs/hsync and fsync are decoded from a fixed reference value of an auxillary sample counter. it is possible to change the relation between this auxillary counter and the main sample counter, thus causing the vcs/hsync and fsync locations to be shifted. the synchro_delay register codes the shift required in terms of clock periods with reference to the default position. figures 14 and 15 illustrate this default position. d[11:0] is the 2?s complement value that codes the desired shift, i.e : d[11] : when ?0?, vcs/hsync and fsync output signals lead with reference to default location by n (= d[10:0]) samples. d[11] : when ?1?, vcs/hsync and fsync output signals lag with reference to default location by n (= not d[10:0] + 1) samples. if sym2 = 1 (vcs/hsync = hsync is a synchro input) : the synchro_delay register has no effect. in that particular case, the fsync output is synchronous with the analog synchronization present in the output analog video signals (y and cvbs). the default value of the synchro delay register is 0000 hex, but they should be set to fce0 hex for direct compatibility with an sgs-thomson mpeg application. caution : changing the synchro delay from its default value (0000 hex) to a new value must be done whilst the chip is not in master mode and is out of sync . STV0117 37/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) registers 9-10-11 : increment for direct digital frequency synthesizer (read/write) msb lsb register 9 xx xx d21 d20 d19 d18 d17 d16 register 10 d15 d14 d13 d12 d11 d10 d9 d8 register 11 d7 d6 d5 d4 d3 d2 d1 d0 22-bit increment of sinus rom address : 1 lsb ~ 6.44hz in ccir ~ 7.03hz in square pixel-625 ~ 5.85hz in square pixel-525 hardware reset values with reference to standard selected : these values are those selected when selrst bit equals ?0?, (in that case, content of registers 9-10-11 is not taken into account). moreover, registers 9-10-11 are never reset and must be explicitly written into to contain sensible information. rectangular pixel mode : synthesized subcarrier frequency ref. clock (*) d(21:0) : 087c1f hexa, 556063 dec for ntsc m f = 3.5795452mhz 27mhz d(21:0) : 0a8263 hexa, 688739 dec for pal bghin f = 4.43361875mhz 27mhz d(21:0) : 087da5 hexa, 556453 dec for pal n f = 3.5820558mhz 27mhz d(21:0) : 0879bc hexa, 555452 dec for pal m f = 3.57561149mhz 27mhz square pixel mode : synthesized subcarrier frequency ref. clock d(22:0) : 095555 hexa, 611669 dec for ntsc m f = 3.579545mhz 24.5454mhz d(22:0) : 099e63 hexa, 630371 dec for pal bghin f = 4.43361875mhz 29.50mhz d(22:0) : 07c570 hexa, 509296 dec for pal n f = 3.582056mhz 29.50mhz d(22:0) : 0952b5 hexa, 610997 dec for pal m f = 3.575610mhz 24.5454mhz these hard-wired values being out of any user register, they cannot be read out from the STV0117. note : the value loaded in these registers are taken into account after a software reset with selrst equals ?1? (see register 2, bit selrst) (refer to figure 12). registers 12-13-14 : static phase offset for direct digital frequency synthesizer (read/write) msb lsb register 12 xx xx o21 o20 o19 o18 o17 o16 register 13 o15 o14 o13 o12 o11 o10 o9 o8 register 14 o7 o6 o5 o4 o3 o2 o1 o0 hardware reset values with reference to standard selected : these values are those selected when selrst bit equals ?0?, (in that case, content of registers 12-13-14 is not taken into account). moreover, registers 12-13-14 are never reset and must be explicitly written into to contain sensible information. hard-wired values being out of register ; they cannot be read out from the STV0117. the hard-wired values fro phase offset are the following : rectangular pixel format : (*) o(21:0) : 1e2de8 hexa for ntsc m o(21:0) : 000f40 hexa for pal bghin, m square pixel format : o(21:0) : 000000 hexa for all standards the recommended values are : 05bfa0 for bgi-n-mpal and 17f4ff for m-ntsc. note : the value loaded in these registers are taken into account after an oscillator reset (bit rstosc of register 2) with selrst equals ?1? (see register 2, bit selrst). STV0117 38/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) registers 15-16-17-18-19-20-21-22 : palety (read/write) msb lsb register 15 y75 y74 y73 y72 y71 y70 xx xx register 16 y65 y64 y63 y62 y61 y60 xx xx register 17 y55 y54 y53 y52 y51 y50 xx xx register 18 y45 y44 y43 y42 y41 y40 xx xx register 19 y35 y34 y33 y32 y31 y30 xx xx register 20 y25 y24 y23 y22 y21 y20 xx xx register 21 y15 y14 y13 y12 y11 y10 xx xx register 22 y05 y04 y03 y02 y01 y00 xx xx 8 x 6-bit words for y component (*) default value y(hexa) y(dec) color (100% white to black) ri, gi, bi (osd index inputs) register15 y7x=ec 236 white 111 register16 y6x=a0 160 yellow 110 register17 y5x=50 80 magenta 101 register18 y4x=40 64 red 100 register19 y3x=84 132 cyan 011 register20 y2x=74 116 green 010 register21 y1x=24 36 blue 001 register22 y0x=10 16 black 000 default color bar pattern display is from left to right : white, yellow, cyan, green, magenta, red, blue, black registers 23-24-25-26-27-28-29-30 : paletcr (read/write) msb lsb register 23 cr75 cr74 cr73 cr72 cr71 cr70 xx xx register 24 cr65 cr64 cr63 cr62 cr61 cr60 xx xx register 25 cr55 cr54 cr53 cr52 cr51 cr50 xx xx register 26 cr45 cr44 cr43 cr42 cr41 cr40 xx xx register 27 cr35 cr34 cr33 cr32 cr31 cr30 xx xx register 28 cr25 cr24 cr23 cr22 cr21 cr20 xx xx register 29 cr15 cr14 cr13 cr12 cr11 cr10 xx xx register 30 cr05 cr04 cr03 cr02 cr01 cr00 xx xx 8 x 6-bit words for cr component (*) default value cr(hexa) cr(dec) color (75% r, g, b) ri, gi, bi (osd index inputs) register23 cr7x=80 128 white 111 register24 cr6x=8c 140 yellow 110 register25 cr5x=c4 196 magenta 101 register26 cr4x=d4 212 red 100 register27 cr3x=2c 44 cyan 011 register28 cr2x=38 56 green 010 register29 cr1x=70 112 blue 001 register30 cr0x=80 128 black 000 STV0117 39/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) registers 31-32-33-34-35-36-37-38 : paletcb (read/write) msb lsb register 31 cb75 cb74 cb73 cb72 cb71 cb70 xx xx register 32 cb65 cb64 cb63 cb62 cb61 cb60 xx xx register 33 cb55 cb54 cb53 cb52 cb51 cb50 xx xx register 34 cb45 cb44 cb43 cb42 cb41 cb40 xx xx register 35 cb35 cb34 cb33 cb32 cb31 cb30 xx xx register 36 cb25 cb24 cb23 cb22 cb21 cb20 xx xx register 37 cb15 cb14 cb13 cb12 cb11 cb10 xx xx register 38 cb05 cb04 cb03 cb02 cb01 cb00 xx xx 8 x 6-bit words for cb component (*) default value cb(hexa) cb(dec) color (75% r, g, b) ri, gi, bi (osd index inputs) register31 cb7x=80 128 white 111 register32 cb6x=2c 44 yellow 110 register33 cb5x=b8 184 magenta 101 register34 cb4x=64 100 red 100 register35 cb3x=9c 156 cyan 011 register36 cb2x=48 72 green 010 register37 cb1x=d4 212 blue 001 register38 cb0x=80 128 black 000 registers 39-40 : cccf1 (read/write) : closed caption characters/extended data for field 1 (see note) first byte to encode : msb lsb register 39 opc11 c117 c116 c115 c114 c113 c112 c111 opc11 : odd-parity bit of us-ascii 7-bit character c11(7:1) second byte to encode : msb lsb register 40 opc12 c127 c126 c125 c124 c123 c122 c121 opc12 : odd-parity bit of us-ascii 7-bit character c12(7:1) default value : none, but closed captions enabling without loading these registers will issue character null. registers 39-40 are never reset. note : there is a one bit rotation when reading the values stored in these registers. if register 39 or 40 contains the following 8 bits : b8.b7.b6.b5.b4.b3.b2.b1, the value read will be : b1.b8.b7.b6.b5.b4.b3.b2. STV0117 40/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) registers 41-42 : cccf2 (read/write) : closed caption characters/extended data for field 2 (see note) first byte to encode : msb lsb register 41 opc21 c217 c216 c215 c214 c213 c212 c211 opc21 : odd-parity bit of us-ascii 7-bit character c21(7:1) second byte to encode : msb lsb register 42 opc22 c227 c226 c225 c224 c223 c222 c221 opc22 : odd-parity bit of us-ascii 7-bit character c22(7:1) default value : none, but closed captions enabling without loading these registers will issue character null. registers 41-42 are never reset. note : there is a one bit rotation when reading the values stored in these registers. if register 41 or 42 contains the following 8 bits : b8.b7.b6.b5.b4.b3.b2.b1, the value read will be : b1.b8.b7.b6.b5.b4.b3.b2. register 43 : cclif1 (read/write) : closed caption/extended data line insertion for field 1 tv field1 line number where closed caption/extended data is to be encoded is programmable through the following register : msb lsb xx xx xx l14 l13 l12 l11 l10 - 525/60 system : (525-smpte line number convention). only lines 10 through 22 should be used for closed caption or extended data services (line 1 through 9 contain the vertical sync pulses with equalizing pulses). l1(4:0) = 00000 no line selected for closed caption encoding l1(4:0) = 000xx do not use these codes l1(4:0) = 00100 line 10 (smpte) selected for encoding .... l1(4:0) = 10000 line 22 (smpte) selected for encoding l1(4:0) = others from line 23 upto 37 (smpte) - 625/50 system : (625-ccir line number convention). only lines 7 through 23 should be used for closed caption or extended data services. l1(4:0) = 00000 no line selected for closed caption encoding l1(4:0) = 00001 line 7 (ccir) selected for encoding .... l1(4:0) = 10001 line 23 (ccir) selected for encoding l1(4:0) = others from line 24 upto 37 (ccir) (*) default value = 0 1111 line 21 (525/60, 525-smpte line number convention) line 21 (625/50, 625-ccir line number convention) note : see also note 1 concerning ?blkli? bit in configuration register 1. STV0117 41/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) register 44 : cclif2 (read/write) : closed caption/extended data line insertion for field 2 tv field2 line number where closed caption/extended data is to be encoded is programmable through the following register : msb lsb xx xx xx l24 l23 l22 l21 l20 - 525/60 system : (525-smpte line number convention). only lines 273 through 284 should be used for closed caption or extended data services (preceding lines contain the vertical sync pulses with equalizing pulses), although it is possible to program over a wider range. l2(4:0) = 00000 no line selected for closed caption encoding l2(4:0) = 000xx do not use these codes l2(4:0) = 00100 line 273 (smpte) selected for encoding .... l2(4:0) = 0 1111 line 284 (smpte) selected for encoding l2(4:0) = others from line 285 upto 292 (smpte) - 625/50 system : (625-ccir line number convention). only lines 319 through 336 should be used for closed caption or extended data services (preceding lines contain the vertical sync pulses with equalizing pulses), although it is possible to program over a wider range. l2(4:0) = 00000 no line selected for closed caption encoding l2(4:0) = 00001 line 319 (ccir) selected for encoding l2(4:0) = 00010 line 320 (ccir) selected for encoding .... l2(4:0) = 10010 line 336 (ccir) selected for encoding l2(4:0) = others from line 337 upto 349 (ccir) (*) default value = 0 1111 line 284 (525/60, 525-smpte line number convention) line 333 (625/50, 625-ccir line number convention) note : see also note 1 concerning ?blkli? bit in configuration register 1. registers 45 up to 60 : reserved registers register 61 : chipid (read only) : chip part identification number msb lsb 01110101 register 62 : revid (read only) : chip revision identification number msb lsb xxxxxxxx may be used by the manufacturer to indicate revision level of the silicon (the revid register for version 1.0 contains 0000 0001). STV0117 42/45
registers mapping and description (continued) (*) default mode when nreset pin is active (low level) register 63 : status (read only) msb lsb hok atfr buf2_free buf1_free fieldct2 fieldct1 fieldct0 over_delay (*) hok : 0 1 hamming decoding of odd/even signal from ycrcb (see note) multiple errors 0 or 1 error (*) atfr : 0 1 frame synchronization flag encoder not synchronized in slave mode : encoder synchronized (*) buf2_free : closed caption field2-registers access condition. closed caption data is buffered before being output on the relevant tv line ; buf2_free is reset if the buffer is temporarily unavailable. if the microcontroller can guarantee that registers 41 and 42 (cccf2) are never written more than once between two frame reference signals, then the buf2_free bit will always be true (set). otherwise, closed caption field2 register access might be temporarily forbidden by resetting the buf2_free bit until the next field2 closed caption line occurs. note that this bit is false (reset) when 2 pairs of data bytes are awaiting to be encoded, and is set back immediately after one of these pairs has been encoded (so at that time, encoding of the last pair of bytes is still pending) reset value = 1 (access authorized) (*) buf1_free : closed caption field1-registers access condition. same signification of buf2_free bit but for closed caption of field1. reset value = 1 (free access) (*) fieldct[2:0] : 000 ... 111 digital field identification number indicates field 1 indicates field 8 fieldct[0] is the odd/even information (?0? for odd field, ?1? for even field) (*) over_delay : 0 1 limit of registers 5-6 adjustment value no overflow with loaded value in registers 5-6 value loaded in registers 5-6 is outside allowed limits, but forced to maximum authorized note : signal quality detector issued from hamming decoding on eav, sav from ycrcb. registers 64-65-66-67 : reserved registers register 64 : test (read/write) msb lsb t7 t6 t5 t4 t3 t2 t1 t0 default value is 40 hex. i 2 c registers can be accessed in read mode by writing 60 hex in this register. all other values are reserved and should not be used. STV0117 43/45
v ddp 4.7k ? v ddp 4.7k ? scl sda mcu 7 8 9 10 16 17 18 19 20 26 27 28 29 30 36 37 38 39 40 11 12 13 14 15 21 22 23 24 31 32 33 34 35 25 1 2 3 4 5 6 44434241 ri gi bi fb ckref v ssp i ref v ssa v ddc 100nf 10 f 22k ? odd/even y/cr/cb7 y/cr/cb6 y/cr/cb5 y/cr/cb4 y/cr/cb3 y/cr/cb2 y/cr/cb1 y/cr/cb0 mpeg decoder v ddp 100nf 10 f v dda 100nf 10 f v dda STV0117 (master) v dda v ddc v ddp :5v :5v :5v 75 ? 470 ? 68 ? :v ssa (0v) h6osd i 2 c interface osd interface ccir 656 interface luminance processing 9 bit tridac s ynchronism processing chrominance processing :v ss (0v) = v ssp =v ssc hs ync vide o output sta ge 75 ? in vide o output sta ge 75 ? in vide o output sta ge 75 ? in in out video output stage nreset cs i2c ys c cvbs edvid cfc (from ge n-lock) fs ync cs i2c 9 dvid hsync oddeven vcs /hs ync dvid8 dvid7 dvid6 dvid5 dvid4 dvid3 dvid2 dvid1 dvid0 f f : low p a ss filter v ssc 22 f 1.2k ? os d generator (o ptio nn a l) fs ync or oddeven hsync ys c cvbs 0117-36.eps note : when unused, dvid (8:0), edvid, fb, ri, gi, bi inputs must be tied to ground (vssp) ; and cfc input must be tied to vddp. typical application diagram STV0117 44/45
pmplcc44.eps package mechanical data 44 pins - plastic chip carrier dimensions millimeters inches min. typ. max. min. typ. max. a 17.4 17.65 0.685 0.695 b 16.51 16.65 0.650 0.656 c 3.65 3.7 0.144 0.146 d 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 e 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 f 0.46 0.018 f1 0.71 0.028 g 0.101 0.004 m 1.16 0.046 m1 1.14 0.045 plcc44.tbl information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without noti ce. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1996 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system confo rms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. STV0117 45/45

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