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preliminary data sheet 1 LH7A400 preliminary data sheet 32-bit system-on-chip features ? 32-bit arm9tdmi? risc core ? 16 kb cache: 8 kb instruction and 8 kb data ? mmu (windows ce? enabled) ? up to 250 mhz; see table 1 for options 80 kb on-chip static ram programmable interrupt controller external bus interface ? up to 125 mhz; see table 1 for options ? asynchronous sram/rom/flash ? synchronous dram/flash ? pcmcia ? compactflash clock and power management ? 32.768 khz and 14. 7456 mhz oscillators ? programmable pll programmable lcd controller ? up to 1,024 768 resolution ? supports stn, color stn, ad-tft, hr-tft, tft ? up to 64 k-colors and 15 gray shades dma (10 channels) ?ac97 ?mmc ?usb usb device interface (usb 2.0, full speed) synchronous serial port (ssp) ? motorola spi? ? texas instruments ssi ? national microwire? three programmable timers three uarts ? classic irda (115 kbit/s) smart card interface (iso7816) two dc-to-dc converters multimediacard? interface ac97 codec interface smart battery monitor interface real time clock (rtc) up to 60 general purpose i/os watchdog timer jtag debug interface and boundary scan operating voltage ? 1.8 v core ? 3.3 v input/output 5 v tolerant digital inputs (except oscillator pins) ? oscillator pins p15, p16, r13, and t13 are 1.8 v 10 %. operating temperature: ? 40c to +85c 256-ball bga or 256-ball lfbga package description the LH7A400, powered by an arm922t, is a com- plete system-on-chip with a high level of integration to satisfy a wide range of requirements and expectations. this high degree of integration lowers overall system costs, reduces development cycle time and accelerates product introduction. table 1. LH7A400 versions part number core clock bus clock low power current by mo de (typ.) temp. range LH7A400n0f076b5 250 mhz/ 245 mhz 125 mhz run = 250 ma; halt = 50 ma; standby = 129 a 0c to +70c/ ? 40c to +85c LH7A400n0f000b3a 200 mhz/ 195 mhz 100 mhz run = 125 ma; halt: 25 ma; standby = 42 a 0c to +70c/ ? 40c to +85c LH7A400n0f000b5 200 mhz/ 195 mhz 100 mhz run = 125 ma; halt: 25 ma; standby = 42 a 0c to +70c/ ? 40c to +85c LH7A400n0g000b5 200 mhz/ 195 mhz 100 mhz run = 125 ma; halt: 25 ma; standby = 42 a 0c to +70c/ ? 40c to +85c
LH7A400 32-bit system-on-chip 2rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors table 2. ordering information type number package version name description LH7A400n0g000b5 bga256 plastic ball grid array package; 256 balls sot1018-1 LH7A400n0f000b3a lfbga256 plastic low profile fine -pitch ball grid array package; 256 balls sot1020-1 LH7A400n0f000b5 lfbga256 plastic low profile fine -pitch ball grid array package; 256 balls sot1020-1 LH7A400n0f076b5 lfbga256 plastic low profile fine -pitch ball grid array package; 256 balls sot1020-1
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 3 nxp semiconductors figure 1. LH7A400 block diagram LH7A400-1 oscillator, pll1 and pll2, power management, and reset control interrupt controller real time clock 14.7456 mhz 32.768 khz synchronous dynamic ram controller (sdmc) pcmcia/cf controller color lcd controller 80kb sram lcd ahb bus static (asynchronous) memory controller (smc) external bus interface arm922t advanced peripheral bus bridge dma controller advanced high-performance bus (ahb) advanced perpheral bus (apb) advanced lcd interface general purpose i/o (60) synchronous serial port timer (3) battery monitor interface usb device interface watchdog timer irda interface uart (3) multimediacard interface smart card interface (iso7816) audio codec interface advanced audio codec (ac97) dc to dc interface (2) LH7A400
LH7A400 32-bit system-on-chip 4rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors figure 2. pin configuration (bga256) figure 3. pin configuration (lfbga256) 002aad223 LH7A400 transparent top view t r n l p m k j h g f d b e c a 24681012 13 14 15 16 1357911 ball a1 index area 002aad224 LH7A400 transparent top view t r n l p m k j h g f d b e c a 24681012 13 14 15 16 1357911 ball a1 index area
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 5 nxp semiconductors table 3. functional pin list bga pin lfbga pin signal description reset state standby state output drive i/o notes g7 c10 vdd i/o ring power f1 f9 k7 f11 m1 f14 m5 g8 t6 h13 r14 j9 m14 k15 j11 l7 j12 n6 f13 n8 b14 n12 e10 n13 b8 p11 h7 b8 vss i/o ring ground g3 c6 k4 d5 n5 d13 p6 e8 t14 f7 r16 g13 n16 h9 k13 j14 h9 k7 c15 l8 a11 l10 e8 l12 a5 m11 f7 m14 e1 c4 vddc core power j4 d7 p3 d10 t8 f4 k9 f10 l13 j4 e15 j8 d12 k8 a7 l6 h5 g7 vssc core ground m3 h4 l9 h8 t10 l4 n15 l9 h12 n3 b15 n7 c9 n10 g6 r5
LH7A400 32-bit system-on-chip 6rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors r11 p12 vdda analog power for pll n12 m10 p12 r13 vssa analog ground for pll t11 n11 d3 e4 npor power on reset input no change i 3 h6 d1 nureset user reset; should be pulled high for normal or jtag operation. input no change i 3 d4 e2 wakeup wake up input no change i 3 e4 f2 npwrfl power fail signal input no change i 3 c2 d2 nextpwr external power input no change i 3 r13 r14 xtalin 14.7456 mhz crystal oscillator pins. an external clock source can be connected to xtalin leaving xtalout open. input no change i t13 r15 xtalout high high o p16 n14 xtal32in 32.768 khz real time cloc k crystal oscillator pins. an external clock source can be connected to xtal32in leaving xtal32out open. input no change i p15 m13 xtal32out output no change o p14 m12 clken external osc clock enable output low low 8 ma o j6 j5 pgmclk programmable clock (14.745 6 mhz max.) low low or high 8 ma o k11 p14 ncs0 async memory chip select 0 high no change 12 ma o k10 p16 ncs1 async memory chip select 1 high no change 12 ma o p13 n15 ncs2 async memory chip select 2 high no change 12 ma o m12 n16 ncs3/ nmmspics async memory chip select 3 multimediacard spi mode chip select high: ncs3 no change 12 ma o l12 l11 d0 data bus low low 12 ma i/o m15 l13 d1 n13 l14 d2 l16 k11 d3 l15 l16 d4 l14 k14 d5 h11 j15 d6 k12 j12 d7 j15 j10 d8 j13 h16 d9 j10 h14 d10 h15 h11 d11 h13 g16 d12 g15 g9 d13 g11 g14 d14 g12 g12 d15 f15 f15 d16 f12 e15 d17 e14 d16 d18 d16 f12 d19 h10 e13 d20 d14 d14 d21 f10 e12 d22 a16 b16 d23 a14 d12 d24 b13 a16 d25 table 3. functional pin list (cont?d) bga pin lfbga pin signal description reset state standby state output drive i/o notes
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 7 nxp semiconductors c13 b13 d26 data bus low low 12 ma i/o e12 b14 d27 g10 c12 d28 b12 a14 d29 b11 b12 d30 d11 a12 d31 m16 m15 a0/nwe1 asynchronous address bus asynchronous memory write byte enable 1 high: nwe1 high 12 ma o n14 m16 a1/nwe2 asynchronous address bus asynchronous memory write byte enable 2 high: nwe2 high 12 ma o m13 l15 a2/sa0 asynchronous address bus synchronous address bus low low 12 ma o k16 k12 a3/sa1 k15 k13 a4/sa2 k14 k16 a5/sa3 j8 j13 a6/sa4 j16 j11 a7/sa5 j14 j16 a8/sa6 j9 h15 a9/sa7 h16 h10 a10/sa8 h14 h12 a11/sa9 g16 g15 a12/sa10 g14 g10 a13/sa11 g13 g11 a14/sa12 f16 f16 a15/sa13 f14 e16 a16/sb0 async address bus sync device bank address 0 low low 12 ma o e16 f13 a17/sb1 async address bus sync device bank address 1 low low 12 ma o e13 e14 a18 asynchronous address bus low low 12 ma o f11 d15 a19 d15 c16 a20 c16 c15 a21 b16 c14 a22 a15 b15 a23 a13 e11 a24 g8 d8 a25/scio async memory address bus smart card interface i/o (data) low: a25 low 12 ma i/o f8 b7 a26/scclk async memory address bus smart card interface clock low: a26 low 12 ma i/o a8 a7 a27/scrst async memory address bus smart card interface reset low: a27 low 12 ma o d8 c8 noe async memory output enable high no change 12 ma o c8 f8 nwe0 async memory write byte enable 0 high no change 12 ma o d10 d9 nwe3 async memory write byte enable 3 high no change 8 ma o b10 e9 cs6/scke1_2 async memory chip select 6 sync memory clock enable 1 or 2 low: cs6 no change 12 ma o c10 a10 cs7/scke0 async memory chip select 7 sync memory clock enable 0 low: cs7 no change 12 ma o g9 a11 scke3 sync memory clock enable 3 low low 12 ma o a10 b10 sclk sync memory clock low no change i/o 2 c14 c13 nscs0 sync memory chip select 0 high no change 12 ma o table 3. functional pin list (cont?d) bga pin lfbga pin signal description reset state standby state output drive i/o notes
LH7A400 32-bit system-on-chip 8rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors d13 a15 nscs1 sync memory chip select 1 high no change 12 ma o e11 d11 nscs2 sync memory chip select 2 high no change 12 ma o a12 e10 nscs3 sync memory chip select 3 high no change 12 ma o c12 a13 nswe sync memory write enable high no change 12 ma o c11 b11 ncas sync memory column address strobe signal high no change 12 ma o f9 c11 nras sync memory row address strobe signal high no change 12 ma o a9 c9 dqm0 sync memory data mask 0 high no change 12 ma o b9 a9 dqm1 sync memory data mask 1 high no change 12 ma o d9 b9 dqm2 sync memory data mask 2 high no change 12 ma o e9 a8 dqm3 sync memory data mask 3 high no change 12 ma o j5 k1 pa0/lcdvd16 gpio port a lcd data bit 16. this clcdc output signal is always low. input: pa0 no change 8 ma i/o k1 k2 pa1/lcdvd17 gpio port a lcd data bit 17. this clcdc output signal is always low. input: pa1 no change 8 ma i/o k2 k3 pa2 gpio port a input no change 8 ma i/o k3 k4 pa3 i/o k5 k6 pa4 i/o l1 k5 pa5 i/o l2 l1 pa6 i/o l3 l2 pa7 i/o l4 l3 pb0/ uartrx1 gpio port b uart1 receive data input input: pb0 no change 8 ma i/o l5 m1 pb1/uarttx3 gpio port b uart3 transmit data out input: pb1 low if pinmux: uart3con = 1 (bit 3); otherwise no change 8 ma i/o l7 m2 pb2/ uartrx3 gpio port b uart3 receive data in input: pb2 no change 8 ma i/o m2 m3 pb3/ uartcts3 gpio port b uart3 clear to send input: pb3 no change 8 ma i/o m4 l5 pb4/ uartdcd3 gpio port b uart3 data carrier detect input: pb4 no change 8 ma i/o n1 n1 pb5/ uartdsr3 gpio port b uart3 data set ready input: pb5 no change 8 ma i/o n2 n2 pb6/swid/ smbd gpio port b single wire data smart battery data input: pb6 no change 8 ma i/o n3 m4 pb7/ smbclk gpio port b smart battery clock input: pb7 no change 8 ma i/o 7 p1 p1 pc0/ uarttx1 gpio port c uart1 transmit data output low: pc0 no change 12 ma i/o p2 p2 pc1/lcdps gpio port c hr-tft power save low: pc1 no change 12 ma i/o r1 r1 pc2/ lcdvdden gpio port c hr-tft power sequence control low: pc2 no change 12 ma i/o k6 m5 pc3/lcdrev gpio port c hr-tft gray scale voltage reverse low: pc3 no change 12 ma i/o l8 p3 pc4/ lcdsps gpio port c hr-tft reset row driver counter low: pc4 no change 12 ma i/o table 3. functional pin list (cont?d) bga pin lfbga pin signal description reset state standby state output drive i/o notes
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 9 nxp semiconductors t1 n4 pc5/ lcdcls gpio port c hr-tft row driver clock low: pc5 no change 12 ma i/o t2 r2 pc6/lcdhr- lp gpio port c lcd latch pulse low: pc6 no change 12 ma i/o r2 n5 pc7/ lcdspl gpio port c lcd start pulse left low: pc7 no change 12 ma i/o m11 m9 pd0/lcdvd8 gpio port d lcd video data bus low: pd0 low if pinmux: pdocon = 1 (bit 1); otherwise, no change 12 ma i/o l11 k10 pd1/lcdvd9 low: pd1 i/o k8 p10 pd2/lcdvd10 low: pd2 i/o n11 t11 pd3/lcdvd11 low: pd3 i/o r9 t12 pd4/lcdvd12 low: pd4 i/o t9 r11 pd5/lcdvd13 low: pd5 i/o p10 r12 pd6/lcdvd14 low: pd6 i/o r10 t13 pd7/lcdvd15 low: pd7 i/o l10 t9 pe0/lcdvd4 gpio port e lcd video data bus input: pe0 low if pinmux: pdocon or peocon = 1 (bits [1:0]); otherwise no change 12 ma i/o n10 k9 pe1/lcdvd5 input: pe1 i/o m9 t10 pe2/lcdvd6 input: pe2 i/o m10 r10 pe3/lcdvd7 input: pe3 i/o a6 a5 pf0/int0 gpio port f external fiq interrupt. interrupts can be level or edge triggered and are in ternally debounced. input: pf0 no change 8 ma i/o 3 b6 b4 pf1/int1 gpio port f external irq interrupts. interrupts can be level or edge triggered and are in ternally debounced. input: pf1 no change 8 ma i/o 3 c6 e7 pf2/int2 input: pf2 no change 8 ma i/o 3 h8 b3 pf3/int3 gpio port f external irq interrupt. interrupts can be level or edge triggered and are in ternally debounced. input: pf3 no change 8 ma i/o 3 b5 c5 pf4/int4/ scvccen gpio port f external irq interrupt. interrupts can be level or edge triggered and are in ternally debounced. smart card supply voltage enable input: pf4 low if sci is enabled; otherwise no change 8 ma i/o 3 d6 d6 pf5/int5/ scdetect gpio port f external irq interrupt. interrupts can be level or edge triggered and are in ternally debounced. smart card detection input: pf5 no change 8 ma i/o 3 e6 a4 pf6/int6/ pcrdy1 gpio port f external irq interrupt. interrupts can be level or edge triggered and are in ternally debounced. ready for card 1 for pc card (pcmcia or cf) in single or dual card mode input: pf6 no change 8 ma i/o 3 c5 a3 pf7/int7/ pcrdy2 gpio port f external irq interrupt. interrupts can be level or edge triggered and are in ternally debounced. ready for card 2 for pc card (pcmcia or cf) in single or dual card mode input: pf7 no change 8 ma i/o 3 r3 m6 pg0/npcoe gpio port g output enable for pc card (pcmcia or cf) in single or dual card mode low: pg0 no change 8 ma i/o t3 t1 pg1/npcwe gpio port g write enable for pc card (pcmcia or cf) in sin- gle or dual card mode low: pg1 no change 8 ma i/o table 3. functional pin list (cont?d) bga pin lfbga pin signal description reset state standby state output drive i/o notes
LH7A400 32-bit system-on-chip 10 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors l6 p4 pg2/ npcior gpio port g i/o read strobe for pc card (pcmcia or cf) in single or dual card mode low: pg2 no change 8 ma i/o m6 r3 pg3/ npciow gpio port g i/o write strobe for pc card (pcmcia or cf) in single or dual card mode low: pg3 no change 8 ma i/o n6 t2 pg4/npcreg gpio port g register memory access for pc card (pcmcia or cf) in single or dual card mode low: pg4 no change 8 ma i/o m7 p5 pg5/npcce1 gpio port g card enable 1 for pc card (pcmcia or cf) in single or dual card mode. this signal and npcce2 are used by the pc card for decoding low and high byte accesses. low: pg5 no change 8 ma i/o m8 r4 pg6/npcce2 gpio port g card enable 2 for pc card (pcmcia or cf) in single or dual card mode. this signal and npcce1 are used by the pc card for decoding low and high byte accesses. low: pg6 no change 8 ma i/o n4 t3 pg7/pcdir gpio port g direction for pc card (pcmcia or cf) in single or dual card mode low: pg7 no change 8 ma i/o p4 p6 ph0/ pcreset1 gpio port h reset card 1 for pc card (pcmcia or cf) in sin- gle or dual card mode input: ph0 no change 8 ma i/o r4 t4 ph1/cfa8/ pcreset2 gpio port h address bit 8 for pc card (cf) in single card mode reset card 2 for pc card (pcmcia or cf) in dual card mode input: ph1 no change 8 ma i/o t4 m7 ph2/ npcslote1 gpio port h enable card 1 for pc card (pcmcia or cf) in sin- gle or dual card mode. this signal is used for gating other control signals to the appropriate pc card. input: ph2 no change 8 ma i/o n7 t5 ph3/cfa9/ pcmciaa25/ npcslote2 gpio port h address bit 9 for pc card (c f) in single card mode address bit 25 for pc card (pcmcia) in single card mode enable card 2 for pc card (pcmcia or cf) in dual card mode. this signal is used for gating other control signals to the appropriate pc card. input: ph3 no change 8 ma i/o p8 r6 ph4/ npcwait1 gpio port h wait signal for card 1 for pc card (pcmcia or cf) in single or dual card mode input: ph4 no change 8 ma i/o p5 r7 ph5/cfa10/ pcmciaa24/ npcwait2 gpio port h address bit 10 for pc card (cf) in single card mode address bit 24 for pc card (pcmcia) in single card mode wait signal for card 2 for pc card (pcmcia or f) in dual card mode input: ph5 no change 8 ma i/o r5 p7 ph6/ nac97reset gpio port h audio codec (ac97) reset input: ph6 no change 8 ma i/o t5 t6 ph7/ npcstatre gpio port h status read enable for pc card (pcmcia or f) in single or dual card mode input: ph7 no change 8 ma i/o r6 t7 lcdfp lcd frame synchronization pulse low low 12 ma o r8 r9 lcdlp lcd line synchroni zation pulse low low 12 ma o table 3. functional pin list (cont?d) bga pin lfbga pin signal description reset state standby state output drive i/o notes
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 11 nxp semiconductors p9 p9 lcdenab/ lcdm lcd tft data enable lcd stn ac bias low: lcdenab low 12 ma o n9 n9 lcddclk lcd data clock low low 12 ma o p7 m8 lcdvd0 lcd video data bus low low 12 ma o r7 p8 lcdvd1 o t7 r8 lcdvd2 o n8 t8 lcdvd3 o t15 t16 usbdp usb data positive (differential pair) input no change i/o 10 t16 r16 usbdn usb data negative (differential pair) input no change i/o 10 e7 c7 npwme0 dc-dc converter pulse width modulator 0 enable input no change i d7 a6 npwme1 dc-dc converter pulse width modulator 1 enable input no change i c7 b6 pwm0 dc-dc converter pulse width modulator 0 output during normal operation and polarity selection input at reset input no change 8 ma i/o b7 b5 pwm1 dc-dc converter pulse width modulator 1 output during normal operation and polarity selection input at reset input no change 8 ma i/o c4 a2 acbitclk audio codec (ac97) clock audio codec (aci) clock input no change 8 ma i/o d5 a1 acout audio codec (ac97) output audio codec (aci) output low no change 8 ma o b4 b2 acsync audio codec (ac97) synchronization audio codec (aci) synchronization low no change 8 ma o a4 e6 acin audio codec (ac97) input audio codec (aci) input input no change i a3 c3 mmcclk/ mmspiclk multimediacard clock (20 mhz max.) multimediacard spi mode clock low: mmcclk low 8 ma o b3 b1 mmccmd/ mmspidin multimediacard command multimediacard spi mode data input input: mmccmd input 8 ma i/o a2 d4 mmcdata/ mmspidout multimediacard data multimediacard spi mode data output input: mmcdata input 8 ma i/o e2 e1 uartcts2 uart2 clear to send signal. this pin is an output for jtag boundary scan only. input no change i e3 f3 uartdcd2 uart2 data carrier detect signal. this pin is output for jtag boundary scan only. input no change i e5 g4 uartdsr2 uart2 data set ready signal input no change i f2 g5 uartirtx1 irda transmit low no change 8 ma o f3 g6 uartirrx1 irda receive. this pin is an output for jtag boundary scan only. input no change i f4 f1 uarttx2 uart2 transmit data output high no change 8 ma o j7 g3 uartrx2 uart2 receive data input. this pin is an output for jtag boundary scan only. input no change i h4 j3 sspclk synchronous serial port clock low no change 8 ma o j1 j6 ssprx synchronous serial port receive input no change i j2 j7 ssptx synchronous serial port transmit low low 8 ma i/o j3 j2 sspfrm/ nsspfrm synchronous serial port frame sync input input 8 ma i/o table 3. functional pin list (cont?d) bga pin lfbga pin signal description reset state standby state output drive i/o notes
LH7A400 32-bit system-on-chip 12 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors 1. signals beginning with ?n? are active low. 2. the sclk pin can source up to 12 ma and si nk up to 20 ma. see ? dc characteristics?. 3. schmitt trigger input; see ?d c specifications?, page 31 for triggers points and hysteresis. 4. input only for jtag boundary scan mode. 5. output only for jtag boundary scan mode. 6. the internal pullup and pull-down resist ance on all digital i/o pins is 50 k ? 7. when used as smbclk, this pin must have a resistor. 8. the reset state is defined as the state during power-on reset. 9. the standby state is defined as the state w hen the device is in standby. during this state, i/o cells are forced to input (input ), output driving low (low), output driving high (high), or their current state is preserved (no change). in some case, func tion selection has an overall effect on the standby state. 10. all unused usb device pins with a differential pair must be pulled to ground with a 15 k ? resistor. f6 g2 col0 keyboard interface high high 8 ma o f5 g1 col1 g1 h3 col2 g2 h5 col3 g4 h6 col4 g5 h7 col5 h1 h2 col6 h2 h1 col7 h3 j1 tbuz timer buzzer (254 khz max.) low low 8 ma o c3 f5 medchg boot device media change. used with width0 and width1 to specify boot memory device. input no change i 3 p11 t14 width0 external memory width pins. also, used with medchg to specify the boot memory device size. the pins must be pulled high with a 33 k ? resistor. input no change i 3 r12 t15 width1 d1 e3 batok battery ok input no change i 3 d2 f6 nbatchg battery change input no change i 3 a1 e5 tdi jtag data in. this signal is internally pulled-up t o vdd. input no change i 4 b1 c2 tck jtag clock. this signal should be externally pulled-up to vdd with a 33 k ? resistor. input no change i 3 b2 d3 tdo jtag data out. this signal should be externally pulled up to vdd with a 33 k ? resistor. high-z no change 4 ma o c1 c1 tms jtag test mode select. th is signal is internally pulled-up to vdd. input no change i 4 t12 p15 ntest0 test pin 0. internally pulled up to vdd. for normal mode, leave open. for jtag mode, tie to gnd. see table 4. input no change i 4 r15 p13 ntest1 test pin 1. internally pulled up to vdd. for normal and jtag mode, leave open. see table 4. table 3. functional pin list (cont?d) bga pin lfbga pin signal description reset state standby state output drive i/o notes table 4. ntest pin function mode ntest0 ntest1 nureset jtag 0 1 1 normal 1 1 x
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 13 nxp semiconductors notes: 1. the intensity bit is identical ly generated for all three colors. 2. mu = monochrome upper 3. cu = color upper 4. cl = color lower table 5. lcd data multiplexing bga pin lfbga pin lcd data signal stn tft ad-tft/ hr-tft mono 4-bit mono 8-bit color single panel dual panel single panel dual panel single panel dual panel k1 k2 lcdvd17 low j5 k1 lcdvd16 low r10 t13 lcdvd15 mlstn7 clstn7 intensity intensity p10 r12 lcdvd14 mlstn6 clstn6 blue4 blue4 t9 r11 lcdvd13 mlstn5 clstn5 blue3 blue3 r9 t12 lcdvd12 mlstn4 clstn4 blue2 blue2 n11 t11 lcdvd11 mlstn3 clstn3 blue1 blue1 k8 p10 lcdvd10 mlstn2 clstn2 blue0 blue0 l11 k10 lcdvd9 mlstn1 clstn1 green4 green4 m11 m9 lcdvd8 mlstn0 clstn0 green3 green3 m10 r10 lcdvd7 mlstn3 mustn7 mustn7 custn7 custn7 green2 green2 m9 t10 lcdvd6 mlstn2 mustn6 mustn6 custn6 custn6 green1 green1 n10 k9 lcdvd5 mlstn1 mustn5 mustn5 custn5 custn5 green0 green0 l10 t9 lcdvd4 mlstn0 mustn4 mustn4 custn4 custn4 red4 red4 n8 t8 lcdvd3 mustn3 mustn3 mustn3 mustn3 custn3 custn3 red3 red3 t7 r8 lcdvd2 mustn2 mustn2 mustn2 mustn2 custn2 custn2 red2 red2 r7 p8 lcdvd1 mustn1 mustn1 mustn1 mustn1 custn1 custn1 red1 red1 p7 m8 lcdvd0 mustn0 mustn0 mustn0 mustn0 custn0 custn0 red0 red0
LH7A400 32-bit system-on-chip 14 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors table 6. 256-ball bga package numerical pin list bga pin signal a1 tdi a2 mmcdata/mmspidout a3 mmcclk/mmspiclk a4 acin a5 vss a6 pf0/int0 a7 vddc a8 a27/scrst a9 dqm0 a10 sclk a11 vss a12 nscs3 a13 a24 a14 d24 a15 a23 a16 d23 b1 tck b2 tdo b3 mmccmd/mmspidin b4 acsync b5 pf4/int4/scvccen b6 pf1/int1 b7 pwm1 b8 vdd b9 dqm1 b10 cs6/scke1_2 b11 d30 b12 d29 b13 d25 b14 vdd b15 vssc b16 a22 c1 tms c2 nextpwr c3 medchg c4 acbitclk c5 pf7/int7/pcrdy2 c6 pf2/int2 c7 pwm0 c8 nwe0 c9 vssc c10 cs7/scke0 c11 ncas c12 nswe c13 d26 c14 nscs0 c15 vss c16 a21 d1 batok d2 nbatchg d3 npor d4 wakeup d5 acout d6 pf5/int5/scdetect d7 npwme1 d8 noe d9 dqm2 d10 nwe3 d11 d31 d12 vddc d13 nscs1 d14 d21 d15 a20 d16 d19 e1 vddc e2 uartcts2 e3 uartdcd2 e4 npwrfl e5 uartdsr2 e6 pf6/int6/pcrdy1 e7 npwme0 e8 vss e9 dqm3 e10 vdd e11 nscs2 e12 d27 e13 a18 e14 d18 e15 vddc e16 a17/sb1 f1 vdd f2 uartirtx1 f3 uartirrx1 f4 uarttx2 f5 col1 f6 col0 f7 vss f8 a26/scclk f9 nras f10 d22 table 6. 256-ball bga package numerical pin list (cont?d) bga pin signal
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 15 nxp semiconductors f11 a19 f12 d17 f13 vdd f14 a16/sb0 f15 d16 f16 a15/sa13 g1 col2 g2 col3 g3 vss g4 col4 g5 col5 g6 vssc g7 vdd g8 a25/scio g9 scke3 g10 d28 g11 d14 g12 d15 g13 a14/sa12 g14 a13/sa11 g15 d13 g16 a12/sa10 h1 col6 h2 col7 h3 tbuz h4 sspclk h5 vssc h6 nureset h7 vss h8 pf3/int3 h9 vss h10 d20 h11 d6 h12 vssc h13 d12 h14 a11/sa9 h15 d11 h16 a10/sa8 j1 ssprx j2 ssptx j3 sspfrm/nsspfrm j4 vddc j5 pa0/lcdvd16 j6 pgmclk j7 uartrx2 table 6. 256-ball bga package numerical pin list (cont?d) bga pin signal j8 a6/sa4 j9 a9/sa7 j10 d10 j11 vdd j12 vdd j13 d9 j14 a8/sa6 j15 d8 j16 a7/sa5 k1 pa1/lcdvd17 k2 pa2 k3 pa3 k4 vss k5 pa4 k6 pc3/lcdrev k7 vdd k8 pd2/lcdvd10 k9 vddc k10 ncs1 k11 ncs0 k12 d7 k13 vss k14 a5/sa3 k15 a4/sa2 k16 a3/sa1 l1 pa5 l2 pa6 l3 pa7 l4 pb0/uartrx1 l5 pb1/uarttx3 l6 pg2/npcior l7 pb2/uartrx3 l8 pc4/lcdsps l9 vssc l10 pe0/lcdvd4 l11 pd1/lcdvd9 l12 d0 l13 vddc l14 d5 l15 d4 l16 d3 m1 vdd m2 pb3/uartcts3 m3 vssc table 6. 256-ball bga package numerical pin list (cont?d) bga pin signal
LH7A400 32-bit system-on-chip 16 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors m4 pb4/uartdcd3 m5 vdd m6 pg3/npciow m7 pg5/npcce1 m8 pg6/npcce2 m9 pe2/lcdvd6 m10 pe3/lcdvd7 m11 pd0/lcdvd8 m12 ncs3/nmmspics m13 a2/sa0 m14 vdd m15 d1 m16 a0/nwe1 n1 pb5/uartdsr3 n2 pb6/swid/smbd n3 pb7/smbclk n4 pg7/pcdir n5 vss n6 pg4/npcreg n7 ph3/cfa9/pcmciaa25/npcslote2 n8 lcdvd3 n9 lcddclk n10 pe1/lcdvd5 n11 pd3/lcdvd11 n12 vdda n13 d2 n14 a1/nwe2 n15 vssc n16 vss p1 pc0/uarttx1 p2 pc1/lcdps p3 vddc p4 ph0/pcreset1 p5 ph5/cfa10/pcmciaa24/npcwait2 p6 vss p7 lcdvd0 p8 ph4/npcwait1 p9 lcdenab/lcdm p10 pd6/lcdvd14 p11 width0 p12 vssa p13 ncs2 p14 clken p15 xtal32out table 6. 256-ball bga package numerical pin list (cont?d) bga pin signal p16 xtal32in r1 pc2/lcdvdden r2 pc7/lcdspl r3 pg0/npcoe r4 ph1/cfa8/pcreset2 r5 ph6/nac97reset r6 lcdfp r7 lcdvd1 r8 lcdlp r9 pd4/lcdvd12 r10 pd7/lcdvd15 r11 vdda r12 width1 r13 xtalin r14 vdd r15 ntest1 r16 vss t1 pc5/lcdcls t2 pc6/lcdhrlp t3 pg1/npcwe t4 ph2/npcslote1 t5 ph7/npcstatre t6 vdd t7 lcdvd2 t8 vddc t9 pd5/lcdvd13 t10 vssc t11 vssa t12 ntest0 t13 xtalout t14 vss t15 usbdp t16 usbdn table 6. 256-ball bga package numerical pin list (cont?d) bga pin signal
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 17 nxp semiconductors table 7. 256-ball lfbga package numerical pin list lfbga pin signal a1 acout a2 acbitclk a3 pf7/int7/pcrdy2 a4 pf6/int6/pcrdy1 a5 pf0/int0 a6 npwme1 a7 a27/scrst a8 dqm3 a9 dqm1 a10 cs7/scke0 a11 scke3 a12 d31 a13 nswe a14 d29 a15 nscs1 a16 d25 b1 mmccmd/mmspidin b2 acsync b3 pf3/int3 b4 pf1/int1 b5 pwm1 b6 pwm0 b7 a26/scclk b8 vss b9 dqm2 b10 sclk b11 ncas b12 d30 b13 d26 b14 d27 b15 a23 b16 d23 c1 tms c2 tck c3 mmcclk/mmspiclk c4 vddc c5 pf4/int4/scvccen c6 vss c7 npwme0 c8 noe c9 dqm0 c10 vdd c11 nras c12 d28 c13 nscs0 c14 a22 c15 a21 c16 a20 d1 nureset d2 nextpwr d3 tdo d4 mmcdata/mmspidout d5 vss d6 pf5/int5/scdetect d7 vddc d8 a25/scio d9 nwe3 d10 vddc d11 nscs2 d12 d24 d13 vss d14 d21 d15 a19 d16 d18 e1 uartcts2 e2 wakeup e3 batok e4 npor e5 tdi e6 acin e7 pf2/int2 e8 vss e9 cs6/scke1_2 e10 nscs3 e11 a24 e12 d22 e13 d20 e14 a18 e15 d17 e16 a16/sb0 f1 uarttx2 f2 npwrfl f3 uartdcd2 f4 vddc f5 medchg f6 nbatchg f7 vss f8 nwe0 f9 vdd table 7. 256-ball lfbga package numerical pin list lfbga pin signal
LH7A400 32-bit system-on-chip 18 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors f10 vddc f11 vdd f12 d19 f13 a17/sb1 f14 vdd f15 d16 f16 a15/sa13 g1 col1 g2 col0 g3 uartrx2 g4 uartdsr2 g5 uartirtx1 g6 uartirrx1 g7 vssc g8 vdd g9 d13 g10 a13/sa11 g11 a14/sa12 g12 d15 g13 vss g14 d14 g15 a12/sa10 g16 d12 h1 col7 h2 col6 h3 col2 h4 vssc h5 col3 h6 col4 h7 col5 h8 vssc h9 vss h10 a10/sa8 h11 d11 h12 a11/sa9 h13 vdd h14 d10 h15 a9/sa7 h16 d9 j1 tbuz j2 sspfrm/nsspfrm j3 sspclk j4 vddc j5 pgmclk table 7. 256-ball lfbga package numerical pin list lfbga pin signal j6 ssprx j7 ssptx j8 vddc j9 vdd j10 d8 j11 a7/sa5 j12 d7 j13 a6/sa4 j14 vss j15 d6 j16 a8/sa6 k1 pa0/lcdvd16 k2 pa1/lcdvd17 k3 pa2 k4 pa3 k5 pa5 k6 pa4 k7 vss k8 vddc k9 pe1/lcdvd5 k10 pd1/lcdvd9 k11 d3 k12 a3/sa1 k13 a4/sa2 k14 d5 k15 vdd k16 a5/sa3 l1 pa6 l2 pa7 l3 pb0/uartrx1 l4 vssc l5 pb4/uartdcd3 l6 vddc l7 vdd l8 vss l9 vssc l10 vss l11 d0 l12 vss l13 d1 l14 d2 l15 a2/sa0 l16 d4 m1 pb1/uarttx3 table 7. 256-ball lfbga package numerical pin list lfbga pin signal
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 19 nxp semiconductors m2 pb2/uartrx3 m3 pb3/uartcts3 m4 pb7/smbclk m5 pc3/lcdrev m6 pg0/npcoe m7 ph2/npcslote1 m8 lcdvd0 m9 pd0/lcdvd8 m10 vdda m11 vss m12 clken m13 xtal32out m14 vss m15 a0/nwe1 m16 a1/nwe2 n1 pb5/uartdsr3 n2 pb6/swid/smbd n3 vssc n4 pc5/lcdcls n5 pc7/lcdspl n6 vdd n7 vssc n8 vdd n9 lcddclk n10 vssc n11 vssa n12 vdd n13 vdd n14 xtal32in n15 ncs2 n16 ncs3/nmmspics p1 pc0/uarttx1 p2 pc1/lcdps p3 pc4/lcdsps p4 pg2/npcior p5 pg5/npcce1 p6 ph0/pcreset1 p7 ph6/ac97reset p8 lcdvd1 p9 lcdenab/lcdm p10 pd2/lcdvd10 p11 vdd p12 vdda p13 ntest1 table 7. 256-ball lfbga package numerical pin list lfbga pin signal p14 ncs0 p15 ntest0 p16 ncs1 r1 pc2/lcdvdden r2 pc6/lcdhrlp r3 pg3/npciow r4 pg6/npcce2 r5 vssc r6 ph4/npcwait1 r7 ph5/cfa10/pcmc iaa24/npcwait2 r8 lcdvd2 r9 lcdlp r10 pe3/lcdvd7 r11 pd5/lcdvd13 r12 pd6/lcdvd14 r13 vssa r14 xtalin r15 xtalout r16 usbdn t1 pg1/npcwe t2 pg4/npcreg t3 pg7/pcdir t4 ph1/cfa8/pcreset2 t5 ph3/cfa9/pcmci aa25/npcslote2 t6 ph7/npcstatre t7 lcdfp t8 lcdvd3 t9 pe0/lcdvd4 t10 pe2/lcdvd6 t11 pd3/lcdvd11 t12 pd4/lcdvd12 t13 pd7/lcdvd15 t14 width0 t15 width1 t16 usbdp table 7. 256-ball lfbga package numerical pin list lfbga pin signal
LH7A400 32-bit system-on-chip 20 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors system descriptions arm922t processor the LH7A400 microcontroller features the arm922t cached core with an advanced high perfor- mance bus (ahb) interface. the processor is a mem- ber of the arm9t family of processors. for more information, see the arm document, ?arm922t tech- nical reference manual?, available on arm?s website at www.arm.com. clock and state controller the clocking scheme in the LH7A400 is based around two primary oscillator inputs. these are the 14.7456 mhz input crystal and the 32.768 khz real time clock oscillator. see figure 5. the 14.7456 mhz oscil- lator is used to generate the main system clock domains for the LH7A400, where as the 32.768 khz is used for controlling the po wer down operations and real time clock peripheral. the clock and state control- ler provides the clock gating and frequency division necessary, and then supplies the clocks to the proces- sor and to the rest of the system. the amount of clock gating that actually takes place is dependent on the current power saving mode selected. the 32.768 khz clock provides the source for the real time clock tree and powe r-down logic.this clock is used for the power state control in the design and is the only clock in the LH7A400 that runs permanently. the 32.768 khz clock is divided down to 1 hz using a ripple divider to save power. this generated 1 hz clock is used in the real time clock counter. the 14.7456 mhz source is used to generate the main system clocks for the LH7A400. it is the source for pll1 and pll2, it acts as the primary clock to the peripherals and is the source clock to the programma- ble clock (pgm) divider. pll1 provides the main clock tree for the chip, it generates the following clocks: fclk, hclk and pclk. fclk is the clock that drives the arm922t core. hclk is the main bus (ahb) clock, as such it clocks all memory interfaces, bus arbitrators and the ahb peripherals. hclk is generated by dividing fclk by 1, 2, 3, or 4. hclk can be gated by the system to enable low power operation. pclk is the peripheral bus (apb) clock. it is generated by dividing hclk by either 2, 4, or 8. pll2 is used to generate a fixed frequency of 48 mhz for the usb peripheral. figure 4. application diagram codec battery dc to dc voltage generation circuitry multimedia card touch screen contr. mmc sci pcmcia compact flash uart usb sdram sram rom flash dma ac97 stn/tft/ ad-tft ir gpio ssp uart LH7A400 pc card LH7A400-3 1 2 3 4 5 6 7 8 9 * 0 # bmi smart card
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 21 nxp semiconductors power modes the LH7A400 has three operational states: run, halt, and standby. in run mode, all clocks are hard- ware-enabled and the processor is clocked. halt mode stops the processor clock while waiting for an event such as a key press, but the device continues to func- tion. finally, standby equates to the computer being switched ?off?, i.e. no display (lcd disabled) and the main oscillator is shut down . the 32.768 khz oscillator operates in all three modes. reset modes there are three external signals that can generate resets to the LH7A400; these are npor (power on reset), npwrfl (power fa ilure) and nureset (user reset). if any of these are active, a system reset is gen- erated internally. a npor reset performs a full system reset. the npwrfl and nureset resets will perform a full system reset except for the sdram refresh con- trol, sdram global config uration, sdram device configuration and the rtc peripheral registers. the sdram controller will issue a self-refresh command to external sdram before the system enters this reset (the npwrfl and nureset resets only, not so for the npor reset). this allows th e system to maintain its real time clock and sdram contents. on coming out of reset, the chip enters standby mode. once in run mode the pwrsr register can be interrogated to deter- mine the nature of the reset, and the trigger source, after which software can then take appropriate actions. data paths the data paths in the LH7A400 are: the amba ahb bus the amba apb bus the external bus interface the lcd ahb bus the dma busses. amba ahb bus the advanced microprocessor bus architecture advanced high-performance bus (amba ahb) bus is a high speed 32-bit-wide data bus. the amba ahb is for high-performance, high clock frequency system modules. peripherals that have high bandwidth requirements are connected to the LH7A400 core processor using the ahb bus. these include the external and internal memory interfaces, the lcd registers, palette ram and the bridge to the advanced peripheral bus (apb) interface. the apb bridge tr ansparently converts the ahb access into the slow er speed apb accesses. all of the control registers for the apb peripherals are pro- grammed using the ahb - apb bridge interface. the main ahb data and address lines are configured using a multiplexed bus. this removes the need for tri-state buffers and bus holders, and simplifies bus arbitration. figure 5. clock and state controller block diagram 14.7456 mhz main osc. hclk 32.768 khz rtc osc. /2, /4, /8 pclks fclk hclk (to processor core) LH7A400-4 state controller divide register
LH7A400 32-bit system-on-chip 22 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors amba apb bus the amba apb bus is a lower-speed 32-bit-wide peripheral data bus. the speed of this bus is selectable to be a divide-by-2, divide-by-4 or divide-by-8 of the speed of the ahb bus. external bus interface the external bus interface (ebi) provides a 32-bit wide, high speed gateway to external memory devices. the memory devices supported include: asynchronous ram/rom/flash synchronous dram/flash pcmcia interfaces compactflash interfaces. the ebi can be controlled by either the asynchro- nous memory controller or synchronous memory con- troller. there is an arbiter on the ebi input, with priority given to the synchronous memory controller interface. lcd ahb bus the lcd controller has its own local memory bus that connects it to the system?s embedded memory and external sdram. the function of this local data bus is to allow the lcd controller to perform its video refresh function without congesting the ahb bus. this leads to better system performance and lower power consump- tion. there is an arbiter on both the embedded memory and the synchronous memory controller. in both cases the lcd bus is given priority. dma buses the LH7A400 has a dma system that connects the higher speed/higher data volume apb peripherals (mmc, usb and ac97) to the ahb bus. this enables the efficient transfer of data between these peripherals and external memory without the intervention of the arm922t core. the dma engine does not support memory to memory transfers. memory map the LH7A400 system has a 32-bit-wide address bus. this allows it to address up to 4gb of memory. this memory space is subdivided into a number of memory banks; see figure 6. four of these banks (each of 256mb) are allocated to the synchronous memory con- troller. eight of the banks (again, each 256mb) are allo- cated to the asynchronous memory controller. two of these eight banks are designed for pcmcia systems. part of the remaining memory space is allocated to the embedded sram, and to the control registers of the ahb and apb. the rest is unused. the LH7A400 can boot from either synchronous or asynchronous rom/flash. the selection is determined by the value of the medchg pin at power on reset as shown in table 8. when booting from synchronous memory, then synchronous bank 4 (nscs3) is mapped into memory location zero. when booting from asyn- chronous memory, asynchronous memory bank 0 (nscs0) is mapped into memory location zero. figure 6 shows the memory map of the LH7A400 system for the two boot modes. once the LH7A400 has booted, the boot code can configure the arm922t mmu to remap the low mem- ory space to a location in ra m. this allows the user to set the interrupt vector table. interrupt controller the LH7A400 interrupt controller is designed to con- trol the interrupts from 28 different sources. four inter- rupt sources are mapped to the fiq input of the arm922t and 24 are mapped to the irq input. fiqs have a higher priority than the irqs. if two interrupts with the same priority become active at the same time, the priority must be resolved in software. when an interrupt becomes active, the interrupt con- troller generates an fiq or irq if the corresponding mask bit is set. no latching of interrupts takes place in the controller. after a power on reset all mask register bits are cleared, therefore masking all interrupts. hence, enabling of the mask register must be done by software after a power-on-reset. table 8. boot modes boot mode latched boot- width1 latched boot- width0 latched medchg 8-bit rom 0 0 0 16-bit rom 0 1 0 32-bit rom 1 0 0 32-bit rom 1 1 0 16-bit sflash (initializes mode register) 0 0 1 16-bit srom (initializes mode register) 0 1 1 32-bit sflash (initializes mode register) 1 0 1 32-bit srom (initializes mode register) 1 1 1
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 23 nxp semiconductors external bus interface the external bus interface allows the arm922t, lcd controller and dma engine access to an external memory system. the lcd co ntroller has access to an internal frame buffer in embedded sram and an exten- sion buffer in synchronous memory for large displays. the processor and dma engine share the main system bus, providing access to al l external memory devices and the embedded sram frame buffer. an arbitration unit ensures that control over the external bus interface (ebi) is only granted when an existing access has been completed. see figure 7. embedded sram the amount of embedded sram contained in the LH7A400 is 80 kb. this embedded memory is designed to be used for storing code, data, or lcd frame data and to be contiguous with external sdram. the 80 kb is large enough to store a qvga panel (320 240) at 8 bits per pixel, equivalent to 70 kb of informa- tion. containing the frame buffer on chip reduces the overall power consumed in any application that uses the LH7A400. normally, the system has to perform external accesses to acquire this data. the lcd con- troller is designed to automatically use an overflow frame buffer in sdram if a larger screen size is required. this overflow buffer can be located on any 4 kb page boundary in sdram, allowing software to set the mmu (in the lcd controller) page tables such that the two memory areas appear contiguous. byte, half-word and word accesses are permissible. asynchronous memory controller the asynchronous memory controller is incorpo- rated as part of the memory controller to provide an interface between the amba ahb system bus and external (off-chip) memory devices. the asynchronous memory controller provides sup- port for up to eight independently configurable memory banks simultaneously. each memory bank is capable of supporting: sram rom flash eprom burst rom memory. each memory bank may use devices using either 8-, 16-, or 32-bit external memory data paths. the memory controller supports only little-endian operation. the memory banks can be configured to support: non-burst read and write accesses only to high- speed cmos static ram. non-burst write accesses , nonburst read accesses and asynchronous page mode read accesses to fast-boot block flash memory. figure 6. memory mapping for each boot mode asynchronous memory (ncs0) f000.0000 synchronous memory (nscs2) synchronous memory (nscs1) d000.0000 synchronous memory (nscs0) reserved b001.4000 embedded sram reserved 8000.3800 e000.0000 c000.0000 ahb internal registers apb internal registers 8000.0000 asynchronous memory (cs7) asynchronous memory (cs6) 6000.0000 pcmcia/compactflash (npcslote2) pcmcia/compactflash (npcslote1) 4000.0000 asynchronous memory (ncs3) asynchronous memory (ncs2) 2000.0000 7000.0000 5000.0000 b000.0000 8000.2000 3000.0000 1000.0000 asynchronous memory (ncs1) synchronous rom (nscs3) 0000.0000 synchronous memory boot synchronous memory (nscs3) synchronous memory (nscs2) synchronous memory (nscs1) synchronous memory (nscs0) reserved embedded sram reserved ahb internal registers apb internal registers asynchronous memory (cs7) asynchronous memory (cs6) pcmcia/compactflash (npcslote2) pcmcia/compactflash (npcslote1) asynchronous memory (ncs3) asynchronous memory (ncs2) asynchronous memory (ncs1) asynchronous rom (ncs0) 256mb 256mb 256mb 256mb 256mb 256mb 256mb 256mb 256mb 80kb 256mb 256mb 256mb asynchronous memory boot LH7A400-6
LH7A400 32-bit system-on-chip 24 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors figure 7. external bus interface block diagram LH7A400-8 synchronous dynamic memory controller (sdmc) pcmcia/cf support arbiter color lcd controller (clcdc) 80kb embedded sram lcd ahb asynchronous static memory controller (smc) external bus interface (ebi) sdram data address and control sdram arm922t lcd memory management unit (mmu) dma controller ad-tft lcd timing controller sram rom advanced high-performance bus (ahb) arbiter arbiter arbiter internal to the LH7A400 external to the LH7A400
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 25 nxp semiconductors the asynchronous memory controller has six main functions: memory bank select access sequencing wait states generation byte lane write control external bus interface compactflash or pcmcia interfacing. synchronous memory controller the synchronous memory co ntroller provides a high speed memory interface to a wide variety of synchro- nous memory devices, including sdram, synchro- nous flash and sy nchronous roms. the key features of the controller are: lcd dma port for high bandwidth up to four synchronous memory banks that can be independently set up special configuration bits for synchronous rom operation ability to program synchr onous flash devices using write and erase commands on booting from synchronous rom, (and optionally with synchronous flash), a configuration sequence is performed before releasing the processor from reset data is transferred between the controller and the sdram in quad-word bursts. longer transfers within the same page are concatenated, forming a seam- less burst programmable for 16- or 32-bit data bus size two reset domains are provided to enable sdram contents to be preserved over a ?soft? reset power saving synchronous memory scke and external clock modes provided. multimediacard (mmc) the mmc adapter combines all of the requirements and functions of an mmc host. the adapter supports the full mmc bus protocol, defined by the mmc defini- tion group?s specification v.2.11. the controller can also implement the spi interface to the cards. interface description and mmc overview the mmc controller uses the three-wire serial data bus (clock, command, and data) to transfer data to and from the mmc card, and to configure and acquire status information from the card?s registers. mmc bus lines can be divided into three groups: power supply: vdd and vss data transfer: mmccmd, mmcdata clock: mmclk. multimediacard adapter the multimediacard adapter implements multimedia- card specific functions, serves as the bus master for the multimediacard bus and implements the standard inter- face to the multimediacard cards (card initialization, crc generation and validation, command/response transactions, etc.). smart card interface (sci) the sci (iso7816) interfaces to an external smart card reader. the sci can autonomously control data transfer to and from the smart card. transmit and receive data fifos are provided to reduce the required interaction between the cpu core and the peripheral. sci features supports asynchronous t0 and t1 transmission protocols supports clock rate conversion factor f = 372, with bit rate adjustment factors d = 1, 2, or 4 supported eight-character-deep buffered tx and rx paths direct interrupts for tx and rx fifo level monitoring interrupt status register hardware-initiated card deactivation sequence on detection of card removal software-initiated card deactivation sequence on transaction complete limited support for synchronous smart cards via registered input/output. programmable parameters smart card clock frequency communication baud rate protocol convention card activation/deactivation time check for maximum time for first character of answer to reset - atr reception check for maximum duration of atr character stream check for maximum time of receipt of first character of data stream check for maximum time allowed between characters character guard time block guard time transmit/receive character retry.
LH7A400 32-bit system-on-chip 26 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors direct memory acce ss controller (dma) the dma controller interfac es streams from the fol- lowing three peripherals to the system memory: usb (1 tx and 1 rx dma channel) mmc (1 tx and 1 rx dma channel) ac97 (3 tx and 3 rx dma channels). each has its own bi-directional peripheral dma bus capable of transferring data in both directions simulta- neously. all memory transfers take place via the main system ahb bus. dma specific features are: independent dma channels for tx and rx two buffer descriptors per channel to avoid poten- tial data under/over-flows due to software introduced latency no buffer wrapping buffer size may be equal to, greater than, or less than the packet size. tr ansfers can automatically switch between buffers. maskable interrupt generation internal arbitration between dma channels and external bus arbiter. for dma data transfer sizes, byte, word and quad- word data transfers are supported. a set of control and status registers are available to the system processor for se tting up dma operations and monitoring their status. a system interrupt is gen- erated when any or all of the dma channels wish to inform the processor that a new buffer needs to be allo- cated. the dma controller services three peripherals using ten dma channels, each with its own peripheral dma bus capable of transferring data in both directions simultaneously. the mmc and usb peripherals each use two dma channels, one for transmit and one for receive. the ac97 peripheral uses six dma channels (three trans- mit and three receive) to allow different sample fre- quency data queues to be handled with low software overheads. the dma controller does not support memory to memory transfers. usb device the features of the usb are: fully compliant to usb 1.1 specification provides a high level interf ace that shields the firm- ware from usb protocol details compatible with both openhci and intel?s uhci standards supports full-speed (12 mbps) functions supports suspend and resume signalling. color lcd controller the LH7A400?s lcd controller is programmable to support up to 1,024 768, 16-bit color lcd panels. it interfaces directly to st n, color stn, tft, ad-tft, and hr-tft panels. unlike ot her lcd controllers, the LH7A400?s lcd controller incorporates the timing con- version logic from tft to hr- and ad-tft, allowing a direct interface to these pan els and minimizing external chip count. the color lcd controller features support for: up to 1,024 768 resolution 16-bit video bus stn, color stn, ad-tft, hr-tft, tft panels single and dual scan stn panels up to 15 gray shades up to 64,000 colors ac97 advanced audio codec interface the ac97 advanced audi o codec controller includes a 5-pin serial interface to an external audio codec. the ac97 link is a bi-directional, fixed rate, serial pulse code modulation (pcm) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. the ac97 controller contains logic that controls the ac97 link to the audio codec and an interface to the amba apb. its main features include: serial-to-parallel conversi on for data received from the external codec parallel-to-serial conversion for data transmitted to the external codec reception/transmission of control and status infor- mation via the amba apb interface supports up to 4 different codec sampling rates at a time with its 4 transmit and 4 receive channels. the transmit and receive paths are buffered with internal fifo memories, allowing data to be stored indepen- dently in both transmit and receive modes. the out- going data for the fifos can be written via either the apb interface or with dma channels 1 - 3.
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 27 nxp semiconductors audio codec in terface (aci) the aci provides: a digital serial interface to an off-chip 8-bit codec all the necessary clocks and timing pulses to per- form serialization or de-serialization of the data stream to or from the codec device. the interface supports full duplex operation and the transmit and receive paths are buffered with internal fifo memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. the aci includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip aci clock input (aciclk). transmit data values are output synchronous with the rising edge of the bit clock output. receive data values are sampled on the falling edge of the bit clock output. the start of a data frame is indicated by a synchroniza- tion output signal that is synchronous with the bit clock. synchronous serial port (ssp) the LH7A400 ssp is a master-only interface for synchronous serial communication with device periph- eral devices that has either motorola spi, national semiconductor microwire or texas instruments synchronous serial interfaces. the LH7A400 ssp performs serial-to-parallel con- version on data received from a peripheral device. the transmit and receive paths are buffered with internal fifo memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. serial data is transmitted on ssptxd and received on ssprxd. the LH7A400 ssp includes a programmable bit rate clock divider and prescaler to generate the serial output clock sclk from the input clock sspclk. bit rates are supported to 2 mhz and beyond, subject to choice of frequency for sspclk; the maximum bit rate will usu- ally be determined by peripheral devices. uart/irda the LH7A400 contains three uarts, uart1, uart2, and uart3. the uart performs: serial-to-parallel conversion on data received from the peripheral device parallel-to-serial conversion on data transmitted to the peripheral device. the transmit and receive paths are buffered with inter- nal fifo memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. the uart can generate: four individually maskab le interrupts from the receive, transmit and modem status logic blocks a single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. if a framing, parity, or break error occurs during reception, the appropriate error bit is set, and is stored in the fifo. if an overrun condition occurs, the overrun register bit is set immediately and the fifo data is pre- vented from being overwritten. uart1 also supports irda 1.0 (15.2 kbit/s). the modem status input signals clear to send (cts), data carrier detect (dcd) and data set ready (dsr) are supported on uart2 and uart3. timers two identical timers are integrated in the LH7A400. each of these timers has an associated 16-bit read/write data register and a control register. each timer is loaded with the value written to the data register immediately, this value will then be de cremented on the next active clock edge to arrive after the write. when the timer underflows, it will immediately assert its appropriate interrupt. the timers can be read at any time. the clock source and mode is selectable by writing to various bits in the system control register. clock sources are 508 khz and 2 khz. timer 3 (tc3) has the same basic operation, but is clocked from a single 7.3728 mhz source. it has the same register arrangement as timer 1 and timer 2, pro- viding a load, value, control and clear register. once the timer has been enabled and is written to, unlike the timer 1 and timer 2, will decrement the timer on the next rising edge of the 7.3728 mhz clock after the data register has been updated. all the timers can operate in two modes, free running mode or pre-scale mode. free-running mode in free-running mode, the timer will wrap around to 0xffff when it underflows and continue counting down. pre-scale mode in pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. this mode can be used to produce a pro- grammable frequency to drive an external buzzer or generate a periodic interrupt.
LH7A400 32-bit system-on-chip 28 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors real time clock (rtc) the rtc can be used to provide a basic alarm func- tion or long time-base counter. this is achieved by gen- erating an interrupt signal after counting for a programmed number of cycles of a real-time clock input. counting in one second intervals is achieved by use of a 1 hz clock input to the rtc. battery monitor interface (bmi) the LH7A400 bmi is a serial communication inter- face specified for two type s of battery monitors/gas gauges. the first type employs a single wire interface. the second interface employs a two-wire multi-master bus, the smart battery system specification. if both interfaces are enabled at the same time, the single wire interface will have priority. a brief overview of these two interface types are given here. single wire interface the single wire interface performs: serial-to-parallel conversion on data received from the peripheral device parallel-to-serial conversion on data transmitted to the peripheral device data packet coding/decoding on data transfers (incorporating start/data/stop data packets) the single wire interface uses a command-based protocol, in which the host initiates a data transfer by sending a writedata/command word to the battery monitor. this word will always contain the command section, which tells the single wire interface device the location for the current transaction. the most signifi- cant bit of the command determines if the transaction is read or write. in the case of a write transaction, then the word will also cont ain a writedata section with the data to be written to the peripheral. smart battery interface the smbus interface performs: serial-to-parallel conversion on data received from the peripheral device parallel-to-serial conversion of data transmitted to the peripheral device. the smart battery interface uses a two-wire multi- master bus (the smbus), meaning that more than one device capable of controlling the bus can be connected to it. a master device initiates a bus transfer and provides the clock signals. a slave device can receive data pro- vided by the master or it can provide data to the master. since more than one device may attempt to take control of the bus as a master, smbus provides an arbitration mechanism, by relying on the wired-and connection of all smbus interfaces to the smbus. dc-to-dc converter the features of the dc-dc converter interface are: dual drive pwm outputs, with independent closed loop feedback software programmable configuration of one of 8 output frequencies (each being a fixed divide of the input clock). software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. output polarity (for positive or negative voltage gen- eration) is hardware-configured during power-on reset via the polarity select inputs each pwm output can be dynamically switched to one of a pair of preprogrammed frequency/duty cycle combinations via external pins. watchdog timer (wdt) the watchdog timer provides hardware protection against malfunctions. it is a programmable timer that is reset by software at regular intervals. failure to reset the timer will cause a fiq inte rrupt. failure to service the fiq interrupt will then generate a system reset. the wdt features are: driven by the system clock 16 programmable time-out periods: 2 16 through 2 31 clock cycles generates a system reset (resets LH7A400) or a fiq interrupt whenever a time-out period is reached software enable, lockout, and counter-reset mecha- nisms add security against inadvertent writes protection mechanism guards against interrupt-service-failure: ? the first wdt time-out triggers fiq and asserts nwdfiq status flag ? if fiq service routine fails to clear nwdfiq, then the next wdt time-out triggers a system reset. general purpose i/o (gpio) the LH7A400 gpio has eight ports, each with a data register and a data direction register. it also has added registers including keyboard scan, pinmux, gpio interrupt enable, intype1/2, gpiofeoi, and pghcon. the data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the gpio pins. the gpio interrupt enable, intype1/2, and gpi- ofeoi registers are used to control edge-triggered interrupts on port f. the pinmux register controls what signals are output of port d and port e when they are set as outputs, while the pghcon controls the operations of port g and h.
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 29 nxp semiconductors electrical specifications absolute maximum ratings note: except for storage temperature, these ratings are only for transient conditions. operati on at or beyond absolute maxi- mum rating conditions may affe ct reliability and cause per- manent damage to the device. recommended operat ing conditions notes: 1. core voltage should never exceed i/o voltage after in itial power up. see ?power supply sequencing? on page 33 2. usb is not functional below 3.0 v 3. using 14.7456 mhz main oscillator crysta l and 32.768 khz rtc oscillator crystal 4. vddc = 1.71 v to 1.89 v (LH7A400n0g000xx) 5. vddc = 2.1 v 5 % (LH7A400n0g076xx only) 6. vdd = 3.0 v to 3.6 v (LH7A400n0g000xx) 7. vdd = 3.14v to 3.60 v (LH7A400n0g076xx only) 8. important: most peripherals will not func tion with crystals other than 14.7456 mhz. parameter minimum maximum dc core supply voltage (vddc) ? 0.3 v 2.4 v dc i/o supply voltage (vdd) ? 0.3 v 4.6 v dc analog supply voltage (vdda) ? 0.3 v 2.4 v 5 v tolerant digital input pin voltage ? 0.5 v 5.5 v esd, human body model (analog pins an0 - an9 rated at 500 v) 2 kv esd, charged device model 1 kv storage temperature ? 55c 125c parameter minimum typical maximum notes dc core supply voltage (vddc) 1.71 v 1.8 v 1.89 v 1, 4 dc core supply voltage (vddc) 2.0 v 2.1 v 2.2 v 1, 5 dc i/o supply voltage (vdd) 3.0 v 3.3 v 3.6 v 2, 6 dc i/o supply voltage (vdd) 3.14 v 3.3 v 3.6 v 2, 7 dc analog supply voltage for plls (vdda) 1.71 v 1.8 v 1.89 v clock frequency ( 0c to +70c) 10 mhz 200 mhz 3, 4, 6 clock frequency ( ? 40c to +85c) 10 mhz 195 mhz 3, 4, 6 bus clock frequency ( ? 40c to +85c) 100 mhz 3, 4, 6 clock frequency ( 0c to +70c) 10 mhz 250 mhz 3, 5, 7 clock frequency ( ? 40c to +85c) 10 mhz 245 mhz 3, 5, 7 bus clock frequency ( ? 40c to +85c) 125 mhz 3, 5, 7 external clock input (xtalin) 14 mhz 14.7456 mhz 20 mhz 8 external clock input (xtalin) voltage 1.71 v 1.8 v 1.89 v operating temperature ? 40c 25c +85c
LH7A400 32-bit system-on-chip 30 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors notes: 1. table 9 is representative of a typical wafer process. guaranteed values are in the recommended operating conditions table. 2. LH7A400n0g000xx figure 8. temperature/voltage/speed chart (for LH7A400n0g000xx) table 9. c loc k frequency vs. voltages (vddc) vs. temperature parameter 1.71 v 1.8 v 1.89 v 25c clock frequency (fclk) 211 mhz 225 mhz 240 mhz clock period (fclk) 4.74 ns 4.44 ns 4.17 ns 70c clock frequency (fclk) 200 mhz 212 mhz 227 mhz clock period (fclk) 5.00 ns 4.72 ns 4.41 ns 85c clock frequency (fclk) 195 mhz 208 mhz 222 mhz clock period (fclk) 5.13 ns 4.81 ns 4.50 ns LH7A400-206 frequency (mhz) 245 240 235 230 225 220 215 210 205 200 195 25 35 45 55 temp ( c) 65 75 85 1.89 v (+5%) 1.80 v 1.71 v (-5%)
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 31 nxp semiconductors dc/ac specifications unless otherwise noted, all data provided in these specifications are based on ? 40c to +85c, vddc = 1.71 v to 1.89 v, vdd = 3.0 v to 3.6 v, vdda = 1.71 v to 1.89 v. dc specifications notes: 1. output drive 5 can sink 20 ma of current, but sources 12 ma of current. 2. current consumption until oscillators are stabilized. ac test conditions symbol parameter min. typ. max. unit conditions notes vih cmos and schmitt tri gger input high volt- age 2.0 5.5 v vil cmos and schmitt tri gger input low volt- age ? 0.2 0.8 v vhst schmitt trigger hysteresis 0.25 v vil to vih voh output drive 2 2.6 v ioh = ? 4 ma output drive 3 2.6 v ioh = ? 8 ma output drive 4 and 5 2.6 v ioh = ? 12 ma 1 vol output drive 2 0.4 v iol = 4 ma output drive 3 0.4 v iol = 8 ma output drive 4 0.4 v iol = 12 ma output drive 5 0.4 v iol = 20 ma 1 iin input leakage current ? 10 10 a vin = vdd or gnd input leakage current (with pull-up resistors installed) ? 200 ? 20 a vin = vdd or gnd ioz output tri-state leakage current ? 10 10 a vout = vdd or gnd istartup startup current 50 a2 iactive active current 125 180 ma ihalt halt current 25 41 ma istandby standby current 42 a cin input capacitance 4 pf cout output capacitance 4 pf parameter rating unit dc i/o supply voltage (vdd) 3.0 to 3.6 v dc core supply voltage (vddc) 1.71 to 1.89 v input pulse levels vss to 3 v input rise and fall times 2 ns input and output timing reference levels vdd/2 v
LH7A400 32-bit system-on-chip 32 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors current consumption by operating mode current consumption can depend on a number of parameters. to make this data more usable, the values presented in table 10 were derived under the condi- tions presented here. maximum specified value the values specified in the maximum column were determined using these operating characteristics: all ip blocks either operating or enabled at maximum frequency and size configuration core operating at maximum power configuration all voltages at maximum specified values maximum specified ambient temperature (tamb). typical the values in the typical column were determined using a ?typical? application under ?typical? environmental conditions and the following operating characteristics: linux operating system running from sdram uart and ac97 peripherals operating; all other peripherals as needed by the os lcd enabled with 320 240 16-bit color, 60 hz refresh rate, data in sdram i/o loads at nominal cache enabled fclk = 200 mhz or 250 mhz; hclk = 100 mhz or 125 mhz; pclk = 50 mhz or 62.5 mhz all voltages at typical values nominal case temperature (tamb). peripheral current consumption in addition to the modal current consumption, table 11 shows the typical current consumption for each of the on-board peripheral blocks. the values were deter- mined with the cpu clock running at 200 mhz, typical conditions, and no i/o loads. this current is supplied by the 1.8 vddc power supply. table 10. current consumption by mode symbol parameter LH7A400n0g000xx (fclk = 200 mhz) LH7A400n0g076xx (fclk = 250 mhz) typ. max. typ. units active mode icore core current 110 135 250 ma iio i/ o current 15 45 ma halt mode (all peripherals disabled) icore core current 24 39 50 ma iio i/ o current 1 2 ma standby mode (typical conditions only) icore core current 40 125 a iio i/ o current 2 4 a table 11. peripheral current consumption peripheral typical units ac97 1.3 ma uart (each) 1.0 ma rtc 0.005 ma timers (each) 0.1 ma lcd (+i/o) 5.4 (1.0) ma mmc 0.6 ma sci 23 ma pwm (each) < 0.1 ma bmi-swi 1.0 ma bmi-sbus 1.0 ma sdram (+i/o) 1.5 (14.8) ma usb (+pll) 5.6 (3.3) ma aci 0.8 ma
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 33 nxp semiconductors power supply sequencing nxp recommends that the 1.8 v power supply be energized before the 3.3 v supply. if this is not possi- ble, the 1.8 v supply may not lag the 3.3 v supply by more than 100 s. if longer delay time is needed, it is recommended that the voltage difference between the two power supplies be within 1.5 v during power supply ramp up. to avoid a potential latchup condition, voltage should be applied to input pins only after the device is powered-on as described above. ac specifications all signals described in table 12 relate to transi- tions after a reference clock signal. the illustration in figure 9 represents all cases of these sets of mea- surement parameters. the reference clock signals in this design are: hclk, internal system bus clock (?c? in timing data) pclk, peripheral bus clock sspclk, synchronous serial port clock uartclk, uart interface clock lcddclk, lcd data clock from the lcd controller acbitclk, ac97 clock sclk, synchronous memory clock. all signal transitions are measured at the 50 % point. for outputs from the LH7A400, tovxxx (e.g. tova) represents the amount of time for the output to become valid from a valid address bus, or rising edge of the peripheral clock. maximum requirements for tovxxx are shown in table 12. the signal tohxxx (e.g. toha) represents the amount of time the output will be held valid from the valid address bus, or rising edge of the peripheral clock. min- imum requirements for tohxxx are listed in table 12. for inputs, tisxxx (e.g. tisd) represents the amount of time the input signal must be valid before a valid address bus, or rising edge of the peripheral clock (except ssp and aci). maximum requirements for tisxxx are shown in table 12. the signal tihxxx (e.g. tihd) represents the amount of time the output must be held valid from the valid address bus, or rising edge of the peripheral clock (except ssp and aci). minimum requirements are shown in table 12. figure 9. LH7A400 signal timing reference clock output signal (o) input signal (i) tovxxx tohxxx tisxxx tihxxx 7a400-28
LH7A400 32-bit system-on-chip 34 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors table 12. ac signal characteristics signal type load symbol min. max. description asynchronous memory interface signals (+ [wait states hclk period]) 1 a[27:0] output 50 pf trc 4 thclk ? 7.0 ns 4 thclk + 7.5 ns read cycle time output 50 pf twc 4 thclk ? 7.0 ns 4 thclk + 7.5 ns write cycle time ? ? tws thclk ns thclk ns wait state width d[31:0] output 50 pf tdvwe thclk ? 6.0 ns thclk ? 2.0 ns data valid to write edge (nwe invalid) tdhwe thclk ? 7.0 ns thclk + 2.0 ns data hold after write edge (nwe invalid) tdvbe thclk ? 5.0 ns thclk ? 1.0 ns data valid to nble invalid tdhbe thclk ? 7.0 ns thclk + 3.0 ns data hold after nble invalid input ? tdscs 15 ns ? data setup to ncsx invalid tdhcs 0 ns ? data hold to ncsx invalid tdsoe 15 ns ? data setup to noe invalid tdhoe 0 ns ? data hold to noe invalid tdsbe 15 ns ? data setup to nble invalid tdhbe 0 ns ? data hold to nble invalid ncs[7:0] output 30 pf tcs 2 thclk ? 3.0 ns 2 thclk + 3.0 ns ncsx width tavcs thclk ? 4.0 ns thclk address valid to ncsx valid tahcs thclk thclk + 4.5 ns address hold after ncsx invalid synchronous memory interface signals sa[13:0] output 50 pf tova 5.5 3 /7.5 4 ns address valid toha 1.5 3 /1.5 4 ns address hold sa[17:16]/sb[1:0] output 50 pf tovb 5.5 3 /7.5 4 ns bank select valid d[31:0] output 50 pf tohd 1.5ns data hold tovd 2 ns 5.5 3 /7.5 4 ns data valid input tisd 1.5 3 /2.5 4 ns data setup tihd 1.0 3 /1.5 4 ns data hold ncas output 30 pf tovca 2 ns 5.5 3 /7.5 4 ns cas valid tohca 1.5 3 /2 4 ns cas hold nras output 30 pf tovra 2 ns 5.5 3 /7.5 4 ns ras valid tohra 1.5 3 /2 4 ns ras hold nswe output 30 pf tovsdw 2 ns 5.5 3 /7.5 4 ns write enable valid tohsdw 1.5 3 /2 4 ns write enable hold scke[1:0] output 30 pf tovc 2 ns 5.5 3 /7.5 4 ns clock enable valid dqm[3:0] output 30 pf tovdq 2 ns 5.5 3 /7.5 4 ns data mask valid nscs[3:0] output 30 pf tovsc 2 ns 5.5 3 /7.5 4 ns synchronous chip select valid tohsc 1.5 3 /2 4 ns synchronous chip select hold pcmcia interface signals (+ wait states hclk period) npcreg output 30 pf tovdreg thclk nreg valid tohdreg 4 thclk ? 5 ns nreg hold d[31:0] output 50 pf tovd thclk data valid tohd 4 thclk ? 5 ns data hold input tisd thclk - 10 ns data setup time tihd 4 thclk ? 5 ns data hold time npcce1 output 30 pf tovce1 thclk chip enable 1 valid tohce1 4 thclk ? 5 ns chip enable 1 hold npcce2 output 30 pf tovce2 thclk chip enable 2 valid tohce2 4 thclk ? 5 ns chip enable 2 hold npcoe output 30 pf tovoe thclk + 1 ns output enable valid tohoe 3 thclk ? 5 ns output enable hold npcwe output 30 pf tovwe thclk + 1 ns write enable valid tohwe 3 thclk ? 5 ns write enable hold pcdir output 30 pf tovpcd thclk card direction valid tohpcd 4 thclk ? 5 ns card direction hold
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 35 nxp semiconductors notes: 1. register bcrx:wst1 = 0b000 2. for output drive strength spec ifications, refer to table 3 3. LH7A400n0g076xx only 4. LH7A400n0g000xx only mmc interface signals mmccmd output 100 pf tos 5 ns mmc command setup toh 5 ns mmc command hold mmcdata output 100 pf tos 5 ns mmc data setup toh 5 ns mmc data hold mmcdata input tis 3 ns mmc data setup tih 3 ns mmc data hold mmccmd input tis 3 ns mmc command setup tih 3 ns mmc command hold ac97 interface signals acout/acsync output 30 pf tovac97 15 ns ac97 output valid/sync valid tohac97 10 ns ac97 output hold/sync hold acin input tisac97 10 ns ac97 input setup tihac97 2.5 ns ac97 input hold acbitclk input tacbitclk 72 ns 90 ns ac97 clock period synchronous serial port (ssp) sspfrm output tovsspfrm 10 ns sspfrm valid tohsspfrm 5 ns sspfrm hold ssptx output 50 pf tovsspout 10 ns ssp transmit valid tohsspout 5 ns ssp transmit hold ssprx input tissspin 14 ns ssp receive setup sspclk output tsspclk 8.819 ms 271 ns ssp clock period audio codec interface (aci) acout output 30 pf tovd 15 ns acout delay from rising clock edge tohd 10 ns acout hold acin input tis 10 ns acin setup tih 2.5 ns acin hold color lcd controller lcdvd [17:0] output 30 pf tov ? 3 ns lcd data clock to data valid table 12. ac signal characteristics (cont?d) signal type load symbol min. max. description
LH7A400 32-bit system-on-chip 36 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors smc waveforms figure 10 and figure 11 show the waveform and timing for an external asynchronous memory write. note that the deassertion of nwe can precede the deassertion of ncs by a maximum of one hclk, or at minimum, can coincide (see table 12). figure 12 and figure 13 show the waveform and timing for an exter- nal asynchronous memory read. figure 10. external asynchronous memory write with 0 wait states (bcrx:wst1 = 0b000) LH7A400-201 hclk a[27:0] twc valid address valid data tdvwe, tdvbe tdhwe, tdhbe 01 2 34 tcs ncs valid nwe valid nble valid tavcs tahcs twe tcshwe tavwe tbew tcshbe tavbe d[31:0] ncsx nwe nble write edge
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 37 nxp semiconductors figure 11. external asynchronous memory write with 4 wait states (bcrx:wst1 = 0b100) LH7A400-203 a[27:0] hclk valid address 0 wait state wait state 1 wait state 2 wait state 3 wait state 4 d[31:0] ncsx nwe valid data nble write edge 8 7 6 5 4 3 2 1 0 ncsx valid nwe valid nble valid tws tws tws tws
LH7A400 32-bit system-on-chip 38 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors figure 12. external asynchronous memory read with 0 wait states (bcrx:wst1 = 0b000) LH7A400-200 hclk a[27:0] trc tahcs, tahoe, tahbe tdhcs tdhbe tdhoe valid data valid address data latched here 01 234 tavcs tdscs tdsbe tcs ncs valid noe valid nble valid tber tdsoe toe tavoe tavbe d[31:0] ncsx noe nble
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 39 nxp semiconductors synchronous memory controller waveforms figure 14 shows the timing for a synchronous burst read (page already open). figure 15 shows the timing for activate a bank and write. ssp waveforms the synchronous serial po rt (ssp) supports three data frame formats: texas instruments ssi motorola spi national semiconductor microwire each frame format is between 4 and 16 bits in length, depending upon the programmed data size. each data frame is transmitted beginning with the most significant bit (msb) i. e. ?big endian?. for all three formats, the ssp serial clock is held low (inac- tive) while the ssp is idle. the ssp serial clock tran- sitions only during active transmission of data. the sspfrm signal marks the beginning and end of a frame. the sspen signal controls an off-chip line driver?s output enable pin. figure 16 and figure 17 show texas instruments synchronous serial frame format, figure 18 through figure 25 show the motorola spi format, and figure 26 and figure 27 show national semiconductor?s micro- wire data frame format. for texas instruments ssi format, the sspfrm pin is pulsed prior to each frame?s transmission for one serial clock period beginning at its rising edge. for this frame format, both the ssp and the external slave device drive their output data on the rising edge of the clock and latch data from the other device on the falling edge. see figure 16 and figure 17. figure 13. external asynchronous memory read with 4 wait states (bcrx:wst1 = 0b100) LH7A400-202 10 9 8 7 6 5 4 3 2 1 0 a[27:0] hclk valid address d[31:0] ncs[3:0, cs[7:6] noe valid data nble 0 wait state, data would be latched here tws 4 wait states, data latched here wait state 1 wait state 2 wait state 3 wait state 4 ncsx valid noe valid nble valid tws tws tws
LH7A400 32-bit system-on-chip 40 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors figure 14. synchronous burst read figure 15. synchronous bank activate and write t sclk LH7A400-23 sa[13:0], sb[1:0] d[31:0] notes: 1. sdramcmd is the combination of nras, ncas, nswe, and nscsx. 2. tovxxx represents tovra, tovca, tovsvw, or tovsc. 3. tohxxx represents tohra, tohca, tohsvw, or tohsc. 4. dqm[3:0] is static low. 5. scke is static high. sclk sdramcmd ndqm t ovxxx t oha, tohb t ohxxx read bank, column tova, tovb tisd tihd data n data n + 1 data n + 2 data n + 3 LH7A400-24 d[31:0] sclk scke sdramcmd tovc tovxxx tova tohxxx toha notes: 1. sdramcmd is the combination of nras, ncas, nswe, and nscsx. 2. tovxxx represents tovra, tovca, tovsvw, or tovsc. refer to the ac timing table. 3. tohxxx represents tohra, tohca, tohsvw, or tohsc. active write data bank, row bank, column tovd tohd sa[13:0], sb[1:0]
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 41 nxp semiconductors figure 16. texas instruments synchronous serial frame format (single transfer) figure 17. texas instruments synchronous serial frame format (continuous transfer) figure 18. motorola spi frame format (single transfer) with spo = 0 and sph = 0 LH7A400-97 sspclk sspfrm msb lsb ssptxd/ ssprxd 4 to 16 bits LH7A400-98 sspclk sspfrm ssptxd/ ssprxd msb lsb 4 to 16 bits LH7A400-99 sspclk nsspfrm ssprxd msb ssptxd 4 to 16 bits msb lsb lsb q note: q is undefined.
LH7A400 32-bit system-on-chip 42 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors figure 19. motorola spi frame format (continuous transfer) with spo = 0 and sph = 0 figure 20. motorola spi frame format (single transfer) with spo = 0 and sph = 1 figure 21. motorola spi frame format (continuous transfer) with spo = 0 and sph = 1 figure 22. motorola spi frame format (continuous transfer) with spo = 1 and sph = 1 LH7A400-100 sspclk nsspfrm ssptxd/ sssrxd 4 to 16 bits lsb lsb msb msb LH7A400-101 sspclk nsspfrm ssprxd ssptxd note: q is undefined. 4 to 16 bits lsb lsb q q msb msb LH7A400-102 sspclk nsspfrm ssptxd/ sssrxd 4 to 16 bits lsb msb lsb msb LH7A400-103 sspclk nsspfrm ssptxd/ sssrxd 4 to 16 bits lsb msb lsb msb
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 43 nxp semiconductors figure 23. motorola spi frame format (single transfer) with spo = 1 and sph = 0 figure 24. motorola spi frame format (continuous transfer) with spo = 1 and sph = 0 figure 25. motorola spi frame format (single transfer) with spo = 1 and sph = 1 LH7A400-104 sspclk nsspfrm ssprxd ssptxd note: q is undefined. msb msb lsb lsb q 4 to 16 bits LH7A400-105 sspclk nsspfrm ssptxd/ ssprxd msb lsb msb lsb 4 to 16 bits LH7A400-106 sspclk nsspfrm ssprxd ssptxd 4 to 16 bits msb msb q lsb lsb q note: q is undefined.
LH7A400 32-bit system-on-chip 44 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors for national semiconductor microwire format, the serial frame pin (sspfrm) is active low. both the ssp and external sl ave device drive their output data on the falling edge of the cloc k, and latch data from the other device on the rising edge of the clock. unlike the full-duplex transmission of the other two frame formats, the national semiconducto r microwire format uti- lizes a master-slave messaging technique that oper- ates in half-duplex. when a frame begins in this mode, an 8-bit control message is transmitted to the off-chip slave. during this transmission no incoming data is received by the ssp. after the message ha s been sent, the external slave device decodes the message. after waiting one serial clock period after the last bit of the 8- bit control message was received it responds by return- ing the requested data. the returned data can be 4 to 16 bits in length, making the total frame length between 13 to 25 bits. see figure 26 and figure 27. figure 26. microwire frame format (single transfer) figure 27. microwire frame format (continuous transfers) LH7A400-107 lsb msb 0 lsb msb 8-bit control sspclk nsspfrm ssptxd ssprxd 4 to 16 bits output data LH7A400-108 sspclk nsspfrm ssptxd ssprxd 4 to 16 bits output data 8-bit control msb msb lsb lsb 0 lsb msb
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 45 nxp semiconductors pc card (pcmcia) waveforms figure 28 shows the waveforms and timing for a pcmcia read transfer, figure 29 shows the wave- forms and timing for a pcmcia write transfer. figure 28. pcmcia read transfer tovdreg hclk a[25:0] tisd tohdreg address precharge time (see note 1) access time (see note 1) hold time (see note 1) data tihd tovcex tohcex LH7A400-11 npcreg npccex (see note 2) pcdir d[15:0] npcoe notes: 1. precharge time, access time, and hold time are programmable wait-state times. 2. npcce1 0 0 1 1 npcce2 0 1 0 1 transfer type common memory attribute memory i/o none tovoe tohoe tovpcd tohpcd
LH7A400 32-bit system-on-chip 46 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors figure 29. pcmcia write transfer figure 30. pcmcia precharge, access, and hold waveform tovdreg hclk a[25:0] tovpcd tovd tovwe tohdreg address precharge time (see note 1) access time (see note 1) hold time (see note 1) data tohd tohwe tovcex tohcex LH7A400-12 npcreg npccex (see note 2) pcdir d[15:0] npcwe notes: 1. precharge time, access time, and hold time are programmable wait-state times. 2. npcce1 0 0 1 1 npcce2 0 1 0 1 transfer type common memory attribute memory i/o none LH7A400-209 access precharge npcwe, npcoe ncsx hold
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 47 nxp semiconductors mmc interface waveform figure 31 shows the waveforms and timing for an mmc command or data read and write. ac97 interface waveform figure 32 shows the waveforms and timing for the ac97 interface data setup and hold. figure 31. mmc command/data read and write timing figure 32. ac97 data setup and hold LH7A400-14 tis tos toh data data invalid invalid soc output data /cmd soc input data/cmd mmc clock tih LH7A400-16 tovac97 acbitclk acout/acsync acin tisac97 tihac97 tohac97 tacbitclk
LH7A400 32-bit system-on-chip 48 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors audio codec in terface waveforms figure 33 and figure 34 show the timing for the aci. transmit data is clocked on the rising edge of acbit- clk (whether transmitted by the LH7A400 aci or by the external codec chip); receive data is clocked on the fall- ing edge. this allows full -speed, full duplex operation. color lcd controller waveforms figure 35 shows the valid output setup time for lcd data. timing diagrams for each clcdc mode appear in figure 36 through figure 41. figure 33. aci signal timing figure 34. aci data stream figure 35. clcdc valid output data time tos tis tih toh acbitclk acsync/acout acin LH7A400-169 LH7A400-181 acbitclk acsync acin/acout acin/acout sampled on falling edge 76 bit 5 4 3 2 1 0 7 6 lcddclk data valid tov LH7A400-211 lcdvd (soc output)
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 49 nxp semiconductors figure 36. stn horizontal timing diagram 1 stn horizontal line clcdc clock (internal) lcdlp (line sync pulse) timing2:ihs lcddclk (panel data clock) timing2:pcd timing2:bcd timing2:ipc timing2:cpl lcdvd[17:0] (lcd data) the active data lines will vary with the type of stn panel: 4-bit, 8-bit, color, or mono note: circled numbers are LH7A400 pin numbers. timing0:hsw timing0:hbp timing0:ppl d001 d002 d.... one 'line' of lcd data dnnn timing0:hfp horizontal back porch horizontal front porch enumerated in 'lcddclks' enumerated in 'lcddclks' LH7A400-113 lcddclk is suppressed during lcdllp r8 n9
LH7A400 32-bit system-on-chip 50 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors figure 37. stn vert ical timing diagram vdd display-dependent turn-on delay 1 stn frame panel positive high-voltage supply active panel negative high-voltage supply active panel logic active panel data clock active ac bias active back porch enumerated in horizontal 'lines' see 'stn horizontal timing diagram' enumerated in horizontal 'lines' front porch all 'lines' for one frame vss lcdvdden (display enable) lcddclk (panel data clock) timing2:pcd timing2:bcd timing2:ipc timing2:cpl lcdmux:pin133 lcdenab (ac bias) timing2:acb lcdfp (frame pulse) timing1:ivs (see note 2) pixel data and horizontal control signals for one frame notes: 1. signal polarties may vary for some displays. 2. lcdfp with timing1:vsw = 0 is only a single horizontal ine period. 3. circled numbers are LH7A400 pin numbers. timing1: vbp timing1:lpp timing1:vfp timing1:vsw = 0 n9 r1 p9 r6 LH7A400-112 display-dependent turn-off delay
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 51 nxp semiconductors figure 38. tft horizontal timing diagram 1 tft horizontal line clcdc clock (internal) lcdllp (horiz. sync pulse) timing2:ihs lcddclk (panel data clock) timing2:pcd timing2:bcd timing2:ipc timing2:cpl lcdvd[17:0] (lcd data) note: circled numbers are LH7A400 pin numbers. timing0:hsw timing0:hbp d001 d002 d.... one 'line' of lcd data dnnn timing0:hfp horizontal back porch horizontal front porch enumerated in 'lcddclks' enumerated in 'lcddclks' LH7A400-192 r8 n9 16 (timing0:ppl+1)
LH7A400 32-bit system-on-chip 52 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors figure 39. tft vertical timing diagram vdd see note 2 display-dependent turn-on delay 1 tft frame panel positive high-voltage supply active panel negative high-voltage supply active panel logic active panel data clock active data enable back porch enumerated in horizontal 'lines' see 'tft horizontal timing diagram' enumerated in horizontal 'lines' front porch all 'lines' for one frame vss lcdvdden (enable for low-voltage digital logic and analog supplies) lcddclk (panel data clock) timing2:pcd timing2:bcd timing2:ipc lcdenab (data enable) timing2:ioe lcdfp (vertical sync pulse) timing1:ivs pixel data and horizontal control signals for one frame notes: 1. signal polarties may vary for some displays. 2. the use of lcdvdden for high-voltage power control is optional on some tft panels. 3. circled numbers are LH7A400 pin numbers. display dependent turn-off delay timing1:vbp timing1:lpp timing1: vfp timing1: vsw n9 r1 p9 r6 LH7A400-109
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 53 nxp semiconductors figure 40. ad-tft and hr-tft horizontal timing diagram 1 ad-tft or hr-tft horizontal line timing0:hsw timing0:hsw + timing0:hbp pixel data 1 lcddclk 002 003 004 005 006 318 317 319 320 001 1 lcddclk alitiming1:lpdel alitiming1:pscls alitiming1:revdel alitiming2:ps2cls2 alitiming2:spldel 002 003 004 005 006 007 008 320 001 clcdc clock (internal) lcdlp (horizontal sync pulse) inputs to the ali from the clcdc outputs from the ali to the panel lcddclk (panel data clock) timing2:pcd timing2:bcd timing2:ipc timing2:cpl lcdvd[17:0] 16 (timing0:ppl+1) lcddclk (delayed for hr-tft) lcdvd[17:0] (delayed for hr-tft) lcdspl (line start pulse left) lcdlp (horizontal sync pulse) lcdcls lcdps lcdrev lcdenab (internal data enable) n9 r8 r2 t1 p2 k6 r8 note: circled numbers are lha400 pin numbers. LH7A400-111
LH7A400 32-bit system-on-chip 54 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors clock and state controller (csc) waveforms figure 42 shows the behavior of the LH7A400 when coming out of reset or power on. figure 43 shows exter- nal reset timing, and table 13 gives the timing parame- ters. figure 44 depicts signal timing following a reset. at power-on, npor must be held low at least until the 32.768 khz oscillator is stable, and must be deas- serted at least two 32.768 khz clock periods before the wakeup signal is asserted. once the 14.7456 mhz oscillator is stable, the plls require 250 s to lock. on transition from standby to run (including a cold boot), the wakeup pin must not be asserted for 2 sec- onds after assertion of npor to allow time for sampling batok and nextpwr. the delay prevents a false ?battery good? indication caused by alkaline battery recovery that can immediately follow a battery-low switch off. the battery sampling takes place on the ris- ing edge of the 1 hz clock. this clock is derived from the 32.768 khz oscillator. the wakeup pin can be pulsed, but at least one edge must follow the 2 second delay to be recognized. for more information, see the application note ?implementing auto-wakeup on the lh7a4xx series devices? at www.nxp.com. figure 45 shows the recommended components for the nxp LH7A400 32.768 khz external oscillator cir- cuit. figure 46 shows the same for the 14.7456 mhz external oscillator circuit. in both figures, the nand gate represents the internal logic of the chip. note: *vddc = vddcmin figure 41. ad-tft and hr-tft vertical timing diagram lcdsps (vertical sync) lcdhrlp (horizontal sync) lcdvd (lcd data) lcdspl LH7A400-66 timing1:vsw 1.5 s - 4 s 2x h-line l8 t2 r2 table 13. reset ac timing parameter description min. max. unit tosc32 32.768 khz oscillator stabilization time after power on* 550 ms tosc14 14.7456 mhz oscillator stabilization time after wake up 4 ms tureset/tpwrfl nureset/npwrfl puls e width 4 32.768 khz clock periods
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 55 nxp semiconductors figure 42. oscillator start-up figure 43. external reset figure 44. signal timing after reset LH7A400-25 tosc32 vddc vddcmin xtal32 npor tosc14 xtal14 wakeup LH7A400-26 tureset tpwrfl nureset npwrfl 7.8125 ms 2 sec. 7.8125 ms start up wakeup (asynchronous) clken npor hclk stable clock LH7A400-175
LH7A400 32-bit system-on-chip 56 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors figure 45. 32.768 khz external oscillator components and schematic enable xtalin xtalout gnd notes: 1. y1 is a parallel-resonant type crystal. (see table) 2. the nominal values for c1 and c2 shown are for a crystal specified at 12.5 pf load capacitance (cl). 3. the values for c1 and c2 are dependent upon the cystal's specified load capacitance and pcb stray capacitance. 4. r1 must be in the circuit. 5. ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. tolerance for r1, c1, c2 is 5%. gnd 32.768 khz 18 m ? LH7A400-187 parameter description 32.768 khz crystal tolerance aging load capacitance esr (max.) drive level recommended part parallel mode 30 ppm 3 ppm 12.5 pf 50 k ? 1.0 w (max.) mtron sx1555 or equivalent c1 15 pf c2 18 pf r1 y1 internal to the LH7A400 external to the LH7A400 recommended crystal specifications
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 57 nxp semiconductors figure 46. 14.7456 mhz external oscillator components and schematic enable xtalin xtalout gnd notes: 1. y1 is a parallel-resonant type crystal. (see table) 2. the nominal values for c1 and c2 shown are for a crystal specified at 18 pf load capacitance (cl). 3. the values for c1 and c2 are dependent upon the cystal's specified load capacitance and pcb stray capacitance. 4. r1 must be in the circuit. 5. ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. tolerance for r1, c1, c2 is 5%. gnd 14.7456 mhz 1 m ? LH7A400-188 c1 18 pf c2 22 pf r1 y1 internal to the LH7A400 external to the LH7A400 parameter description 14.7456 mhz crystal tolerance stability aging load capacitance esr (max.) drive level recommended part (at-cut) parallel mode 50 ppm 100 ppm 5 ppm 18 pf 40 ? 100 w (max.) mtron sx2050 or equivalent recommended crystal specifications
LH7A400 32-bit system-on-chip 58 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors operating temperature and noise immunity the junction temperature, tj, is the operating tem- perature of the transistors in the integrated circuit. the switching speed of the cmos circuitry within the soc depends partly on tj, and the lower the operating tem- perature, the faster the cmos circuits will switch. increased switching noise generated by faster switch- ing circuits could affect th e overall system stability. the amount of switching noise is directly affected by the application executed on the soc. nxp recommends that users implementing a system to meet industrial temperature standards should use an external oscillator rather than a crystal to drive the sys- tem clock input of the system-on-chip. this change from crystal to oscillator will increase the robustness (i.e., noise immunity of the clock input to the soc). printed circuit b oard layout practices LH7A400 power supply decoupling the LH7A400 has separate power and ground pins for different internal circuitry sections. the vdd and vss pins supply power to i/o buffers, while vddc and vssc supply power to the co re logic, and vdda/vssa supply analog power to the plls. each of the vdd and vddc pins must be provided with a low impedance path to the corresponding board power supply. likewise, the vss, vssa, and vssc pins must be provided with a low impedance path to the board ground. each power supply must be decoupled to ground using at least one 0.1 f high frequency capacitor located as close as possible to a vddx, vssx pin pair on each of the four sides of the chip. if room on the cir- cuit board allows, add one 0.01 f high frequency capacitor near each vddx , vssx pair on the chip. to be effective, the capacitor leads and associated circuit board traces connecting to the chip vddx, vssx pins must be kept to less than half an inch (12.7 mm) per capacitor lead. there must be one bulk 10 f capacitor for each power supply placed near one side of the chip. recommended pll, vdda, vssa filter the vdda pins supply power to the chip pll cir- cuitry. vssa is the ground re turn path for the pll cir- cuit. nxp recommends a low-pass filter attached as shown in figure 47. the values of the inductor and capacitors are not critical. the low-pass filter prevents high frequency noise from adversely affecting the pll circuits. the distance from the ic pin to the high fre- quency capacitor should be as short as possible. unused input signal conditioning floating input signals can cause excessive power consumption. unused inputs without internal pull-up or pull-down resistors should be pulled up or down exter- nally (nxp recommends tying high), to tie the signal to its inactive state. 33 k ? or less is recommended. some gpio signals default to inputs. if the pins that carry these signals are unused, software can program these signals as outputs, eliminating the need for pull- ups or pull-downs. power consumption may be higher than expected until software completes programming the gpio. some LH7A400 inputs have internal pull- ups or pull-downs. if unused, these inputs do not require external conditioning. other circuit board layout practices all outputs have fast rise and fall times. printed cir- cuit trace interconnection length must therefore be reduced to minimize overshoo t, undershoot and reflec- tions caused by transmission line effects of these fast output switching times. this recommendation particu- larly applies to the address and data buses. when considering capacitance, calculations must consider all device loads and capacitances due to the circuit board traces. capacit ance due to the traces will depend upon a number of factors, including the trace width, dielectric material the circuit board is made from and proximity to ground and power planes. attention to power supply decoupling and printed cir- cuit board layout becomes mo re critical in systems with higher capacitive loads. as these capacitive loads increase, transient currents in the power supply and ground return paths also increase. figure 47. vdda, vssa filter circuit LH7A400-189 vdda vddc vssa 22 f 10 h vddc (source) 0.1 f + LH7A400
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 59 nxp semiconductors package specifications figure 48. package outline sot1018-1 (bga256) references outline version european projection issue date iec jedec jeita sot1018-1 sot1018-1 07-07-07 07-07-07 unit a max mm 1.95 0.5 0.3 1.45 1.25 17.2 16.8 15.75 14.75 17.2 16.8 15.75 14.75 15 15 0.1 a 1 dimensions (mm are the original dimensions) bga256: plastic ball grid array package; 256 balls a 2 b 0.55 0.45 d d 1 e e 1 e 1 e 1 e 2 v 0.25 w y 0.15 y 1 0.35 c y c y 1 x 0 5 10 mm scale a b c d e f h k g l j m n p r t 246810121416 13579111315 b e 2 e 1 e e 1/2 e 1/2 e a c b ? v m c ? w m ball a1 index area ball a1 index area e 1 a e d 1 b d detail x a 2 a 1 a
LH7A400 32-bit system-on-chip 60 rev. 01 ? 16 july 2007 preliminary data sheet nxp semiconductors figure 49. package outline sot1020-1 (lfbga256) references outline version european projection issue date iec jedec jeita sot1020-1 sot1020-1 07-07-07 07-07-07 unit a max mm 1.7 0.4 0.3 1.35 1.15 14.1 13.9 14.1 13.9 0.8 12 0.15 0.08 0.1 a 1 dimensions (mm are the original dimensions) lfbga256: plastic low profile fine-pitch ball grid array package; 256 balls 0 5 10 mm scale a 2 b 0.5 0.4 d e e 12 v e 2 e 1 w y 0.12 y 1 c y c y 1 x detail x a a 2 a 1 b a ball a1 index area d e b e 2 e 1 e e 1/2 e 1/2 e a c b ? v m c ? w m a b c d e f h k g l j m n p r t 2 4 6 8 10121416 1 3 5 7 9 11 13 15 ball a1 index area
32-bit system-on-chip LH7A400 preliminary data sheet rev. 01 ? 16 july 2007 61 nxp semiconductors revision history table 14. revision history document id release date data sheet status change notice supersedes LH7A400_n_1 20070716 preliminary data sheet - fast LH7A400 v1-5 5-9-07 modifications: ? first nxp version based on the LH7A400 data sheet of 20070509
nxp semiconductors ? nxp b.v. 2007. all rights reserved. LH7A400 32-bit system-on-chip 1. legal information 1.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 1.2 definitions draft ? the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp se miconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 1.3 disclaimers general ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors pr oduct can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equi pment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other c onditions above those given in the characteristics sections of this documen t is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale ? nxp semiconductors products are sold subject to the general terms and condi tions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or conflict between in formation in this document and such terms and conditions, the latter will prevail. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products th at is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 1.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 2. contact information for additional information, please visit: http://www.nxp.com for sales office addresses, send an email to: salesaddresses@nxp.com document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objectiv e specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docum ent contains the pro duct specification.
important no tice dea r cu st om er, as from june 1 st , 2007 nx p semiconductors has acquired the lh7xxx ar m microcontrollers from sharp mi croe lectro nics. th e followin g ch ange s are ap plica b le to the attache d da ta sheet. in data she e ts where the previou s sharp o r sha r p co rp oratio n referen c e s remai n , plea se use the n e w links as sho w n belo w . for ww w.sh a r ps ma.c om use www.nxp. com/mi cro c o n trolle rs for indicated sale s ad dre s se s use sal e saddresse s@nxp.com (em a il) the co pyrig h t notice at the bottom of each page (or el sewh ere in the docum ent, depen ding on t h e ver s ion) - copy right ? ( year ) by sharp corporation. is repl aced wi th: - ? nxp b.v. ( ye ar ). all rights re se rv ed. if you have any questio n s related to the data sh eet, please co ntact our ne arest sales office via e-mail o r pho ne (detail s via sale sa ddre s ses@nxp. co m ). than k yo u for your coo peratio n and unde rsta ndin g , in addition to that the annex a (attach ed hereto) i s adde d to the document. nx p s e mico ndu ct or s
annex a: disclaimers (11) 1. t001dis100.fm: general (ds, an, um) general ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 2. t001dis101.fm: right to make changes (ds, an, um) right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, includi ng without limitation specifications and product descriptions, at any time and without notice . this document supersedes and replaces all information supplied prior to the publication hereof. 3. t001dis102.fm: suitability for use (ds, an, um) suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. 4. t001dis103.fm: applications (ds, an, um) applications ? applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified us e without further testing or modification. 5. t001dis104.fm: limiting values (ds) limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) may ca use permanent damage to the device. limiting values are stress ratings only and operation of t he device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. 6. t001dis105.fm: terms and conditions of sale (ds) terms and conditions of sale ? nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwi se agreed to in writing by nxp semiconductors. in case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.
7. t001dis106.fm: no offer to sell or license (ds) no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other in dustrial or intellectual property rights. 8. t001dis107.fm: hazardous voltage (ds, an, um; if applicable) hazardous voltage ? although basic supply voltages of the product may be much lower, circuit voltages up to 60 v may appear when operatin g this product, depending on settings and application. customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, asse mbly, test etc. of such application, do so at their own risk. customers agree to fully i ndemnify nxp semiconductors for any damages resulting from or in connection with such hi gh voltages. furthermore, customers are drawn to safety standards (iec 950, en 60 950, cenelec, iso, etc.) and other (legal) requirements applying to such high voltages. 9. t001dis108.2.fm: bare die (ds; if applicable) bare die (if applicable) ? products indicated as bare die are subject to separate specifications and are not tested in accordance with standard testing procedures. product warranties and guarantees as stated in this document are not applicable to bare die products unless such warranties and guarantees are explicitly stated in a valid separate agreement entered into by nxp semiconductors and customer. 10. t001dis109.fm: aec unqualified products (ds, an, um; if applicable) aec unqualified products ? this product has not been qualified to the appropriate automotive electronics council (aec) standard q100 or q101 and should not be used in automotive critical applications, including but not limited to applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semicon ductors accepts no liabilit y for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer?s own risk. 11. t001dis110.fm: suitability for use in auto motive applications only (ds, an, um; if applicable) suitability for use in automotive applications only ? this nxp semiconductors product has been developed for use in automotive applications only. the product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk.

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