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1 pcm3000/3001 49% fpo pcm3000 pcm3001 pcm3000e pcm3001e stereo audio codec 18-bits, serial interface tm features l monolithic 18-bit ds adc and dac l 16- or 18-bit input/output data l stereo adc: single-ended voltage input 64x oversampling high performance: C88db thd+n 94db snr 94db dynamic range digital high-pass filter l stereo dac: single-ended voltage output analog low pass filter 64x oversampling high performance: C90db thd+n 98db snr 97db dynamic range l special features (pcm3000): digital de-emphasis digital attenuation (256 steps) soft mute analog loop back l sample rate: up to 48khz l system clock: 256f s , 384f s , 512f s l single +5v power supply l small package: ssop-28 description the pcm3000/3001 is a low cost single chip stereo audio codec (analog-to-digital and digital-to-analog converter) with single-ended analog voltage input and output. both adcs and dacs employ delta-sigma modula- tion with 64x oversampling. the adcs include a digital decimation filter and the dacs include an 8x oversampling digital interpolation filter. the dacs also include digital attenuation, de-emphasis, infinite zero detection and soft mute to form a complete subsystem. the pcm3000/3001 operates with left- justified, right-justified, i 2 s or dsp data formats. pcm3000 can be programmed with a 3-wire serial interface for special features and data formats. pcm3001 can be pin-programmed for data formats. fabricated on a highly advanced cmos process, the pcm3000/3001 is suitable for a wide variety of cost- sensitive consumer applications where good perfor- mance is required. applications include sampling key- boards, digital mixers, mini-disc recorders, hard-disk recorders, karaoke systems, dsp-based car stereo, dat recorders, and video conferencing. ? 1996 burr-brown corporation pds-1342e printed in u.s.a., january, 2000 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 for most current data sheet and other product information, visit www.burr-brown.com lch in rch in analog front-end delta-sigma modulator digital decimation filter serial interface and mode control digital out digital in mode control system clock lch out rch out low pass filter and output buffer multi-level delta-sigma modulator digital interpolation filter sbas055
2 pcm3000/3001 specifications all specifications at +25 c, v dd = v cc = +5v, f s = 44.1khz, sysclk = 384f s , clkio input, 18-bit data, unless otherwise noted. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. price s and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. notes: (1) pins 16, 17, 18, 22, 25, 26, 27, 28: lrcin, bckin, din, clkio, mc/fmt2, md/fmt1, ml/fmt0, rstb. (2) pins 16, 17, 18, 22: lrcin, bckin, din, clkio (schmitt trigger input). (3) pins 25, 26, 27, 28: mc/fmt2, md/fmt1, ml/fmt0, rstb (schmitt trigger input, 70k w internal pull-up resistor). (4) pin 20: xti. (5) pins 19, 22: dout,clkio. (6) pin 21: xto. (7) refer to application bulletin ab-148 for information relating to operati on at lower sampling frequencies. (8) high pass filter disabled (pcm3000 only) to measure dc offset. (9) f in = 1khz, using audio precision system ii, rms mode with 20khz lpf, 400hz hpf used for performance calculation. (10) with no load on xto and clkio. pcm3000e/3001e parameter conditions min typ max units digital input/output input logic input logic level: v ih (1) 2.0 vdc v il (1) 0.8 vdc input logic current: i in (2) 1 m a input logic current: i in (3) C120 m a input logic level: v ih (4) 0.64 ? v dd vdc v il (4) 0.28 ? v dd vdc input logic current: i in (4) 40 m a output logic output logic level: v oh (5) i out = C1.6ma 4.5 vdc v ol (5) i out = +3.2ma 0.5 vdc output logic level: v oh (6) i out = C3.2ma 4.5 vdc v ol (6) i out = +3.2ma 0.5 vdc clock frequency sampling frequency (f s ) 32 (7) 44.1 48 khz system clock frequency 256f s 8.1920 11.2896 12.2880 mhz 384f s 12.2880 16.9344 18.4320 mhz 512f s 16.3840 22.5792 24.5760 mhz adc characteristics resolution 18 bits dc accuracy gain mismatch channel-to-channel 1.0 5.0 % of fsr gain error 2.0 5.0 % of fsr gain drift 20 ppm of fsr/ c bipolar zero error high-pass filter off (8) 1.7 %of fsr bipolar zero drift high-pass filter off (8) 20 ppm of fsr/ c dynamic performance (9) thd+n: v in = C0.5db f = 1khz C88 C80 db v in = C60db f = 1khz C31 db dynamic range f = 1khz, a-weighted 90 94 db signal-to-noise ratio f = 1khz, a-weighted 90 94 db channel separation 88 92 db digital filter performance passband 0.454f s hz stopband 0.583f s hz passband ripple 0.05 db stopband attenuation C65 db delay time (latency) 17.4/f s sec digital high pass filter response C3db frequency 0.019f s mhz analog input voltage range 0db (full scale) 2.9 vp-p center voltage 2.1 v input impedance 15 k w anti-aliasing filter C3db frequency c ext = 470pf 170 khz
3 pcm3000/3001 pcm3000e/3001e parameter conditions min typ max units specifications (cont.) all specifications at +25 c, v dd = v cc = 5v, f s = 44.1khz, sysclk = 384f s , clkio input, 18-bit data, unless otherwise noted. supply voltage +v dd , +v cc 1, +v cc 2 ...................................................................... +6.5v supply voltage differences ............................................................... 0.1v gnd voltage differences .................................................................. 0.1v digital input voltage ...................................................... C0.3 to v dd + 0.3v analog input voltage ......................................... C0.3 to v cc 1, v cc 2 + 0.3v power dissipation .......................................................................... 300mw input current ................................................................................... 10ma operating temperature range ......................................... C25 c to +85 c storage temperature ...................................................... C55 c to +125 c lead temperature (soldering, 5s) .................................................. +260 c (reflow, 10s) ..................................................... +235 c thermal resistance, q ja .............................................................. 100 c/w absolute maximum ratings electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. dac characteristics resolution 18 bits dc accuracy gain mismatch channel-to-channel 1.0 5.0 % of fsr gain error 1.0 5.0 % of fsr gain drift 20 ppm of fsr/ c bipolar zero error 1.0 % of fsr bipolar zero drift 20 ppm of fsr/ c dynamic performance (9) thd+n: v out = 0db (full scale) C90 C80 db v out = C60db C34 db dynamic range eiaj a-weighted 90 97 db signal-to-noise ratio (idle channel) eiaj a-weighted 92 98 db channel separation 90 95 db digital filter performance passband 0.445f s hz stopband 0.555f s hz passband ripple 0.17 db stopband attenuation C35 db delay time 11.1/f s sec analog output voltage range 0.62 ? v cc vp-p center voltage 0.5 ? v cc vdc load impedance ac load 5 k w analog low pass filter frequency response f = 20khz C0.16 db power supply requirements voltage range: v cc 4.5 5 5.5 vdc v dd 4.5 5 5.5 vdc supply current: +i cc , +i dd (10) v cc = v dd = 5v 32 50 ma power dissipation v cc = v dd = 5v 160 250 mw temperature range operation C25 +85 c storage C55 +125 c package specified drawing temperature package ordering transport product package number range marking number (1) media pcm3000e ssop-28 324 C25 c to +85 c pcm3000e pcm3000e rails " " " " " pcm3000e/2k tape and reel pcm3001e ssop-28 324 C25 c to +85 c pcm3001e pcm3001e rails " " " " " pcm3001e/2k tape and reel notes: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k indicates 2000 de vices per reel). ordering 2000 pieces of pcm3000e/2k will get a single 2000-piece tape and reel. package/ordering information
4 pcm3000/3001 v in l v cc 1 agnd1 v ref l v ref r v in r c in pr c in nr c in nl c in pl vcom v out r agnd2 v cc 2 rstb fmt0 fmt1 fmt2 dgnd v dd clkio xto xti dout din bckin lrcin v out l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v in l v cc 1 agnd1 v ref l v ref r v in r c in pr c in nr c in nl c in pl vcom v out r agnd2 v cc 2 rstb ml md mc dgnd v dd clkio xto xti dout din bckin lrcin v out l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pin configurationpcm3000 top view ssop pin configurationpcm3001 top view ssop pin name i/o description 1v in l in adc analog input, lch 2v cc 1 adc analog power supply 3 agnd1 adc analog ground 4v ref l adc input reference, lch 5v ref r adc input reference, rch 6v in r in adc analog input, rch 7c in pr adc anti-alias filter capacitor (+), rch 8c in nr adc anti-alias filter capacitor (C), rch 9c in nl adc anti-alias filter capacitor (C), lch 10 c in pl adc anti-alias filter capacitor (+), lch 11 vcom dac output common 12 v out r out dac analog output, rch 13 agnd2 dac analog ground 14 v cc 2 dac analog power supply 15 v out l out dac analog output, lch 16 lrcin in sample rate clock input (f s ) (2) 17 bckin in bit clock input (2) 18 din in data input (2) 19 dout out data output 20 xti in oscillator input 21 xto out oscillator output 22 clkio i/o buffered output of oscillator or external clock input (2) 23 v dd digital power supply 24 dgnd digital ground 25 mc/fmt2 in serial control bit clock (pcm3000)/data format control 2 (pcm3001) (1, 2) 26 md/fmt1 in serial control data (pcm3000)/data format control 1 (pcm3001) (1, 2) 27 ml/fmt0 in serial control strobe pulse/data format control 0 (pcm3001) (1, 2) 28 rstb in reset (1, 2) notes: (1) with 70k w typical internal pull-up resistor. (2) schmitt trigger input. pin assignments pcm3000/3001
5 pcm3000/3001 typical performance curves adc section at t a = +25 c, v cc = v dd = +5v, f in = 1.0khz, f s = 44.1khz, 18-bit data, v in = 2.9vp-p, and sysclk = 384f s , unless otherwise noted. thd+n vs temperature temperature (?) thd+n at 0db (%) 0.01 0.008 0.006 0.004 0.002 ?5 0 25 50 75 85 100 thd+n at ?0db (%) 4.0 3.0 2.0 1.0 0 ?0db 0db thd+n vs power supply v cc (v) thd+n at 0db (%) 0.01 0.008 0.006 0.004 0.002 4.5 4.75 5.0 5.25 5.5 thd+n at ?0db (%) 4.0 3.0 2.0 1.0 0 ?0db 0db thd+n vs system clock and sampling frequency system clock thd+n at 0db (%) 0.01 0.008 0.006 0.004 0.002 256f s 384f s 512f s thd+n at ?0db (%) 4.0 3.0 2.0 1.0 0 44.1khz 44.1khz 48khz 48khz ?0db 0db snr and dynamic range vs power supply v cc (v) snr (db) 98 96 94 92 90 4.5 4.75 5.0 5.25 5.50 dynamic range (db) 98 96 94 92 90 snr dynamic range thd+n vs output data resolution resolution thd+n at 0db (%) thd+n at ?0db (%) 0.01 0.008 0.006 0.004 0.002 16-bit 18-bit 4.0 3.0 2.0 1.0 0 0db ?0db
6 pcm3000/3001 typical performance curves dac section at t a = +25 c, v cc = v dd = +5v, f in = 1.0khz, f s = 44.1khz, 18-bit data, and sysclk = 384f s , unless otherwise noted. thd+n vs temperature temperature (?) thd+n at 0db (%) 0.01 0.008 0.006 0.004 0.002 ?5 0 25 50 75 85 100 thd+n at ?0db (%) 4.0 3.0 2.0 1.0 0 ?0db 0db thd+n vs power supply v cc (v) thd+n at 0db (%) 0.01 0.008 0.006 0.004 0.002 4.5 4.75 5.0 5.25 5.5 thd+n at ?0db (%) 4.0 3.0 2.0 1.0 0 ?0db 0db snr and dynamic range vs power supply v cc (v) snr (db) 100 98 96 94 92 4.5 4.75 5.0 5.25 5.50 dynamic range (db) 100 98 96 94 92 dynamic range snr thd+n vs system clock and sampling frequency system clock thd+n at 0db (%) 0.01 0.008 0.006 0.004 0.002 256f s 384f s 512f s thd+n at ?0db (%) 4.0 3.0 2.0 1.0 0 44.1khz 44.1khz 48khz 48khz ?0db 0db thd+n vs input data resolution resolution thd+n at 0db (%) thd+n at ?0db (%) 0.01 0.008 0.006 0.004 0.002 16-bit 18-bit 4.0 3.0 2.0 1.0 0 0db ?0db
7 pcm3000/3001 high pass filter response normalized frequency (x f s /1000 hz) amplitude (db) 0.2 0.0 ?.2 ?.4 ?.6 ?.8 ?.0 1234 0 typical performance curves at t a = +25 c, v cc = v dd = +5v, and sysclk = 384f s , unless otherwise noted. adc digital filter stopband attenuation characteristics normalized frequency (x f s hz) amplitude (db) 0 ?0 ?0 ?0 ?0 ?00 0.25 0.50 0.75 1.00 0 passband ripple characteristics normalized frequency (x f s hz) amplitude (db) 0.2 0.0 ?.2 ?.4 ?.6 ?.8 ?.0 0.125 0.250 0.375 0.500 0 overall characteristics normalized frequency (x f s hz) amplitude (db) 0 ?0 ?00 ?50 ?00 8162432 0 anti-aliasing filter passband frequency response (c ext = 470pf, 1000pf) frequency (hz) amplitude (db) 0.2 0.0 ?.2 ?.4 ?.6 ?.8 ?.0 10 100 1k 10k 100k 0 470pf 1000pf anti-aliasing filter overall frequency response (c ext = 470pf, 1000pf) frequency (hz) amplitude (db) 0 ?0 ?0 ?0 ?0 ?0 10 100 1k 10k 100k 1m 10m 0 470pf 1000pf anti-aliasing filter
8 pcm3000/3001 typical performance curves at t a = +25 c, v cc = v dd = +5v, and sysclk = 384f s , unless otherwise noted. dac digital filter 0 0.4536f s 1.3605f s 2.2675f s 3.1745f s 4.0815f s 0 ?0 ?0 ?0 ?0 ?00 db overall frequency characteristic frequency (hz) passband ripple characteristic 0 ?.2 ?.4 ?.6 ?.8 ? 0 0.1134f s 0.2268f s 0.3402f s 0.4535f s db frequency (hz) de-emphasis error (3khz) 0 3628 7256 10884 14512 0 4999.8375 9999.675 14999.5125 19999.35 0 5442 10884 16326 21768 frequency (hz) 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 de-emphasis error (44.1khz) frequency (hz) de-emphasis error (48khz) frequency (hz) error (db) error (db) error (db) de-emphasis frequency response (3khz) 0 5k 10k 15k 20k 25k frequency (hz) 0 ? ? ? ? ?0 ?2 de-emphasis frequency response (44.1khz) 0 5k 10k 15k 20k 25k frequency (hz) 0 ? ? ? ? ?0 ?2 de-emphasis frequency response (48khz) 0 5k 10k 15k 20k 25k frequency (hz) 0 ? ? ? ? ?0 ?2 level (db) level (db) level (db) 1.0 0.5 0 ?.5 ?.0 db 20 frequency (hz) 100 1k 10k 24k internal analog filter frequency response (20hz~24khz, expanded scale) analog output filter 10 5 0 ? ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 10 100 1k 10k 100k 1m 10m frequency (hz) db ?0 internal analog filter frequency response (10hz~10mhz)
9 pcm3000/3001 block diagram figure 1. analog front-end (single-channel). 15k w 1k w 470pf 9 10 v in l v ref l c in pl c in nl 1 4 1k w delta-sigma modulator (+) (? v ref + + 2.2? 4.7? interpolation filter 8x oversampling interpolation filter 8x oversampling multi-level delta-sigma modulator multi-level delta-sigma modulator clock/osc manager reset rstb clkio xto agnd2 v cc 2 agnd1 v cc 1 loop control reference mode control interface md (fmt1) (1) ml (fmt0) (1) mc (fmt2) (1) serial data interface dout bckin lrcin din c in pl c in nl v in l v ref l v ref r v in r c in nr c in pr v out l vcom v out r power supply xti dgnd v dd analog low-pass filter analog low-pass filter decimation and high pass filter delta-sigma modulator (? (+) analog front-end circuit decimation and high pass filter delta-sigma modulator adc dac (+) (? analog front-end circuit note: (1) fmt0, fmt1, fmt2 are for pcm3001 only.
10 pcm3000/3001 pcm audio interface the three-wire digital audio interface for pcm3000/3001 is on lrcin (pin 16), bckin (pin 17), din (pin 18), and dout (pin 19). the pcm3000/3001 can operate with seven different data formats. for the pcm3000, these for- mats are selected through program register 3 in the software mode. for pcm3001, data formats are selected by pin-strapping the three format pins. figures 2, 3 and 4 illustrate audio data input/output format and timing. pcm3000/3001 can accept 32, 48, or 64 bit clocks (bckin) in one clock of lrcin. only formats 0, 2, and 6 can be selected when 32 bit clocks/lrcin are applied. figure 2. audio data input/output format. msb l?h r?h l?h r?h lsb lrcin bckin format 0: fmt[2:0] = ?00 din msb lsb dac: 16-bit, msb-first, right-justified adc: 16-bit, msb-first, left-justified 1 16 2 3 14 15 16 123 14 15 16 msb lsb lrcin bckin dout msb lsb 123 14 15 16 123 14 15 16 1 msb l?h r?h l?h r?h lsb lrcin bcin format 2: fmt[2:0] = ?10 din msb lsb dac: 16-bit, msb-first, right-justified adc: 16-bit, msb-first, right-justified 1 16 16 23 14 15 16 123 14 15 16 msb lsb lrcin bcin dout msb lsb 123 14 15 16 123 14 15 16 msb l?h r?h l?h r?h lsb lrcin bckin format 1: fmt[2:0] = ?01 din msb lsb dac: 18-bit, msb-first, right-justified adc: 18-bit, msb-first, left-justified 1 18 2 3 16 17 18 123 16 17 18 msb lsb lrcin bckin dout msb lsb 123 16 17 18 123 16 17 18 1
11 pcm3000/3001 figure 3. audio data input/output format. msb l-ch r-ch l-ch r-ch lsb lrcin bckin format 3: fmt[2:0] = "011" din msb lsb dac: 18-bit, msb-first, right-justified adc: 18-bit, msb-first, right-justified 1 18 18 23 16 17 18 123 16 17 18 msb lsb lrcin bckin dout msb lsb 123 16 17 18 123 16 17 18 msb l_ch r-ch l-ch r-ch lsb lrcin bckin format 5: fmt[2:0] = "101" din msb lsb dac: 18-bit, msb-first, i 2 s adc: 18-bit, msb-first, i 2 s 123 16 17 18 123 16 17 18 msb lsb lrcin bckin dout msb lsb 123 16 17 18 123 16 17 18 l-ch r-ch l-ch r-ch lsb lrcin bckin format 4: fmt[2:0] = "100 " din msb lsb dac: 18-bit, msb-first, left-justified adc: 18-bit, msb-first, left-justified 123 16 17 18 123 16 17 18 msb lsb lrcin bckin dout msb lsb 123 16 17 18 123 16 17 18 1 1 l-ch r-ch format 6: fmt[2:0] = "110" adc: 16-bit, msb-first, dsp-frame lrcin bckin dout l-ch r-ch dac: 16-bit, msb-first, dsp-frame msb lsb lrcin bckin din msb lsb 16 1 2 345 678 91011 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 msb lsb msb lsb 16 1 2 345 678 91011 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
12 pcm3000/3001 figure 4. audio data input/output timing. 256f s , 384f s , or 512f s . when a 384f s or 512f s system clock is used, the clock is divided into 256f s automatically. the 256f s clock is used to operate the digital filters and the modulators. table i lists the relationship of typical sampling frequencies and system clock frequencies, and figures 5 and 6 illustrate the typical system clock connections and external system clock timing. sampling rate frequency system clock frequency (khz) (mhz) 256f s 384f s 512f s 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9340 22.5792 48 12.2880 18.4320 24.5760 table i. system clock frequencies. t bch t bcy t bcl t lb t dih t dis t lrp t bl t ldo t bdo bckin lrcin din dout 1.4v 1.4v 1.4v 0.5 x v dd bckin pulse cycle time t bcy 300ns (min) bckin pulse width high t bch 120ns (min) bckin pulse width low t bcl 120ns (min) bckin rising edge to lrcin edge t bl 40ns (min) lrcin edge to bckin rising edge t lb 40ns (min) lrcin pulse width t lrp t bcy (min) din set-up time t dis 40ns (min) din hold time t dih 40ns (min) dout delay time to bckin falling edge t bdo 40ns (max) dout delay time to lrcin edge t ldo 40ns (max) rising time of all signals t rise 20ns (max) falling time of all signals t fall 20ns (max) system clock the system clock for the pcm3000/3001 must be either 256f s , 384f s or 512f s , where f s is the audio sampling frequency. the system clock can be either a crystal oscillator placed between xti (pin 20) and xto (pin 21), or an external clock input. if an external clock is used, the clock is provided to either xti or clkio (pin 22), and xto is open. the pcm3000/3001 has an xti clock detection circuit which senses if an xti clock is operating. when the external clock is delivered to xti, clkio is a buffered output of xti. when xti is connected to ground, the external clock must be tied to clkio. for best performance, the external clock input 2 circuit in figure 5 is recommended. the pcm3000/3001 also has a system clock detection circuit which automatically senses if the system clock is operating at
13 pcm3000/3001 figure 5. system clock connections. t clkih system clock pulse width high t clkih 12ns (min) system clock pulse width low t clkil 12ns (min) t clkil 3.2v xti or clkio 1.4v 2.0v xti clkio 0.8v figure 6. external system clock timing. c 1 c 2 c 1 = c 2 = 10 to 33pf 256f s internal system clock clock divider 256f s internal system clock clock divider xti r x?al xto pcm3000/3001 clkio crystal resonator connection (x?al must be fundamental made, parallel resonant) external clock (cmos i/f) external clock (ttl i/f) xti xto r pcm3000/3001 external clock input 1: (xto is open) clkio 256f s internal system clock clock divider xti xto r pcm3000/3001 external clock input 2: (xto is open) clkio
14 pcm3000/3001 power-on reset both the pcm3000 and pcm3001 have internal power-on reset circuitry. power-on reset occurs when system clock (xti or clkio) is active and v dd > 4.0v. for the pcm3001, the system clock must complete a minimum of 3 complete cycles prior to v dd > 4.0v to ensure proper reset operation. the initialization sequence requires 1024 system cycles for completion, as shown in figure 7. figure 10 shows the state of the dac and adc outputs during and after the reset sequence. external reset the pcm3000 and pcm3001 include a reset input, rstb (pin 28). as shown in figure 8, the external reset signal must drive rstb low for a minimum of 40 nanoseconds while system clock is active in order to initiate the reset sequence. initialization starts on the rising edge of rstb, and requires 1024 system clock cycles for completion. figure 10 shows the state of the dac and adc outputs during and after the reset sequence. figure 9. control data input format. b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ml mc md figure 7. internal power-on reset timing. 1024 system clock periods reset reset removal 4.4v 4.0v 3.6v v dd internal reset system clock (xti or clkio) figure 8. external forced reset timing. 1024 system clock periods reset reset removal system clock (xti or clkio) internal reset rstb t rst t rst = 40ns minimum
15 pcm3000/3001 synchronization with the digital audio system pcm3000/3001 operates with lrcin synchronized to the system clock. the codec does not require any specific phase relationship between lrcin and the system clock, but there must be synchronization. if the synchronization be- tween the system clock and lrcin changes more than 6 bit clocks (bckin) during one sample (lrcin) period because of phase jitter on lrcin, internal operation of the dac will stop within 1/f s , and the analog output will be forced to bipolar zero (v cc /2) until the system clock is re-synchronized to lrcin. internal operation of the adc will also stop with 1/f s , and the digital output codes will be set to bipolar zero until re-synchronization occurs. if lrcin is synchronized with 5 or less bit clocks to the system clock, operation will be normal. figure 11 illustrates the effects on the output when synchro- nization is lost. before the outputs are forced to bipolar zero (<1/f s seconds), the outputs are not defined and some noise may occur. during the transitions between normal data and undefined states, the output has discontinuities, which will cause output noise. figure 11. dac output and adc output when synchronization is lost. figure 10. dac output and adc output for reset and power-down. normal normal synchronous asynchronous within 1/f s synchronous normal normal (1) zero 32/f s undefined data undefined data undefined data vcom (= 1/2 x v cc 2) 22.2/f s state of synchronization dac v out adc dout note: (1) the hpf transient response (exponentially attenuationed signal with 200ms time constant) appears initally. reset internal reset dac v out adc dout zero vcom (= 1/2 x v cc 2) 32/f s 4096/f s reset removal or power-down (1) off (2) notes: (1) power-down is for pcm3000 only. (2) the hpf transient response (exponentially attenuationed signal with 200ms time constant) appears intially.
16 pcm3000/3001 operational control pcm3000 can be controlled in a software mode with a three- wire serial interface on mc (pin 25), md (pin 26), and ml b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 register 0 res res res res res a1 a0 ldl al7 al6 al5 al4 al3 al2 al1 al0 register 1 res res res res res a1 a0 ldr ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 register 2 res res res res res a1 a0 pdwn byps res atc izd out dm1 dm0 mut register 3 res res res res res a1 a0 res res res lop fmt2 fmt1 fmt0 lrp res mapping of program registers figure 12. control data input timing. mc pulse cycle time t mcy 100ns (min) mc pulse width low t mcl 40ns (min) mc pulse width high t mch 40ns (min) md setup time t mds 40ns (min) md hold time t mdh 40ns (min) ml low level time t mll 40ns + 1sysclk (min) ml high level time t mlh 40ns + 1sysclk (min) ml setup time t mls 40ns (min) ml hold time t mlh 40ns (min) sysclk: 1/256f s or 1/384f s or 1/512f s 1.4v 1.4v 1.4v ml mc md t mll t mhh t mch t mcl t mds t mcy t mls t mlh t mdh lsb function adc/dac default (pcm3000) audio data format (7 selectable formats) adc/dac dac: 16-bit, msb-first, right-justified adc: 16-bit, msb-first, left-justified lrcin polarity adc/dac left/right = high/low loop back control adc/dac off left channel attenuation dac 0db right channel attenuation dac 0db attenuation control dac left channel and right channel = individual control infinite zero detection dac off dac output control dac output enabled soft mute control dac off de-emphasis (off, 32khz, 44.1khz, 48khz) dac off power down control adc off high pass filter operation adc on table ii. selectable functions. (pin 27). table ii indicates selectable functions, and figures 9 and 12 illustrate control data input format and timing. the pcm3001 only allows for control of data format.
17 pcm3000/3001 register bit name name description register 0 a (1:0) register address 00 res reserved, should be set to 0 ldl dac attenuation data load control for lch al (7:0) attenuation data for lch register 1 a (1:0) register address 01 res reserved, should be set to 0 ldr dac attenuation data load control for rch ar (7:0) dac attenuation for rch register 2 a (1:0) register address 10 res reserved, should be set to 0 pdwn adc power down control byps adc high-pass filter operation control atc dac attenuation data mode control izd dac infinite zero detection circuit control out dac output enable control dem (1:0) dac de-emphasis control mut lch and rch soft mute control register 3 a (1:0) register address 11 res reserved, should be set to 0 lop adc/dac analog loop-back control fmt (2:0) adc/dac audio data format selection lrp adc/dac polarity of lr-clock selection table iii. functions of the registers. program register (pcm3000) the software mode allows the user to control special functions. pcm3000s special functions are controlled using four pro- gram registers which are 16 bits long. there are four distinct registers, with bits 9 and 10 determining which register is in use. table iii describes the functions of the four registers. program register 0 a (1:0): bit 10, 9 register address these bits define the address for register 0: a1 a0 0 0 register 0 res: bit 11 : 15 reserved these bits are reserved and should be set to 0. ldl: bit 8 dac attenuation data load control for left channel this bit is used to simultaneously set analog outputs of the left and right channels. the output level is controlled by al (7:0) attenuation data when this bit is set to 1. when set to 0, the new attenuation data will be stored into a register, and the output level will remain at the previous attenuation level. the ldr bit in register 1 has the equivalent function as ldl. when either ldl or ldr is set to 1, the output level of the left and right channels are simultaneously con- trolled. al (7:0): bit 7 :0 dac attenuation data for left channel al7 and al0 are msb and lsb, respectively. the attenuation level (att) is given by: att = 20 x log 10 (att data/256) (db) al (7:0) attenuation level 00h C db (mute) 01h C48.16db :: feh C0.07db ffh 0db (default) program register 1 a (1:0): register address these bits define the address for register 1: a1 a0 0 1 register 1 res: bit 15 : 11 reserved these bits are reserved and should be set to 0 ldr: bit 8 dac attenuation data load control for right channel this bit is used to simultaneously set analog outputs of the left and right channels. the output level is controlled by ar (7:0) attenuation data when this bit is set to 1. when set to 0, the new attenuation data will be stored into a register, and the output level will remain at the previous attenuation level. the ldl bit in register 0 has the equivalent function as ldr. when either ldl or ldr is set to 1, the output level of the left and right channels are simultaneously con- trolled. ar (7:0): bit 7 : 0 dac attenuation data for right channel ar7 and ar0 are msb and lsb respectively. see register 0 for the attenuation formula. program register 2 a (1:0): bit 10, 9 register address these bits define the address for register 2: a1 a0 1 0 register 2 res: bit 15:11, 6 reserved these bits are reserved and should be set to 0. pdwn: bit 8 adc power-down control this bit places the adc section in a power-down mode, forcing the output data to all zeroes. this has no effect on the dac section. pdwn 0 power down mode disabled (default) 1 power down mode enabled
18 pcm3000/3001 program register 3 a (1:0): bit 10, 9 register address these bits define the address for register 3: a1 a0 1 1 register 3 res: bit 15:11, 8:6, 0 reserved these bits are reserved, and should be set to 0. fmt (2:0) bit 4:2 audio data format select these bits determine the input and output audio data formats. (default: fmt [2:0] = 000 h ) fmt2 fmt1 fmt0 dac adc data format data format 0 0 0 16-bit, msb-first, 16-bit, msb-first, right-justified left-justified 0 0 1 18-bit, msb-first, 18-bit, msb-first, right-justified left-justified 0 1 0 16-bit, msb-first, 16-bit, msb-first, right-justified right-justified 0 1 1 18-bit, msb-first, 18-bit, msb-first, right-justified right-justified 1 0 0 16-/18-bit, msb-first, 18-bit, msb-first, left-justified left-justified 1 0 1 16-/18-bit, msb-first, i 2 s 18-bit, msb-first, i 2 s 1 1 0 16-bit, msb-first, 16-bit, msb-first, dsp-frame dsp-frame 1 1 1 reserved reserved lop: bit 5 adc to dac loop-back control when this bit is set to 1, the adcs audio data is sent directly to the dac. the data format will default to i 2 s. in format 6 (dsp frame), loop- back is not supported. lop 0 loop-back disable (default) 1 loop-back enable lrp: bit 1 polarity of lrcin applies only to formats 0 through 4. lrp 0 left-channel is h, right-channel is l. (default) 1 left-channel is l, right-channel is h. pcm3001 data format control the input and output data formats are controlled by pins 27 (fmt0), 26 (fmt1), and 25 (fmt2). set these pins to the same values shown for the bit-mapped pcm3000 controls in program register 3. byps: bit 7 adc high-pass filter bypass control this bit determines enables or disables the high- pass filter for the adc. byps 0 high-pass filter enabled (default) 1 high-pass filter disabled (bypassed) atc: bit 5 dac attenuation channel control when set to 1, the register 0 attenuation data can be used for both dac channels. in this case, the register 1 attenuation data is ig- nored. atc 0 individual channel attenuation data control (default) 1 common channel attenuation data control izd: bit 4 dac infinite zero detection circuit control this bit enables the infinite zero detection circuit in pcm3000. when enabled, this circuit will dis- connect the analog output amplifier from the delta- sigma dac when the input is continuously zero for 65,536 consecutive cycles of bckin. izd 0 infinite zero detection disabled (default) 1 infinite zero detection enabled out: bit 3 dac output enable control when set to 1, the outputs are forced to v cc /2 (bipolar zero). in this case, all registers in pcm3000 hold the present data. therefore, when set to 0, the outputs return to the previous programmed state. out 0 dac outputs enabled (default normal operation) 1 dac outputs disabled (forced to bpz) dm (1:0):bit 2,1 dac de-emphasis control these bits select the de-emphasis mode as shown below: dm1 dm0 0 0 de-emphasis off (default) 0 1 de-emphasis 48khz on 1 0 de-emphasis 44.1khz on 1 1 de-emphasis 32khz on mut: bit 0 dac soft mute control when set to 1, both left and right-channel dac outputs are muted at the same time. this muting is done by attenuating the data in the digital filter, so there is no audible click noise when soft mute is turned on. mut 0 mute disable (default) 1 mute enable
19 pcm3000/3001 figure 13. typical connection diagram for pcm3000/3001. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 470pf 470pf + 4.7? 4.7? + 2.2? (2) + 2.2? (2) + 10 to 33pf 10? + register control interface reference bias analog front-end decimation filter interpolation filter lpf and buffer lpf and buffer digital audio interface analog front-end clk/osc manager delta-sigma delta-sigma post low-pass filter post low-pass filter (1) (1) (1) serial control or format control digital audio data reset line in left-channel +5v line in right-channel line out right-channel line out left-channel notes: (1) bypass capacitor = 0.1? to 10?. (2) the input capacitor affects the pole of the hpf. example: 2.2? sets the cut-off frequency to 4.8hz, with a 66ms time constant. application and layout considerations power supply bypassing the digital and analog power supply lines to pcm3000/ 3001 should be bypassed to the corresponding ground pins with both 0.1 m f ceramic and 10 m f tantalum capacitors as close to the device pins as possible. although pcm3000/ 3001 has three power supply lines to optimize dynamic performance, the use of one common power supply is generally recommended to avoid unexpected latch-up or pop noise due to power supply sequencing problems. if separate power supplies are used, back-to-back diodes are recom- mended to avoid latch-up problems. grounding in order to optimize dynamic performance of pcm3000/ 3001, the analog and digital grounds are not internally connected. pcm3000/3001 performance is optimized with a single ground plane for all returns. it is recommended to tie all pcm3000/3001 ground pins with low impedance con- nections to the analog ground plane. pcm3000/3001 should reside entirely over this plane to avoid coupling high fre- quency digital switching noise into the analog ground plane. voltage input pins a tantalum or aluminum electrolytic capacitor, between 2.2 m f and 10 m f, is recommended as an ac-coupling capacitor at the inputs. combined with the 15k w characteristic input impedance, a 2.2 m f coupling capacitor will establish a 4.8hz cutoff frequency for blocking dc. the input voltage range can be increased by adding a series resistor on the analog input line. this series resistor, when combined with the 15k w input impedance, creates a voltage divider and enables larger input ranges. v ref inputs a 4.7 m f to 10 m f tantalum capacitor is recommended be- tween v ref l, v ref r, and agnd to ensure low source impedance for the adcs references. these capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the adc reference. c in p and c in n inputs a 470pf to 1000pf film or npo ceramic capacitor is recom- mended between c in pl and c in nl, c in pr, and c in nr to create an anti-alias filter, which will have an 170khz to 80khz cut-off frequency. these capacitors should be located as close as possible to the c in p and c in n pins to avoid introducing undesirable noise or dynamic errors into the delta-sigma modulator.
20 pcm3000/3001 vcom inputs a 4.7 m f to 10 m f tantalum capacitor is recommended be- tween vcom and agnd to ensure low source impedance of the dac output common. this capacitor should be located as close as possible to the vcom pin to reduce dynamic errors on the dac common. system clock the quality of the system clock can influence dynamic performance of both the adc and dac in the pcm3000/ 3001. the duty cycle, jitter, and threshold voltage at the system clock input pin must be carefully managed. when power is supplied to the part, the system clock, bit clock (bckin) and a word clock (lcrin) should also be supplied simultaneously. failure to supply the audio clocks will result in a power dissipation increase of up to three times normal dissipation and may degrade long term reliability if the maximum power dissipation limit is exceeded. theory of operation adc section the pcm3000/3001 adc consists of a bandgap reference, a stereo single-to-differential converter, a fully differential 5th-order delta-sigma modulator, a decimation filter (includ- ing digital high pass), and a serial interface circuit. the block diagram in this data sheet illustrates the architecture of the adc section, figure 1 shows the single-to-differential converter, and figure 14 illustrates the architecture of the 5th-order delta-sigma modulator and transfer functions. an internal high precision reference with two external ca- pacitors provides all reference voltages which are required by the adc, which defines the full scale range for the converter. the internal single-to-differential voltage con- verter saves the space and extra parts needed for external circuitry required by many delta-sigma converters. the internal full differential signal processing architecture pro- vides a wide dynamic range and excellent power supply rejection performance. the input signal is sampled at 64x oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying anti-alias filtering requirements. the 5th-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator and a feedback loop consisting of a one-bit dac. the delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. the high order of the modulator enables it to randomize the modulator out- puts, reducing idle tone levels. the 64f s one-bit data stream from the modulator is con- verted to 1f s 18-bit data words by the decimation filter, which also acts as a low pass filter to remove the shaped quantization noise. the dc components are removed by a high pass filter function contained within the decimation filter. theory of operation dac section the delta-sigma dac section of pcm3000/3001 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. this section converts the oversampled input data to 5-level delta-sigma format. a block diagram of the 5-level delta- sigma modulator is shown in figure 15. this 5-level delta- sigma modulator has the advantage of improved stability and reduced clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. the combined oversampling rate of the delta-sigma modu- lator and the internal 8x interpolation filter is 64f s for a 256f s system clock. the theoretical quantization noise per- formance of the 5-level delta-sigma modulator is shown in figure 16.
21 pcm3000/3001 figure 16. quantization noise spectrum. out 64f s (256f s ) in 8f s 18-bit + + + 4 3 2 1 0 5-level quantizer + + z ? + + z ? + + z ? figure 15. 5-level ds modulator block diagram. 3rd order ds modulator frequency (khz) gain (?b) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 ?40 ?50 0 5 10 15 20 25 30 + + + + + 5th sw-cap integrator 4th sw-cap integrator 3rd sw-cap integrator 2nd sw-cap integrator 1st sw-cap integrator + + + + + + 1-bit dac h(z) qn(z) analog in x(z) digital out y(z) y(z) = stf(z) ?x(z) + ntf(z) ?qn(z) signal transfer function noise transfer function stf(z) = h(z) / [1 + h(z)] ntf(z) = 1/ [1 + h(z)] comparator figure 14. simplified 5th-order delta-sigma modulator.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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