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pin functions a0-14 address inputs d0-31 data inputs/outputs cs1-4 chip select oe output enable we1-4 write enable nc no connect v cc power (+5v) gnd ground 1 12 23 view from above 213 24 3 14 25 4 15 26 5 16 27 6 17 28 7 18 29 8 19 30 9 20 31 10 21 32 11 22 33 34 45 56 35 46 57 36 47 58 37 48 59 38 49 60 39 50 61 40 51 62 41 52 63 42 53 64 43 54 65 44 55 66 d8 we2 d15 d9 cs2 d14 d10 gnd d13 a13 d11 d12 a14 a10 oe a11 nc a12 we1 nc vcc d7 d0 cs1 d6 d1 nc d5 d2 d3 d4 d24 vcc d31 d25 cs4 d30 d26 we4 d29 a6 d27 d28 a7 a3 a0 nc a4 a1 a8 a5 a2 a9 we3 d23 d16 cs3 d22 d17 gnd d21 d18 d19 d20 nc nc 32k x 32 eepr 32k x 32 eepr 32k x 32 eepr 32k x 32 eepr 32k x 32 eepr om module om module om module om module om module puma 2e1000-70/90/12 issue 4.4 : january 2001 d16~23 d0~7 d8~15 d24~31 cs1 cs2 cs3 cs4 oe we1 we4 we3 we2 a0~a14 32k x 8 eeprom 32k x 8 32k x 8 32k x 8 eeprom eeprom eeprom block diagram pin definition description the puma 2e1000 is a 1mbit high speed eeprom module user configurable as 32kx32, 64kx16 or 128kx8. available with access times of 70, 90 & 120ns the device has an industry standard ceramic 66 pin p.g.a footprint. the device features byte and page write facility, 10,000 write erase cycle capability and data retention time of 10 years. the device may be screened in accordance with mil-std-883 hmp ltd, west chirton, north shields, tyne & wear ne29 8se england tel. (+44) 191 293 0500 fax. (+44) 191 259 0997 1,048,576 bit cmos high speed eeprom features very fast access times of 70/90/120 ns. user configurable as 8 / 16 / 32 bit wide. upgradeable footprint. operating power 1760 mw (max). standby power 1320 mw (max). package suitable for thermal ladder applications. single byte and page write operation. data polling and toggle bit for end of write detection. hardware and software data protection. may be screened in accordance with mil-std-883.
issue 4.4 : january 2001 puma 2e1000-70/90/12 2 absolute maximum ratings (1) temperature under bias t bias -55 to +125 c storage temperature t stg -65 to +150 c all input voltages (including n.c. pins) with respect to gnd v t -0.6 to +6.25 v all output voltages with respect to gnd v out -0.6 to v cc +0.6 v voltage on oe and a9 with respect to gnd v oea -0.6 to +13.5 v notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated below is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc operating conditions dc electrical characteristics (v cc =5.0v10%, t a =-55 to +125c) parameter symbol test condition min typ max unit input leakage current address, oe i li1 0v v in v cc +1v - - 40 a cs1~4, we1~4 i li2 as above. --10a output leakage current i lo cs1~4=v ih , v i/o =gnd to vcc --40a operating supply current i cc32 f=5mhz, i i/o =0ma - - 320 ma standby supply current i sb1 2.0v cs1~4 v cc +1v - - 240 ma output low voltage v ol i ol = 6.0ma - - 0.45 v output high voltage v oh i oh = -4.0ma 2.4 - - v recommended operating conditions parameter symbol min typ max dc power supply voltage v cc 4.5 5.0 5.5 v input low voltage v il -0.1 - 0.8 v input high voltage v ih 2.0 - v cc +1 v operating temp range t a 0 - 70 c t ai -40 - 85 c (2e1000i) t am -55 - 125 c (2e1000m, mb) capacitance (v cc =5v10%,t a =25 c) parameter symbol test condition typ max unit input capacitance: c in v in =0v 26 34 pf i/o capacitance: c i/o v i/o =0v, 8 bit mode 42 58 pf 645 w 100pf i/o pin 1.76v ac test conditions output test load * input pulse levels: 0v to 3.0v * input rise and fall times: 5ns * input and output timing reference levels: 1.5v * output load: 1 ttl gate + 100pf * v cc =5v10%
puma 2e1000-70/90/12 issue 4.4 : january 2001 3 ac read characteristics read cycle -70 -90 -12 parameter symbol min max min max min max unit read cycle time t rc - 70 - 90 - 120 ns address to output delay t acc - 70 - 90 - 120 ns cs1~4 to output delay (1) t cs - 70 - 90 - 120 ns oe to output delay (2) t oe 040 045 050 ns cs1~4 or oe to output float (3,4) t df 040 045 050 ns output hold from oe, cs1~4 or t oh 0- 0- 0- ns address, (whichever occured first) notes: (1) cs1~4 may be delayed up to t acc - t cs after the address transition without impact on t acc . (2) oe may be delayed up to t cs - t oe after the falling edge of cs1~4 without impact on t cs or by t acc - t oe after an address change without impact on t acc . (3) t df is specified from oe or cs1~4 whichever occurs first (c l = 5pf). (4) this parameter is only sampled and is not 100% tested. data polling characteristics parameter symbol min typ max unit data hold time t dh 0- - ns oe hold time t oeh 0- - ns oe to output delay (1) t oe ns write recovery time t wr 0- - ns note : (1) see ac read characteristics. page mode write cycle parameter symbol min typ max unit write cycle time t wc -510ms address set-up time t as 0- -ns address hold time t ah 50 - - ns data set-up time t ds 50 - - ns data hold time t dh 0- -ns write pulse width t wp 100 - - ns byte/word load cycle time t blc - - 150 s write pulse width high t wph 50 - - ns see notes on page 6, mode write waveform. write cycle parameter symbol min typ max unit address, oe set-up time t as , t oes 0- -ns address hold time t ah 50 - - ns chip select set-up time t cs 0- -ns chip select hold time t ch 0- -ns write pulse width (we1~4 or cs1~4) t wp 100 - - ns data set-up time t ds 50 - - ns data, oe hold time t dh , t oeh 0- -ns time to data valid t dv nr (1) --ns note: (1) nr = no restriction
issue 4.4 : january 2001 puma 2e1000-70/90/12 4 toggle bit characteristics (1,2,3,4) parameter symbol min typ max unit data hold time t dh 10 - - ns oe hold time t oeh 10 - - ns oe to output delay (1) t oe ns oe high pulse t oehp 150 - - ns write recovery time t wr 0- - ns note : (1) see ac read characteristics. (2) toggling either oe or cs1~4, or both oe and cs1~4 will operate toggle bit. (3) beginning and ending state of d6 will vary. (4) any address location may be used but the address should not vary. read cycle timing waveform (1,2,3,4) ac write waveform - we1~4 controlled address cs1~4 oe high z t cs t oe t acc t df t oh t rc output valid address valid data out t as t ah t wp t cs t oes t ds t dh t oeh t ch t wph data valid address we1~4 oe cs1~4 data in high-z t wc t dv
puma 2e1000-70/90/12 issue 4.4 : january 2001 5 ac write waveform - cs1~4 controlled page mode write waveform (1,2) note: (1) a6 through a14 must specify the page address during each high to low transition of we1~4 (or cs1~4). (2) oe must be high only when we1~4 and cs1~4 are both low. t wc t as t ah t wp t cs t oes t ds t dh t oeh t ch t wph data valid address we1~4 cs1~4 oe data in high-z t dv oe cs1~4 we1~4 a0-a5 data t wp t wph t blc t as t ah t dh t ds valid add valid data byte 0 byte 1 byte 2 byte 3 byte 62 b
issue 4.4 : january 2001 puma 2e1000-70/90/12 6 notes: (1) a6 through a14 must specify the page address during each high to low transition of we1~4 (or cs1~4). (2) oe must be high only when we1~4 and cs1~4 are both low. data polling waveform (1) toggle bit waveform (1,2,3,4) software protected write waveform (1,2) we1~4 cs1~4 oe d7,d15, d23,d31 a0-a14 t oe t oeh t dh an an an an high z cs1~4 we1~4 oe t oe t oeh t dh d6,d14, d22,d30 high-z high-z high-z t oehp oe cs1~4 we1~4 a0~a5 t wp t as t ah t dh data t ds byte 0 byte 62 b 05555 02aaa 05555 aa 55 a0 a6~a14 byte address page address t wph blc t
puma 2e1000-70/90/12 issue 4.4 : january 2001 7 chip erase waveform cs1~4 oe we1~4 t s t w t h v ih v il v h v il v ih v il t s = t h = 5s (min) t w = 10 ms (min) v h = 12v 0.5v
issue 4.4 : january 2001 puma 2e1000-70/90/12 8 toggle bit in addition to data polling, another method is provided to determine the end of a write cycle. during a write operation successive attempts to read data will result in d6 toggling between 1 and 0. once a write is complete, this toggling will stop and valid data will be read. reading the toggle bit may begin at any time during the write cycle. read the puma 2e1000 read operations are initiated by both output enable and chip select(s) low, while write enable(s) is high. the read operation is terminated by either chip select(s) or output enable returning high. this dual-line control architecture eliminates bus contention in a system environment. the data bus will be in a high impendence state when either output enable or chip select is high. write write operations are initiated when both chip select(s) and write enable(s) are low and output enable is high. the puma 2e1000 supports both a chip select(s) and write enable(s) controlled write cycle. that is, the address is latched by the falling edge of either chip select(s) or write enable(s), whichever occurs last. similarly, the data is latched internally by the rising edge of either chip select(s) or write enable(s), whichever occurs first. a byte/ word write operation, once initiated, will automatically continue to completion, within 10 ms max. page mode write the page write feature of the puma 2e1000 allows the entire memory to be written in typically 5.12 seconds. page write allows 1 to 64 bytes/words of data to be written into the device during a single programming cycle. the host can fetch data from another location within the system during a page write operation (change the source address), but the page address (a6 through a14) for each subsequent valid write cycle to the part, during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following the initial byte/word write cycle, the host can write up to 63 bytes/words in the same manner as the first byte/word written. each successive byte/word load cycle, started by the write enable(s) high to low transition, must begin within 150 s of the falling edge of the preceding write enable(s). if a subsequent write enable(s) high to low transition is not detected within 150 s, the internal automatic programming cycle will commence. the a0 to a5 inputs are used to specify which bytes/words within the page are to be written. the bytes/words may be loaded in any order and altered within the same load period. only bytes/words which are specified for writing will be written; unnecessary cycling of other bytes/words within the page does not occur. data polling the puma 2e1000 features data polling to indicate if the write cycle is completed. during the internal programming cycle, any attempt to read the last byte/word written will produce the complement of that data on d7. once the programming is complete, d7 will refect the true data. note: if the the puma 2e1000 is in a protected state and an illegal write operation is attempted data polling will not operate. data polling may begin at any time during the write cycle. device operation where references are made to byte/word operations, the user will control the memory configuration of 8, 16, or 32 bits wide using cs1~4.
puma 2e1000-70/90/12 issue 4.4 : january 2001 9 hardware data protection the puma 2e1000 provides hardware features to protect non-volatile data from inadvertent writes. ?v cc sense - if v cc is below 3.8v (typical) the write function is inhibited. ?v cc power-on-delay - once v cc has reached 3.8v the device will automatically time out 5ms (typical) before allowing a write. ? write inhibit - holding any one of oe low, cs high, we high inhibits write cycles ? noise filter - pulses of less than 15ns (typical) on the we or cs inputs will not initiate a write cycle. chip erase all of the memory locations on the puma 2e1000 can be erased in 10 ms by placing 12.0v0.5v onto oe and controlling we1~4 and cs1~4 to follow the chip erase timing characteristics. this function will operate even if the module is in software data protection mode as explained later. software data protection the puma 2e1000 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protect feature. the internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. this circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. once the software protection is enabled, the puma 2e1000 is also protected against inadvertent and accidental writes in that, the software algorithm must be issued prior to writing additional data to the device. operating modes the table below shows the logic inputs required to control the operation of the puma 2e1000. 0 = v il : 1 = v ih : x = v ih or v il notes : (1) oe must be 12.0v 0.5v device indentification an extra 64 bytes of eeprom memory are avaliable to the user for device identification, accessed by placing 12v0.5v on a9 and using locations 7fc0 h to 7fff h . these locations can be used during the initial programming of each eeprom to record data such as issue number and release date, and subsequent reprogramming can change these locations to record the alterations performed. mode cs1~4 oe outputs read write standby/write inhibit write inhibit w e1~4 0 0 1 x x 1 0 x 1 x 0 1 x x 0 data out data in high-z x 1 1 0 x 0 output disable chip erase (1) high-z high-z
issue 4.4 : january 2001 puma 2e1000-70/90/12 10 software data protection software controlled data protection, once enabled by the user, necessitates the use of a software algorithm before any write can be performed. to enable this feature a special sequence of 3 writes to 3 specific addresses must be performed, and must be reused for each subsequent write cycle. once set the data protection remains operational until it is disabled by using a second algorithm; power transitions will not reset this feature. note that the puma 2e1000 is supplied with the software data protection feature disabled . the algorithms to enable and disable the protection are shown below: notes : (1) data d7 - d0 (hex); address a14 - a0 (hex). (2) write protect mode will be activated at end of write even if no other data is loaded. (3) write protect state will be disabled at end of write period even if no other data is loaded. (4) 1 to 64 bytes/words of data can be loaded. once initiated, the enable sequence of write operations should not be interrupted all software write commands must obey the page write timing specifications. the process of disabling the data protection mode is very similar to that described for enable, except 6 bytes/words must be loaded to specific locations in the eeprom as shown. note here the use of the word 'load' to describe enabling and disabling the protection modes in preference to 'write'. although it may seem that if the write command sequence is performed to enable protection then the three bytes/ words at those addresses will be overwritten with aa,55,a0, this is not the case. sdp enable sdp disable load data a0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 load last byte/ word to last address load data xx to any address (4) writes enabled (2) enter data protect state load last byte/ word to last address load data xx to any address load data 20 to address 5555 load data 55 to address2aaa load data aa to address 5555 load data 80 to address 5555 load data 55 to address 2aaa load data aa to address 5555 (4) exit data protect state (3) note: load data above represents 8 bit mode. for 16 or 32 bit mode, place the load data in the 2 bytes or all 4 bytes on the data lines, respectively. eg/ 8 bit load data = 55 hex , 16 bit load data = 5555 hex .
puma 2e1000-70/90/12 issue 4.4 : january 2001 11 package details dimensions in mm (inches). 27.69 (1.090) sq. max. 4.83 (0.190) 4.32 (0.170) 1.40 (0.055) 1.52 (0.060) 8.13 (0.320) max 1.27 (0.050) 0.64 (0.025) 2.54 (0.100) typ. 1.02 (0.040) 0.53 (0.021) 0.38 (0.015) 1.14 (0.045) military screening procedure module screening flow for high reliability product is in accordance with mil-std-883 method 5004 level b and is detailed below: visual and mechanical external visual 2017 condition b (or manufacturers equivalent) 100% temperature cycle 1010 condition c (10 cycles,-65 c to +150 c) 100% burn-in pre burn-in electrical per applicable device specifications at t a = +25 c (optional) 100% burn-in method 1015, condition d, t a = +125 c 100% final electrical tests per applicable device specification static (dc) a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% functional a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% switching (ac) a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% percent defective allowable (pda) calculated at post burn-in at t a =+25 c 10% quality conformance per applicable device specification sample external visual 2009 per hmp or customer specification mb module screening flow screen test method level
issue 4.4 : january 2001 puma 2e1000-70/90/12 12 although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantability or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director. ordering information puma 2e1000mb-70 speed 70 = 70 ns 90 = 90 ns 12 = 120 ns temp. range/screening blank = commercial temp. i = industrial temp. m = military temp. mb = screened in accordance with mil-std-883 memory type e1000 = eeprom (configurable as 32kx32, 64kx16 or 128kx8)

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