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| integrating mixed-signal solutions product data sheet stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output two channel ac?97 codecs with i 2 s digital i/o and spdif output 2-9756-d1-3.3-0303
2 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 1. table of contents 1. table of contents .......................................................................................................... ... 2 1.1. list of figures .......................................................................................................... ..........................4 1.2. list of tables ........................................................................................................... ...........................5 2. product brief .............................................................................................................. ........ 6 2.1. features ................................................................................................................. ............................6 2.2. description .............................................................................................................. ...........................6 2.3. ordering information ..................................................................................................... .....................7 2.4. stac9756/57 block diagram ............................................................................................... ............8 2.5. key specifications ....................................................................................................... .......................8 2.6. related materials ........................................................................................................ .......................8 2.7. additional support ....................................................................................................... .......................8 3. characteristics/specifications .................................................................................. 9 3.1. electrical specifications ................................................................................................ .....................9 3.1.1. absolute maximum ratings: .............................................................................................. ..9 3.1.2. recommended operating conditions ................................................................................9 3.1.3. power consumption .................................................................................................... .......9 3.1.4. ac-link static digital specifications .................................................................................. 10 3.1.5. stac9756 analog performance characteristics ...............................................................10 3.1.6. stac9757 analog performance characteristics ...............................................................11 3.2. ac timing characteristics ................................................................................................ ...............13 3.2.1. cold reset ............................................................................................................. ............13 3.2.2. warm reset ............................................................................................................. ..........13 3.2.3. clocks ................................................................................................................. ...............14 3.2.4. data setup and hold .................................................................................................... ......14 3.2.5. signal rise and fall times ............................................................................................. ...15 3.2.6. ac-link low power mode timing ......................................................................................15 3.2.7. ate test mode .......................................................................................................... ........16 4. typical connection diagram (3.3v operation) ......................................................17 5. ac-link .................................................................................................................... ...............18 5.1. clocking ................................................................................................................. ..........................18 5.2. reset .................................................................................................................... ............................18 6. digital interface .......................................................................................................... ....19 6.1. ac-link digital serial interface protocol ................................................................................ ..........19 6.1.1. ac-link audio output frame (sdata_out) ...................................................................19 6.1.1.1. slot 1: command address port .......................................................................21 6.1.1.2. slot 2: command data port ..............................................................................21 6.1.1.3. slot 3: pcm playback left channel ..................................................................21 6.1.1.4. slot 4: pcm playback right channel ...............................................................22 6.1.1.5. slot 5: reserved ...............................................................................................22 6.1.1.6. slot 6: pcm center channel ............................................................................22 6.1.1.7. slot 7: pcm left surround channel .................................................................22 6.1.1.8. slot 8: pcm right surround channel ...............................................................22 6.1.1.9. slot 9: pcm low frequency channel ...............................................................22 6.1.1.10. slot 10: pcm alternate left ............................................................................22 6.1.1.11. slot 11: pcm alternate right ..........................................................................23 copyright ? 2001 sigmatel, inc. all rights reserved. all contents of this document are protected by copyright law and may not be reproduced without the express written consent of s igmatel, inc. sigmatel, the sigmatel logo, and combinations thereof are trademarks of sigmatel, inc. other product names used in this public ation are for identification purposes only and may be trademarks or registered trademarks of their respective companies. the content s of this document are provided in connection with sigmatel, inc. products. sigmatel, inc. has made best efforts to ensure that the info rmation contained herein is accurate and reliable. however, sigmatel, inc. makes no warranties, express or implied, as to the accuracy or com- pleteness of the contents of this publication and is providing this publication "as is". sigmatel, inc. reserves the right to make changes to specifications and product descriptions at any time without notice, and to discontinue or make changes to its products at an y time without notice. sigmatel, inc. does not assume any liability arising out of the application or use of any product or circuit, and spec ifically disclaims any and all liability, including without limitation special, consequential, or incidential damages. 2-9756-d1-3.3-0303 3 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 6.1.1.12. slot 12: reserved ...........................................................................................23 6.1.2. ac-link audio input frame (sdata_in) ...........................................................................23 6.1.2.1. slot 1: status address port ..............................................................................24 6.1.2.2. slot 2: status data port ...................................................................................25 6.1.2.3. slot 3: pcm record left channel .....................................................................25 6.1.2.4. slot 4: pcm record right channel ..................................................................25 6.1.2.5. slots 5-12: reserved ........................................................................................25 6.2. ac-link low power mode ................................................................................................... ............25 6.2.1. waking up the ac-link .................................................................................................. ....26 6.3. i2s (zv_port) digital audio interface .................................................................................... .......26 7. stac9756/57 mixer .......................................................................................................... ....27 7.1. analog mixer input ....................................................................................................... ....................28 7.2. mixer analog output ...................................................................................................... ..................29 7.3. mixer digital input ...................................................................................................... ......................29 7.4. mixer digital output ..................................................................................................... ....................29 7.5. pc beep implementation ................................................................................................... ..............29 7.6. programming registers .................................................................................................... ...............30 7.6.1. reset (00h) ............................................................................................................ ............31 7.6.2. play master volume registers (index 02h, 04h, and 06h) .................................................31 7.6.2.1. master volume (02h) ........................................................................................31 7.6.2.2. lnlvl mixer volume (04h) ..............................................................................32 7.6.2.3. master volume mono (06h) ............................................................................32 7.6.3. pc beep mixer volume (index 0ah) ..................................................................................32 7.6.4. analog mixer input gain registers (index 0ch - 18h) .......................................................33 7.6.4.1. phone mixer volume (0ch) .............................................................................33 7.6.4.2. mic mixer volume (0eh) ...................................................................................33 7.6.4.3. line in mixer volume (10h) ...............................................................................33 7.6.4.4. cd mixer volume (12h) ....................................................................................33 7.6.4.5. video mixer volume (14h) ................................................................................34 7.6.4.6. aux mixer volume (16h) ..................................................................................34 7.6.4.7. pcm out mixer volume (18h) ...........................................................................34 7.6.5. record select (1ah) .................................................................................................... .......34 7.6.6. record gain (1ch) ...................................................................................................... .......35 7.6.7. general purpose (20h) .................................................................................................. .....35 7.6.8. 3d control (22h) ....................................................................................................... ..........36 7.6.9. powerdown ctrl/stat (26h) .............................................................................................. ...36 7.6.9.1. ready status ....................................................................................................37 7.6.9.2. powerdown controls .........................................................................................37 7.6.9.3. external amplifier power down control ............................................................37 7.6.10. extended audio id (28h) ............................................................................................... ...37 7.6.11. extended audio control/status (2ah) ..............................................................................38 7.6.11.1. variable rate sampling enable ......................................................................38 7.6.11.2. spdif .............................................................................................................39 7.6.11.3. spcv (spdif configuration valid) .................................................................39 7.6.11.4. spsa1, spsa0 (spdif slot assignment) ......................................................39 7.6.12. pcm dac rate registers (2ch and 32h) ........................................................................39 7.6.12.1. pcm dac rate (2ch) .....................................................................................40 7.6.12.2. pcm lr adc rate (32h) ................................................................................40 7.6.13. z_data volume (60h) ................................................................................................... ..40 7.6.14. digital audio control (6ah) ........................................................................................... ....41 7.6.14.1. spdif control (3ah) .......................................................................................42 7.6.15. revision code (6ch) ................................................................................................... .....42 7.6.16. analog special (6eh) .................................................................................................. .....43 7.6.16.1. 72h enable (70h) ............................................................................................43 7.6.16.2. analog current adjust (72h) ...........................................................................43 7.6.16.3. internal power-on/off anti-pop circuit ...........................................................44 7.6.17. multi-channel selection (74h) ......................................................................................... .44 4 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 7.6.17.1. digital audio slot selection .............................................................................45 7.6.18. clock access (index 76h and 78h) ..................................................................................46 7.6.18.1. 78h enable (76h) ............................................................................................46 7.6.18.2. clock access (78h) .........................................................................................46 7.6.19. vendor id1 and id2 (index 7ch and 7eh) .......................................................................47 7.6.19.1. vendor id1 (7ch) ............................................................................................47 7.6.19.2. vendor id2 9756 (7eh) ...................................................................................47 8. low power modes ............................................................................................................ 48 9. multiple codec support ...............................................................................................50 9.1. primary/secondary codec selection ........................................................................................ .......50 9.1.1. primary codec operation ................................................................................................ ...50 9.1.2. secondary codec operation .............................................................................................. 50 9.2. secondary codec register access definitions .............................................................................. ..51 10. testability ............................................................................................................... .........52 11. pin description ........................................................................................................... .....53 11.1. digital i/o ............................................................................................................. ..........................54 11.2. analog i/o .............................................................................................................. ........................55 11.3. filter/references ....................................................................................................... .....................55 11.4. power and ground signals ................................................................................................ ............56 12. package drawing .......................................................................................................... 57 13. appendix a: split independent power supply operation ..............................58 14. appendix c: programming registers .....................................................................59 1.1. list of figures figure 1. stac9756/57 block diagram ........................................................................................... ................8 figure 2. cold reset timing ................................................................................................... .......................13 figure 3. warm reset timing ................................................................................................... .....................13 figure 4. clocks timing ....................................................................................................... ..........................14 figure 5. data setup and hold timing .......................................................................................... .................14 figure 6. signal rise and fall times timing ................................................................................... ...............15 figure 7. ac-link low power mode timing ....................................................................................... ............15 figure 8. ate test mode timing ................................................................................................ ...................16 figure 9. stac9757 typical connection diagram ................................................................................. .......17 figure 10. ac-link to its companion controller ................................................................................ .............18 figure 11. ac?97 standard bi-directional audio frame .......................................................................... .......20 figure 12. ac-link audio output frame ......................................................................................... ...............20 figure 13. start of an audio output frame ..................................................................................... ...............20 figure 14. stac9756/57 audio input frame ...................................................................................... ...........23 figure 15. start of an audio input frame ...................................................................................... .................24 figure 16. stac9756/57 powerdown timing ....................................................................................... .........25 figure 17. i 2 s digital audio interface ..................................................................................................... ........26 figure 18. stac9756 5v analog mode, 2-channel mixer functional diagram ............................................28 figure 19. stac9756 +3.3v analog mode and stac9757 2-channel mixer functional diagram ...............28 figure 20. example of stac9756/57 powerdown/powerup flow ..................................................................48 figure 21. stac9756/57 powerdown/powerup flow with analog still alive ...................................................49 figure 22. stac9756/57 pin description drawing ................................................................................ ........53 figure 23. 48-pin tqfp package drawing ........................................................................................ ............57 figure 24. stac9756 split independent power supply operation typical connection diagram .................58 2-9756-d1-3.3-0303 5 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 1.2. list of tables table 1. recommended operating conditions ..................................................................................... ...........9 table 2. power consumption .................................................................................................... .......................9 table 3. ac-link static specifications ........................................................................................ ...................10 table 4. stac9756 analog performance characteristics .......................................................................... ...10 table 5. stac9757 analog performance characteristics .......................................................................... ...11 table 6. cold reset specifications ............................................................................................ ....................13 table 7. warm reset specifications ............................................................................................ ..................13 table 8. clocks specifications ................................................................................................ .......................14 table 9. data setup and hold specifications ................................................................................... ..............14 table 10. signal rise and fall times specifications ........................................................................... ..........15 table 11. ac-link low power mode timing specifications ........................................................................ ...15 table 12. ate test mode specifications ........................................................................................ ...............16 table 13. stac9756/57 available data streams .................................................................................. ........19 table 14. command address port bit assignments ................................................................................ ......21 table 15. command data port bit assignments ................................................................................... .........21 table 16. status address port bit assignments ................................................................................. ............24 table 17. status data port bit assignments .................................................................................... ..............25 table 18. stac9756/57 mixer ................................................................................................... ....................27 table 19. programming registers ............................................................................................... ...................30 table 20. play master volume register ......................................................................................... ................31 table 21. pc_beep register .................................................................................................... ....................32 table 22. analog mixer input gain register .................................................................................... ..............33 table 23. record select control registers ..................................................................................... ...............34 table 24. record gain registers .............................................................................................. ....................35 table 25. general purpose register ............................................................................................ ..................35 table 26. 3d control registers ............................................................................................... ......................36 table 27. powerdown status registers .......................................................................................... ...............36 table 28. extended audio id register functions ............................................................................... ..........38 table 29. slot assignment relationship between spsa1 and spsa0 ............................................................39 table 30. hardware supported sample rates ..................................................................................... ..........39 table 31. z_data register ..................................................................................................... ........................40 table 32. digital audio control (6ah) registers ............................................................................... ..............41 table 33. digital output source selection table ............................................................................... ............41 table 34. spdif control (3ah) registers ....................................................................................... ...............42 table 35. analog current adjust ............................................................................................... .....................44 table 36. stac9756/57 multi-channel programming register .....................................................................4 4 table 37. spdif slot selection (reg. 2ah: d5, d4 with reg. 6ah: d12 (i2s sel) = 0) ...............................45 table 38. i 2 s out2 slot selection (reg. 2ah: d5, d4 with reg. 6ah: d12 (i2s sel) = 1) ..........................45 table 39. i 2 s out1 slot selection (reg. 6ah: d5, d4) .................................................................................45 table 40. spdif control (3ah) registers ....................................................................................... ...............46 table 41. low power modes ..................................................................................................... .....................48 table 42. codec id selection .................................................................................................. ......................50 table 43. secondary codec register access slot 0 bit definitions .............................................................. .51 table 44. digital connection signals .......................................................................................... ...................54 table 45. analog connection signals ........................................................................................... .................55 table 46. filtering and voltage references .................................................................................... ...............55 table 47. power and ground signals ............................................................................................ ................56 table 48. 48-pin tqfp package dimensions ...................................................................................... ..........57 6 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 2. product brief 2.1. features high performance ? technology 18-bit full duplex stereo adc, dacs independent sample rates for adc & dacs 5-wire ac-link protocol compliance zv-port i 2 s digital input i 2 s digital i/o and spdif output digital-ready status 20 db microphone boost capability +3.3v (stac9757) and +5v (stac9756) analog power supply options pin compatible with the stac9700/21/44 sigmatel surround (ss3d) stereo enhancement energy saving dynamic power modes multi-codec option (intel ac'97 rev 2.1) six analog line-level inputs 98 db snr line-line 2.2. description sigmatel's stac9756/57 are general purpose 18-bit, full duplex, audio codecs con- forming to the analog component specification of ac'97 (audio codec 97 compo- nent specification rev. 2.1). the stac9756/57 incorporate sigmatel's proprietary ? technology to achieve a dac snr in excess of 95 db. the dacs, adcs, and mixer are integrated with analog i/os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. the stac9756/57 include digital input output capability for support of modern pc systems. there is an i 2 s input for zv-port audio, a dedicated i 2 s output and an output that supports either i 2 s or the spdif format. the stac9756/57 is a standard 2-channel stereo codec. the stac9756/57 may be used as a secondary codec, with the stac9700/21/44/56/08/84 as the primary, in a multiple codec con- figuration conforming to the ac'97 rev. 2.1 specification. this configuration can pro- vide true six-channel, ac-3 playback required for dvd applications. the stac9756/57 communicates via the five-wire ac-link to any digital component of ac'97 providing flexibility in the audio system design. packaged in an ac'97 compli- ant 48-pin tqfp, the stac9756/57 can be placed on the motherboard, daughter boards, pci, amr, cnr, or acr cards. the stac9756/57 block diagram is illustrated in figure 1. it provides variable sam- ple rate d-a & a-d conversion, mixing, and analog processing. supported audio sample rates include 48 khz, 44.1 khz, 22.05 khz, 16 khz, 11.025 khz, and 8 khz; additional rates are supported in the stac9756/57 soft audio drivers. the digital interface communicates with the ac'97 controller via the five-wire ac-link and con- tains the 64-word by 16-bit registers. the two dacs convert the digital stereo pcm-out content to audio. the mixer block combines the pcm_out with any 2-9756-d1-3.3-0303 7 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output analog sources, to drive the line_out and lnlvl_out outputs. the mono_out delivers either mic only, or a mono mix of sources from the mixer. the stereo variable sample rate adc ? s provide record capability for any mix of mono or stereo sources, and deliver a digital stereo pcm-in signal back to the ac-link. the microphone input and mono analog mix can be recorded simulta- neously, thus allowing for an all digital output in support of the digital ready initiative. all adc ? s and dac ? s operate at 18-bit resolution. for a digital ready record path, the microphone is connected to the left channel adc while the mono output of the ste- reo mixer is connected to the right channel adc. make sure the microphone input is not connected to the stereo mixer when in this mode. the stac9756/57 supports one i 2 s digital audio input, one dedicated i 2 s output, and a dual mode spdif/i 2 s output. these digital i/o options provide for a number of advance architectural implementations, with volume controls and digtial mixing capabilities built directly into the codec. the stac9756/57 is designed primarily to support stereo (2-speaker) audio. true ac-3 playback can be achieved for 6-speaker applications by taking advantage of the multi-codec option available in the stac9756/57 to support multiple codecs in an ac ? 97 architecture. additionally, the stac9756/57 provides for a stereo enhancement feature, sigmatel surround 3d (ss3d). ss3d provides the listener with several options for improved speaker separation beyond the normal 2/ 4-speaker arrangements. together with the logic component (controller or advanced core logic chip-set) of ac ? 97, stac9756/57 can be soundblaster ? and windows sound system ? compat- ible with sigmatel ? s wdm driver for win 98/2k/me. soundblaster is a registered trademark of creative labs. windows is a registered trademark of microsoft corpo- ration. 2.3. ordering information part number package temp range supply range stac9756t 48-pin tqfp 7mm x 7mm x 1.4mm 0 c to +70 c dvdd = 3.3v, avdd = 5.0v stac9757t 48-pin tqfp 7mm x 7mm x 1.4mm 0 c to +70 c dvdd = 3.3v, avdd = 3.3v 8 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 2.4. stac9756/57 block diagram 2.5. key specifications analog line_out snr: 98 db digital dac snr: 98 db digital adc snr: 87 db full-scale total harmonic distortion: 0.02% crosstalk between input channels: -70 db spurious tone rejection: 100 db 2.6. related materials product brief reference designs for mb, amr, cnr, and acr applications audio precision performance plots 2.7. additional support additional product and company information can be obtained by going to the sigmatel website at: www.sigmatel.com ac-link digital interface registers 64x16 bits sync bit_clk sdata_out sdata_in reset# power management dac dac adc adc pcm out dacs pcm in adcs 4 stereo sources 2 mono sources mono_out mic boost 0/20 db mic1 mono stereo mixer analog mixing and gain control m u x mic2 line_out multi-codec id0 id1 spdif / i2s_out2 i2s_out1 mixer digital mixing and gain control z_data (i 2 s_input) variable sample rate 18-bit dacs and adcs lnlvl_out figure 1. stac9756/57 block diagram 2-9756-d1-3.3-0303 9 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 3. characteristics/specifications 3.1. electrical specifications 3.1.1. absolute maximum ratings: voltage on any pin relative to ground vss - 0.3v to vdd + 0.3v operating temperature 0 o c to 70 o c storage temperature -55 o c to +125 o c soldering temperature 260 o c for 10 seconds output current per pin 4 ma except vrefout = 5ma maximum supply voltage 5.5 volts = vdd 3.1.2. recommended operating conditions 3.1.3. power consumption parameter min typ max unit power supplies + 3.3v digital 3.135 3.3 3.465 v + 5v analog 4.75 5 5.25 v + 3.3v analog 3.135 3.3 3.465 v ambient temperature 0 - 70 o c table 1. recommended operating conditions parameter min typ max unit digital supply current + 3.3v digital - 35 - ma analog supply current + 5v analog - 80 - ma + 3.3v analog - 70 - ma power down status pr0 +5v analog supply current - 68 - ma pr1 +5v analog supply current - 54 - ma pr2 +5v analog supply current - 30 - ma pr3 +5v analog supply current - 0.1 - ma pr4 +3.3v digital supply current - 0.1 - ma pr5 internal clk disable - 0.1 - ma table 2. power consumption 10 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 3.1.4. ac-link static digital specifications (tambient = 25 o c, dvdd = 3.3v 5%, avss=dvss=0v; 50pf external load) 3.1.5. stac9756 analog performance characteristics (t ambient = 25 o c, avdd = 5.0v 5%, dvdd = 3.3v 5%, avss=dvss=0v; 1 khz input sine wave; sample frequency = 48 khz; 0 db = 1 vrms, 10k ?// 50pf load, testbench characterization bw: 20 hz ? 20 khz, 0 db settings on all gain stages) parameter symbol min typ max unit input voltage range vin -0.30 - dvdd + 0.30 v low level input range vil - - 0.35xdvdd v high level input voltage vih 0.65xdvdd - - v high level output voltage voh 0.90xdvdd - - v low level output voltage vol - - 0.1xdvdd v input leakage current (ac-link inputs) - -10 - 10 ua output leakage current (hi-z ? d ac-link outputs) - -10 - 10 ua output buffer drive current - - 4 ma table 3. ac-link static specifications parameter min typ max unit full scale input voltage: line inputs - 1.0 - vrms mic inputs (note 1) - 0.1 - vrms full scale output voltage: line output - 1.0 - vrms analog s/n: cd to line_out 90 98 - db other to line_out - 98 - db analog frequency response (note 2) 20 - 20,000 hz digital s/n (note 3) d/a 85 96 - db a/d 75 86 - db total harmonic distortion: line output (note 4) - - 0.02 % d/a & a/d frequency response (note 5) 20 - 19,200 hz transition band 19,200 - 28,800 hz stop band 28,800 - - hz stop band rejection (note 6) 85 - - db out-of-band rejection (note 7) - 40 - db group delay - - 1 ms power supply rejection ratio (1khz) - 40 - db crosstalk between input channels - - 70 db table 4. stac9756 analog performance characteristics 2-9756-d1-3.3-0303 11 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output note: 1. with +20 db boost on, 1.0vrms with boost off 2. 1 db limits 3. the ratio of the rms output level with 1 khz full scale input to the rms output level with all zeros into the digital input. measured ? a weighted ? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio). 4. 0 db gain, 20 khz bw, 48 khz sample frequency 5. 0.25db limits 6. stop band rejection determines filter requirements. out-of-band rejection determines audible noise. 7. the integrated out-of-band noise generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output. 3.1.6. stac9757 analog performance characteristics (t ambient = 25 o c, avdd = dvdd = 3.3v 5%, avss=dvss=0v; 1 khz input sine wave; sample frequency = 48 khz; 0 db = 1 vrms, 10k ?// 50pf load, testbench characterization bw: 20 hz ? 20 khz, 0 db settings on all gain stages) spurious tone rejection - 100 - db attenuation, gain step size - 1.5 - db input impedance 10 50 - k ? input capacitance - 15 - pf vrefout - 0.45 x avdd - v interchannel gain mismatch adc - - 0.5 db interchannel gain mismatch dac - - 0.5 db gain drift - 100 - ppm/ o c dac offset voltage - 10 50 mv deviation from linear phase - - 1 deg. analog output load capacitance - - 50 pf analog output load resistance 10 - - k ? mute attenuation 90 96 - db parameter min typ max unit full scale input voltage: line inputs - 1.0 - vrms mic inputs (note 1) - 0.1 - vrms full scale output voltage: line inputs to line_out @ gain setting of -6 db - 0.5 - vrms pcm to line_out - 0.5 - vrms mic inputs to line_out - 0.5 - vrms analog s/n: cd to line_out - 90 - db other to line_out - 90 - db analog frequency response (note 2) 20 - 20,000 hz table 5. stac9757 analog performance characteristics parameter min typ max unit table 4. stac9756 analog performance characteristics (continued) 12 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output note: 1. with +20 db boost on, 1.0vrms with boost off 2. 1 db limits 3. the ratio of the rms output level with 1 khz full scale input to the rms output level with all zeros into the digital input. measured ? a weighted ? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio). 4. 0 db gain, 20 khz bw, 48 khz sample frequency 5. 0.25db limits 6. stop band rejection determines filter requirements. out-of-band rejection determines audible noise. 7. the integrated out-of-band noise generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output. digital s/n (note 3) d/a 85 90 - db a/d 75 85 - db total harmonic distortion: line output (note 4) - - 0.02 % d/a & a/d frequency response (note 5) 20 - 19,200 hz transition band 19,200 - 28,800 hz stop band 28,800 - - hz stop band rejection (note 6) 85 - - db out-of-band rejection (note 7) - 40 - db group delay - - 1 ms power supply rejection ratio (1khz) - 40 - db crosstalk between input channels - - 70 db spurious tone rejection - 100 - db attenuation, gain step size - 1.5 - db input impedance 10 50 - k ? input capacitance - 15 - pf vrefout - 0.41 x avdd - v interchannel gain mismatch adc - - 0.5 db interchannel gain mismatch dac - - 0.5 db gain drift - 100 - ppm/ o c dac offset voltage - 10 50 mv deviation from linear phase - - 1 degree analog output load capacitance - - 50 pf analog output load resistance 10 - - k ? mute attenuation 90 96 - db parameter min typ max unit table 5. stac9757 analog performance characteristics (continued) 2-9756-d1-3.3-0303 13 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 3.2. ac timing characteristics (t ambient = 25 c, avdd = 3.3v 5%, dvdd = 3.3v 5%, avss=dvss+0v; 50pf external load) 3.2.1. cold reset note: bit_clk and sdatain are in a high impedance state during reset. 3.2.2. warm reset parameter symbol min typ max units reset# active low pulse width tres_low 1.0 - - us reset# inactive to bit_clk startup delay trst2clk +1.0 - - ns table 6. cold reset specifications parameter symbol min typ max units sync active high pulse width tsync_high 1.0 1.3 - us sync inactive to bit_clk startup delay tsync2clk 162.8 - - ns table 7. warm reset specifications tres_low trst2clk reset# bit_clk sdata_in figure 2. cold reset timing tsync_high tsync_2clk sync bit_clk figure 3. warm reset timing 14 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 3.2.3. clocks 3.2.4. data setup and hold (50pf external load) parameter symbol min typ max units bit_clk frequency - 12.288 - mhz bit_clk period tclk_period - 81.4 - ns bit_clk output jitter - 750 - ps blt_clk high pulsewidth (note 8) tclk_high 32.56 40.7 48.84 ns bit_clk low pulse width (note 8) tclk_low 32.56 40.7 48.84 ns sync frequency - 48.0 - khz sync period tsync_period - 20.8 - us sync high pulse width tsync_high - 1.3 - us sync low_pulse width tsync_low - 19.5 - us note: 8. worst case duty cycle restricted to 40/60. table 8. clocks specifications parameter symbol min typ max units setup to falling edge of bit_clk tsetup 15.0 - - ns hold from falling edge of bit_clk thold 5.0 - - ns note: setup and hold time parameters for sdata_in are with respect to the ac ? 97 controller. table 9. data setup and hold specifications sync bit_clk tclk_high tclk_low tclk_period tsync_high tclk_period tsync_low figure 4. clocks timing bit_clk t hold t setup sdata_out sdata_in sync tco v ih v il v oh v ol figure 5. data setup and hold timing 2-9756-d1-3.3-0303 15 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 3.2.5. signal rise and fall times (50pf external load; from 10% to 90% of vdd) 3.2.6. ac-link low power mode timing parameter symbol min typ max units bit_clk rise time triseclk 2 - 6 ns bit_clk fall time tfallclk 2 - 6 ns sdata_in rise time trisedin 2 - 6 ns sdata_in fall time tfalldin 2 - 6 ns table 10. signal rise and fall times specifications parameter symbol min typ max units end of slot 2 to bit_clk, sdata_in low ts2_pdown - - 1.0 us table 11. ac-link low power mode timing specifications bit_clk sdata_in tfallclk triseclk trisedin tfalldin figure 6. signal rise and fall times timing bit_clk sdata_in note: bit_clk not to scale ts2_pdown don ? t care data pr4 write to 0x20 slot 2 slot 1 sdata_out sync figure 7. ac-link low power mode timing 16 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 3.2.7. ate test mode note: 1. all ac-link signals are normally low through the trailing edge of reset#. bringing sdata_out high for the trailing edge of reset# causes stac9756/57 ac-link outputs to go high impedance which is suitable for ate in circuit testing. 2. once the test mode has been entered, the stac9756/57 must be issued another reset# with all ac-link signals low to return to the normal operating mode. 3. # denotes active low. parameter symbol min typ max units setup to trailing edge of reset# (also applies to sync) tsetup2rst 15.0 - - ns rising edge of reset# to hi-z delay toff - - 25.0 ns table 12. ate test mode specifications tsetup2rst hi-z toff reset# sdata_out sdata_in, bit_clk figure 8. ate test mode timing 2-9756-d1-3.3-0303 17 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 4. typical connection diagram (3.3v operation) 0.1 f 1 f 0.1 f 0.1 f 10 f 0.1 f 2 ? * ferrite bead* *suggested 3.3v 5% avdd1 avdd2 dvdd1 dvdd2 xtl_in xtl_out 9 2 3 27 pf 27 pf 24.576 mhz 1 38 25 pc_beep 12 phone 13 aux_l 14 aux_r 15 video_l 16 video_r 17 cd_l 18 cd_gnd 19 cd_r 20 mic1 21 mic2 22 line_in_l 23 line_in_r 41 cap2 32 *optional 0.1 f 1 f* 820 pf 29 30 afilt1 afilt2 820 pf avss1 avss2 26 42 4 7 dvss1 dvss2 lnlvl_out *terminate ground plane as close to codec as possible analog ground digital ground lnlvl_out 39 37 mono_out 36 line_out_r 35 line_out_l 43 d_lrclk 44 i2s_out1 40 d_sclk 48 spdif/i2s_out2 34 z_sclk 33 z_data 31 z_lrclk 0.1 f 1 f* *optional 27 vref vrefout eapd cid1 cid0 28 47 46 45 11 reset# 10 sync 24 sdata_in0 bit_clk sdata_out 5 6 8 27 pf 22 ? emi filter optional stac9757 note: 1. see appendix b for specific connection requirements prior to operation. 2. see figure 24 on page 58 for split supply connections. figure 9. stac9757 typical connection diagram 18 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 5. ac-link figure 10 shows the ac-link point to point serial interconnect between the stac9756/57 and its companion controller. all digital audio streams and com- mand/status information are communicated over this ac-link. see ? digital inter- face ? on page 19 for details. 5.1. clocking stac9756/57 derives its clock internally from an externally connected 24.576 mhz crystal or an oscillator through the xtal_in pin. synchronization with the ac'97 controller is achieved through the bit_clk pin at 12.288 mhz. the beginning of all audio sample packets, or ? audio frames ? , transferred over ac-link is synchronized to the rising edge of the ? sync ? signal driven by the ac'97 controller. data is transitioned on ac-link on every rising edge of bit_clk, and subsequently sampled by the receiving side on each immediately following falling edge of bit_clk. 5.2. reset there are 3 types of resets: 1. a ? cold ? reset where all stac9756/57 logic and registers are initialized to their default state 2. a ? warm ? reset where the contents of the stac9756/57 register set are left unal- tered 3. a ? register ? reset which only initializes the stac9756/57 registers to their default states after signaling a reset to the stac9756/57 , the ac'97 controller should not attempt to play or capture audio data until it has sampled a ? codec ready ? indication via register 26h from the stac9756/57 . for proper reset operation sdata_out should be ? 0 ? during ? cold ? reset. sync digital dc ? 97 controller ac ? 97 codec bit_clk sdata_out sdata_in reset# xtal_in xtal_out figure 10. ac-link to its companion controller 2-9756-d1-3.3-0303 19 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 6. digital interface 6.1. ac-link digital serial interface protocol the stac9756/57 communicates to the ac ? 97 controller via a 5-pin digital serial ac-link interface, which is a bi-directional, fixed rate, serial pcm digital stream. all digital audio streams, commands and status information are communicated over this point-to-point serial interconnect. the ac-link handles multiple inputs, and out- put audio streams, as well as control register accesses using a time division multi- plexed (tdm) scheme. the ac ? 97 controller synchronizes all ac-link data transaction. table 13 shows the data streams available on the stac9756/57 : synchronization of all ac-link data transactions is handled by the ac ? 97 controller. the stac9756/57 drives the serial bit clock onto ac-link. the ac ? 97 controller then qualifies with a synchronization signal to construct audio frames. sync, fixed at 48 khz, is derived by dividing down the serial bit clock (bit_clk). bit_clk, fixed at 12.288 mhz, provides the necessary clocking granularity to sup- port 12, 20-bit outgoing and incoming time slots. ac-link serial data is transitioned on each rising edge of bit_clk. the receiver of ac-link data, stac9756/57 for outgoing data and ac ? 97 controller for incoming data, samples each serial bit on the falling edges of bit_clk. the ac-link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit positions) time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. a ? 1 ? in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. if a slot is ? tagged ? invalid, it is the responsibility of the source of the data, (stac9756/57 for the input stream, ac'97 controller for the output stream), to stuff all bit positions with 0 ? s during that slot ? s active time. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is defined as the ? tag phase ? . the remainder of the audio frame where sync is low is defined as the ? data phase ? . additionally, for power savings, all clock, sync, and data signals may be halted by the controller. 6.1.1. ac-link audio output frame (sdata_out) the audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the stac9756/57 dac inputs, and control registers. each audio output frame supports up to twelve 20-bit outgoing data time slots. slot 0 is a special reserved time slot containing 16 bits that are used for ac-link protocol infrastructure. pcm playback 2 output slots 2 channel composite pcm output stream pcm record data 2 input slots 2 channel composite pcm input stream control 2 output slots control register write port status 2 input slots control register read port table 13. stac9756/57 available data streams 20 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output within slot 0, the first bit is a global bit (sdata_out slot 0, bit 15) which flags the validity for the entire audio frame. if the ? valid frame ? bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. the next 12 bit positions sampled by the stac9756/57 indicate which of the corresponding 12 times slots contain valid data. in this way data streams of differing sample rates can be transmitted across ac-link at its fixed 48khz audio frame rate. the following diagram illustrates the time slot based ac-link protocol. a new audio output frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the stac9756/57 samples the assertion of sync. this following edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising edge of bit_clk, the ac'97 controller transitions sdata_out into the first bit position of slot 0 (valid frame bit). each new bit posi- tion is presented to ac-link on a rising edge of bit_clk, and subsequently sam- pled by the stac9756/57 on the following falling edge of bit_clk. this sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. outgoing streams incoming streams sync tag phase data phase pcm left cmd adr na pcm lsurr pcm lfe pcm ralt tag cmd data pcm rt pcm ctr pcm rsurr pcm lalt rsvd pcm left status adr na rsvd rsvd rsvd tag status data pcm rt na rsvd rsvd rsvd figure 11. ac?97 standard bi-directional audio frame sync bit_clk sdata_out slot1 slot2 end of previous audio frame slot(12) "0" 19 data phase tag phase 12.288 mhz time slot "valid" bits slot 1 slot 2 slot 3 slot 12 ("1" = time slot contains valid pcm data) cid1 cid0 valid "0" 19 19 "0" frame 19 "0" "0" figure 12. ac-link audio output frame sync bit_clk sdata_out slot1 slot2 end of previous audio frame valid frame sync asserted first sdata_out bit of frame figure 13. start of an audio output frame 2-9756-d1-3.3-0303 21 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output sdata_out ? s composite stream is msb justified (msb first) with all non-valid slots ? bit positions stuffed with 0 ? s by the ac'97 controller. when mono audio sample streams are sent from the ac'97 controller, it is neces- sary that both left and right sample stream time slots be filled with the same data. 6.1.1.1. slot 1: command address port the command port is used to control features, and monitor status (see audio input frame slots 1 and 2) of the stac9756/57 functions including, but not limited to, mixer settings, and power management (refer to the control register section of this specification). the control interface architecture supports up to sixty-four 16-bit read/write regis- ters, addressable on even byte boundaries. only the even registers (00h, 02h, etc.) are valid. odd accesses are considered invalid and return 0 0 0 0. audio output frame slot 1 communicates control register address, and write/read command information to the stac9756/57. the first bit (msb) sampled by stac9756/57 indicates whether the current control transaction is a read or a write operation. the following 7 bit positions communicate the targeted control register address. the trailing 12 bit positions within the slot are reserved and must be stuffed with 0's by the ac'97 controller. 6.1.1.2. slot 2: command data port the command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle (as indicated by slot 1, bit 19). if the current command port operation is a read then the entire slot time must be stuffed with 0's by the ac'97 controller. 6.1.1.3. slot 3: pcm playback left channel audio output frame slot 3 is the composite digital audio left playback stream. in a typical ? games compatible" pc this slot is composed of standard pcm (.wav) out- put samples digitally mixed (on the ac'97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20-bits is trans- bit description comments 19 read/write command 1= read, 0=write 18:12 control register index sixty-four 16-bit locations, addressed on even byte boundaries 11:0 reserved stuffed with 0 ? s table 14. command address port bit assignments bit description comments 19:4 control register write data stuffed with 0 ? s if current operation is a read 3:0 reserved stuffed with 0 ? s table 15. command data port bit assignments 22 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output ferred, the ac ? 97 controller must stuff all trailing non-valid bit positions within this time slot with 0 ? s. 6.1.1.4. slot 4: pcm playback right channel audio output frame slot 4 is the composite digital audio right playback stream. in a typical ? games compatible" pc this slot is composed of standard pcm (.wav) out- put samples digitally mixed (on the ac'97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20-bits is trans- ferred, the ac'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's. 6.1.1.5. slot 5: reserved audio output frame slot 5 is reserved for modem operation and is not used by the stac9756/57. 6.1.1.6. slot 6: pcm center channel audio output frame slot 6 is the composite digital audio center stream used in a multi-channel application where the stac9756/57 is programmed to accept the pri- mary dac pcm data from slots 6 and 9. please refer to the register programming section for details on the multi-channel programming options. 6.1.1.7. slot 7: pcm left surround channel audio output frame slot 7 is the composite digital audio left surround stream. as a programming option, pcm data from slots 7 and 8 may be used to supply data to the primary dacs. please refer to the register programming section for details on the multi-channel programming options. 6.1.1.8. slot 8: pcm right surround channel audio output frame slot 8 is the composite digital audio right surround stream. as a programming option, pcm data from slots 7 and 8 may be used to supply data to the primary dacs. please refer to the register programming section for details on the multi-channel programming options. 6.1.1.9. slot 9: pcm low frequency channel audio output frame slot 9 is the composite digital audio low frequency stream used in a multi-channel application where the stac9756/57 is programmed to accept the primary dac pcm data from slots 6 and 9. please refer to the register programming section for details on the multi-channel programming options. 6.1.1.10. slot 10: pcm alternate left audio output frame slot 10 is the composite digital audio alternate left stream used in a multi-channel applications. please refer to the register programming section for details on the multi channel programming options. 2-9756-d1-3.3-0303 23 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 6.1.1.11. slot 11: pcm alternate right audio output frame slot 11 is the composite digital audio alternate right stream used in a multi-channel applications. please refer to the register programming section for details on the multi channel programming options. 6.1.1.12. slot 12: reserved audio output frame slot 12 is reserved for modem operations and is not used by the stac9756/57. 6.1.2. ac-link audio input frame (sdata_in) the audio input frame data streams correspond to the multiplexed bundles of all dig- ital input data targeting the ac ? 97 controller. as is the case for audio output frame, each ac-link audio input frame consists of 12, 20-bit time slots. slot 0 is a special reserved time slot containing 16 bits that are used for ac-link protocol infrastruc- ture. within slot 0 the first bit is a global bit (sdata_in slot 0, bit 15) which flags whether the stac9756/57 is in the "codec ready" state or not. if the ? codec ready ? bit is a 0, this indicates that stac9756/57 is not ready for normal operation. this condition is normal following the de-assertion of power on reset, for example, while stac9756/57 ? s voltage references settle. when the ac-link "codec ready" indica- tor bit is a 1, it indicates that the ac-link and stac9756/57 control/status registers are in a fully operational state. the ac'97 controller must further probe the power- down control status register (refer to mixer register section) to determine exactly which subsections, if any, are ready. prior to any attempts at putting stac9756/57 into operation the ac'97 controller should poll the first bit in the audio input frame (sdata_in slot 0, bit 15) for an indi- cation that stac9756/57 has become "codec ready". once the stac9756/57 is sampled "codec ready", the next 12 bit positions sampled by the ac'97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. the following diagram illustrates the time slot based ac-link protocol. a new audio input frame begins with a low to high transition of sync. sync is syn- chronous to the rising edge of bit_clk. immediately following the falling edge of bit_clk, the stac9756/57 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the stac9756/57 transitions sdata_in into the first bit position of slot 0 ("codec ready" bit). each new bit position is presented sync bit_clk sdata_in slot1 slot2 end of previous audio frame slot(12) "0" 19 data phase tag phase 12.288 mhz time slot "valid" bits slot 1 slot 2 slot 3 slot 12 ("1" = time slot contains valid pcm data) valid "0" 19 19 "0" frame 19 "0" "0" "0" "0" figure 14. stac9756/57 audio input frame 24 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output to ac-link on a rising edge of bit_clk and subsequently sampled by the ac ? 97 controller on the following falling edge of bit_clk. this sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. sdata_in ? s composite stream is msb justified (msb first) with all non-valid bit posi- tions (for assigned and/or unassigned time slots) stuffed with 0 ? s by stac9756/57. sdata_in data is sampled on the falling edges of bit_clk. 6.1.2.1. slot 1: status address port the status port is used to monitor status for stac9756/57 functions including, but not limited to, mixer settings, and power management. audio input frame slot 1 ? s stream echoes the control register index, for historical ref- erence, for the data to be returned in slot 2. (assuming that slots 1 and 2 had been tagged ? valid ? by stac9756/57 during slot 0) bit description comments 19 reserved stuffed with 0 ? s 18:12 control register index echo of register index for which data is being returned 11:0 on demand dac slot request bits 0 = send data, 1 = do not send data 11 slot 3 request: pcm left channel 10 slot 4 request: pcm right channel 9 slot 5 request: modem line 1 8 slot 6 request: pcm center 7 slot 7 request: pcm left surround 6 slot 8 request: pcm right surround 5 slot 9 request: pcm lfe 4 slot 10 request: modem line 2 or pcm left (n+1) 3 slot 11 request: modem handset or pcm right (n+1) 2 slot 12 request: pcm center (n+1) 1,0 reserved (set to 0) table 16. status address port bit assignments sync bit_clk sdata_in slot1 slot2 end of previous audio frame codec ready sync asserted first sdata_out bit of frame figure 15. start of an audio input frame 2-9756-d1-3.3-0303 25 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 6.1.2.2. slot 2: status data port the status data port delivers 16-bit control register read data. if slot 2 is tagged "invalid" by stac9756/57 , then the entire slot will be stuffed with 0 ? s. 6.1.2.3. slot 3: pcm record left channel audio input frame slot 3 is the left channel output of stac9756/57 input mux, post-adc. stac9756/57 adcs are implemented to support 18-bit resolution. stac9756/57 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 ? s to fill out its 20-bit time slot. 6.1.2.4. slot 4: pcm record right channel audio input frame slot 4 is the right channel output of stac9756/57 input mux, post-adc. stac9756/57 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 ? s to fill out its 20-bit time slot. 6.1.2.5. slots 5-12: reserved audio input frame slots 5-12 are not used by the stac9756/57 and are always stuffed with 0 ? s. 6.2. ac-link low power mode the stac9756/57 ac-link can be placed in the low power mode by programming register 26h to the appropriate value. both bit_clk and sdata_in will be brought to, and held at a logic low voltage level. the ac ? 97 controller can wake up the stac9756/57 by providing the appropriate reset signals. bit description comments 19:4 control register read data stuffed with 0 ? s if tagged "invalid" 3:0 reserved stuffed with 0 ? s table 17. status data port bit assignments sync bit_clk sdata_out note: bit_clk not to scale sdata_in tag write to 0x20 slot 2 per frame data pr4 tag slot 2 per frame figure 16. stac9756/57 powerdown timing 26 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output bit_clk and sdata_in are transitioned low immediately (within the maximum specified time) following the decode of the write to the powerdown register (26h) with pr4. when the ac ? 97 controller driver is at the point where it is ready to pro- gram the ac-link into its low power mode, slots (1 and 2) are assumed to be the only valid stream in the audio output frame (all sources of audio input have been neutralized). the ac ? 97 controller should also drive sync, and sdata_out low after program- ming the stac9756/57 to this low power mode. 6.2.1. waking up the ac-link once the stac9756/57 has halted bit_clk, there are only two ways to ? wake up ? the ac-link. both methods must be activated by the ac'97 controller. the ac-link protocol provides for a ? cold ac'97 reset ? , and a ? warm ac'97 reset ? . the current power down state would ultimately dictate which form of reset is appropriate. unless a ? cold ? or ? register ? reset (a write to the reset register) is performed, wherein the ac'97 registers are initialized to their default values, registers are required to keep state during all power down modes. once powered down, re-acti- vation of the ac-link via re-assertion of the sync signal must not occur for a mini- mum of 4 audio frame times following the frame in which the power down was triggered. when ac-link powers up it indicates readiness via the codec ready bit (input slot 0, bit 15). cold reset - a cold reset is achieved by asserting reset# for the minimum speci- fied time, and then bringing reset# back high. the reset occurs on the rising edge when reset# is deasserted. by asserting and deasserting reset#, bit_clk and sdata_in will be activated, or re-activated as the case may be, and all stac9756/57 control registers will be initialized to their default power on reset values. note: reset# is an asynchronous input. (# denotes active low) warm reset - a warm reset will re-activate the ac-link without altering the current stac9756/57 register values. a warm reset is signaled by driving sync high for a minimum of 1us in the absence of bit_clk. note: within normal audio frames, sync is a synchronous input. however, in the absence of bit_clk, sync is treated as an asynchronous input used in the generation of a warm reset to the stac9756/57. 6.3. i 2 s (zv_port) digital audio interface the i 2 s input is controlled by registers and figure 17 shows the standard i 2 s inter- face timing. see the register section for details on programming the zv_port. left channel right channel z_lrclk, d_lrck z_sclk, d_sclk z_data, i2s_out1/2 msb lsb msb lsb figure 17. i 2 s digital audio interface 2-9756-d1-3.3-0303 27 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 7. stac9756/57 mixer the stac9756/57 includes analog and digital mixers for maximum flexibility. the analog mixer is designed to the ac ? 97 specification to manage the playback and record of all digital and analog audio sources in the pc environment. the analog mixer also includes several extensions of the ac ? 97 specification to support ? all ana- log record ? capability as well as ? pop bypass ? mode for all digital playback. the analog sources include: system audio : digital pcm input and output for business, games and multime- dia cd/dvd : analog cd/dvd-rom audio with internal connections to codec mixer mono microphone : choice of desktop mic, with programmable boost and gain speakerphone : use of system mic and speakers for telephone, dsvd, and video conferencing video : tv tuner or video capture card with internal connections to codec mixer aux/synth : analog fm or wavetable synthesizer, or other internal source the digital mixer includes inputs for the pcm dac, the recorded adc output, and the i 2 s zv_port data. z_data : i 2 s digital audio stream from the pc-card slot of notebook computers source function connection pc_beep pc beep pass thru from pc beeper output phone speakerphone or dlp in from telephony subsystem mic1 desktop microphone from mic jack mic2 second microphone from second mic jack line_in external audio source from line-in jack cd audio from cd-rom cable from cd-rom video audio from tv tuner or video camera cable from tv or vidcap card aux upgrade synth or other external source internal connector pcm out digital audio output from ac ? 97 controller ac-link line_out stereo mix of all sources to output jack dac_out surround stereo dac output to output jack mono_out mic or mix for speakerphone or dlp out to telephony subsystem pcm in digital data from the codec to the ac ? 97 controller ac-link i2s_out1 i 2 s digital output to i 2 s output connector z_data i 2 s digital input from secondary pc-card zv-port source from i 2 s pc-card source spdif/i2s_out2 i 2 s or spdif digital audio output to i 2 s or spdif output connector table 18. stac9756/57 mixer 28 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 7.1. analog mixer input the mixer provides recording and playback of any audio sources or output mix of all sources. the stac9756/57 supports the following input sources: any mono or stereo source mono or stereo mix of all sources 2-channel input w/mono output reference (mic + stereo mix) note: all unused inputs should be tied together and have a capacitor (0.1 f suggested) to ground. 0ah 0ch 0eh 10h 12h 16h 14h pc_beep phone cd aux video linein mic1 mic2 20h:d8 20 db allanalog vs allrecord 6eh:d12 -6db mux adc 04h mono volume mono_out master volume 3d line_out lnlvl volume 3d lnlvl_out 02h 06h mux 1ch 20h:d15 analog audio sources d_lrclk d_sclk z_lrclk z_sclk 6ah:d11 z_data 60h i2sclock interface slot select slot select slot select digital mixer mux mux 6ah:d0-d1 6ah:d2-d3 pcm to i2s out1 pcm to spdif or i2s out2 i2s_out1 d spdif/i2s out2 pcmout 2ah:d5-d4 6ah:d5-d4 74h:d1-d0 6ah:d10-d8 20h:d15 "pop bypass" pcmin ganged3dcontrol 20h:d13 22h:d2-d3 1ah -6db 8eh:d13 monoanalog stereoanalog digital key 20h:d9 adcrecord 0eh:d6 mux vol mute vol mute vol mute vol mute vol mute vol mute vol mute vol mute mux dac 3d record volume vol 6ah:d6-d7 vol 6ah:d12 18h figure 18. stac9756 5v analog mode, 2-channel mixer functional diagram 0ah 0ch 0eh 10h 12h 16h 14h pc_beep phone cd aux video linein mic1 mic2 20h:d8 20 db allanalog vs allrecord 6eh:d12 -6db mux adc 04h mono volume mono_out master volume 3d line_out lnlvl volume 3d lnlvl_out 02h 06h mux 1ch 20h:d15 analog audio sources d_lrclk d_sclk z_lrclk z_sclk 6ah:d11 z_data 60h i2sclock interface slot select slot select slot select digital mixer mux mux 6ah:d0-d1 6ah:d2-d3 pcm to i2s out1 pcm to spdif or i2s out2 i2s_out1 d spdif/i2s out2 pcmout 2ah:d5-d4 6ah:d5-d4 74h:d1-d0 6ah:d10-d8 20h:d15 "pop bypass" pcmin ganged3dcontrol 20h:d13 22h:d2-d3 1ah -6db 8eh:d13 monoanalog stereoanalog digital key 20h:d9 adcrecord 0eh:d6 mux vol mute vol mute vol mute vol mute vol mute vol mute vol mute vol mute mux dac 3d record volume +6db -6db -6db -6db -6db -6db -6db -6db vol 6ah:d12 6ah:d6-d7 vol 18h figure 19. stac9756 +3.3v analog mode and stac9757 2-channel mixer functional diagram 2-9756-d1-3.3-0303 29 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 7.2. mixer analog output the mixer generates three distinct outputs: a stereo mix of all sources for output to the line_out a stereo mix of all sources for output to lnlvl_out a mono, mic only or mix of all sources for mono_out note:mono output of stereo mix is attenuated by -6 db. 7.3. mixer digital input the digital mixer includes inputs for the pcm dac, the recorded adc output, and a single i 2 s zv_port digital input. the zv_port input is generally used for the audio input from zoomvideo enabled pc-cards for notebook computers. external dvd disk players and video capture cards are examples of typical zoomvideo enabled pc-cards. 7.4. mixer digital output the stac9756/57 spdif/i2s_out2 dual mode digital output supports both i 2 s and spdif formats. only one format can be supported at a time. a multiplexer determines which of two input digital input streams are used for the digital output conversion process. these three streams include the pcm out data from the audio controller and the adc recorded output. the normal analog line_out signal can be converted to the i 2 s or spdif formats by using the internal adc to record the ? mix ? output which is the combination of all analog and all digital sources. alter- nately, only the analog sources can be recorded using the adc and then routed to the digital output to support docking schemes while the pop_bypass mode is used to route the dac output directly to the line_out, avoiding the mixer alto- gether. in the case of digital controllers with support for 4 or more channels, the spdif output mode can be used to support compressed 6-channel output streams for delivery to home theater systems. modern applications such as soft dvd decod- ers often generate compressed audio streams. these can be routed on alternate ac-link slots to the spdif output, while the standard 2-channel output is delivered via slots 3 and 4 to the analog stereo outputs. if the digital controller supports 6 channels, a spdif output with 4 analog channels can also be configured. 7.5. pc beep implementation pc beep is active on power up and defaults to an un-muted state. the pc-beep input is routed directly to the mono_out, line_out and lnlvl_out pins of the codec. because the pc_beep input drive is often a full scale digital signal, some resistive attenuation of the pc_beep input is recommended to keep the beep tone within reasonable volume levels. the user should mute this input before using any other mixer input because the pc beep input can contribute noise to the lineout dur- ing normal operation. 30 2-9756-d1-3.3-0303 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 7.6. programming registers address name default location 00h reset 6940h 7.6.1; page 31 02h master volume 8000h 7.6.2.1; page 31 04h lnlvl volume 8000h 7.6.2.2; page 32 and 35 06h master volume mono 8000h 7.6.2.3; page 32 0ah pc beep mixer volume 0000h 7.6.3; page 32 0ch phone mixer volume 8008h 7.6.4.1; page 33 0eh mic mixer volume 8008h 7.6.4.2; page 33 10h line in mixer volume 8808h 7.6.4.3; page 33 12h cd mixer volume 8808h 7.6.4.4; page 33 14h video mixer volume 8808h 7.6.4.5; page 34 16h aux mixer volume 8808h 7.6.4.6; page 34 18h pcm out mixer volume 8808h 7.6.4.7; page 34 1ah record select 0000h 7.6.5; page 34 1ch record gain 8000h 7.6.6; page 35 20h general purpose 0000h 7.6.7; page 35 22h 3d control 0000h 7.6.8; page 36 26h powerdown ctrl/stat 000fh 7.6.9; page 36 28h extended audio id 0205h 7.6.10; page 37 2ah extended audio control/status 0400h 7.6.11; page 38 2ch pcm dac rate bb80h 7.6.12.1; page 40 32h pcm lr adc rate bb80h 7.6.12.2; page 40 3ah spdif control 2a00h 7.6.14.1; page 42 60h z_data volume 8808h 7.6.13; page 40 6ah digital audio control 0000h 7.6.14; page 41 6ch revision code 0000h 7.6.15; page 42 6eh analog special 1000h 7.6.16; page 43 70h 72h enable 0000h 7.6.16.1; page 43 72h analog current adjust 0000h 7.6.16.2; page 43 74h multi-channel selection 0000h 7.6.17; page 44 76h 78h enable 0000h 7.6.18.1; page 46 78h clock access 0000h 7.6.18.2; page 46 7ch vendor id1 8384h 7.6.19.1; page 47 7eh vendor id2 7656h 7.6.19.2; page 47 table 19. programming registers 2-9756-d1-3.3-0303 31 stac9756/57 two channel ac?97 codecs with i 2 s digital i/o and spdif output 7.6.1. reset (00h) default: 6940h writing any value to this register performs a register reset, which causes all regis- ters to revert to their default values. reading this register returns the id code of the part. 7.6.2. play master volume registers (index 02h, 04h, and 06h) these registers manage the output signal volumes. register 02h controls the ste- reo line_out master volume (both right and left channels), register 04h controls the lnlvl_out master volume, and register 06h controls the mono volume out- put. each step corresponds to 1.5 db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. ml5 through ml0 is for left channel level, mr5 through mr0 is for the right channel and mm5 through mm0 is for the mono out channel. when bits d5 and d13 are set in any of these registers it automatically writes all 1 ? s to the next lower 5-bits. the default value is 8000h for registers 02h, 04h, and 06h, which corresponds to 0 db attenuation with mute on. 7.6.2.1. master volume (02h) default: 8000h note: if optional bits d13, d5 of register 02h or d5 of register 06h are set to 1, then the corresponding attenuation is set to 46db and the register reads will produce 1fh as a value for this attenuation/gain block. d15 d14 d13 d12 d11 d10 d9 d8 rsrvd4 se4 se3 se2 se1 se0 id9 id8 d7 d6 d5 d4 d3 d2 d1 d0 id7 id6 id5 id4 id3 id2 id1 id0 mute mx 5 ? mx0 function range 0 00 0000 0db attenuation req. 0 01 1111 46.5 attenuation req. 1 xx xxxx db attenuation req. table 20. play master volume register d15 d14 d13 d12 d11 d10 d9 d8 mute rsrvd ml5 ml4 ml3 ml2 ml1 ml0 d7 d6 d5 d4 d3 d2 d1 d0 reserved mr5 mr4 mr3 mr2 mr1 mr0 32 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.2.2. lnlvl mixer volume (04h) default: 8000h 7.6.2.3. master volume mono (06h) default: 8000h note: if optional bits d13, d5 of register 02h or d5 of register 06h are set to 1, then the corresponding attenuation is set to 46db and the register reads will produce 1fh as a value for this attenuation/gain block. 7.6.3. pc beep mixer volume (index 0ah) default: 0000h note: pc_beep default to 0000h, mute off. this register controls the level for the pc beep input. each step corresponds to approximately 3 db of attenuation. the msb of the register is the mute bit. when this bit is set to 1, the level for that channel is set at - db. pc_beep supports motherboard implementations. the intention of routing pc_beep through the stac9756/57 mixer is to eliminate the requirement for an onboard speaker by guar- anteeing a connection to speakers connected via the output jack. in order for this to be viable the pc_beep signal needs to reach the output jack at all times. note: the pc_beep is routed to the mono outputs even when the stac9756/57 is in a reset state. this is so that power on self test (post) codes can be heard by the user in case of a hardware problem with the pc. for further pc_beep implementa- tion details please refer to the ac ? 97 technical faq sheet. the default value can be 0000h, which corresponds to 0 db attenuation with mute off. d15 d14 d13 d12 d11 d10 d9 d8 mute rsrvd ml5 ml4 ml3 ml2 ml1 ml0 d7 d6 d5 d4 d3 d2 d1 d0 reserved mr5 mr4 mr3 mr2 mr1 mr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved mm5 mm4 mm3 mm2 mm1 mm0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved pv3 pv2 pv1 pv0 rsrvd mute pv3 ? pv0 function 0 0000 0 db attenuation 0 1111 45 db attenuation 1xxxx db attenuation table 21. pc_beep register 2-9756-d1-3.3-0303 33 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.4. analog mixer input gain registers (index 0ch - 18h) these registers control the gain/attenuation for each of the analog inputs. each step corresponds to approximately 1.5 db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. register 0eh (mic volume register) has an extra bit that is for a 20 db boost. when bit 6 is set to 1, the 20 db boost is on. the default value for stereo registers is 8808h, corresponding to 0 db gain with mute on. 7.6.4.1. phone mixer volume (0ch) default: 8008h 7.6.4.2. mic mixer volume (0eh) default: 8008h 7.6.4.3. line in mixer volume (10h) default: 8808h 7.6.4.4. cd mixer volume (12h) default: 8808h mute gx4 ? gx0 function 0 00000 +12 db gain 0 01000 0 db gain 0 11111 -34.5 db gain table 22. analog mixer input gain register d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gn4 gn3 gn2 gn1 gn0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 rsrvd 20db rsrvd gn4 gn3 gn2 gn1 gn0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 34 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.4.5. video mixer volume (14h) default: 8808h 7.6.4.6. aux mixer volume (16h) default: 8808h 7.6.4.7. pcm out mixer volume (18h) default: 8808h (8888h in secondary mode) 7.6.5. record select (1ah) default: 0000h (corresponding to mic in) used to select the record source independently for right and left. d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 reserved sl2 sl1 sl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved sr2 sr1 sr0 sr2 ? sr0 right record source sl2 ? sl0 left record source 0 mic 0 mic 1 cd in (right) 1 cd in (l) 2 video in (right) 2 video in (l) 3 aux in (right) 3 aux in (l) 4 line in (right) 4 line in (l) 5 stereo mix (right) 5 stereo mix (l) 6 mono mix 6 mono mix 7 phone 7 phone table 23. record select control registers 2-9756-d1-3.3-0303 35 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.6. record gain (1ch) default: 8000h (corresponding to 0 db gain with mute on) the 1ch register adjusts the stereo input record gain. each step corresponds to 1.5 db. 22.5 db corresponds to 0f0fh and 000fh respectively. the msb of the regis- ter is the mute bit. when this bit is set to 1, the level for that channel(s) is set at - db. 7.6.7. general purpose (20h) default: 0000h this register is used to control some miscellaneous functions. table 25 gives a summary of each bit and its function. the ms bit controls the mic selector. the lpbk bit enables loopback of the adc output to the dac input without involving the ac-link, allowing for full system performance measurements. d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr3 gr2 gr1 gr0 mute gx3 ? gx0 function 0 1111 +22.5 db gain 0 0000 0 db gain 1xxxx- gain table 24. record gain registers d15 d14 d13 d12 d11 d10 d9 d8 pop byp rsrvd 3d reserved mix ms d7 d6 d5 d4 d3 d2 d1 d0 lpbk reserved bit function 3d 3d stereo enhancement on/off 1 = on mix mono output select 0 = mix, 1= mic ms mic select 0 = mic1, 1 = mic2 pop byp dac bypasses mixer and connects directly to line out lpbk adc/dac loopback mode table 25. general purpose register 36 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.8. 3d control (22h) default: 0000h this register is used to control the 3d stereo enhancement function, sigmatel sur- round 3d (ss3d), built into the ac ? 97 component. note that register bits dp3-dp2 are used to control the separation ratios in the 3d control for line_out. ss3d pro- vides for a wider soundstage extending beyond the normal 2-speaker arrangement. note that the 3d bit in the general purpose register (20h) must be set to 1 to enable ss3d functionality and for the bits in 22h to take effect. the three separation ratios are implemented as shown in table 26. the separation ratio defines a series of equations that determine the amount of depth difference (high, medium, and low) perceived during two-channel playback. the ratios pro- vide for options to narrow or widen the soundstage. 7.6.9. powerdown ctrl/stat (26h) default: 000fh this read/write register is used to program powerdown states and monitor sub- system readiness. the eapd external control and gpo is also supported through this register. d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved dp3 dp2 reserved dp3, dp2 line_out separation ratio 0 0 0 (off) 0 1 3 (low) 1 0 4.5 (med) 1 1 6 (high) table 26. 3d control registers d15 d14 d13 d12 d11 d10 d9 d8 eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 d7 d6 d5 d4 d3 d2 d1 d0 reserved ref anl dac adc bit function eapd/gpo external amplifier power down/general purpose output ref vref ? s up to nominal level anl analog mixers, etc. ready dac dac section ready to playback data adc adc section ready to playback data table 27. powerdown status registers 2-9756-d1-3.3-0303 37 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.9.1. ready status the lower half of this register is read only status, a "1" indicating that the subsection is "ready". ready is defined as the subsection ? s ability to perform in its nominal state. when this register is written, the bit values that come in on ac-link will have no effect on read only bits 0-7. when the ac-link "codec ready" indicator bit (sdata_in slot 0, bit 15) is a 1, it indicates that the ac-link and ac ? 97 control and status registers are in a fully oper- ational state. the ac ? 97 controller must further probe this powerdown control/sta- tus register to determine exactly which subsections, if any are ready. when this register is written, the bit values that come in on ac-link will have no effect on read only bits 0-7. 7.6.9.2. powerdown controls the stac9756/57 is capable of operating at reduced power when no activity is required. the state of power down is controlled by the powerdown register (26h). see the section "low power modes" for more information. 7.6.9.3. external amplifier power down control the eapd bit 15 of the powerdown control/status register (index 26h) directly controls the output of the eapd output, pin 45, and produces a logical "1" when this bit is set to logic high. this function is used to control an external audio amplifier power down. eapd = 0 places approximately 0v on the output pin, enabling an external audio amplifier. eapd = 1 places approximately dvdd on the output pin, disabling the external audio amplifier. audio amplifiers that operate with reverse polarity will likely require an external inverter to maintain software driver compatibil- ity. 7.6.10. extended audio id (28h) default: 0205h the extended audio id register is a read only register. id1 and id0 echo the config- uration of the codec as defined by the programming of pins 45 and 46 externally. ? 00 ? returned defines the codec as the primary codec, while any other code identi- fies the codec as one of three secondary codec possibilities. sdac=0 tells the con- troller that the stac9756/57 is a two-channel codec as defined by the intel spec. the default condition assumes that 0, 0 are loaded in the mc1 and mc0 bits of the multi-channel programming register (index 74h). with 0s in the mcx bits, the codec slot assignments are as per the ac ? 97 specification recommendations. if the mcx bits do not contain 0s, the slot assignments are as per table 36 in section 7.6.17, describing the multi-channel programming register (index 74h). the vra d15 d14 d13 d12 d11 d10 d9 d8 id1 id0 reserved amap ldac d7 d6 d5 d4 d3 d2 d1 d0 sdac cdac reserved spdif dra vra 38 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output bit, d0, will return a 1 indicating that the codec supports the optional variable sample rate conversion as defined by the ac ? 97 specification. 7.6.11. extended audio control/status (2ah) default: 0400h 7.6.11.1. variable rate sampling enable the extended audio status control register also contains one active bit to enable or disable the variable sampling rate capabilities of the dacs and adcs. if the vra, bit d0, is 1 the variable sample rate control registers (2ch and 32h) are active, and ? on-demand ? slot data required transfers are allowed. if the vra bit is 0, the dacs and adcs will operate at the default 48 khz data rate. the stac9756/57 supports ? on-demand ? slot request flags. these flags are passed from the codec to the ac ? 97 controller in every audio input frame. each time a slot request flag is set (active low) in a given audio frame, the controller will pass the next pcm sample for the corresponding slot in the audio frame that immediately follows. the vra enable bit must be set to 1 to enable ? on-demand ? data transfers. if the vra enable bit is not set, the codec will default to 48 khz transfers and every audio frame will include an active slot request flag and data is transferred every frame. for variable sample rate output, the codec examines its sample rate control regis- ters, the state of the fifos, and the incoming sdata_out tag bits at the beginning of each audio output frame to determine which slotreq bits to set active (low). slotreq bits are asserted during the current audio input frame for active output slots, which will require data in the next audio output frame. for variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. thus, even in variable sample rate mode, the codec is always the master: for sdata_in (codec to controller), the codec sets the tag bit; for sdata_out (controller to codec), the codec sets the slotreq bit and then bit function idx external cid pin status amap multi-channel slot support ldac low frequency effect support (always 0) sdac surround dac support (always 0) cdac center channel support (always 0) spdif spdif digital audio support dra double rate audio support (always 0) vra variable sample rates supported table 28. extended audio id register functions d15 d14 d13 d12 d11 d10 d9 d8 reserved spcv reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved spsa1 spsa0 rsrvd spdif rsrvd vra enable 2-9756-d1-3.3-0303 39 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output checks for the tag bit in the next frame. whenever vra is set to 0 the pcm rate registers (2ch and 32h) are overwritten with bb80h (48 khz). note:see section 7.6.17.1 for digital audio slot select. 7.6.11.2. spdif the spdif bit in the extended audio status control register is used to enable and disable the spdif functionality within the stac9756/57. if the spdif is set to a 1, then the function is enabled and when set to a 0 it is disabled. 7.6.11.3. spcv (spdif configuration valid) the spcv bit is read only and indicates whether or not the spdif system is set up correctly. when spcv is a 0, it indicates the system configuration is invalid and valid if it is a 1. 7.6.11.4. spsa1, spsa0 (spdif slot assignment) spsa1 and spsa0 combine to provide the slot assignments for the spdif data. the following details the slot assignment relationship between spsa1 and spsa0. 7.6.12. pcm dac rate registers (2ch and 32h) the internal sample rate for the dacs and adcs are controlled by the value in these read/write registers that contain a 16-bit unsigned value between 0 and 65535 representing the conversion rate in hz. in vra mode (register 2ah bit d0 = 1), if the value written to these registers is supported that value will be echoed back when read, otherwise the closest (higher in the case of a tie) sample rate is supported and returned. per pc 99 / pc 2001 specification, independent sample rates are sup- ported for record and playback. whenever vra is set to 0 the pcm rate registers (2ch and 32h) will readback bb80h (48 khz). spsa[1,0] slot assignment comments 00 3 & 4 spdif source data slot assignment 01 7 & 8 2-ch codec default 10 6 & 9 4-ch codec default 11 10 & 11 6-ch codec default table 29. slot assignment relationship between spsa1 and spsa0 sample rate sr15-sr0 value 8 khz 1f40h 11.025 khz 2b11h 16 khz 3e80h 22.05 khz 5622h 44.1 khz ac44h 48 khz bb80h table 30. hardware supported sample rates 40 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.12.1. pcm dac rate (2ch) default: bb80h 7.6.12.2. pcm lr adc rate (32h) default: bb80h 7.6.13. z_data volume (60h) default: 8000h this register controls the gain/attenuation mix of the z_data i 2 s digital input. the i 2 s digital input has a mute and volume control. each step corresponds to approxi- mately 1.5 db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. the default value for this stereo register is 8000h corresponding to 0 db gain with mute on. d15 d14 d13 d12 d11 d10 d9 d8 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 d7 d6 d5 d4 d3 d2 d1 d0 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 d15 d14 d13 d12 d11 d10 d9 d8 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 d7 d6 d5 d4 d3 d2 d1 d0 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 mute gx4 ? gx0 function 0 00000 0 db gain 0 11111 -46.5 db gain 1 xxxxx - db gain table 31. z_data register 2-9756-d1-3.3-0303 41 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.14. digital audio control (6ah) default: 0000h this read/write register is used to program the digital mixer input status. in the default state, the pcm dac path is enabled and the i 2 s z_data and the adc record inputs are disabled. the pcm dis bit is used to disable the pcm dac input. the adc ena bit is used to enable the adc recorded input. the i 2 s ena bit is used to enable the i 2 s z_data input. the i2s_sel bit is used to switch between the default spdif digital output mode and the alternate i 2 s output mode available at pin-48. the i 2 s ena bit enables the zv_port, zv_data line. admix gain1 and admix gain0 bits control the adc gain through the digital mixer to the dac. the dox pins control the input source for the pcm to digital output converters. table 33 describes the four available options. note:see section 7.6.17.1 for digital audio slot select. d15 d14 d13 d12 d11 d10 d9 d8 reserved i2s sel i2s ena zvp ena adc ena pcm dis d7 d6 d5 d4 d3 d2 d1 d0 admix gain1 admix gain0 i2s ssl1 i2s ssl0 do3 do2 do1 do0 bit(s) name description 15:13 rsrvd reserved 12 i2s sel selects i2s_out2(1) or spdif(0 defaul) output format from d_spdif/i2s_out2 11 i2s ena enables the i 2 s outputs 10 zvp ena enables the zv_port data from z_data 9 adc ena enables the adc record input 8 pcm dis disables the pcm input 7:6 admix gain[1,0] 00 = 0db = 0.75, 01 = -3.5db = 0.5, 10 = -9.5db = 0.25, 11 = +2.5db = 1.0 5:4 i2s sls[1,0] 00 = 3 & 4, 01 = 7 & 8, 10 = 6 & 9, 11 = 10 & 11 3:2 do[3,2] adc, or pcm data muxed to i2s_out1 1:0 do[1,0] adc, or pcm data muxed to d_spdif/i2s_out2 note: 1. i 2 s out2 slot assignment is controlled by spsa[1,0] in reg 2ah. 2. see section 7.6.17.1 for digital slot selection. table 32. digital audio control (6ah) registers i2s_out1 do3, do2 i2s_out2 do1, do0 effect 0,0 0,0 pcm data from the ac-link to spdif 0,1 0,1 disable 1,0 1,0 adc record data 1,1 1,1 disable table 33. digital output source selection table 42 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.14.1. spdif control (3ah) default: 2a00h register 3ah is a read/write register that controls spdif functionality and manages bit fields propagated as channel status (or sub-frame in the v case). with exception of v, this register should only be written to when the spdif transmitter is disabled (spdif bit register 2 ah is ? 0 ? ). this ensures that control and status information start up correctly at the beginning of spdif transmission. the default is 2a00h which sets the spdif output sample rate at 48khz and the normal spdif expecta- tions . 7.6.15. revision code (6ch) default: 0000h the device revision register (index 6ch) contains a software readable revision-spe- cific code used to identify performance, architectural, or software differences between various device revisions. bits 7:0 of the revision register are user read- able; bits 15:8 are not used at this time and will return zeros when read. the lower order bits of the revision register (bits 7:0) are currently set to 00h, and will likely change if there are any stac9756/57 metal revisions. this value can be used by the audio driver, or miniport driver in the case of win98 ? wdm approaches, to adjust software functionality to match the feature-set of the stac9756/57. this will allow the software driver to identify any required operational differences between the existing stac9756/57 and any future versions. d15 d14 d13 d12 d11 d10 d9 d8 #v drs spsr1 spsr0 l cc6 cc5 cc4 d7 d6 d5 d4 d3 d2 d1 d0 cc3 cc2 cc1 cc0 pre copy #pcm/ audio pro bit(s) name description 15 #v validity bit is set indicating each sub-frame ? s samples are invalid. if #v is 0, then it indicates that each sub-frame was transmitted and received correctly by the interface. 14 drs double rate spdif is not supported therefore the bit is always 0. 13:12 spsr[1,0] spdif sample rate is currently set to 48khz. optional rates are not supported. 11 l generation level is defined by the iec standard, or as appropriate. 10:4 cc[6:0] category code is defined by the iec standard or as appropriate by media. 3 pre pre-emphasis is 50/15 usec when set to 1 and 0 usec when set to 0. 2 copy copyright is asserted when the bit is set to 1 and not asserted if set to 0. 1 /audio non-audio or non-pcm format = 1, pcm data = 0. 0 pro professional use of the channel = 1, consumer use = 0. table 34. spdif control (3ah) registers d15 d14 d13 d12 d11 d10 d9 d8 00 00000 0 d7 d6 d5 d4 d3 d2 d1 d0 00 00000 0 2-9756-d1-3.3-0303 43 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.16. analog special (6eh) default: 1000h the analog special register has several bits used to control various functions spe- cific to the stac9756/57. bit d1, dac -6db, is used to reduce the dac output level by 6db. similarly, bit d0, adc -6db, attenuates any signal input to the adc by 6db. this second function is very useful in applications with greater than 1vrms input lev- els, as is the case with many cdroms. the ac ? 97 all mix, bit d12 of register 6eh, controls the record source when the stereo mix option is selected for recording. if the ac97 mode is selected (default logic 1), the stereo mix record option will include the sum of the analog sources with or without 3d enhancement, and the main pcm dac output. if the ? all ana- log record ? option is selected, the stereo mix record option will include the sum of the analog sources only, with or without 3d enhancement. the ? ac ? 97 mode ? is useful for recording all sound sources. the ? all analog ? mode is useful in conjunc- tion with the pop bypass mode for recording all analog sources, which are often further processed and combined with other pcm data to be output directly to the dac outputs which are configured in pop_bypass mode using the general pur- pose register (index 20h). 7.6.16.1. 72h enable (70h) default: 0000h 7.6.16.2. analog current adjust (72h) default: 0000h the analog current adjust register (index 72h) is a locked register and can only be properly written and read from when abbah has been written into register 70h. the biasx bits allow the analog current to be adjusted with minimal reduction in perfor- mance. the ? 50% analog current setting is not recommended when a 5v analog d15 d14 d13 d12 d11 d10 d9 d8 reserved ac97 all mix reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved dac -6db adc -6db d15 d14 d13 d12 d11 d10 d9 d8 en15 en14 en13 en12 en11 en10 en9 en8 d7 d6 d5 d4 d3 d2 d1 d0 en7 en6 en5 en4 en3 en2 en1 en0 d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 int apop reserved bias1 bias0 rsrvd 44 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output supply is used. the ? 50% setting for 3.3v supplies is recommended to reduce power consumption for notebook computers to its lowest level. 7.6.16.3. internal power-on/off anti-pop circuit the stac9756/57 includes an internal power supply anti-pop circuit that prevents audible clicks and pops from being heard when the codec is powered on and off. this function is accomplished by delaying the charge/discharge of the vref capac- itor (pin 27). c vref value of 1uf will cause a turn-on delay of roughly 3 seconds, which will allow the power supplies to stabilize before the codec outputs are enabled. the delay will be extended to 30 seconds if a value of c vref value of 10uf is used. the codec outputs are also kept stable for the same amount of time at power-off to allow the system to be gracefully turned off. the int_apop bit d7 of register 72 allows this delay circuit to be bypassed for rapid production testing. any external component anti-pop circuit is unaffected by the internal circuit. 7.6.17. multi-channel selection (74h) default: 0000h this read/write register is used to program the various options for multi-channel configurations. only the two lsbs are used (mc0 and mc1), and they define which ac-link slot data is supplied to the two pcm output channels on the stac9756/57. also see ? multiple codec support ? discussion for information on the use of external pins cid1 and cid0. bias1 bias0 analog current 0 0 normal current 0 1 -50% analog current 1 0 -25% analog current 1 1 +25% analog current table 35. analog current adjust d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved mc1 mc0 external pins cid1, cid0 extended audio id 28h id1, id0 codec designation multi-channel selection 74h mc1, mc0 pcm out left pcm out right cid1 = dvdd or floating, cid0 = dvdd or floating 0, 0 primary, 00 0, 0 slot 3 slot 4 0, 1 slot 7 slot 8 1, 0 slot 6 slot 9 1, 1 slot 10 slot 11 table 36. stac9756/57 multi-channel programming register 2-9756-d1-3.3-0303 45 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.17.1. digital audio slot selection the spsa1 and spsa0 digital slot select bits determine which of the ac-link slots are routed to the pcm to i 2 s and pcm to spdif converters. the ssl1 and ssl0 determine which slots are routed to the pcm to i2s1 converter. tables 37, 38, and 39 describe the assignment options. cid1 = dvdd or floating, cid0 = gnd 0, 1 secondary, 01 0, 0 slot 3 slot 4 0, 1 slot 7 slot 8 1, 0 slot 6 slot 9 1, 1 slot 10 slot 11 cid1 = gnd, cid0 = dvdd or floating 1, 0 secondary, 10 0, 0 slot 7 slot 8 0, 1 slot 3 slot 4 1, 0 slot 10 slot 11 1, 1 slot 6 slot 9 cid1 = gnd, cid0 = gnd 1, 1 secondary, 11 0, 0 slot 6 slot 9 0, 1 slot 10 slot 11 1, 0 slot 3 slot 4 1, 1 slot 7 slot 8 spsa1, spsa0 spdif left spdif right 0, 0 slot 3 slot 4 0, 1 slot 7 slot 8 1, 0 slot 6 slot 9 1, 1 slot 10 slot 11 table 37. spdif slot selection (reg. 2ah: d5, d4 with reg. 6ah: d12 (i2s sel) = 0) spsa1, spsa0 i2s_out2 left i2s_out2 right 0, 0 slot 3 slot 4 0, 1 slot 7 slot 8 1, 0 slot 6 slot 9 1, 1 slot 10 slot 11 table 38. i 2 s out2 slot selection (reg. 2ah: d5, d4 with reg. 6ah: d12 (i2s sel) = 1) i2s ssl1, i2s ssl0 i2s_out1 left i2s_out1 right 0, 0 slot 3 slot 4 0, 1 slot 7 slot 8 1, 0 slot 6 slot 9 1, 1 slot 10 slot 11 table 39. i 2 s out1 slot selection (reg. 6ah: d5, d4) external pins cid1, cid0 extended audio id 28h id1, id0 codec designation multi-channel selection 74h mc1, mc0 pcm out left pcm out right table 36. stac9756/57 multi-channel programming register (continued) 46 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.18. clock access (index 76h and 78h) the clock access register (index 78h) is a locked register and can only be properly written and read from when abbah has been written into register 76h. the stac9756/57 can operate as a remotely located secondary without a master clock input or local crystal. the stac9756/57 can synchronize to the bit_clk after two register adjustments. the first adjustment starts the synchronization process by enabling the alt clk d12, clk inv d14, and osc pwd d10 bits of register 78h. the xtal_in can either be left floating, or connected to dgnd with a 10k ? or larger resistor. 7.6.18.1. 78h enable (76h) default: 0000h 7.6.18.2. clock access (78h) default: 0000h d15 d14 d13 d12 d11 d10 d9 d8 en15 en14 en13 en12 en11 en10 en9 en8 d7 d6 d5 d4 d3 d2 d1 d0 en7 en6 en5 en4 en3 en2 en1 en0 d15 d14 d13 d12 d11 d10 d9 d8 rsrvd alt clk reserved d7 d6 d5 d4 d3 d2 d1 d0 xtal2 xtal1 xtal0 dith dis dith en1 dith en0 osc pwd hpass filt bit(s) name description 12 altclk selects/enables clock doubler for secondary mode 7:5 xtal[2:0] xtal oscillator power level 4 dith dis adc sigma delta modulator (sdm) dither disable 3:2 dith en[1:0] adc sdm dither rate 1 osc pwd xtal oscillator disable (powerdown) 0 hpass filt adc high pass filter bypass table 40. spdif control (3ah) registers 2-9756-d1-3.3-0303 47 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 7.6.19. vendor id1 and id2 (index 7ch and 7eh) these two registers contain four 8-bit id codes. the first three codes have been assigned by microsoft using their plug and play vendor id methodology. the fourth code is a sigmatel, inc. assigned code identifying the stac9756/57. the id1 reg- ister (index 7ch) contains the value 8384h, which is the first (83h) and second (84h) characters of the microsoft id code. the id2 register (index 7eh) contains the value 7656h, which is the third (76h) of the microsoft id code, and 56h which is the stac9756/57 id code. note: the lower half of the vendor id2 register (index 7eh) currently contains the value 56h identifying the stac9756/57. this value can be used by the audio driver, or miniport driver in the case of win98 ? , to adjust software functionality to match the feature-set of the stac9756/57. this portion of the register will likely contain different values if the software profile of the stac9756/57 changes, as in the case of silicon level device modifications. this will allow the software driver to identify any required operational differences between the existing stac9756/57 and any future versions. 7.6.19.1. vendor id1 (7ch) default: 8384h 7.6.19.2. vendor id2 9756 (7eh) default: 7656h d15 d14 d13 d12 d11 d10 d9 d8 10 00001 1 d7 d6 d5 d4 d3 d2 d1 d0 10 00010 0 d15 d14 d13 d12 d11 d10 d9 d8 01 11011 0 d7 d6 d5 d4 d3 d2 d1 d0 01 01011 0 48 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 8. low power modes the stac9756/57 is capable of operating at reduced power when no activity is required. the state of power down is controlled by the powerdown register (26h). there are 7 commands of separate power down. the power down options are listed in table 41. the first three bits , pr0..pr2, can be used individually or in combination with each other, and control power distribution to the adc ? s, dac ? s and mixer. the last analog power control bit, pr3, affects analog bias and reference voltages, and can only be used in combination with pr1, pr2, and pr3. pr3 essentially removes power from all analog sections of the codec, and is generally only asserted when the codec will not be needed for long periods. pr0 and pr1 control the pcm adc ? s and dac ? s only. pr2 and pr3 do not need to be "set" before a pr4, but pr0 and pr1 must be "set" before pr4. the figure 20 illustrates one example procedure to do a complete powerdown of stac9756/57. from normal operation, sequential writes to the powerdown regis- ter are performed to power down stac9756/57 a piece at a time. after everything has been shut off, a final write (of pr4) can be executed to shut down the ac-link. the part will remain in sleep mode with all its registers holding their static values. to wake up, the ac'97 controller will send an extended pulse on the sync line, issuing a warm reset. this will restart the ac-link (resetting pr4 to zero). the grp bits function pr0 pcm in adc ? s & input mux powerdown pr1 pcm out dacs powerdown pr2 analog mixer powerdown (vref still on) pr3 analog mixer powerdown (vref off) pr4 digital interface (ac-link) powerdown (extnl clk off) pr5 internal clk disable table 41. low power modes warm reset cold reset ready =1 normal adcs off pr0 dacs off pr1 analog off pr2 or pr3 digital i/f off pr4 shut off ac-link default pr0=0 & adc=1 pr1=0 & dac=1 pr2=0 & anl=1 pr0=1 pr1=1 pr2=1 pr4=1 figure 20. example of stac9756/57 powerdown/powerup flow 2-9756-d1-3.3-0303 49 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output stac9756/57 can also be woken up with a cold reset. a cold reset will reset all of the registers to their default states. when a section is powered back on, the power- down control/status register (index 26h) should be read to verify that the section is ready (stable) before attempting any operation that requires it. figure 21 illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. this configuration can be used when playing a cd (or external line_in source) through stac9756/57 to the speakers, while most of the system in low power mode. the procedure for this fol- lows the previous except that the analog mixer is never shut down. warm reset normal adcs off pr0 dacs off pr1 digital i/f off pr4 shut off ac-link pr0=0 & adc=1 pr1=0 & dac=1 pr0=1 pr1=1 pr4=1 figure 21. stac9756/57 powerdown/powerup flow with analog still alive 50 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 9. multiple codec support the stac9756/57 provides support for the multi-codec option according to the intel ac ? 97, rev 2.1 specification. by definition there can be only one primary codec (codec id 00) and up to three secondary codecs (codec ids 01,10, and 11). the codec id functions as a chip select. secondary devices therefore have completely orthogonal register sets; each is individually accessible and they do not share regis- ters. 9.1. primary/secondary codec selection in a multi-codec environment the codec id is provided by external programming of pins 45 and 46 (cid0 and cid1). the cid pin electrical function is logically inverted from the codec id designation. the corresponding pin state and its associated codec id are listed in table 42. also see slot assignment discussion, ? multi-channel programming register (index 74) ? . 9.1.1. primary codec operation as a primary device the stac9756/57 is completely compatible with existing ac'97 definitions and extensions. primary codec registers are accessed exactly as defined in the ac'97 component specification and ac'97 extensions. the stac9756/57 operates as primary by default, and the external id pins (45 and 46), have internal pull-ups so that these pins may be left as no-connects for primary operation. when used as the primary codec, the stac9756/57 generates the master ac-link bit_clk for both the ac'97 digital controller and any secondary codecs. the stac9756/57 can support up to 4, 10 k ? 50 pf loads on the bit_clk. this is to insure that up to 4 codec implementations will not load down the clock output. 9.1.2. secondary codec operation when the stac9756/57 is configured as a secondary device the bit_clk pin is configured as an input at power up. using the bit_clk provided by the primary codec insures that everything on the ac-link will be synchronous. as a secondary device it can be defined as codec id 01, 10, or 11 in the two-bit field(s) of the extended audio and/or extended modem id register(s). cid1 state cid0 state codec id codec status dvdd or floating dvdd or floating 00 primary dvdd or floating 0v 01 secondary 0v dvdd or floating 10 secondary 0v 0v 11 secondary table 42. codec id selection 2-9756-d1-3.3-0303 51 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 9.2. secondary codec register access definitions the ac ? 97 digital controller can independently access primary and secondary codec registers by using a 2-bit codec id field (chip select) which is defined as the lsbs of output slot 0. for secondary codec access, the ac ? 97 digital controller must invalidate the tag bits for slot 1 and 2 command address and data (slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the codec id field (slot 0, bits 1 and 0). as a secondary codec, the stac9756/57 will disregard the command address and command data (slot 0, bits 14 and 13) tag bits when it sees a 2-bit codec id value (slot 0, bits 1 and 0) that matches its configuration. in a sense the secondary codec id field functions as an alternative valid command address (for secondary reads and writes) and command data (for secondary writes) tag indicator. secondary codecs must monitor the frame valid bit, and ignore the frame (regard- less of the state of the secondary codec id bits) if it is not valid. ac ? 97 digital con- trollers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the secondary codec id bits are set. this method is designed to be backward compatible with existing ac ? 97 controllers and codecs. there is no change to output slot 1 or 2 definitions. output tag slot (16-bits) bit description 15 frame valid 14 slot 1 valid command address bit ( ? primary codec only) 13 slot 2 valid command data bit ( ? primary codec only) 12-3 slot 3-12 valid bits as defined by ac'97 2 reserved (set to ? 0 ? ) ? 1-0 2-bit codec id field (00 reserved for primary; 01, 10, 11 indicate secondary) note: ? new definitions for secondary codec register access table 43. secondary codec register access slot 0 bit definitions 52 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 10. testability the stac9756/57 has two test modes. one is for ate in-circuit test and the other is restricted for sigmatel ? s internal use. stac9756/57 enters the ate in circuit test mode if sdata_out is sampled high at the trailing edge of reset#. once in the ate test mode, the digital ac-link outputs (bit_clk and sdata_in) are driven to a high impedance state. this allows ate in-circuit testing of the ac'97 controller. use of the ate test mode is the recommended means of removing the codec from the ac-link when another codec is to be used as the primary. this case will never occur during standard operating conditions. once either of the two test modes have been entered, the stac9756/57 must be issued another reset# with all ac-link signals held low to return to the normal operating mode. 2-9756-d1-3.3-0303 53 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 11. pin description dvdd1 1 xtl_in 2 xtl_out 3 dvss1 4 sdata_out 5 bit_clk 6 dvss2 7 sdata_in 8 dvdd2 9 sync 10 reset# 11 pc_beep 12 24 line_in_r 23 line_in_l 22 mic2 21 mic1 20 cd_r 19 cd_gnd 18 cd_l 17 video_r 16 video_l 15 aux_r 14 aux_l 13 phone 36 line_out_r 35 line_out_l 34 z_sclk 33 z_data 32 cap2 31 z_lrclk 30 afilt2 29 afilt1 28 vrefout 27 vref 26 avss1 25 avdd1 mono_out 37 avdd2 38 lnlvl_out_l 39 d_sclk 40 lnlvl_out_r 41 avss2 42 d_lrclk 43 i2s_out1 44 cid0 45 cid1 46 eapd 47 spdif/i2s_out2 48 figure 22. stac9756/57 pin description drawing 48-pin tqfp 54 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 11.1. digital i/o these signals connect the stac9756/57 to its ac ? 97 controller counterpart, an external crystal, multi-codec selection and external audio amplifier. pin name pin # type description reset# 11 i ac ? 97 master h/w reset xtl_in 2 i 24.576 mhz crystal or external oscillator xtl_out 3 o 24.576 mhz crystal sync 10 i 48 khz fixed rate sample sync bit_clk 6 i/o 12.288 mhz serial data clock sdata_out 5 i serial, time division multiplexed, ac ? 97 input stream sdata__in 8 o serial, time division multiplexed, ac ? 97 output stream cid0 45 i multi-codec id select ? bit 0 cid1 46 i multi-codec id select ? bit 1 eapd 47 o external amplifier power down z_data 33* i zv_port i 2 s digital data input i2s_out1 44 o i 2 s digital data output d_sclk 40 o i 2 s digital data bit clock d_lrclk 43 o i 2 s digital data left/right clock z_sclk 34* i zv_port i 2 s digital data bit clock z_lrclk 31* i zv_port i 2 s digital data left/right clock spdif/i2s_out2 48 o dual mode i 2 s/spdif digital output note: * pullups recommended if not used. table 44. digital connection signals 2-9756-d1-3.3-0303 55 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 11.2. analog i/o these signals connect the stac9756/57 to analog sources and sinks, including microphones and speakers. note: * any unused input pins should be tied together through a capacitor (0.1 f suggested) to ground, except the mic inputs which should have their own capacitor to ground if not used. 11.3. filter/references these signals are connected to resistors, capacitors, specific voltages. pin name pin # type description pc-beep 12 i* pc speaker beep pass-through phone 13 i* from telephony subsystem speakerphone (or dlp:down line phone) mic1 21 i* desktop microphone input mic2 22 i* second microphone input line_in_l 23 i* line in left channel line_in_r 24 i* line in right channel cd_l 18 i* cd audio left channel cd_gnd 19 i* cd audio analog ground cd_r 20 i* cd audio right channel video_l 16 i* video audio left channel video_r 17 i* video audio right channel aux_l 14 i* aux left channel aux_r 15 i* aux right channel line_out_l 35 o line out left channel line_out_r 36 o line out right channel mono_out 37 o to telephony subsystem speakerphone (or dlp ? down line phone) lnlvl_out_l 39 o line level out left channel lnlvl_out_r 41 o line level out right channel table 45. analog connection signals signal name pin number type description vref 27 o reference voltage vrefout 28 o reference voltage out 5ma drive (intended for mic bias) afilt1 29 o anti-aliasing filter cap - adc channel afilt2 30 o anti-aliasing filter cap - adc channel cap2 32 o adc reference cap table 46. filtering and voltage references 56 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 11.4. power and ground signals pin name pin # type description avdd1 25 i analog vdd = 5.0v or 3.3v avdd2 38 i analog vdd = 5.0v or 3.3v avss1 26 i analog gnd avss2 42 i analog gnd dvdd1 1 i digital vdd = 3.3v dvdd2 9 i digital vdd = 3.3v dvss1 4 i digital gnd dvss2 7 i digital gnd table 47. power and ground signals 2-9756-d1-3.3-0303 57 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 12. package drawing key tqfp dimensions d9.00 mm d1 7.00 mm e9.00 mm e1 7.00 mm a (lead width) 0.20 mm e (pitch) 0.50 mm thickness 1.4 mm table 48. 48-pin tqfp package dimensions 48 pin tqfp a d1 d e e1 e 38 26 14 2 figure 23. 48-pin tqfp package drawing 58 2-9756-d1-3.3-0303 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 13. appendix a: split independent power supply operation in pc applications, one power supply input to the stac9756/57 may be derived from a supply regulator (as shown in figure 24) and the other directly from the pci power supply bus. when power is applied to the pc, the regulated supply input to the ic will be applied some time delay after the pci power supply. without proper on-chip partitioning of the analog and digital circuitry, some manufacturer ? s codecs would be subject to on-chip scr type latch-up. sigmatel ? s stac9756/57 specifically allows power-up sequencing delays between the analog (avddx) and digital (vdddx) supply pins. these two power supplies can power-up independently and at different rates with no adverse effects to the codec. the ic is designed with independent analog and digital circuitry that prevents on-chip scr type latch-up. 0.1 f 1 f 0.1 f 0.1 f 10 f 0.1 f *suggested avdd1 avdd2 dvdd1 dvdd2 xtl_in xtl_out 9 2 3 27 pf 27 pf 24.576 mhz 1 38 25 pc_beep 12 phone 13 aux_l 14 aux_r 15 video_l 16 video_r 17 cd_l 18 cd_gnd 19 cd_r 20 mic1 21 mic2 22 line_in_l 23 line_in_r 41 cap2 32 *optional 0.1 f 1 f* 820 pf 29 30 afilt1 afilt2 820 pf avss1 avss2 26 42 4 7 dvss1 dvss2 lnlvl_out_r *terminate ground plane as close to codec as possible analog ground digital ground lnlvl_out_l 39 37 mono_out 36 line_out_r 35 line_out_l 43 d_lrclk 44 i2s_out1 40 d_sclk 48 spdif/i2s_out2 34 z_sclk 33 z_data 31 z_lrclk 0.1 f 1 f* *optional 27 vref vrefout eapd cid1 cid0 28 47 46 45 11 reset# 10 sync 24 sdata_in0 bit_clk sdata_out 5 6 8 27 pf 22 ? emi filter 3.3v 5% 3.3v or 5v 5% optional stac9756 figure 24. stac9756 split independent power supply operation typical connection diagram 2-9756-d1-3.3-0303 59 stac9756/57 two channel ac ? 97 codecs with i 2 s digital i/o and spdif output 14. appendix c: programming registers note: 1. all registers not shown and bits containing an x are reserved. they can be written to but are don ? t care upon read back. 2. pc_beep default to 0000h, mute off. 3. if optional bits d13, d5 of register 02h or d5 of register 06h are set to 1, then the corresponding attenuation is set to 46db and the register reads will produce 1fh as a value for this attenuation/gain block. 4. if in secondary mode the default for reg. 18h = 8888h., otherwise 8808h for primary mode. reg #name d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0default 00h reset rsrvd se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 6940h 02h master volume mute rsrvd ml5 ml4 ml3 ml2 ml1 ml0 reserved mr5 mr4 mr3 mr2 mr1 mr0 8000h 04h lnlvl_out mixer volume mute rsrvd ml5 ml4 ml3 ml2 ml1 ml0 reserved mr5 mr4 mr3 mr2 mr1 mr0 8000h 06h master volume mono mute reserved mm5 mm4 mm3 mm2 mm1 mm0 8000h 0ah pc_beep volume mute reserved pv3 pv2 pv1 pv0 rsrvd 0000h 0ch phone volume mute reserved gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute reserved 20db rsrvd gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 1ah record select reserved sl2 sl1 sl0 reserved sr2 sr1 sr0 0000h 1ch record gain mute reserved gl3 gl2 gl1 gl0 reserved gr3 gr2 gr1 gr0 8000h 20h general purpose pop byp rsrvd 3d reserved mix ms lpbk reserved 0000h 22h 3d control reserved dp3 dp2 reserved 0000h 26h powerdown ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 reserved ref anl dac adc 000fh 28h extended audio id id1 id0 reserved amap ldac sdac cdac rsvd spdif dra vra 0205h 2ah extended audio control/ status reserved spcv rsrvd spsa1 spsa0 rsrvd spdif rsrvd vra enable 0400h 2ch pcm dac rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 32h pcm lr adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 3ah spdif control #v drs spsr1 spsr2 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy #pcm/ audio pro 2a00h 60h z_data volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 6ah digital audio control reserved i2s sel i2s ena zvp ena adc ena pcm dis admix gain1 admix gain0 i2s ssl1 i2s ssl0 do3 do2 do1 do0 0000h 6chrevision code0000000000000000 0000h 6eh analog special reserved ac97 all mix reserved dac -6db adc -6db 1000h 70h 72h enable en15 en14 en13 en12 en11 en10 en9 en8 en7 en6 en5 en4 en3 en2 en1 en0 0000h 72h analog current adjust reserved int apop reserved bias1 bias0 rsrvd 0000h 74h multi-channel selection reserved mc1 mc0 0000h 76h 78h enable en15 en14 en13 en12 en11 en10 en9 en8 en7 en6 en5 en4 en3 en2 en1 en0 0000h 78h clock access rsrvd alt clk reserved xtal2 xtal1 xtal0 dith dis dith en1 dith en0 osc pwd hpass filt 0000h 7ch vendor id1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 8384h 7eh vendor id2 9756 0111011001010110 7656h |
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