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data sheet 1 2001-06-19 type ordering code package tle 5209 gp q67007-a9347 p-dso-20-12 h-bridge for dc-motor applications data sheet tle 5209 gp version 1.0 p-dso-20-12 1overview 1.1 features ? delivers up to 5 a continuous current limit at max 7.5 a optimized for dc motor management applications operates at supply voltages from 5.2 v up to 40 v very low r ds on ; typ. 280 m ? @25 c per switch output full short circuit protected overtemperature protection with hysteresis short circuit and open load diagnosis undervoltage lockout cmos/ttl compatible inputs with hysteresis internal freewheeling diodes wide temperature range; ? 40 c < t j < 150 c description the tle 5209 gp is an integrated power h-bridge with dmos output stages for driving dc-motors and torque-motors. the part is built using the infineon multi-technology process spt ? which allows bipolar and cmos control circuitry plus dmos power mos- fets on the same monolithic structure. operation modes forward (cw), reverse (ccw) and brake are invoked from the two control pins dir and pwm with ttl/cmos compatible levels. a diagnostic logic recognizes three failures at the output stage: overcurrent, open load and overtemperature. these failures are shown at the two diagnostic outputs status1 (non latched) and status2 (latched). the combination of an extremely low r ds on and the use of a power ic package with low thermal resistance leads to high permissible output currents. the dir/pwm input interface minimises the effort of control signal generation and the integrated functionality reduces the external circuitry to a minimum.
tle 5209 gp overview data sheet 2 2001-06-19 1.2 pin configuration figure 1 pin configuration (top view) tle 5209gp aep02785 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v s gnd st1 out2 out2 v s gnd st2 gnd pwm gnd out1 out1 v s dir gnd v s gnd gnd gnd
tle 5209 gp overview data sheet 3 2001-06-19 1.3 pin definitions and functions pin no. symbol function 1, 9, 10, 11, 12, 20 gnd ground; internally connected to cooling tab; pins have to be connected to each other externally; 2, 4, 17, 19 v s supply voltage; needs a blocking capacitor to gnd; pins have to be connected to each other externally 3dir direction input; ttl/cmos compatible input. 5, 6 out1 output of halfbridge 1; pins have to be connected to each other externally. 8pwm pulse width modulation input; ttl/cmos compatible input 13 st1 status flag output 1; open drain output, requires external pull- up; not latched. 15; 16 out2 output of halfbridge 2; pins have to be connected to each other externally. 18 st2 status flag output 1; open drain output with internal pull-up; latched, reset if dir or pwm is toggled.
tle 5209 gp overview data sheet 4 2001-06-19 1.4 functional block diagram figure 2 block diagram aeb02786 over temperature detection gate drivers over- and undercurrent detection logic charge pump under voltage detection 5 v regulator 13 18 st1 st2 8 pwm 3 dir gnd 1, 7, 9, 10, 11, 12, 14, 20 15, 16 power stages 5, 6 out 1 out 2 v s 2, 4, 17, 19
tle 5209 gp circuit description data sheet 5 2001-06-19 2 circuit description 2.1 input circuit the control inputs dir and pwm consist of ttl/cmos-compatible schmitt-triggers with hysteresis. buffer amplifiers are driven by this stages. operation modes forward (cw), reverse (ccw) and brake are invoked by these two inputs. if the inputs are not connected, then the load between out1 and out2 is braked. (both highside switches on). there ? s no need for synchronization of the input signals dir and pwm. 2.2 output stages the output stages consist of a dmos h-bridge built by two highside switches and two lowside switches. integrated circuits protect the outputs against overcurrent and overtemperature if there is a short-circuit to ground (scg) or to the supply voltage (scb) or short of the load (scl). positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes. a monitoring circuit for each output transistor detects whether the particular transistor is active and in this case prevents the corresponding source transistor (sink transistor) from conducting in sink operation (source operation). therefore no crossover currents can occur. 2.3 input logic truth table table 1 functional truth table dir pwm out1 out2 comments l l h h brake; both highside transistors switched on. l h h l motor turns clockwise. h l h h brake; both highside transistors are turned on. h h l h motor turns counterclockwise. table 2 notes for output stage symbol value l low side transistor is turned-on. high side transistor is turned-off. h high side transistor is turned-on. low side transistor is turned-off.
tle 5209 gp circuit description data sheet 6 2001-06-19 2.4 monitoring functions undervoltage lockout (uvlo): when v s reaches the switch on voltage v uv on the ic becomes active with a hysteresis. all output transistors are switched off if the supply voltage v s drops below the switch off voltage v uv off. 2.5 protective and diagnostic functions the device is fully protected against all kinds of shorts at the outputs and overtemperature and also detects open load. a) output shorted to ground detection if a high side transistor is switched on and the output current rises above the shutdown threshold i cs for longer than the delay time t dcs , all output transistors are switched off and the status outputs are set. b) output shorted to + v s if a low side transistor is switched on and the output current rises above the shutdown threshold i cs for longer than the delay time t dcs , all output transistors are switched off and the status outputs are set. c) overload detection if a low side transistor and a hide side transistor is switched on and the current through the load rises above the shutdown threshold i cs for longer than the delay time t dcs , all output transistors are switched off and the status outputs are set. the diagnostic behaviour at short circuit is shown schematically in figure 4 . d) overtemperature protection at a junction temperature higher than t off the thermal shutdown turns off all four output stages commonly and the status outputs are set. e) open load detection if the current through the low side transistor is lower than the reference current i dol in the on-state, a timer is started. after a filter time t dol an open load failure will be recognized and the status outputs are set. if the current exceeds the reference current i dol the open load timer is reset. if the h-bridge is switched to off-state (pwm = l) during the open load filter time, the timer is stopped. the timer continues if the h-bridge is switched in on-state again. there is no reset of the open load timer if the direction is changed using the dir input in open load condition. this is shown schematically in figure 3 . 2.6 diagnosis truth table various errors as listed in the table ? diagnosis ? are detected. short circuits and overload result in turning off the output stages after a delay. st1 is active as long as the error exists, but at least 10 s. st2 provides a latched output, this means if a fault occurs it is active until at least one of the inputs dir or pwm are toggled.
tle 5209 gp circuit description data sheet 7 2001-06-19 table 3 flag dir pwm out1 out2 st1 st2 remark no. normal operation 0 0 1 1 0 1 0 1 h h h l h l h h 1 1 1 1 1 1 1 1 ? 1 2 3 4 open circuit between out1 and out2 0 0 1 1 0 1 0 1 h h h l h l h h 1 0 1 0 1 0 1 0 not detectable detected not detectable detected 5 6 7 8 short circuit of out1 to out2 0 0 1 1 0 1 0 1 h z h z h z h z 1 0 1 0 1 0 1 0 not detectable detected not detectable detected 9 10 11 12 short circuit of out1 to gnd 0 0 1 1 0 1 0 1 z z z l z z z h 0 0 0 1 0 0 0 1 detected detected detected not detectable 13 14 15 16 short circuit of out2 to gnd 0 0 1 1 0 1 0 1 z h z z z l z z 0 1 0 0 0 1 0 0 detected not detectable detected detected 17 18 19 20 short circuit of out1 to v s 0 0 1 1 0 1 0 1 h h h z h l h z 1 1 1 0 1 1 1 0 not detectable not detectable not detectable detected 21 22 23 24 short circuit of out2 to v s 0 0 1 1 0 1 0 1 h z h l h z h h 1 0 1 1 1 0 1 1 not detectable detected not detectable not detectable 25 26 27 28 overtempera- ture or undervoltage 0 0 1 1 0 1 0 1 z z z z z z z z 0 0 0 0 0 0 0 0 detected detected detected detected 29 30 31 32 in: 0 = logic low 1 = logic high out: z = both output transistors off l = low-side transistor on h = high-side transistor on status: 1 = high, no error 0 = low, error
tle 5209 gp circuit description data sheet 8 2001-06-19 figure 3 open load diagnosis aet02787 dir = low pwm open circuit st1 st2 < 1 ms > 1 ms > 1 ms
tle 5209 gp circuit description data sheet 9 2001-06-19 figure 4 short circuit diagnosis aet02788 dir = low pwm st1 st2 short of the load st1 (high) short to v bat of out1 st2 (high) st1 st2 short to v bat of out2 st1 st2 short to gnd of out1 st1 st2 short to gnd of out2
tle 5209 gp characteristics data sheet 10 2001-06-19 3 characteristics note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 3.1 absolute maximum ratings ? 40 c < t j < 150 c parameter symbol limit values unit remarks min. max. voltages supply voltage v s ? 0.3 40 v ? ? 140 v t < 0.5 s; i s > ? 5 a logic input voltage v dir, v pwm ? 0.3 7 v 0 v < v s < 40 v diagnostics output voltage v st1, 2 ? 0.3 7 v ? currents of dmos-transistors and freewheeling diodes output current (cont.) i out1, 2 ? 55 a ? output current (peak) i out1, 2 ? 10 10 a t < 2 ms temperatures junction temperature t j ? 40 150 c ? storage temperature t stg ? 50 150 c ? thermal resistances junction case r thjc ? 4k/w ? junction ambient r thja ? 65 k/w ?
tle 5209 gp characteristics data sheet 11 2001-06-19 3.2 operating range parameter symbol limit values unit remarks min. max. supply voltage v s v uv off 40 v after v s rising above v uv on supply voltage increasing ? 0.3 v uv on v outputs in tristate condition supply voltage decreasing ? 0.3 v uv off v logic input voltage v dir, v pwm ? 0.3 7 v ? status1 input current i st1 ? 500 a status active junction temperature t j ? 40 150 c ? input frequency (pwm, dir) f in ? 1000 hz ? note: the following restrictions for the operation frequency and the duty cycle have to be considered: a) switching power dissipation b) diagnostic filter time c) switching characteristics
tle 5209 gp characteristics data sheet 12 2001-06-19 3.3 electrical characteristics 6 v < v s < 18 v; i out1, 2 = 0 a (no load); ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max. outputs out1, 2 static drain-source-on resistance high-side transistor i out = ? 1 a; 5.2v < v s < 6 v r ds on h ? 280 600 m ? t j = 25 c ?? 870 m ? ? high-side transistor i out = ? 3 a; 6 v < v s < 9 v r ds on h ? 260 430 m ? t j = 25 c ?? 640 m ? ? high-side transistor i out = ? 3 a; 9 v < v s < 24 v r ds on h ? 250 340 m ? t j = 25 c ?? 560 m ? ? low-side transistor i out = 1 a; 5.2v < v s < 6 v r ds on l ? 280 550 m ? t j = 25 c ?? 850 m ? ? low-side transistor i out = 3 a; 6 v < v s < 9 v r ds on l ? 260 380 m ? t j = 25 c ?? 620 m ? ? low-side transistor i out = 3 a; 9 v < v s < 24 v r ds on l ? 250 340 m ? t j = 25 c ?? 560 m ? ? short circuit protection shutdown current threshold 5.2 v< v s < 6v i cs5 4.5 ? 7.5 a t < t dcs shutdown current threshold 6 < v s < 9 v i cs6 4.8 ? 7.5 a t < t dcs shutdown current threshold 9 < v s < 24 v i cs9 5.0 ? 7.5 a t < t dcs delaytime for overcurrent shutdown t dcs 51828 s ?
tle 5209 gp characteristics data sheet 13 2001-06-19 logic control inputs dir, pwm ; v in = v dir , v pwm ; i in = i dir , i pwm h-input voltage threshold v inh ?? 3.5 v v in rising l-input voltage threshold v inl 1.0 ?? v v in falling hysteresis of input voltage v inhy 0.3 1 ? v ? h-input current i inh 20 ? 100 a v in = 3.5 v l-input current i inl 20 ? 100 a v in = 1 v status outputs ; v st = v st1 , v st2 ; i st = i st1 , i st2 st1, st2 low output voltage v stl ?? 0.4 v i st = 100 a st2 high output voltage v st2h 3.9 ? 5.4 v i st2 = ? 20 a st1 output leakage current i st1(off) ?? 5 a v st1 = 5 v open load detection detection current i dol 10 40 100 ma 5.2 v < v s <18 v filter time t dol 1 510ms under voltage lockout uv-switch-on voltage v uv on 4.5 ? 5.2 v v s increasing uv-switch-off voltage v uv off 4.0 ? 5.1 v v s decreasing uv-on/off-hysteresis v uv hy ? 0.15 ? v v uv on ? v uv off current consumption supply current i s ? 4 20 ma pwm = high 3.3 electrical characteristics (cont ? d) 6 v < v s < 18 v; i out1, 2 = 0 a (no load); ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5209 gp characteristics data sheet 14 2001-06-19 output timing (device active for t > 100 s) output low-to-high switching time t on h ?? 100 s resistive load of 12 ? ; v s = 13 v; pwm h -> l output high-to-low switching time t on l ?? 100 s resistive load of 12 ? ; v s = 13 v; pwm l -> h slew rate rising; 30% - 80% (d v /d t ) r 0.8 ? 6v / s resistive load of 12 ? ; v s = 13 v slew rate falling; 30% - 80% (d v /d t ) f 0.8 ? 6v / s resistive load of 12 ? ; v s = 13 v setup time after power up on v s t ds ?? 100 s ? note: setup time is guaranteed by design. 3.3 electrical characteristics (cont ? d) 6 v < v s < 18 v; i out1, 2 = 0 a (no load); ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5209 gp characteristics data sheet 15 2001-06-19 clamp diodes forward voltage high-side transistor v fh ?? 2v i fh = 5 a low-side transistor v fl ?? 2v i fl = 5 a leakage current (all output transistors off) high-side transistor i lkh ? 200 ?? a v out = 0; v s =14v low-side transistor i lkl ?? 200 a v out = v s = 14 v thermal shutdown thermal shutdown junction temperature t jsd 150 ? 200 c ? thermal switch-on junction temperature t jso 120 ? 170 c ? temperature hysteresis ? t ? 30 ? k ? note: temperatures are guaranteed by design. 3.3 electrical characteristics (cont ? d) 6 v < v s < 18 v; i out1, 2 = 0 a (no load); ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5209 gp diagrams data sheet 16 2001-06-19 4diagrams figure 5 switching time definitions dir high low v out = v out1 v out2 aet02789 80% v s 30% v s t onh ? t r ? t f 50% 50% t onl ? v v / t = ? v / ? t v out pwm input 0 5 v 30% v s 80% v s
tle 5209 gp diagrams data sheet 17 2001-06-19 figure 6 test circuit overcurrent high-side, short to gnd overcurrent low-side, short to vs open load i out ? i cs i cs i dol aes02790 tle 5209gp v dir v pwm v st2 i fl 400 nf 470 f st2 pwm v s out1 out2 gnd dir v out2 v out1 v s r load st1 i st1 v st1 i st2 i pwm i dir i , s - i fh i out2 i out1
tle 5209 gp diagrams data sheet 18 2001-06-19 figure 7 application circuit aes02791 tle 4278g tle 5209gp micro- controller m wd r v cc watchdog reset q d c d 10 nf c q 22 f d1 1n4001 d2 z39 v bb 22 k ? st1 st2 13 18 pwm dir 8 3 5, 6 out 1 15, 16 out 2 v s 2, 4, 17, 19 gnd gnd 1, 7, 9, 10, 11, 12, 14, 20
tle 5209 gp package outlines data sheet 19 2001-06-19 5 package outlines +0.07 -0.02 -0.3 1.2 2.8 1.3 0.25 1) does not include plastic or metal protrusion of 0.15 max. per side 20x 0.25 m 1) heatsink 0.95 14.2 +0.15 index marking 15.9 10 1 0.1 +0.13 0.4 1.27 3.5 max. 0 6.3 11 3.25 20 11 ?.15 ?.1 ?.15 1 x 45? ?.3 5? ?? ?.15 15.74 ?.1 a a 1) b 0.25 m b gps05791 p-dso-20-12 (plastic dual small outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book ?ackage information? dimensions in mm smd = surface mounted device

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